? semiconductor components industries, llc, 2006 may, 2006 ? rev. 1 1 publication order number: NB4N840M/d NB4N840M 3.3v 2.7gb/s dual differential clock/data 2 x 2 crosspoint switch with cml output and internal termination description the NB4N840M is a high ? bandwidth fully differential dual 2 x 2 crosspoint switch with cml inputs/outputs that is suitable for applications such as sdh/sonet dwdm and high speed switching. fully differential design techniques are used to minimize jitter accumulation, crosstalk, and signal skew, which make this device ideal for loop ? through and protection channel switching applications. each 2 x 2 crosspoint switch can fan ? out and/or multiplex up to 2.7 gb/s data and 2.7 ghz clock signals. internally terminated differential cml inputs accept ac ? coupled lvpecl (positive ecl) or direct coupled cml signals. by providing internal 50 input and output termination resistor, the need for external components is eliminated and interface reflections are minimized. differential 16 ma cml outputs provide matching internal 50 terminations, and 400 mv output swings when externally terminated, 50 to v cc . single ? ended lvcmos/lvttl sel inputs control the routing of the signals through the crosspoint switch which makes this device configurable as 1:2 fan ? out, repeater or 2 x 2 crosspoint switch. the device is housed in a low profile 5 x 5 mm 32 ? pin qfn package. features ? plug ? in compatible to the max3840 and sy55859l ? maximum input clock frequency 2.7 ghz ? maximum input data frequency 2.7 gb/s ? 225 ps typical propagation delay ? 80 ps typical rise and fall times ? 7 ps channel to channel skew ? 430 mw power consumption ? < 0.5 ps rms jitter ? 7 ps peak ? to ? peak data dependent jitter ? power saving feature with disabled outputs ? operating range: v cc = 3.0 v to 3.6 v with v ee = 0 v ? cml output level (400 mv peak ? to ? peak output), differential output ? these are pb ? free devices qfn32 mn suffix case 488am see detailed ordering and shipping information on page 8 of this data sheet. ordering information marking diagram http://onsemi.com 32 1 nb4n 840m alywg 1 a = assembly location wl = wafer lot yy = year ww = work week g= pb ? free package cml cml cml cml cml cml cml cml 0 1 0 1 0 1 0 1 figure 1. functional block diagram qa0 qa0 ena0 sela0 qa1 qa1 ena1 sela1 qb0 qb0 enb0 selb0 qb1 qb1 enb1 selb1 da0 da0 da1 da1 db0 db0 db1 db1
NB4N840M http://onsemi.com 2 table 1. truth table sela0/selb0 sela1/selb1 ena0/ena1 ena1/enb1 qa0/qb0 qa1/qb1 function l l h h da0/db0 da0/db0 1:2 fanout l h h h da0/db0 da1/db1 quad repeater h l h h da1/db1 da0/db0 crosspoint switch h h h h da1/db1 da1/db1 1:2 fanout x x l l disable/power down disable/power down no output (@ v cc ) figure 2. pin configuration (top view) 32 31 30 29 28 27 26 25 9 10 11 12 1314 1516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 enb1 selb1 db1 db1 db0 enb0 selb0 db0 gnd v cc qa0 qa1 qa1 v cc qa0 v cc gnd v cc v cc qb0 qb0 qb1 qb1 v cc ena1 da1 da1 da0 da0 ena0 sela0 sela1 NB4N840M
NB4N840M http://onsemi.com 3 table 2. pin description pin name i/o description 1 enb1 lvttl channel b1 output enable. lvttl low input powers down b1 output stage. 2 db1 cml input channel b1 positive signal input 3 db1 cml input channel b1 negative signal input 4 enb0 lvttl channel b0 output enable. lvttl low input powers down b0 output stage. 5 selb0 lvttl channel b0 output select. see table 1. 6 db0 cml input channel b0 positive signal input 7 db0 cml input channel b0 negative signal input 8 selb1 lvttl channel b1 output select. see table 1. 9,24 gnd ? supply ground. all gnd pins must be externally connected to power supply to guarantee proper operation. 10, 13, 16, 17, 20, 23 v cc ? positive supply. all v cc pins must be externally connected to power supply to guarantee proper operation. 11 qb0 cml output channel b0 negative output. 12 qb0 cml output channel b0 positive output. 14 qb1 cml output channel b1 negative output. 15 qb1 cml output channel b1 positive output. 18 qa1 cml output channel a1 negative output. 19 qa1 cml output channel a1 positive output. 21 qa0 cml output channel a0 negative output. 22 qa0 cml output channel a0 positive output. 25 sela1 lvttl channel a1 output select, lvttl input. see table 1. 26 da0 cml input channel a0 positive signal input. 27 da0 cml input channel a0 negative signal input. 28 sela0 lvttl channel a0 output select, lvttl input. see table 1. 29 ena0 lvttl channel a0 output enable. lvttl low input powers down a0 output stage. 30 da1 cml input channel a1 positive signal input. 31 da1 cml input channel a1 negative signal input. 32 ena1 lvttl channel a1 output enable. lvttl low input powers down a1 output stage. ? ep gnd exposed pad. the thermally exposed pad (ep) on package bottom (see case drawing) must be attached to a heat ? sinking conduit. the exposed pad must be soldered to the circuit board gnd for proper electrical and thermal operation.
NB4N840M http://onsemi.com 4 table 3. attributes characteristics value esd protection human body model machine model > 2000 v > 110 v moisture sensitivity (note 1) qfn ? 32 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 380 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, refer to application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 3.8 v v i positive input gnd = 0 v gnd = v i = v cc 3.8 v v inpp differential input voltage |d ? d | 3.8 v i in input current through internal 50 resistor static surge 45 80 ma ma i out output current continuous surge 25 80 ma ma t a operating temperature range qfn ? 32 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 2) 0 lfpm 500 lfpm qfn ? 32 qfn ? 32 31 27 c/w c/w jc thermal resistance (junction ? to ? case) 2s2p (note 3) qfn ? 32 12 c/w t sol wave solder pb ? free <3 sec @ 260 c 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. jedec standard 51 ? 6, multilayer board ? 2s2p (2 signal, 2 power). 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB4N840M http://onsemi.com 5 table 5. dc characteristics, clock inputs, cml outputs v cc = 3.0 v to 3.6 v, t a = ? 40 c to +85 c symbol characteristic min typ max unit i cc power supply current (all outputs enabled) 130 170 ma vout diff cml differential output swing (note 4, figures 5 and 12) 640 800 1000 mv v cmr (note 6) cml output common mode voltage (loaded 50 to v cc ) v cc ? 200 mv cml single ? ended input voltage range v cc ? 0.8 v cc + 0.4 mv v id differential input voltage (v ihd ? v ild ) 300 1600 mv lvttl control input pins v ih input high voltage (lvttl inputs) 2000 mv v il input low voltage (lvttl inputs) 800 mv i ih input high current (lvttl inputs) ? 10 10 a i il input low current (lvttl inputs) ? 10 10 a r tin cml single ? ended input resistance 42.5 50 57.5 r tout differential output resistance 85 100 115 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. cml outputs require 50 receiver termination resistors to v cc for proper operation (figure 10). 5. input and output parameters vary 1:1 with v cc . 6. v cmr min varies 1:1 with v ee , v cmr max varies 1:1 with v cc . table 6. ac characteristics v cc = 3.0 v to 3.6 v, v ee = 0 v (note 7, figure 9) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (@ v inppmin )f in 2 ghz (see figure 3) f in 3 ghz f in 3.5 ghz 280 235 170 365 310 220 280 235 170 365 310 220 280 235 170 365 310 220 mv f data maximum operating data rate 2.7 3.2 2.7 3.2 2.7 3.2 gb/s t plh , t phl propagation delay to output differential d/d to q/q 140 225 340 140 225 340 140 225 340 ps t skew duty cycle skew (note 8) within ? device skew (figure 4) device ? to ? device skew (note 12) 5 5 20 25 25 85 5 5 20 25 25 85 5 5 20 25 25 85 ps t jitter rms random clock jitter (note 10) f in 3.2 ghz peak ? to ? peak data dependent jitter f in = 2.5 gb/s (note 11) f in = 3.2 gb/s 0.15 7 7 0.5 20 20 0.15 7 7 0.5 20 20 0.15 7 7 0.5 20 20 ps crosstalk ? induced rms jitter (note 13) 0.5 0.5 0.5 ps v inpp input voltage swing/sensitivity (differential configuration) (note 9) 150 800 150 800 150 800 mv t r t f output rise/fall times @ 0.5 ghz q, q (20% ? 80%) 80 135 80 135 80 135 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. measured by forcing v inpp (min) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc . input edge rates 40 ps (20% ? 80%). 8. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+ @ 0.5 ghz. 9. v inpp (max) cannot exceed 800 mv. input voltage swing is a single ? ended measurement operating in differential mode. 10. additive rms jitter using 50% duty cycle clock input signal. 11. additive peak ? to ? peak data dependent jitter using input data pattern with prbs 2 23 ? 1 and k28.5, v inpp = 400 mv. 12. device to device skew is measured between outputs under identical transition @ 0.5 ghz. 13. data taken on the same device under identical condition.
NB4N840M http://onsemi.com 6 figure 3. output voltage amplitude (v outpp ) vs. input clock frequency (f in ) at ambient temperature (typ) 0 50 100 150 200 250 300 350 400 450 0.05 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 input clock frequency (ghz) output voltage amplitude (mv) figure 4. within ? device skew vs. temperature at v cc = 3.3 v 0 2 4 6 8 10 12 14 16 18 20 ? 40 25 85 temperature ( c) time (ps) channel b channel a figure 5. cml differential voltage vs. temperature 0 100 200 300 400 500 600 700 800 900 ? 40 25 85 temperature ( c) voltage (mv) figure 6. supply current vs. temperature (all 4 outputs enabled) 110 120 130 140 150 160 170 ? 40 25 85 temperature ( c) current (ma) figure 7. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 (input signal ddj = 12 ps) figure 8. typical output waveform at 3.2 gb/s with k28.5 (input signal ddj = 14 ps) time (80.4 ps/div) voltage (50 mv/div) time (62.5 ps/div) voltage (50 mv/div) ddj = 4 ps ddj = 3 ps
NB4N840M http://onsemi.com 7 figure 9. ac reference measurement dx dx qx qx t phl t plh v inpp = v ih (d x ) ? v il (d x ) v outpp = v oh (q x ) ? v ol (q x ) figure 10. typical termination for output driver and device evaluation (see application note and8057/d) driver device receiver device qd q d z o = 50 z o = 50 50 50 v cc q x q x v cc 16 ma 50 50 figure 11. cml input and output structure gnd v cc 50 gnd gnd d x d x 50 input output
NB4N840M http://onsemi.com 8 (q x ? q x ) 640 mv min 320 mv min 500 mv max 1000 mv max q x q x figure 12. cml output levels q x q x (q x ? q x ) ordering information device package shipping NB4N840Mmng qfn32 (pb ? free) 74 units / rail NB4N840Mmnr4g qfn32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB4N840M http://onsemi.com 9 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NB4N840M/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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