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january 2012 doc id 022152 rev 2 1/167 1 stm32f405xx stm32f407xx arm cortex-m4 32b mcu+fpu, 210d mips, up to 1mb flash/192+4kb ram, usb otg hs/fs, ethernet, 17 tims, 3 adcs, 15 comm. interfaces & camera features core: arm 32-bit cortex?-m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from flash memory, frequency up to 168 mhz, memory protection unit, 210 dmips/ 1.25 dmips/mhz (dhrystone 2.1), and dsp instructions memories ? up to 1 mbyte of flash memory ? up to 192+4 kbytes of sram including 64- kbyte of ccm (core coupled memory) data ram ? flexible static memory controller supporting compact flash, sram, psram, nor and nand memories lcd parallel interface, 8080/6800 modes clock, reset and supply management ? 1.8 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc (1% accuracy) ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc, 2032 bit backup registers + optional 4 kb backup sram 312-bit, 2.4 msps a/d co nverters: up to 24 channels and 7.2 msps in triple interleaved mode 212-bit d/a converters general-purpose dma: 16-stream dma controller with fifos and burst support up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 mhz, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m4 embedded trace macrocell? 1. the wlcsp90 package will soon be available. up to 140 i/o ports with interrupt capability ? up to 136 fast i/os up to 84 mhz ? up to 138 5 v-tolerant i/os up to 15 communication interfaces ? up to 3 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts/2 uarts (10.5 mbit/s, iso 7816 interface, lin, irda, modem control) ? up to 3 spis (37.5 mbits/s), 2 with muxed full-duplex i 2 s to achieve audio class accuracy via internal audio pll or external clock ? 2 can interfaces (2.0b active) ? sdio interface advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii 8- to 14-bit parallel camera interface up to 54 mbytes/s true random number generator crc calculation unit 96-bit unique id rtc: subsecond accuracy, hardware calendar table 1. device summary reference part number stm32f405xx stm32f405rg, stm32f405vg, stm32f405zg stm32f407xx stm32f407vg, stm32f407ig, stm32f407zg, stm32f407ve, stm32f407ze, stm32f407ie lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp144 (20 20 mm) fbga ufbga176 (10 10 mm) lqfp176 (24 24 mm) wlcsp90 www.st.com
contents stm32f405xx, stm32f407xx 2/167 doc id 022152 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 arm ? cortex?-m4f core with embedded flash and sram . . . . . . . . 18 2.2.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . 18 2.2.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 19 2.2.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.9 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.10 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 21 2.2.11 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.12 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.13 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.14 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.15 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.16 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.17 real-time clock (rtc), backup sram and backup registers . . . . . . . . 26 2.2.18 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.19 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.20 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.21 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.22 universal synchronous/asynchronous receiver transmitters (usart) . 31 2.2.23 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.24 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.25 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.26 secure digital input/output interface (sdio) . . . . . . . . . . . . . . . . . . . . . 33 2.2.27 ethernet mac interface with dedicated dma and ieee 1588 support . 33 2.2.28 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.29 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . 34
stm32f405xx, stm32f407xx contents doc id 022152 rev 2 3/167 2.2.30 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . 34 2.2.31 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.32 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.33 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.34 analog-to-digital converters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.35 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.36 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.37 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.38 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.2 vcap1/vcap2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.3 operating conditions at power-up / power-down (regulator on) . . . . . . 68 5.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 68 5.3.5 embedded reset and power control block characteristics . . . . . . . . . . . 69 5.3.6 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3.7 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.8 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.9 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.10 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.11 pll spread spectrum clock generation (sscg) characteristics . . . . . . 92 5.3.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
contents stm32f405xx, stm32f407xx 4/167 doc id 022152 rev 2 5.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.14 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 97 5.3.15 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.16 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.17 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.3.18 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.3.20 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.3.22 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.3.23 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.3.24 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.3.25 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.3.26 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 144 5.3.27 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 144 5.3.28 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 appendix a application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 a.1 main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 a.2 application example with regulator off . . . . . . . . . . . . . . . . . . . . . . . . . 155 a.3 usb otg full speed (fs) interface solutions . . . . . . . . . . . . . . . . . . . . . 156 a.4 usb otg high speed (hs) interface solutions . . . . . . . . . . . . . . . . . . . . 158 a.5 complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 a.6 ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
stm32f405xx, stm32f407xx list of tables doc id 022152 rev 2 5/167 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f405xx and stm32f407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 12 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 4. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 6. stm32f40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 7. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 8. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 9. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 10. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 11. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 12. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 67 table 13. vcap1/vcap2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 14. operating conditions at power-up / power-down (regulator on) . . . . . . . . . . . . . . . . . . . . 68 table 15. operating conditions at power-up / power-down (regulator off). . . . . . . . . . . . . . . . . . . . 68 table 16. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 17. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 18. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram . . . . . . . . . . . . . . . . . . . 72 table 19. typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 75 table 20. typical and maximum current consumptions in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 76 table 21. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 76 table 22. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 77 table 23. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 24. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 25. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 26. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 27. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 28. hse 4-26 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 table 29. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 30. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 31. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 32. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 33. plli2s (audio pll) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 34. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 35. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 36. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 37. flash memory programming with v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 38. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 39. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 40. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 41. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 42. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 43. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 44. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 45. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 46. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
list of tables stm32f405xx, stm32f407xx 6/167 doc id 022152 rev 2 table 47. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 48. characteristics of timx connected to the apb1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 49. characteristics of timx connected to the apb2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 50. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 51. scl frequency (f pclk1 = 42 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 52. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 53. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 54. usb otg fs startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 55. usb otg fs dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 56. usb otg fs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 57. usb fs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14 table 58. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 table 59. usb hs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 table 60. ulpi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 61. ethernet dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 62. dynamics characteristics: ethernet mac signals for smi. . . . . . . . . . . . . . . . . . . . . . . . . 116 table 63. dynamics characteristics: ethernet mac signals for rmii . . . . . . . . . . . . . . . . . . . . . . . . 117 table 64. dynamics characteristics: ethernet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 65. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 66. adc accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 67. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 68. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 69. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 70. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 71. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . 127 table 72. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 128 table 73. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 74. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 75. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 76. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 77. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . 134 table 78. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 79. switching characteristics for pc card/cf read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 80. switching characteristics for pc card/cf read and write cycles in i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 81. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 82. switching characteristics for nand flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 83. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 84. sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 85. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 86. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 147 table 87. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 148 table 88. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 149 table 89. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . 150 table 90. lqfp176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 151 table 91. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 92. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 93. main applications versus package for stm32f407xx microcontrollers . . . . . . . . . . . . . . 154 table 94. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
stm32f405xx, stm32f407xx list of figures doc id 022152 rev 2 7/167 list of figures figure 1. compatible board design between stm32f10xx/stm32f4xx for lqfp64 . . . . . . . . . . . . 14 figure 2. compatible board design stm32f10xx/stm32f2xx/stm32f4xx for lqfp100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. compatible board design between stm32f10xx/stm32f2xx/stm32f4xx for lqfp144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. compatible board design between stm32f2xx and stm32f4xx for lqfp176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. stm32f40x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. regulator on/internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. stm32f40x lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. stm32f40x lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. stm32f40x lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 13. stm32f40x lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 14. stm32f40x ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 figure 15. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 16. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 17. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 18. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 19. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 20. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 21. typical current consumption vs temperature, run mode, code with data processing running from flash (art accelerator on) or ram, and peripherals off . . . . 73 figure 22. typical current consumption vs temperature, run mode, code with data processing running from flash (art accelerator on) or ram, and peripherals on . . . . . 73 figure 23. typical current consumption vs temperature, run mode, code with data processing running from flash (art accelerator off) or ram, and peripherals off . . . 74 figure 24. typical current consumption vs temperature, run mode, code with data processing running from flash (art accelerator off) or ram, and peripherals on . . . . 74 figure 25. typical v bat current consumption (lse and rtc on/backup ram off) . . . . . . . . . . . . 77 figure 26. typical v bat current consumption (lse and rtc on/backup ram on) . . . . . . . . . . . . . 78 figure 27. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 28. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 29. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 30. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 31. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 32. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 33. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 34. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 35. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 36. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 37. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 38. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 39. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
list of figures stm32f405xx, stm32f407xx 8/167 doc id 022152 rev 2 figure 40. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 41. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 42. usb otg fs timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 114 figure 43. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 44. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 45. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 46. ethernet mii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 47. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 48. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 49. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 122 figure 50. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 122 figure 51. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 52. asynchronous non-multiplexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 127 figure 53. asynchronous non-multiplexed sram/psram/nor write waveforms . . . . . . . . . . . . . . 128 figure 54. asynchronous multiplexed psram/nor read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 129 figure 55. asynchronous multiplexed psram/nor write waveforms . . . . . . . . . . . . . . . . . . . . . . . 130 figure 56. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 57. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 58. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 59. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 60. pc card/compactflash controller waveforms for common memory read access . . . . . . 136 figure 61. pc card/compactflash controller waveforms for common memory write access . . . . . . 137 figure 62. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 63. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 64. pc card/compactflash controller waveforms for i/o space read access . . . . . . . . . . . . 139 figure 65. pc card/compactflash controller waveforms for i/o space write access . . . . . . . . . . . . 140 figure 66. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 67. nand controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 68. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 143 figure 69. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 143 figure 70. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 71. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 72. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 147 figure 73. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 74. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 148 figure 75. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 76. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 77. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 78. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline . 150 figure 79. lqfp176 24 x 24 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 151 figure 80. regulator off/internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 81. regulator off/internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 82. usb controller configured as peripheral-only and used in full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 56 figure 83. usb controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 156 figure 84. usb controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 157 figure 85. usb controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 86. complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
stm32f405xx, stm32f407xx list of figures doc id 022152 rev 2 9/167 figure 87. complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 88. audio player solution using pll, plli2s, usb and 1 crystal . . . . . . . . . . . . . . . . . . . . . . 160 figure 89. audio pll (plli2s) providing accurate i2s clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 90. master clock (mck) used to drive the external audio dac. . . . . . . . . . . . . . . . . . . . . . . . 161 figure 91. master clock (mck) not used to drive the external audio dac. . . . . . . . . . . . . . . . . . . . . 161 figure 92. mii mode using a 25 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 62 figure 93. rmii with a 50 mhz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 94. rmii with a 25 mhz crystal and phy with pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
introduction stm32f405xx, stm32f407xx 10/167 doc id 022152 rev 2 1 introduction this datasheet provides the description of the stm32f405xx and stm32f407xx lines of microcontrollers. for more details on the whole stmicroelectronics stm32? family, please refer to section 2.1: full compatib ility throughout the family . the stm32f405xx and stm32f407xx datasheet should be read in conjunction with the stm32f4xx reference manual. for information on programming, erasing and protection of the internal flash memory, please refer to the stm32f4xx flash programming manual (pm0081). the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex?-m4 core please refer to the cortex?-m4 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/.
stm32f405xx, stm32f407xx description doc id 022152 rev 2 11/167 2 description the stm32f405xx and stm32f407xx family is based on the high-performance arm ? cortex?-m4 32-bit risc core operating at a frequency of up to 168 mhz. the cortex-m4 core features a floating point unit (fpu) sing le precision which supports all arm single- precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances application security. the cortex-m4 core with fpu will be referred to as cortex-m4f through out this document. the stm32f405xx and stm32f407xx family incorporates high-speed embedded memories (flash memory up to 1 mbyte, up to 192 kbytes of sram), up to 4 kbytes of backup sram, and an extensive range of enhanced i/os and peripherals connected to two apb buses, two ahb buses and a 32-bit multi-ahb bus matrix. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for motor control, two general-purpose 32-bit timers. a true random number generator (rng). they also feature standard and advanced communication interfaces. up to three i 2 cs three spis, two i 2 ss full duplex. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external clock to allow synchronization. four usarts plus two uarts an usb otg full-speed and a usb otg high- speed with full-speed capability (with the ulpi), tw o c a n s an sdio/mmc interface ethernet and the camera interface available on stm32f407xx devices only. new advanced peripherals include an sdio, an enhanced flexible static memory control (fsmc) interface (for devices offered in packages of 100 pins and more), a camera interface for cmos sensors. refer to table 2: stm32f405xx and stm32f407xx: features and peripheral counts for the list of peripherals available on each part number. the stm32f405xx and stm32f407xx family operates in the ?40 to +105 c temperature range from a 1.8 to 3.6 v power supply. the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range and pdr is disabled. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f405xx and stm32f407xx family offers devices in four packages ranging from 64 pins to 176 pins. the set of included peripherals changes with the device chosen. these features make the stm32f405xx and stm32f407xx microcontroller family suitable for a wide range of applications: motor drive and application control medical equipment industrial applications: plc, inverters, circuit breakers printers, and scanners alarm systems, video intercom, and hvac home audio appliances
description stm32f405xx, stm32f407xx 12/167 doc id 022152 rev 2 figure 5 shows the general block diagram of the device family. table 2. stm32f405xx and stm32f407xx: features and peripheral counts peripherals stm32f405rg stm32f405vg stm32f40 5zg stm32f407vx stm32f407zx stm32f407ix flash memory in kbytes 1024 512 1024 512 1024 512 1024 sram in kbytes system 192(112+16+64) backup 4 fsmc memory controller no yes ethernet no yes timers general-purpose 10 advanced- control 2 basic 2 random number generator yes communication interfaces spi / i 2 s 3/2 (full duplex) i 2 c 3 usart/uart 4/2 usb otg fs no yes usb otg hs yes yes can 2 camera interface no yes gpios 51 82 114 82 114 140 12-bit adc number of channels 3 16 16 24 16 24 24 12-bit dac number of channels ye s 2 maximum cpu frequency 168 mhz operating voltage 1.8 to 3.6 v (1)
stm32f405xx, stm32f407xx description doc id 022152 rev 2 13/167 operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp64 lqfp100 lqfp144 lqfp100 lqfp144 ufbga176 lqfp176 1. v dd /v dda minimum value of 1.7 v is obtained when the device operates in the 0 to 70 c temperature range and pdr is disabled. table 2. stm32f405xx and stm32f407xx: features and peripheral counts (continued) peripherals stm32f405rg stm32f405vg stm32f40 5zg stm32f407vx stm32f407zx stm32f407ix
description stm32f405xx, stm32f407xx 14/167 doc id 022152 rev 2 2.1 full compatibility throughout the family the stm32f405xx and stm32f407xx are part of the stm32f4 family. they are fully pin- to-pin, software and feature compatible with the stm32f2xx devices, allowing the user to try different memory densities, peripherals, and performances (fpu, higher frequency) for a greater degree of freedom during the development cycle. the stm32f405xx and stm32f 407xx devices maintain a close compatibility with the whole stm32f10xxx family. all functional pins are pin-to-pin compatible. the stm32f405xx and stm32f407xx, however, are not drop-in replacements for the stm32f10xxx devices: the two families do not have the same power scheme, and so their power pins are different. nonetheless, transition from the stm32f10xxx to the stm32f40x family remains simple as only a few pins are impacted. figure 4 , figure 3 , figure 2 , and figure 1 give compatible board designs between the stm32f40x, stm32f2xxx, and stm32f10xxx families. figure 1. compatible board design between stm32f10xx/stm32f4xx for lqfp64 6 33 6 33 6 33 6 33 resistororsolderingbridge presentforthe34-&xx configurationnotpresentinthe 34-&xxconfiguration ai
stm32f405xx, stm32f407xx description doc id 022152 rev 2 15/167 figure 2. compatible board design stm32f10xx/stm32f2xx/stm32f4xx for lqfp100 package figure 3. compatible board design between stm32f10xx/stm32f2xx/stm32f4xx for lqfp144 package 6 33 6 33 6 $$ 6 33 6 33 6 33 resistororsolderingbridge a presentforthe34-&xxx configurationnotpresentinthe 34-&xxconfiguration aic 6 33 6 33 6 $$ 4wo resistorsconnectedto 6 33 forthe34-&xx 6 33 forthe34-&xx 6 33 for34-&xx 6 $$ for34-&xx 6 33 6 $$ or.#forthe34-&xx 6 33 resistororsolderingbridge presentforthe34-&xx configurationnotpresentinthe 34-&xxconfiguration 6 33 4wo resistorsconnectedto 6 33 forthe34-&xx 6 $$ orinvertedresetsignalforthe34-&xx 6 33 6 $$ 6 33 6 33 aic 0$2?/. 6 33 6 $$ 6 33 for34-&xx 6 $$ for34-&xx 6 33 6 $$ or.#forthe34-&xx )nverted resetsignal
description stm32f405xx, stm32f407xx 16/167 doc id 022152 rev 2 figure 4. compatible board design between stm32f2xx and stm32f4xx for lqfp176 package 4wo resistorsconnectedto 6 33 6 $$ or.#forthe34-&xx 6 $$ orinvertedresetsignalforthe34-&xx -36 0$2?/. 6 33 6 $$ )nverted resetsignal
stm32f405xx, stm32f407xx description doc id 022152 rev 2 17/167 2.2 device overview figure 5. stm32f40x block diagram 1. the timers connected to apb2 are clocked from timxclk up to 168 mhz, while the timers connected to apb1 are clocked '0)/0/24! !("!0" %84)47+50 !& 0!;= '0)/0/24" 0";= 4)-07- complchannels4)-?#(;=. channels4)-?#(;= %42 "+).as!& 4)-07- '0)/0/24# 0#;= 53!24 2848#+ #43243as!& '0)/0/24$ 0$;= '0)/0/24% 0%;= '0)/0/24& 0&;= '0)/0/24' 0';= 30) -/3)-)3/ 3#+.33as!& !0"-(z !0"-(z analoginputscommon tothe!$#s analoginputscommon tothe!$# 6 $$2%&?!$# analoginputsto!$# channels%42as!& channels%42as!& channels%42as!& channels%42as!& 2848#+ 53!24 2848#+ 53!24 2848as!& 5!24 2848as!& 5!24 -/3)3$-)3/3$?ext 3#+#+ 30))3 .3373-#+as!& -/3)3$-)3/3$?ext 3#+#+ 30))3 .3373-#+as!& 3#,3$!3-"!as!& )#3-"53 3#,3$!3-"!as!& )#3-"53 4828 bx#!. 4828 bx#!. $!#?/54 as!& $!#?/54 as!& )4& 77$' +""+032!- 24#?!& /3#?). /3#?). /3#?/54 /3#?/54 .234 6 $$! 6 33! 6 #!0 6 #!0 53!24 2848#+ #43243as!& smcard ir$! smcard ir$! smcard ir$! smcard ir$! b b b b b b b b #43243as!& #43243as!& 3$)/--# $;= #-$#+as!& 6 "!4 to6 $-! !("!0" $-! 3#,3$!3-"!as!& )#3-"53 '0)/0/24( 0(;= '0)/0/24) 0);= *4!'37 !2-#ortex - -(z 3 "53 ) "53 .6)# %4- -05 .*4234*4$) *4$/37$*4$/ 42!#%#,+ 42!#%$;= *4#+37#,+ %thernet-!# $-! -))or2-))as!& -$)/as!& &)&/ 53" $-! &)&/ /4' (3 $0$- 5,0)#+$ $)2340.84 $-! 3treams &)&/ $-! 3treams &)&/ !24!##%, #!#(% 32!-+" #,+.%;=!;= $;=/%.7%. .",;=.,.2%' .7!)4)/2$9#$ .)/2$)/72).4;= ).4..))3as!& 3#,3$!).4.)$6" 533/& 2.' #amera interface (39.#639.# 0)8#,+$;= 53" 0(9 /4'&3 $0 $- &)&/ &)&/ !( (" -(z 0(9 &)&/ 53!24-"ps 4emperaturesensor !$# !$# !$# )& )& 6$$! 6$$! 0/20$2 3upply 6$$! supervision 06$ 2eset )nt 0/2 84!,/3# -(z 84!,k(z (#,+x -!.!'4 24# 2#(3 &#,+ 2#,3 3tandby )7$' 6 "!4 6$$! 6$$ !75 2eset clock control 0,, 0#,+x interface 6 $$ to6 6 33 6oltage regulator 6to6 6 $$ 0owermanagmt 6$$ 24#?!& "ackup register 3#,3$!).4.)$6"533/& !("bus matrix3- !0" -(z ,3 ,3 channelsas!& channel as!& channel as!& 4)- b b b 4)- channelsas!& 4)- channelas!& b b 4)- channelas!& b "/2 $!# $!# &lash upto -" 32!-032!-./2&lash 0##ard!4! .!.$&lash %xternalmemory controller&3-# 4)- 4)- 4)- 4)- 4)- 4)- 4)- 4)- $ " 53 -36 compl channels4)-?#(;=. channels4)-?#(;= %42 "+).as!& &)&/ &05 !0"-(zmax 32!-+" ##-data2!-+" !(" !("-(z
description stm32f405xx, stm32f407xx 18/167 doc id 022152 rev 2 from timxclk up to 84 mhz. 2. the camera interface is avai lable only on stm32f407xxdevices. 2.2.1 arm ? cortex?-m4f core with embedded flash and sram the arm cortex-m4f processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm cortex-m4f 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructi ons which allow efficient signal processing and complex algorithm execution. its single precision fpu (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f405xx and stm32f407xx family is compatible with all arm tools and software. figure 5 shows the general block diagram of the stm32f40x family. note: cortex-m4f is binary compatible with cortex-m3. 2.2.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelera tor which is optimized for stm32 industry- standard arm ? cortex?-m4f processors. it balances the inherent performance advantage of the arm cortex-m4f over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor full 210 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accelerator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 168 mhz. 2.2.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful fo r applications where some critic al or certified code has to be protected against the misbehavior of other tasks. it is usually managed by an rtos (real- time operating system). if a program accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it.
stm32f405xx, stm32f407xx description doc id 022152 rev 2 19/167 2.2.4 embedded flash memory the stm32f40x devices embed a flash memory of 256 kbytes, 512 kbytes, 768 kbytes or 1 mbytes available for storing programs and data. 2.2.5 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 embedded sram all stm32f40x products embed: up to 192 kbytes of system sram includin g 64 kbytes of ccm (core coupled memory) data ram ram memory is accessed (read/write) at cpu clock speed with 0 wait states. 4 kbytes of backup sram this area is accessible only from the cp u. its content is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 2.2.7 multi-ahb bus matrix the 32-bit multi-ahb bus matrix interconnects all the masters (cpu, dmas, ethernet, usb hs) and the slaves (flash memory, ram, fsmc, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.
description stm32f405xx, stm32f407xx 20/167 doc id 022152 rev 2 figure 6. multi-ahb matrix 2.2.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral tr ansfers. they feature dedicate d fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. !2- #ortex - '0 $-! '0 $-! -!# %thernet 53"/4' (3 "usmatrix 3 3 3 3 3 3 3 3 3 )#/$% $#/$% !##%, &lash memory 32!- +byte 32!- +byte !(" periph !(" periph &3-# 3tatic-em#tl - - - - - - - ) bus $ bus 3 bus $-!?0) $-!?-%- $-!?-%- $-!?0 %4(%2.%4?- 53"?(3?- ai ##-data2!- +byte !0" !0"
stm32f405xx, stm32f407xx description doc id 022152 rev 2 21/167 the dma can be used with the main peripherals: spi and i 2 s i 2 c usart general-purpose, basic and advanced-control timers timx dac sdio camera interface (dcmi) adc. 2.2.9 flexible static memory controller (fsmc) the fsmc is embedded in the stm32f405xx and stm32f407xx family. it has four chip select outputs supporting the following modes: pccard/compact flash, sram, psram, nor flash and nand flash. functionality overview: write fifo maximum fsmc_clk frequency for synchronous accesses is 60 mhz. lcd parallel interface the fsmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel interface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 nested vectored inte rrupt controller (nvic) the stm32f405xx and stm32f407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 87 maskable interrupt channels plus the 16 interrupt lines of the cortex?-m4f. closely coupled nvic gives low-latency interrupt processing interrupt entry vector table address passed directly to the core allows early processing of interrupts processing of late arriving, higher-priority interrupts support tail chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 external interr upt/event controller (exti) the external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a
description stm32f405xx, stm32f407xx 22/167 doc id 022152 rev 2 pulse width shorter than the internal apb2 cloc k period. up to 140 gp ios can be connected to the 16 external interrupt lines. 2.2.12 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-trim med to offer 1% accuracy over the full temperature range. the applicat ion can then select as system clock either the rc oscillator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a failure is detected, the system automatically switches back to the internal rc oscillator and a software interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 168 mhz. similarly, full interrupt management of the pll clock entry is available when necessary (for exam ple if an indirectly us ed external oscillator fails). several prescalers allow the configuration of the two ahb buses, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maximum frequency of the two ahb buses is 168 mhz while the maximum frequenc y of the high-speed apb domains is 84 mhz. the maximum allowed frequency of the low-speed apb domain is 42 mhz. the devices embed a dedicated pll (plli2s) which allows to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. 2.2.13 boot modes at startup, boot pins are used to select one out of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart3 (pc10/pc 11 or pb10/pb11), can2 (pb5/pb13), usb otg fs in device mode (pa11/pa12) through dfu (device firmware upgrade). 2.2.14 power supply schemes v dd = 1.8 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. v ssa , v dda = 1.8 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. refer to figure 18: power supply scheme for more details. note: v dd /v dda minimum value of 1.7 v is obtained when the device operates in the 0 to 70 c temperature range and an inverted reset signal is applied to pdr_on.
stm32f405xx, stm32f407xx description doc id 022152 rev 2 23/167 2.2.15 power supply supervisor the power supply supervisor is enabled by holding pdr_on high. the device has an integrated power-on reset (por) / power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitr y. at power-on, bor is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. all packages, except for the lqfp64 and lqfp100, have an internal reset controlled through the pdr_on signal. 2.2.16 voltage regulator the regulator has eight operating modes: regulator on/internal reset on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down regulator on/internal reset off ? main regulator mode (mr) ? low power regulator (lpr) ? power-down regulator off/internal reset on regulator off/internal reset off regulator on regulator on/internal reset on the regulator on/internal reset on mode is always enabled on lqfp64 and lqfp100 package. on lqfp144 package, this mode is activated by setting pdr_on to v dd . on ufbga176 package, the internal regulator must be activated by connecting bypass_reg to v ss, and pdr_on to v dd . on lqfp176 packages, the internal reset must be activated by connecting pdr_on to v dd .
description stm32f405xx, stm32f407xx 24/167 doc id 022152 rev 2 v dd minimum value is 1.8 v. v dd /v dda minimum value of 1.7 v is obtained when the device operates in the 0 to 70 c temperature range and pdr is disabled. there are three low-power modes: ? mr is used in the nominal regulation mode (run) ? lpr is used in the stop modes ? power-down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, indu cing zero consumption (but the contents of the registers and sram are lost). regulator on/internal reset off the regulator on with internal reset off mode is not available on lqfp64 and lqfp100 packages. on lqfp144, and lqfp176 packages, the internal reset is controlled by applying an inverted reset signal to pdr_on pin. on ufbga176 package, the internal regulator must be activated by connecting bypass_reg to v ss . on lqfp176 packages, the internal reset must be activated by applying an inverted reset signal to pdr_on pin. the nrst pin should be controlled by an external reset controller to keep the device under reset when v dd is below 1.8 v (see figure 7 ). figure 7. regulator on/internal reset off 6 $$ time -36 0$26 time .234 0$2?/.
stm32f405xx, stm32f407xx description doc id 022152 rev 2 25/167 regulator off this mode allows to power the device as soon as v dd reaches 1.8 v. regulator off/internal reset on this mode is available only on ufbga package. it is activated by setting bypass_reg and pdr_on pins to v dd . the regulator off/internal reset on mode allows to supply externally a 1.2 v voltage source through v cap_1 and v cap_2 pins, in addition to v dd . the following conditions must be respected: ?v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach 1.08 v is faster than the time for v dd to reach 1.8 v (v dd /v dda minimum value of 1.7 v is obtained when the device operates in the 0 to 70 c temperature range and pdr is disabled), then pa0 should be connected to the nrst pin (see figure 8 ). otherwise, pa0 should be asserted low externally during por until v dd reaches 1.8 v (see figure 9 ). ?if v cap_1 and v cap_2 go below 1.08 v and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. in regulator off/internal reset on mode, pa0 cannot be used as a gpio pin since it allows to reset the part of the 1.2 v logic which is not reset by the nrst pin, when the internal voltage regulator in off. regulator off/internal reset off this mode is available only on ufbga package. it is activated by setting bypass_reg pin to v dd and by applying an inverted reset signal to pdr_on, and allows to supply externally a 1.2 v voltage source through v cap_1 and v cap_2 pins, in addition to v dd . the following conditions must be respected: ?v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach 1.08 v and until v dd reaches 1.8 v (see figure 8 ). ? nrst should be controlled by an external reset controller to keep the device under reset when v dd is below 1.8 v (see figure 9 ).
description stm32f405xx, stm32f407xx 26/167 doc id 022152 rev 2 figure 8. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid both whatever the internal reset mode (on or off). figure 9. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid both whatever the internal reset mode (on or off). 2.2.17 real-time clock (rtc), backup sram and backup registers the backup domain of the stm32f405xx and stm32f407xx includes: the real-time clock (rtc) 4 kbytes of backup sram 20 backup registers the real-time clock (rtc) is an independent bcd timer/counter. dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in bcd (binary-coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. 6 $$ time 6 aic 0$26 6 #!0? 6 #!0? 6 0!tiedto.234 .234 time 6 $$ time 6 aib 0$26 6 #!0? 6 #!0? 6 0!assertedexternally .234 time
stm32f405xx, stm32f407xx description doc id 022152 rev 2 27/167 it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the intern al low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base clock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the 4-kbyte backup sram is an eeprom-like memory area. it can be used to store data which need to be retained in vbat and standby mode. this memory area is disabled by default to minimize power consumption (see section 2.2.18: low-power modes ). it can be enabled by software. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 2.2.18: low-power modes ). additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. like backup sram, the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin. 2.2.18 low-power modes the stm32f405xx and stm32f407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from the stop mode by any of the exti line (the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup). standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering
description stm32f405xx, stm32f407xx 28/167 doc id 022152 rev 2 standby mode, the sram and register contents are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm / wakeup / tamper /time stamp event occurs. note: when in standby mode, only an rtc alarm/event or an external reset can wake up the device provided v dd is supplied by an external battery. 2.2.19 v bat operation the v bat pin allows to power the device v bat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. 2.2.20 timers and watchdogs the stm32f405xx and stm32f407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. ta bl e 3 compares the features of the advanced-control, general-purpose and basic timers.
stm32f405xx, stm32f407xx description doc id 022152 rev 2 29/167 advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: input capture output compare pwm generation (edge- or center-aligned modes) one-pulse mode output if configured as standard 16-bit timers, they have the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the advanced-control timer can work together with the timx timers via the timer link feature for synchronization or event chaining. tim1 and tim8 support independent dma request generation. table 3. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary output max interface clock (mhz) max timer clock (mhz) advanced- control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s 8 4 1 6 8 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 42 84 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 42 84 tim9 16-bit up any integer between 1 and 65536 no 2 no 84 168 tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no 84 168 tim12 16-bit up any integer between 1 and 65536 no 2 no 42 84 tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no 42 84 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 42 84
description stm32f405xx, stm32f407xx 30/167 doc id 022152 rev 2 general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f40x devices (see ta b l e 3 for differences). tim2, tim3, tim4, tim5 the stm32f40x include 4 full-featured general-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they all feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. this gives up to 16 input capture/output compare/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers tim1 and tim8 via the timer link feature for synchr onization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have independent dma request generation. they are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. tim9, tim10, tim11, tim12, tim13, and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10, tim11, tim13, and tim14 feature one independent channel, whereas tim9 and tim12 have two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. tim6 and tim7 support independent dma request generation. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. window watchdog the window watchdog is based on a 7-bit downc ounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode.
stm32f405xx, stm32f407xx description doc id 022152 rev 2 31/167 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: a 24-bit downcounter autoreload capability maskable system interrupt generation when the counter reaches 0 programmable clock source. 2.2.21 inter-integrated circuit interface (i2c) up to three i2c bus interfaces can operate in multimaster and slave modes. they can support the standard- and fast-modes. they support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. 2.2.22 universal sync hronous/asynchronous receiver transmitters (usart) the stm32f405xx and stm32f407xx embed four universal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart6) and two universal asynchronous receiver transm itters (uart4 and uart5). these six interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usar t1 and usart6 interf aces are able to communicate at speeds of up to 10.5 mbit/s. the other available interfaces communicate at up to 5.25 bit/s. usart1, usart2, usart3 and usart6 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interfaces can be served by the dma controller.
description stm32f405xx, stm32f407xx 32/167 doc id 022152 rev 2 2.2.23 serial perip heral interface (spi) the stm32f40x feature up to three spis in slave and master modes in full-duplex and simplex communication modes. spi1 can communicate at up to 37.5 mbits/s, spi2 and spi3 can communicate at up to 21 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operate in ti mode for communications in master mode and slave mode. 2.2.24 inter-integrated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available. they can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. all i 2 sx can be served by the dma controller. table 4. usart feature comparison usart name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x x x x x 5.25 10.5 apb2 (max. 84 mhz) usart2 x x x x x x 2.62 5.25 apb1 (max. 42 mhz) usart3 x x x x x x 2.62 5.25 apb1 (max. 42 mhz) uart4 x - x - x - 2.62 5.25 apb1 (max. 42 mhz) uart5 x - x - x - 2.62 5.25 apb1 (max. 42 mhz) usart6 x x x x x x 5.25 10.5 apb2 (max. 84 mhz)
stm32f405xx, stm32f407xx description doc id 022152 rev 2 33/167 2.2.25 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s application. it allows to achieve error-free i 2 s sampling clock accuracy without compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i2s flow with an external pll (or codec output). 2.2.26 secure digital i nput/output inte rface (sdio) an sd/sdio/mmc host interface is availabl e, that supports mu ltimediacard system specification version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdio/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 2.2.27 ethernet mac interface with dedicated dma and ieee 1588 support peripheral available only on the stm32f407xx devices. the stm32f407xx devices provid e an ieee-802.3-2002-complia nt media access controller (mac) for ethernet lan communications through an industry-standard medium- independent interface (mii) or a reduced medium-independent interface (rmii). the stm32f407xx requires an external physical interface device (phy) to connect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connected to the stm32f407xx mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) from the stm32f407xx.
description stm32f405xx, stm32f407xx 34/167 doc id 022152 rev 2 the stm32f407xx includes the following features: supports 10 and 100 mbit/s rates dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors (see the stm32f46x reference manual for details) tagged mac frame support (vlan support) half-duplex (csma/cd) and full-duplex operation mac control sublayer (control frames) support 32-bit crc generation and removal several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes. supports hardware ptp (pre cision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp comparator connected to the tim2 input triggers interrupt when system time becomes greater than target time 2.2.28 controller ar ea network (bxcan) the two cans are compliant with the 2.0a and b (active) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can. 2.2.29 universal se rial bus on-the-go full-speed (otg_fs) the stm32f407xx embed an usb otg full-speed device/host/otg peripheral with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillator. the major features are: combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing supports the session request protocol (srp) and host negotiation protocol (hnp) 4 bidirectional endpoints 8 host channels with periodic out support hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.2.30 universal serial bu s on-the-go high-speed (otg_hs) the stm32f405xx and stm32f407xx devices embed a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed operation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (480 mb/s). when using the usb otg hs in hs mode, an external ph y device connected to the ulpi is required.
stm32f405xx, stm32f407xx description doc id 022152 rev 2 35/167 the usb otg hs peripheral is compliant with the usb 2.0 sp ecification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll co nnected to the hse oscillator. the major features are: combined rx and tx fifo size of 1 kbit 35 with dynamic fifo sizing supports the session request protocol (srp) and host negotiation protocol (hnp) 6 bidirectional endpoints 12 host channels with periodic out support internal fs otg phy support external hs or hs otg operation supporting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. internal usb dma hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.2.31 digital came ra interface (dcmi) the camera interface is not available in stm32f405xx devices. stm32f407xx products embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer rate up to 54 mbyte/s at 54 mhz. it features: programmable polarity for the input pixel clock and synchronization signals parallel data communication can be 8-, 10-, 12- or 14-bit supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) supports continuous mode or snapshot (a single frame) mode capability to automati cally crop the image 2.2.32 random num ber generator (rng) all stm32f405xx and stm32f407xx products embed an rng that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.33 general-purpose input/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or withou t pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allowing maximum i/o toggling up to 84 mhz.
description stm32f405xx, stm32f407xx 36/167 doc id 022152 rev 2 2.2.34 analog-to-digit al converters (adcs) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: simultaneous sample and hold interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4, tim5, or tim8 timer. 2.2.35 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.8 v and 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. as the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.36 digital-to-anal og converter (dac) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. this dual digital interface supports the following features: two dac converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channel independent or simultaneous conversions dma capability for each channel external triggers for conversion input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 2.2.37 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target.
stm32f405xx, stm32f407xx description doc id 022152 rev 2 37/167 debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.2.38 embedded trace macrocell? the arm embedded trace ma crocell provides a greater visib ility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f40x through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates with third party debugger software tools.
pinouts and pin description stm32f405xx, stm32f407xx 38/167 doc id 022152 rev 2 3 pinouts and pin description figure 10. stm32f40x lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6"!4 0# 0# .234 0# 0# 0# 0# 633! 6$$! 0! 0! 0! 6$$ 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! 6$$ 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 6#!0? 6$$ ,1&0 aib 0# 0( 0( 633
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 39/167 figure 11. stm32f40x lqfp100 pinout 0% 0% 0% 0% 0% 6"!4 0# 0# 633 6$$ 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$ 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! aib ,1&0 0# 0(
pinouts and pin description stm32f405xx, stm32f407xx 40/167 doc id 022152 rev 2 figure 12. stm32f40x lqfp144 pinout 6 $$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6 $$ 6 33 0' 0' 0' 0' 0' 0' 0$ 0$ 6 $$ 6 33 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 0% 6 $$ 0% 6 33 0% 0% 0! 0% 0! 6"!4 0! 0# 0! 0# 0! 0# 0! 0& 0# 0& 0# 0& 0# 0& 0# 0& 6 $$ 0& 6 33 6 33 0' 6 $$ 0' 0& 0' 0& 0' 0& 0' 0& 0' 0& 0' 0( 0$ 0( 0$ .234 6 $$ 0# 6 33 0# 0$ 0# 0$ 0# 0$ 6 33! 0$ 6 $$ 0$ 6 2%& 0$ 6 $$! 0" 0! 0" 0! 0" 0! 0" 0! 6 33 6 $$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 6 $$ 0& 0& 0& 0' 0' 0% 0% 0% 6 33 6 $$ 0% 0% 0% 0% 0% 0% 0" 0" 6 #!0? 6 $$ ,1&0 aib 6 #!0? 6 33
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 41/167 figure 13. stm32f40x lqfp176 pinout -36 0$2?/. 6 $$ 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6 $$ 6 33 0' 0' 0' 0' 0' 0' 0$ 0$ 6 $$ 6 33 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0) 0) 0% 6 $$ 0% 6 33 0% 0% 0! 0% 0! 6"!4 0! 0) 0! 0# 0! 0#4 0! 0& 0# 0& 0# 0& 0# 0& 0# 0& 6 $$ 0& 6 33 6 33 0' 6 $$ 0' 0& 0' 0& 0' 0& 0' 0& 0' 0& 0' 0( 0$ 0( 0$ .234 6 $$ 0# 6 33 0# 0$ 0# 0$ 0# 0$ 6 33! 0$ 6 $$ 0$ 6 2%& 0$ 6 $$! 0" 0! 0" 0! 0" 0! 0" 0! 6 33 6 $$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6 $$ 0& 0& 0& 0' 0' 0% 0% 0% 6 33 6 $$ 0% 0% 0% 0% 0% 0% 0" 0" 6 #!0? 6 $$ ,1&0 6 #!0? 0) 0! 0! 6 $$ 6 33 0) 0) 0) 0( 0( 0( 0( 0( 0( 0( 0( 0) 0) 0( 0( 0( 6 $$ 6 33 0( 0# 0) 0) 0) 6 33 6 $$ 0( 0(
pinouts and pin description stm32f405xx, stm32f407xx 42/167 doc id 022152 rev 2 figure 14. stm32f40x ufbga176 ballout aib ! 0% 0% 0% 0% 0" 0" 0' 0' 0" 0" 0$ 0# 0! 0! 0! " 0% 0% 0% 0" 0" 0" 0'0'0'0' 0$ 0$ 0#0#0! #6"!4 0) 0) 0) 0$2?/. 6$$ 6$$ 6$$ 6$$ 0' 0$ 0$ 0) 0) 0! $ 0# 0) 0) 0) "//4 633 633 633 0$ 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0( 0( 0) 0! & 0# 633 6$$ 0( 633 633 633 633 633 633 6#!0? 0# 0! ' 0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0# ( 0( 0& 0& 0( 633 633 633 633 633 633 6$$ 0' 0# * .234 0& 0& 0( 633 633 633 633 633 6$$ 6$$ 0' 0' +0& 0& 0& 6$$ 633 633 633 633 633 0( 0' 0' 0' ,0& 0& 0& "90!33? 2%' 0( 0( 0$ 0' - 633! 0# 0# 0# 0# 0" 0' 633 633 6#!0? 0( 0( 0( 0$ 0$ .62%& 0! 0! 0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$ 0 62%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$ 2 6$$! 0! 0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0" 633 table 5. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 43/167 alternate functions functions selected throug h gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers table 5. legend/abbreviations used in the pinout table (continued) name abbreviation definition
pinouts and pin description stm32f405xx, stm32f407xx 44/167 doc id 022152 rev 2 table 6. stm32f40x pin and ball definitions pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176 - 1 1 a2 1 pe2 i/o ft traceclk/ fsmc_a23 / eth_mii_txd3 / eventout - 2 2 a1 2 pe3 i/o ft traced0/fsmc_a19 / eventout - 3 3 b1 3 pe4 i/o ft traced1/fsmc_a20 / dcmi_d4/ eventout - 4 4 b2 4 pe5 i/o ft traced2 / fsmc_a21 / tim9_ch1 / dcmi_d6 / eventout - 5 5 b3 5 pe6 i/o ft traced3 / fsmc_a22 / tim9_ch2 / dcmi_d7 / eventout 16 6c16 v bat s -- -d27 pi8 i/oft (2)(3) eventout rtc_af2 27 7d18 pc13 i/oft (2)(3) eventout rtc_af1 38 8e19 pc14-osc32_in (pc14) i/o ft (2)(3) eventout osc32_in (4) 49 9 f110 pc15- osc32_out (pc15) i/o ft (2)(3) eventout osc32_out (4) - - - d3 11 pi9 i/o ft can1_rx / eventout -- -e312 pi10 i/oft eth_mii_rx_er / eventout -- -e413 pi11 i/oft otg_hs_ulpi_dir / eventout -- -f214 v ss s -- -f315 v dd s - - 10 e2 16 pf0 i/o ft fsmc_a0 / i2c2_sda / eventout --11h317 pf1 i/oft fsmc_a1 / i2c2_scl / eventout --12h218 pf2 i/oft fsmc_a2 / i2c2_smba / eventout --13j219 pf3 i/oft (4) fsmc_a3/eventout adc3_in9 --14j320 pf4 i/oft (4) fsmc_a4/eventout adc3_in14 - - 15 k3 21 pf5 i/o ft (4) fsmc_a5/eventout adc3_in15
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 45/167 -1016g222 v ss s -1117g323 v dd s - - 18 k2 24 pf6 i/o ft (4) tim10_ch1 / fsmc_niord/ eventout adc3_in4 - - 19 k1 25 pf7 i/o ft (4) tim11_ch1/fsmc_nreg/ eventout adc3_in5 - - 20 l3 26 pf8 i/o ft (4) tim13_ch1 / fsmc_niowr/ eventout adc3_in6 - - 21 l2 27 pf9 i/o ft (4) tim14_ch1 / fsmc_cd/ eventout adc3_in7 - - 22 l1 28 pf10 i/o ft (4) fsmc_intr/ eventout adc3_in8 51223g129 ph0-osc_in (ph0) i/o ft eventout osc_in (4) 61324h130 ph1-osc_out (ph1) i/o ft eventout osc_out (4) 7 14 25 j1 31 nrst i/o rst 81526m232 pc0 i/oft (4) otg_hs_ulpi_stp/ eventout adc123_in10 91627m333 pc1 i/oft (4) eth_mdc/ eventout adc123_in11 10 17 28 m4 34 pc2 i/o ft (4) spi2_miso / otg_hs_ulpi_dir / th_mii_txd2 /i2s2ext_sd/ eventout adc123_in12 11 18 29 m5 35 pc3 i/o ft (4) spi2_mosi / i2s2_sd / otg_hs_ulpi_nxt / eth_mii_tx_clk / eventout adc123_in13 -1930g336 v dd s 12 20 31 m1 37 v ssa s -- -n1- v ref ? s -2132p138 v ref+ s 13 22 33 r1 39 v dda s table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f405xx, stm32f407xx 46/167 doc id 022152 rev 2 14 23 34 n3 40 pa 0 - w k u p (pa0) i/o ft (5) usart2_cts/ uart4_tx/ eth_mii_crs / tim2_ch1_etr/ tim5_ch1 / tim8_etr/ eventout adc123_in0/wkup (4) 15 24 35 n2 41 pa1 i/o ft (4) usart2_rts / uart4_rx/ eth_rmii_ref_clk / eth_mii_rx_clk / tim5_ch2 / timm2_ch2/ eventout adc123_in1 16 25 36 p2 42 pa2 i/o ft (4) usart2_tx/tim5_ch3 / tim9_ch1 / tim2_ch3 / eth_mdio/ eventout adc123_in2 - - - f4 43 ph2 i/o ft eth_mii_crs/eventout - - - g4 44 ph3 i/o ft eth_mii_col/eventout -- -h445 ph4 i/oft i2c2_scl / otg_hs_ulpi_nxt/ eventout - - - j4 46 ph5 i/o ft i2c2_sda/ eventout 17 26 37 r2 47 pa3 i/o ft (4) usart2_rx/tim5_ch4 / tim9_ch2 / tim2_ch4 / otg_hs_ulpi_d0 / eth_mii_col/ eventout adc123_in3 18 27 38 - 48 v ss s l4 - bypass_reg i ft 19 28 39 k4 49 v dd s 20 29 40 n4 50 pa4 i/o tta (4) spi1_nss / spi3_nss / usart2_ck / dcmi_hsync / otg_hs_sof/ i2s3_ws/ eventout adc12_in4 /dac1_out 21 30 41 p4 51 pa5 i/o tta (4) spi1_sck/ otg_hs_ulpi_ck / tim2_ch1_etr/ tim8_chin/ eventout adc12_in5/dac2_out 22 31 42 p3 52 pa6 i/o ft (4) spi1_miso / tim8_bkin/tim13_ch1 / dcmi_pixclk / tim3_ch1 / tim1_bkin / eventout adc12_in6 table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 47/167 23 32 43 r3 53 pa7 i/o ft (4) spi1_mosi/ tim8_ch1n / tim14_ch1/tim3_ch2/ eth_mii_rx_dv / tim1_ch1n / rmii_crs_dv/ eventout adc12_in7 24 33 44 n5 54 pc4 i/o ft (4) eth_rmii_rx_d0 / eth_mii_rx_d0/ eventout adc12_in14 25 34 45 p5 55 pc5 i/o ft (4) eth_rmii_rx_d1 / eth_mii_rx_d1/ eventout adc12_in15 26 35 46 r5 56 pb0 i/o ft (4) tim3_ch3 / tim8_ch2n/ otg_hs_ulpi_d1/ eth_mii_rxd2 / tim1_ch2n/ eventout adc12_in8 27 36 47 r4 57 pb1 i/o ft (4) tim3_ch4 / tim8_ch3n/ otg_hs_ulpi_d2/ eth_mii_rxd3 / otg_hs_intn / tim1_ch3n/ eventout adc12_in9 28 37 48 m6 58 pb2-boot1 (pb2) i/o ft eventout - - 49 r6 59 pf11 i/o ft dcmi_12/ eventout - - 50 p6 60 pf12 i/o ft fsmc_a6/ eventout --51m861 v ss s --52n862 v dd s - - 53 n6 63 pf13 i/o ft fsmc_a7/ eventout - - 54 r7 64 pf14 i/o ft fsmc_a8/ eventout - - 55 p7 65 pf15 i/o ft fsmc_a9/ eventout - - 56 n7 66 pg0 i/o ft fsmc_a10/ eventout - - 57 m7 67 pg1 i/o ft fsmc_a11/ eventout - 38 58 r8 68 pe7 i/o ft fsmc_d4/tim1_etr/ eventout - 39 59 p8 69 pe8 i/o ft fsmc_d5/ tim1_ch1n/ eventout - 40 60 p9 70 pe9 i/o ft fsmc_d6/tim1_ch1/ eventout --61m971 v ss s table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f405xx, stm32f407xx 48/167 doc id 022152 rev 2 --62n972 v dd s - 41 63 r9 73 pe10 i/o ft fsmc_d7/tim1_ch2n/ eventout - 42 64 p10 74 pe11 i/o ft fsmc_d8/tim1_ch2/ eventout - 43 65 r10 75 pe12 i/o ft fsmc_d9/tim1_ch3n/ eventout - 44 66 n11 76 pe13 i/o ft fsmc_d10/tim1_ch3/ eventout - 45 67 p11 77 pe14 i/o ft fsmc_d11/tim1_ch4/ eventout - 46 68 r11 78 pe15 i/o ft fsmc_d12/tim1_bkin/ eventout 29 47 69 r12 79 pb10 i/o ft spi2_sck / i2s2_ck / i2c2_scl/ usart3_tx / otg_hs_ulpi_d3 / eth_mii_rx_er / tim2_ch3/ eventout 30 48 70 r13 80 pb11 i/o ft i2c2_sda/usart3_rx/ otg_hs_ulpi_d4 / eth_rmii_tx_en/ eth_mii_tx_en / tim2_ch4/ eventout 31 49 71 m10 81 v cap_1 s 32 50 72 n10 82 v dd s - - - m11 83 ph6 i/o ft i2c2_smba / tim12_ch1 / eth_mii_rxd2/ eventout -- -n1284 ph7 i/oft i2c3_scl / eth_mii_rxd3/ eventout - - - m12 85 ph8 i/o ft i2c3_sda / dcmi_hsync/ eventout - - - m13 86 ph9 i/o ft i2c3_smba / tim12_ch2/ dcmi_d0/ eventout - - - l13 87 ph10 i/o ft tim5_ch1 / dcmi_d1/ eventout - - - l12 88 ph11 i/o ft tim5_ch2 / dcmi_d2/ eventout table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 49/167 - - - k12 89 ph12 i/o ft tim5_ch3 / dcmi_d3/ eventout -- -h1290 v ss s - - - j12 91 v dd s 33 51 73 p12 92 pb12 i/o ft spi2_nss / i2s2_ws / i2c2_smba/ usart3_ck/ tim1_bkin / can2_rx / otg_hs_ulpi_d5/ eth_rmii_txd0 / eth_mii_txd0/ otg_hs_id/ eventout 34 52 74 p13 93 pb13 i/o ft spi2_sck / i2s2_ck / usart3_cts/ tim1_ch1n /can2_tx / otg_hs_ulpi_d6 / eth_rmii_txd1 / eth_mii_txd1/ eventout otg_hs_vbus 35 53 75 r14 94 pb14 i/o ft spi2_miso/ tim1_ch2n / tim12_ch1 / otg_hs_dm/ usart3_rts / tim8_ch2n/i2s2ext_sd/ eventout 36 54 76 r15 95 pb15 i/o ft spi2_mosi / i2s2_sd/ tim1_ch3n / tim8_ch3n / tim12_ch2 / otg_hs_dp/ eventout -5577p1596 pd8 i/oft fsmc_d13 / usart3_tx/ eventout -5678p1497 pd9 i/oft fsmc_d14 / usart3_rx/ eventout - 57 79 n15 98 pd10 i/o ft fsmc_d15 / usart3_ck/ eventout - 58 80 n14 99 pd11 i/o ft fsmc_cle / fsmc_a16/usart3_cts/ eventout - 59 81 n13 100 pd12 i/o ft fsmc_ale/ fsmc_a17/tim4_ch1 / usart3_rts/ eventout table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f405xx, stm32f407xx 50/167 doc id 022152 rev 2 - 60 82 m15 101 pd13 i/o ft fsmc_a18/tim4_ch2/ eventout - - 83 - 102 v ss s - - 84 j13 103 v dd s - 61 85 m14 104 pd14 i/o ft fsmc_d0/tim4_ch3/ eventout/ eventout - 62 86 l14 105 pd15 i/o ft fsmc_d1/tim4_ch4/ eventout - - 87 l15 106 pg2 i/o ft fsmc_a12/ eventout - - 88 k15 107 pg3 i/o ft fsmc_a13/ eventout - - 89 k14 108 pg4 i/o ft fsmc_a14/ eventout - - 90 k13 109 pg5 i/o ft fsmc_a15/ eventout - - 91 j15 110 pg6 i/o ft fsmc_int2/ eventout - - 92 j14 111 pg7 i/o ft fsmc_int3 /usart6_ck/ eventout - - 93 h14 112 pg8 i/o ft usart6_rts / eth_pps_out/ eventout - - 94 g12 113 v ss s - - 95 h13 114 v dd s 37 63 96 h15 115 pc6 i/o ft i2s2_mck / tim8_ch1/sdio_d6 / usart6_tx / dcmi_d0/tim3_ch1/ eventout 38 64 97 g15 116 pc7 i/o ft i2s3_mck / tim8_ch2/sdio_d7 / usart6_rx / dcmi_d1/tim3_ch2/ eventout 39 65 98 g14 117 pc8 i/o ft tim8_ch3/sdio_d0 /tim3_ch3/ usart6_ck / dcmi_d2/ eventout 40 66 99 f14 118 pc9 i/o ft i2s_ckin/ mco2 / tim8_ch4/sdio_d1 / /i2c3_sda / dcmi_d3 / tim3_ch4/ eventout table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 51/167 41 67 100 f15 119 pa8 i/o ft mco1 / usart1_ck/ tim1_ch1/ i2c3_scl/ otg_fs_sof/ eventout 42 68 101 e15 120 pa9 i/o ft usart1_tx/ tim1_ch2 / i2c3_smba / dcmi_d0/ eventout otg_fs_vbus 43 69 102 d15 121 pa10 i/o ft usart1_rx/ tim1_ch3/ otg_fs_id/dcmi_d1/ eventout 44 70 103 c15 122 pa11 i/o ft usart1_cts / can1_rx / tim1_ch4 / otg_fs_dm/ eventout 45 71 104 b15 123 pa12 i/o ft usart1_rts / can1_tx/ tim1_etr/ otg_fs_dp/ eventout 46 72 105 a15 124 pa 1 (jtms-swdio) i/o ft jtms-swdio/ eventout 47 73 106 f13 125 v cap_2 s - 74 107 f12 126 v ss s 48 75 108 g13 127 v dd s - - - e12 128 ph13 i/o ft tim8_ch1n / can1_tx/ eventout - - - e13 129 ph14 i/o ft tim8_ch2n / dcmi_d4/ eventout - - - d13 130 ph15 i/o ft tim8_ch3n / dcmi_d11/ eventout - - - e14 131 pi0 i/o ft tim5_ch4 / spi2_nss / i2s2_ws / dcmi_d13/ eventout - - - d14 132 pi1 i/o ft spi2_sck / i2s2_ck / dcmi_d8/ eventout - - - c14 133 pi2 i/o ft tim8_ch4 /spi2_miso / dcmi_d9 / i2s2ext_sd/ eventout - - - c13 134 pi3 i/o ft tim8_etr / spi2_mosi / i2s2_sd / dcmi_d10/ eventout - - - d9 135 v ss s - - - c9 136 v dd s table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f405xx, stm32f407xx 52/167 doc id 022152 rev 2 49 76 109 a14 137 pa 1 4 (jtck-swclk) i/o ft jtck-swclk/ eventout 50 77 110 a13 138 pa 1 5 (jtdi) i/o ft jtdi/ spi3_nss/ i2s3_ws/tim2_ch1_etr / spi1_nss / eventout 51 78 111 b14 139 pc10 i/o ft spi3_sck / i2s3_ck/ uart4_tx/sdio_d2 / dcmi_d8 / usart3_tx/ eventout 52 79 112 b13 140 pc11 i/o ft uart4_rx/ spi3_miso / sdio_d3 / dcmi_d4/usart3_rx / i2s3ext_sd/ eventout 53 80 113 a12 141 pc12 i/o ft uart5_tx/sdio_ck / dcmi_d9 / spi3_mosi /i2s3_sd / usart3_ck/ eventout - 81 114 b12 142 pd0 i/o ft fsmc_d2/can1_rx/ eventout - 82 115 c12 143 pd1 i/o ft fsmc_d3 / can1_tx/ eventout 54 83 116 d12 144 pd2 i/o ft tim3_etr/uart5_rx/ sdio_cmd / dcmi_d11/ eventout - 84 117 d11 145 pd3 i/o ft fsmc_clk/usart2_cts / eventout - 85 118 d10 146 pd4 i/o ft fsmc_noe/usart2_rts / eventout - 86 119 c11 147 pd5 i/o ft fsmc_nwe/usart2_tx/ eventout - - 120d8148 v ss s - - 121c8149 v dd s - 87 122 b11 150 pd6 i/o ft fsmc_nwait/ usart2_rx/ eventout - 88 123 a11 151 pd7 i/o ft usart2_ck/fsmc_ne1/ fsmc_nce2/ eventout - - 124 c10 152 pg9 i/o ft usart6_rx / fsmc_ne2/fsmc_nce3/ eventout table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 53/167 - - 125 b10 153 pg10 i/o ft fsmc_nce4_1/ fsmc_ne3/ eventout - - 126 b9 154 pg11 i/o ft fsmc_nce4_2 / eth_mii_tx_en/ eth _rmii_tx_en/ eventout - - 127 b8 155 pg12 i/o ft fsmc_ne4 / usart6_rts/ eventout - - 128 a8 156 pg13 i/o ft fsmc_a24 / usart6_cts /eth_mii_txd0/ eth_rmii_txd0/ eventout - - 129 a7 157 pg14 i/o ft fsmc_a25 / usart6_tx /eth_mii_txd1/ eth_rmii_txd1/ eventout - - 130d7158 v ss s - - 131c7159 v dd s - - 132 b7 160 pg15 i/o ft usart6_cts / dcmi_d13/ eventout 55 89 133 a10 161 pb3 (jtdo/ traceswo) i/o ft jtdo/ traceswo/ spi3_sck / i2s3_ck / tim2_ch2 / spi1_sck/ eventout 56 90 134 a9 162 pb4 (njtrst) i/o ft njtrst/ spi3_miso / tim3_ch1 / spi1_miso / i2s3ext_sd/ eventout 57 91 135 a6 163 pb5 i/o ft i2c1_smba/ can2_rx / otg_hs_ulpi_d7 / eth_pps_out/tim3_ch 2 / spi1_mosi/ spi3_mosi / dcmi_d10 / i2s3_sd/ eventout 58 92 136 b6 164 pb6 i/o ft i2c1_scl/ tim4_ch1 / can2_tx / dcmi_d5/usart1_tx/ eventout table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f405xx, stm32f407xx 54/167 doc id 022152 rev 2 59 93 137 b5 165 pb7 i/o ft i2c1_sda / fsmc_nl / dcmi_vsync / usart1_rx/ tim4_ch2/ eventout 60 94 138 d6 166 boot0 i b v pp 61 95 139 a5 167 pb8 i/o ft tim4_ch3/sdio_d4/ tim10_ch1 / dcmi_d6 / eth_mii_txd3 / i2c1_scl/ can1_rx/ eventout 62 96 140 b4 168 pb9 i/o ft spi2_nss/ i2s2_ws / tim4_ch4/ tim11_ch1/ sdio_d5 / dcmi_d7 / i2c1_sda / can1_tx/ eventout - 97 141 a4 169 pe0 i/o ft tim4_etr / fsmc_nbl0 / dcmi_d2/ eventout - 98 142 a3 170 pe1 i/o ft fsmc_nbl1 / dcmi_d3/ eventout 63 99 - d5 - v ss s - - 143c6171 pdr_on i ft 64 10 0 144c5172 v dd s - - - d4 173 pi4 i/o ft tim8_bkin / dcmi_d5/ eventout - - - c4 174 pi5 i/o ft tim8_ch1 / dcmi_vsync/ eventout - - - c3 175 pi6 i/o ft tim8_ch2 / dcmi_d6/ eventout - - - c2 176 pi7 i/o ft tim8_ch3 / dcmi_d7/ eventout 1. function availability depends on the chosen device. 2. pc13, pc14, pc15 and pi8 are supplied through the power switch . since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a cu rrent source (e.g. to drive an led). 3. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main rese t). for details on how to manage these i/os, refer to the rtc register description secti ons in the stm32f4xx reference manual, avai lable from the stmicr oelectronics website: www.st.com. 4. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc 14, pc15, ph0 and ph1). table 6. stm32f40x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp64 lqfp100 lqfp144 ufbga176 lqfp176
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 55/167 5. if the device is delivered in an ufbga176 and the bypass_re g pin is set to vdd (regulator off/internal reset on mode), then pa0 is used as an internal reset (active low).
pinouts and pin description stm32f405xx, stm32f407xx 56/167 doc id 022152 rev 2 table 7. alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi pa 0 tim2_ch1 tim2_etr tim 5_ch1 tim8_etr usart2_cts uart4_tx eth_mii_crs eventout pa1 tim2_ch2 tim5_ch2 usart2_rts uart4_rx eth_mii _rx_clk eth_rmii _ref_clk eventout pa2 tim2_ch3 tim5_ch3 tim9_c h1 usart2_tx eth_mdio eventout pa3 tim2_ch4 tim5_ch4 tim9_ch2 usart2_rx otg_hs_ulpi_d0 eth _mii_col eventout pa 4 spi1_nss spi3_nss i2s3_ws usart2_ck otg_hs_sof dcmi_hsync eventout pa 5 tim2_ch1 tim2_etr tim8_ch1n spi1_sck otg_hs_ulpi_ck eventout pa6 tim1_bkin tim3_ch1 tim8_bkin spi1_miso tim13_ch1 dcmi_pixck eventout pa7 tim1_ch1n tim3_ch2 tim8_ch1n spi1_mosi tim14_ch1 eth_mii _rx_dv eth_rmii _crs_dv eventout pa8 mco1 tim1_ch1 i2c3_scl usart1_ck otg_fs_sof eventout pa9 tim1_ch2 i2c3_smba usart1_tx dcmi_d0 eventout pa10 tim1_ch3 usart1_rx otg_fs_id dcmi_d1 eventout pa11 tim1_ch4 usart1_cts can1_rx otg_fs_dm eventout pa12 tim1_etr usart1_rts can1_tx otg_fs_dp eventout pa 1 3 j t m s - s w d i o eventout pa14 jtck-swclk eventout pa 1 5 j t d i tim 2_ch1 tim 2_etr spi1_nss spi3_nss/ i2s3s_ws eventout pb0 tim1_ch2n tim3_ch3 tim8_ch2n otg_hs_ulpi_d1 eth _mii_rxd2 eventout pb1 tim1_ch3n tim3_ch4 tim8_ch3n otg_hs_ulpi_d2 eth _mii_rxd3 otg_hs_intn eventout pb2 eventout pb3 jtdo/ traceswo tim2_ch2 spi1_sck spi3_sck i2s3_ck eventout pb4 jtrst tim3_ch1 spi1_miso spi3_miso i2s3ext_sd eventout pb5 tim3_ch2 i2c1_smba spi1_mosi spi3_mosi i2s3_sd can2_rx otg_hs_ulpi_d7 eth _pps_out dcmi_d10 eventout pb6 tim4_ch1 i2c1_scl i2s2_ws u sart1_tx can2_tx dcmi_d5 eventout pb7 tim4_ch2 i2c1_sda usart1_rx fsmc_nl dcmi_vsync eventout pb8 tim4_ch3 tim10_ch1 i2c1_scl can1_rx eth _mii_txd3 sdio_d4 dcmi_d6 eventout pb9 tim4_ch4 tim11_ch1 i2c1_sda spi2_nss i2s2_ws can1_tx sdio_d5 dcmi_d7 eventout pb10 tim2_ch3 i2c2_scl spi2_sck i2s2_ck usart3_tx otg_hs_ulpi_d3 eth_ mii_rx_er eventout pb11 tim2_ch4 i2c2_sda usart3_rx otg_hs_ulpi_d4 eth _mii_tx_en eth _rmii_tx_en eventout pb12 tim1_bkin i2c2_smba spi2_nss i2s2_ws usart3_ck can2_rx otg_hs_ulpi_d5 eth _mii_txd0 eth _rmii_txd0 otg_hs_id eventout pb13 tim1_ch1n spi2_sck i2s2_ck usart3_cts can2_tx otg_hs_ulpi_d6 eth _mii_txd1 eth _rmii_txd1 eventout pb14 tim1_ch2n tim8_ch2n spi2_miso i2s2ext_sd usart3_rts tim12_ch1 otg_hs_dm eventout
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 57/167 pb15 rtc_50hz tim1_ch3n tim8_ch3n spi2_mosi i2s2_sd tim12_ch2 otg_hs_dp eventout pc0 otg_hs_ulpi_stp eventout pc1 eth_mdc eventout pc2 spi2_miso i2s2ext_sd otg_hs_ulpi_dir eth _mii_txd2 eventout pc3 spi2_mosi i2s2_sd otg_hs_ulpi_nxt eth _mii_tx_clk eth _rmii_tx_clk eventout pc4 eth_mii_rxd0 eth_rmii_rxd0 eventout pc5 eth _mii_rxd1 eth _rmii_rxd1 eventout pc6 tim3_ch1 tim8_ch1 i2s2_mck usart6_tx sdio_d6 dcmi_d0 eventout pc7 tim3_ch2 tim8_ch2 i2s3_mck usart6_rx sdio_d7 dcmi_d1 eventout pc8 tim3_ch3 tim8_ch3 usart6_ck sdio_d0 dcmi_d2 eventout pc9 mco2 tim3_ch4 tim8_ch4 i2c3_sda i2s_ckin sdio_d1 dcmi_d3 eventout pc10 spi3_sck/ i2s3s_ck usart3_tx/ uart4_tx sdio_d2 dcmi_d8 eventout pc11 spi3_miso i2s3ext_sd/ usart3_rx uart4_rx sdio_d3 dcmi_d4 eventout pc12 spi3_mosi i2s3_sd usart3_ck uart5_tx sdio_ck dcmi_d9 eventout pc13 pc14 pc15 pd0 can1_rx fsmc_d2 eventout pd1 can1_tx fsmc_d3 eventout pd2 tim3_etr uart5_rx sdio_cmd dcmi_d11 eventout pd3 usart2_cts fsmc_clk eventout pd4 usart2_rts fsmc_noe eventout pd5 usart2_tx fsmc_nwe eventout pd6 usart2_rx fsmc_nwait eventout pd7 usart2_ck fsmc_ne1/ fsmc_nce2 eventout pd8 usart3_tx fsmc_d13 eventout pd9 usart3_rx fsmc_d14 eventout pd10 usart3_ck fsmc_d15 eventout pd11 usart3_cts fsmc_a16 eventout pd12 tim4_ch1 usart3_rts fsmc_a17 eventout pd13 tim4_ch2 fsmc_a18 eventout pd14 tim4_ch3 fsmc_d0 eventout table 7. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
pinouts and pin description stm32f405xx, stm32f407xx 58/167 doc id 022152 rev 2 pd15 tim4_ch4 fsmc_d1 eventout pe0 tim4_etr fsmc_nbl0 dcmi_d2 eventout pe1 fsmc_bln1 dcmi_d3 eventout pe2 traceclk eth _mii_txd3 fsmc_a23 eventout pe3 traced0 fsmc_a19 eventout pe4 traced1 fsmc_a20 dcmi_d4 eventout pe5 traced2 tim9_ch1 fsmc_a21 dcmi_d6 eventout pe6 traced3 tim9_ch2 fsmc_a22 dcmi_d7 eventout pe7 tim1_etr fsmc_d4 eventout pe8 tim1_ch1n fsmc_d5 eventout pe9 tim1_ch1 fsmc_d6 eventout pe10 tim1_ch2n fsmc_d7 eventout pe11 tim1_ch2 fsmc_d8 eventout pe12 tim1_ch3n fsmc_d9 eventout pe13 tim1_ch3 fsmc_d10 eventout pe14 tim1_ch4 fsmc_d11 eventout pe15 tim1_bkin fsmc_d12 eventout pf0 i2c2_sda fsmc_a0 eventout pf1 i2c2_scl fsmc_a1 eventout pf2 i2c2_smba fsmc_a2 eventout pf3 fsmc_a3 eventout pf4 fsmc_a4 eventout pf5 fsmc_a5 eventout pf6 tim10_ch1 fsmc_niord eventout pf7 tim11_ch1 fsmc_nreg eventout pf8 tim13_ch1 fsmc_niowr eventout pf9 tim14_ch1 fsmc_cd eventout pf10 fsmc_intr eventout pf11 dcmi_d12 eventout pf12 fsmc_a6 eventout pf13 fsmc_a7 eventout pf14 fsmc_a8 eventout pf15 fsmc_a9 eventout table 7. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
stm32f405xx, stm32f407xx pinouts and pin description doc id 022152 rev 2 59/167 pg0 fsmc_a10 eventout pg1 fsmc_a11 eventout pg2 fsmc_a12 eventout pg3 fsmc_a13 eventout pg4 fsmc_a14 eventout pg5 fsmc_a15 eventout pg6 fsmc_int2 eventout pg7 usart6_ck fsmc_int3 eventout pg8 usart6_rts eth _pps_out eventout pg9 usart6_rx fsmc_ne2/ fsmc_nce3 eventout pg10 fsmc_nce4_1/ fsmc_ne3 eventout pg11 eth _mii_tx_en eth _rmii_tx_en fsmc_nce4_2 eventout pg12 usart6_rts fsmc_ne4 eventout pg13 uart6_cts eth _mii_txd0 eth _rmii_txd0 fsmc_a24 eventout pg14 usart6_tx eth _mii_txd1 eth _rmii_txd1 fsmc_a25 eventout pg15 usart6_cts dcmi_d13 eventout ph0 ph1 ph2 eth _mii_crs eventout ph3 eth _mii_col eventout ph4 i2c2_scl otg_hs_ulpi_nxt eventout ph5 i2c2_sda eventout ph6 i2c2_smba tim12_ch1 eth _mii_rxd2 eventout ph7 i2c3_scl eth _mii_rxd3 eventout ph8 i2c3_sda dcmi_hsync eventout ph9 i2c3_smba tim12_ch2 dcmi_d0 eventout ph10 tim5_ch1 dcmi_d1 eventout ph11 tim5_ch2 dcmi_d2 eventout ph12 tim5_ch3 dcmi_d3 eventout ph13 tim8_ch1n can1_tx eventout ph14 tim8_ch2n dcmi_d4 eventout table 7. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
pinouts and pin description stm32f405xx, stm32f407xx 60/167 doc id 022152 rev 2 ph15 tim8_ch3n dcmi_d11 eventout pi0 tim5_ch4 spi2_nss i2s2_ws dcmi_d13 eventout pi1 spi2_sck i2s2_ck dcmi_d8 eventout pi2 tim8_ch4 spi2_miso i2s2ext_sd dcmi_d9 eventout pi3 tim8_etr spi2_mosi i2s2_sd dcmi_d10 eventout pi4 tim8_bkin dcmi_d5 eventout pi5 tim8_ch1 dcmi_vsync eventout pi6 tim8_ch2 dcmi_d6 eventout pi7 tim8_ch3 dcmi_d7 eventout pi8 pi9 can1_rx eventout pi10 eth _mii_rx_er eventout pi11 otg_hs_ulpi_dir eventout table 7. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af014 af15 sys tim1/2 tim3/4/5 tim8/9/10/11 i2c1/2/3 spi1/spi2/ i2s2/i2s2ext spi3/i2sext/ i2s3 usart1/2/3/ i2s3ext uart4/5/ usart6 can1/can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
stm32f405xx, stm32f407xx memory map doc id 022152 rev 2 61/167 4 memory map the memory map is shown in figure 15 . figure 15. memory map -byte block #ortex -gs internal peripherals -byte block .otused -byte block &3-#registers -byte block &3-#bank bank -byte block &3-#bank bank -byte block 0eripherals -byte block 32!- x x&&&&&&& x x&&&&&&& x x&&&&&&& x x&&&&&&& x x&&&&&&& x! x"&&&&&&& x# x$&&&&&&& x% x&&&&&&&& -byte block #ode &lash x x&&&&&&& x&&& x&&&!& x&&&# x&&&# x x&&&&& x x&&&&&& x x&&&&& 3ystemmemory 2eserved 2eserved !liasedto&lashsystem memoryor32!-depending onthe"//4pins 32!-+"aliased bybit banding 2eserved x x"&&& x# x&&&& x x&&&&&&& !0" x 2eserved x&& x x&& x 2eserved x&& x x&&&& x x&& 2eserved x x&& x x"&& x x"&& x 2esetclockcontroller2## x&& 2eserved x x&&& #2# x x&& 2eserved x# x&&&&&&& x !(" x!&&& x! x"&&&&&&& -36 /ption"ytes 393#&' 2eserved x# x&&&& %84) x# x&&& x&& !(" x 2eserved x&& !(" x&&&& x x&&&&&&& 2eserved x x&&&& !(" x# x x"&& 2eserved x x&& !(" 32!-+"aliased bybit banding 2eserved x&&&# x&&&&&&& x&&&! x&&&&&& 2eserved ##-data2!- +"data32!- x x&&&& 2eserved x x&&%&&&& 2eserved !0" !0" !0" x x&&& 2eserved x x x&&&& !(" x
electrical characteristics stm32f405xx, stm32f407xx 62/167 doc id 022152 rev 2 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.8 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 16 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 17 . figure 16. pin loading condition s figure 17. pin input voltage -36 #p& 34-&pin /3#?/54(i :when using(3%or,3% -36 34-&pin 6 ). /3#?/54(i :when using(3%or,3%
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 63/167 5.1.6 power supply scheme figure 18. power supply scheme 1. each power supply pair must be decoupled with filtering ceramic c apacitors as shown above. these capacitors must be placed as close as possible to , or below, the appropriate pins on the undersi de of the pcb to ensure the good functionality of the device. 2. to connect bypass_reg and pdr_on pins, refer to section 2.2.17: real-time clock (rtc), backup sram and backup registers . 3. the two 2.2 f ceramic capacitors should not be connected when the voltage regulator is off. 4. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. 5. v dda =v dd and v ssa =v ss . -36 6 $$ !n alo g 2#s0,, 0o werswi tch 6 "!4 '0)/s /54 ). +ernellogic #05 digital 2!- "ackupcircuitry /3#+24# "ackupregisters backup2!- 7akeuplogic n& ?& 6"!4 to6 6oltage regulator 6 33 6 $$! 6 2%& 6 2%& 6 33! !$# ,evelshifter )/ ,ogic 6 $$ n& ?& 6 2%& n& ?& 6 $$ &lashmemory 6 #!0? 6 #!0? ?& "90!33?2%' 0$2?/. 2eset controller
electrical characteristics stm32f405xx, stm32f407xx 64/167 doc id 022152 rev 2 5.1.7 current con sumption measurement figure 19. current consumption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 8: voltage characteristics , table 9: current characteristics , and table 10: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 v bat v dd v dda i dd _v bat i dd table 8. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five-volt tolerant pin (2) 2. v in maximum value must always be respected. refer to table 9 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4 input voltage on any other pin v ss ?0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.14: absolute maximum ratings (electrical sensitivity)
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 65/167 5.3 operating conditions 5.3.1 general operating conditions table 9. current characteristics symbol ratings max. unit i vdd total current into v dd power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin 25 i inj(pin) (2) 2. negative injection disturbs the analog performance of the device. see note in section 5.3.20: 12-bit adc characteristics . injected current on five-volt tolerant i/o (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in v dd while a negative inje ction is induced by v in electrical characteristics stm32f405xx, stm32f407xx 66/167 doc id 022152 rev 2 v cap1 when the internal regulator is on, v cap_1 and v cap_2 pins are used to connect a stabilization capacitor. when the internal regulator is off (bypass_reg connected to v dd ), v cap_1 and v cap_2 must be supplied from 1.2 v. 1.1 1.3 v v cap2 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (6) lqfp64 - 435 mw lqfp100 - 465 lqfp144 - 500 lqfp176 - 526 ufbga176 - 513 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (7) ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (7) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 1. the average expected gain in power consumption when vos = 0 compared to vos = 1 is around 10% for the whole temperature range, when the system cl ock frequency is between 30 and 144 mhz. 2. if an inverted reset signal is applied to pdr_on, this value can be lowered to 1.7 v when the device operates in a reduced temperature range (0 to 70 c). 3. when the adc is used, refer to table 65: adc characteristics . 4. if v ref+ pin is present, it must res pect the following condition: v dda -v ref+ < 1.2 v. 5. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 6. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 7. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 11. general operating conditions (continued) symbol parameter conditions min max unit
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 67/167 table 12. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency (f flashmax ) number of wait states at maximum cpu frequency (1) i/o operation maximum fsmc_clk frequency for synchronous accesses possible flash memory operations v dd =1.8 to 2.1 v (2) conversion time up to 1.2 msps 16 mhz with no flash memory wait state (3) 7 (3)(4) ? degraded speed performance ? no i/o compensation up to 30 mhz 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 18 mhz with no flash memory wait state 7 (4) ? degraded speed performance ? no i/o compensation up to 30 mhz 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz with no flash memory wait state 6 (4) ? degraded speed performance ? i/o compensation works up to 48 mhz 16-bit erase and program operations v dd = 2.7 to 3.6 v (5) conversion time up to 2.4 msps 30 mhz with no flash memory wait state 5 (4) ? full-speed operation ? i/o compensation works ?up to 60 mhz when v dd = 3.0 to 3.6 v ?up to 48 mhz when v dd = 2.7 to 3.0 v 32-bit erase and program operations 1. the number of wait states can be reduced by reducing the cpu frequency. 2. if an inverted reset signal is applied to pdr_on, this value can be lowered to 1.7 v when the device operates in a reduced temperature range (0 to 70 c). 3. prefetch is not available. refer to an3430 applicatio n note for details on how to adjust performance and power. 4. thanks to the art accelerator and the 128-bit flash memory , the number of wait states given here does not impact the execution speed from flash memory since the art accelerator al lows to achieve a performance equivalent to 0 wait state program execution. 5. the voltage range for otg usb fs can drop down to 2.7 v. however it is degraded between 2.7 and 3 v.
electrical characteristics stm32f405xx, stm32f407xx 68/167 doc id 022152 rev 2 5.3.2 vcap1/vcap2 external capacitor stabilization for the main regulato r is achieved by connecting an external capacitor c ext to the vcap1/vcap2 pins. c ext is specified in ta bl e 1 3 . figure 20. external capacitor c ext 1. legend: esr is the equivalent series resistance. 5.3.3 operating conditions at power- up / power-down (regulator on) subject to general operating conditions for t a . table 14. operating conditions at power-up / power-down (regulator on) 5.3.4 operating conditions at power- up / power-down (regulator off) subject to general operating conditions for t a . table 13. vcap1/vcap2 operating conditions symbol parameter conditions cext capacitance of external capacitor 2.2 f esr esr of external capacitor < 2 m s 19044v1 e s r r le a k c symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 table 15. operating conditions at power-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 69/167 5.3.5 embedded reset and power control block characteristics the parameters given in ta bl e 1 6 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 1 . table 16. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 v pls[2:0]=001 (rising edge) 2.23 2.30 2.37 v pls[2:0]=001 (falling edge) 2.13 2.19 2.25 v pls[2:0]=010 (rising edge) 2.39 2.45 2.51 v pls[2:0]=010 (falling edge) 2.29 2.35 2.39 v pls[2:0]=011 (rising edge) 2.54 2.60 2.65 v pls[2:0]=011 (falling edge) 2.44 2.51 2.56 v pls[2:0]=100 (rising edge) 2.70 2.76 2.82 v pls[2:0]=100 (falling edge) 2.59 2.66 2.71 v pls[2:0]=101 (rising edge) 2.86 2.93 2.99 v pls[2:0]=101 (falling edge) 2.65 2.84 3.02 v pls[2:0]=110 (rising edge) 2.96 3.03 3.10 v pls[2:0]=110 (falling edge) 2.85 2.93 2.99 v pls[2:0]=111 (rising edge) 3.07 3.14 3.21 v pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v v pvdhyst (3) pvd hysteresis - 100 - mv v por/pdr power-on/power-down reset threshold falling edge tbd (1) 1.70 tbd v rising edge tbd 1.74 tbd v v pdrhyst (3) pdr hysteresis - 40 - mv
electrical characteristics stm32f405xx, stm32f407xx 70/167 doc id 022152 rev 2 5.3.6 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 19: current consumption measurement scheme . all run mode current consumption measurements given in this section are performed using a coremark-compliant code. v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 v rising edge 2.53 2.59 2.63 v v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 v rising edge 2.85 2.92 2.97 v v 12 1.2 v domain voltage (2)(3) vos bit in pwr_cr register = 0 1.08 1.14 1.20 v vos bit in pwr_cr register = 1 1.20 1.26 1.32 v v borhyst (3) bor hysteresis - 100 - mv t rsttempo (3)(4) reset temporization 0.5 1.5 3.0 ms i rush (3) inrush current on voltage regulator power-on (por or wakeup from standby) - 160 200 ma e rush (3) inrush energy on voltage regulator power-on (por or wakeup from standby) v dd = 1.8 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 2. the average expected gain in power consumption when vos = 0 compar ed to vos = 1 is around 10% for the whole temperature range, when the sy stem clock fr equency is between 30 and 144 mhz. 3. guaranteed by design, not tested in production. 4. the reset temporization is measured from the power-on (p or reset or wakeup from v bat ) to the instant when first instruction is read by the user application code. table 16. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 71/167 typical and maximum current consumption the mcu is placed under the following conditions: at startup, all i/o pins are configured as analog inputs by firmware. all peripherals are disabled except if it is explicitly mentioned. the flash memory access time is adjusted to f hclk frequency (0 wait state from 0 to 30 mhz, 1 wait state from 30 to 60 mhz, 2 wait states from 60 to 90 mhz, 3 wait states from 90 to 120 mhz, 4 wait states from 120 to 150 mhz, and 5 wait states from 150 to 168 mhz). when the peripherals are enabled hclk is the system clock, f pclk1 = f hclk /4, and f pclk2 = f hclk /2, except is explicitly mentioned. the maximum values are obtained for v dd = 3.6 v and maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. table 17. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) symbol parameter conditions f hclk typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled (3) 168 mhz 93 109 117 ma 144 mhz 76 89 96 120 mhz 67 79 86 90 mhz 53 65 73 60 mhz 37 49 56 30 mhz 20 32 39 25 mhz 16 27 35 16 mhz 11 23 30 8 mhz 6 18 25 4 mhz 4 16 23 2 mhz 3 15 22 external clock (3) , all peripherals disabled 168 mhz 46 61 69 144 mhz 40 52 60 120 mhz 37 48 56 90 mhz 30 42 50 60 mhz 22 33 41 30 mhz 12 24 31 25 mhz 10 21 29 16 mhz 7 19 26 8 mhz 4 16 23 4 mhz 3 15 22 2 mhz 2 14 21 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 4 mhz and pll is on when f hclk > 25 mhz.
electrical characteristics stm32f405xx, stm32f407xx 72/167 doc id 022152 rev 2 3. when analog peripheral blocks such as (adcs, dacs, hs e, lse, hsi,lsi) are on, an additional power consumption should be considered. table 18. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram (1) symbol parameter conditions f hclk typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (3) , all peripherals enabled (4) 168 mhz 87 102 109 ma 144 mhz 67 80 86 120 mhz 56 69 75 90 mhz 44 56 62 60 mhz 30 42 49 30 mhz 16 28 35 25 mhz 12 24 31 16 mhz (5) 92028 8 mhz 5 17 24 4 mhz 3 15 22 2 mhz 2 14 21 external clock (3) , all peripherals disabled 168 mhz 40 54 61 144 mhz 31 43 50 120 mhz 26 38 45 90 mhz 20 32 39 60 mhz 14 26 33 30 mhz 8 20 27 25 mhz 6 18 25 16 mhz (5) 51624 8 mhz 3 15 22 4 mhz 2 14 21 2 mhz 2 14 21 1. code and data processing running from sram1 using boot pins. 2. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 3. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 4. when the adc is on (adon bit set in t he adc_cr2 register), add an additional po wer consumption of 1.6 ma per adc for the analog part. 5. in this case hclk = system clock/2.
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 73/167 figure 21. typical current consumption vs temperature, run mode, code with data processing running from flash (art accelerator on) or ram, and peripherals off figure 22. typical current consumption vs temperature, run mode, code with data processing running from flash (art accelerator on) or ram, and peripherals on -36 ) $$25. m! #05&requency- ( z ?# ?# ?# ?# ?# ?# -36 ) $$25. m! #05&requency- ( z ?# ?# ?# ?# ?# ?#
electrical characteristics stm32f405xx, stm32f407xx 74/167 doc id 022152 rev 2 figure 23. typical current consumption vs temperature, run mode, code with data processing running from flash (art accelerator off) or ram, and peripherals off figure 24. typical current consumption vs temperature, run mode, code with data processing running from flash (art accelerator off) or ram, and peripherals on -36 ) $$25. m! #05&requency- ( z ?# ?# ?# ?# ?# ?# -36 ) $$25. m! #05&requency- ( z ?# ?# ?# ?# ?# ?#
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 75/167 table 19. typical and maximum current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) , all peripherals enabled (3) 168 mhz 59 77 84 ma 144 mhz 46 61 67 120 mhz 38 53 60 90 mhz 30 44 51 60 mhz 20 34 41 30 mhz 11 24 31 25 mhz 8 21 28 16 mhz 6 18 25 8 mhz 3 16 23 4 mhz 2 15 22 2 mhz 2 14 21 external clock (2) , all peripherals disabled 168 mhz 12 27 35 144 mhz 9 22 29 120 mhz 8 20 28 90 mhz 7 19 26 60 mhz 5 17 24 30 mhz 3 16 23 25 mhz 2 15 22 16 mhz 2 14 21 8 mhz 1 14 21 4 mhz 1 13 21 2 mhz 1 13 21 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 3. add an additional power consumption of 0. 8 ma per adc for the analog part. in applic ations, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register).
electrical characteristics stm32f405xx, stm32f407xx 76/167 doc id 022152 rev 2 table 20. typical and maximum current consumptions in stop mode symbol parameter conditions typ max unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop supply current in stop mode with main regulator in run mode flash in stop mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.60 1.20 11.00 20.00 ma flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.55 1.20 11.00 20.00 supply current in stop mode with main regulator in low power mode flash in stop mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.40 1.10 8.00 15.00 flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.35 1.1 8.00 15.00 table 21. typical and maximum current consumptions in standby mode (1) symbol parameter conditions typ max unit t a = 25 c t a = 85 c t a = 105 c v dd = 1.8 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_stby supply current in standby mode backup sram on, low-speed oscillator and rtc on 3.0 3.4 4.0 tbd (2) tbd (2) a backup sram off, low- speed oscillator and rtc on 2.4 2.7 3.3 tbd (2) tbd (2) backup sram on, rtc off 2.4 2.6 3.0 12.5 (2) 24.8 (2) backup sram off, rtc off 1.7 1.9 2.2 9.8 (2) 19.2 (2) 1. tbd stands for ?to be defined?. 2. based on characterization, not tested in production.
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 77/167 figure 25. typical v bat current consumption (lse and rtc on/backup ram off) table 22. typical and maximum current consumptions in v bat mode (1) symbol parameter conditions typ max unit t a = 25 c t a = 85 c t a = 105 c v bat = 1.8 v v bat = 2.4 v v bat = 3.3 v v bat = 3.6 v i dd_vbat backup domain supply current backup sram on, low-speed oscillator and rtc on 1.29 1.42 1.68 tbd (2) tbd (2) a backup sram off, low-speed oscillator and rtc on 0.62 0.73 0.96 tbd (2) tbd (2) backup sram on, rtc off 0.79 0.81 0.86 9 (2) 16 (2) backup sram off, rtc off 0.10 0.10 0.10 5 (2) 7 (2) 1. tbd stands for ?to be defined?. 2. based on characterization, not tested in production. -36 0 0.5 1 1.5 2 2.5 3 3.5 0 102030405060708090100 ivbat in (a) te m p e r a t u r e i n ( c ) 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v
electrical characteristics stm32f405xx, stm32f407xx 78/167 doc id 022152 rev 2 figure 26. typical v bat current consumption (lse and rtc on/backup ram on) i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 44: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 24: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply -36 0 1 2 3 4 5 6 0 102030405060708090100 ivbat in (a) te m p e r a t u r e i n ( c ) 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 79/167 voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c =
electrical characteristics stm32f405xx, stm32f407xx 80/167 doc id 022152 rev 2 table 23. switching output i/o current consumption symbol parameter conditions (1) i/o toggling frequency (f sw ) typ unit i ddio i/o switching current v dd = 3.3 v (2) c = c int 2 mhz 0.02 ma 8 mhz 0.14 25 mhz 0.51 50 mhz 0.86 60 mhz 1.30 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.10 8 mhz 0.38 25 mhz 1.18 50 mhz 2.47 60 mhz 2.86 v dd = 3.3 v c ext = 10 pf c = c int + c ext + c s 2 mhz 0.17 8 mhz 0.66 25 mhz 1.70 50 mhz 2.65 60 mhz 3.48 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 2 mhz 0.23 8 mhz 0.95 25 mhz 3.20 50 mhz 4.69 60 mhz 8.06 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 0.30 8 mhz 1.22 25 mhz 3.90 50 mhz 8.82 60 mhz - (3) 1. c s is the pcb board capacitance including the pad pin. c s = 7 pf (estinated value). 2. this test is performed by cutting the lqfp package pin (pad removal). 3. at 60 mhz, c maximum load is specified 30 pf.
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 81/167 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 2 4 . the mcu is placed under the following conditions: at startup, all i/o pins are configured as analog pins by firmware. all peripherals are disabled unless otherwise mentioned the code is running from flash memory and the flash memory access time is equal to 5 wait states at 168 mhz. the code is running from flash memory and the flash memory access time is equal to 4 wait states at 144 mhz, and the power scale mode is set to 2. art accelerator and cache off. the given value is calculated by measuring the difference of current consumption ? with all peripherals clocked off ? with one peripheral clocked on (with only the clock applied) when the peripherals are enabled: hclk is the system clock, f pclk1 = f hclk /4, and f pclk2 =f hclk /2. the typical values are obtained for v dd = 3.3 v and t a = 25 c, unless otherwise specified. table 24. peripheral current consumption peripheral (1) 168 mhz 144 mhz unit ahb1 gpio a 0.49 0.36 ma gpio b 0.45 0.33 gpio c 0.45 0.34 gpio d 0.45 0.34 gpio e 0.47 0.35 gpio f 0.45 0.33 gpio g 0.44 0.33 gpio h 0.45 0.34 gpio i 0.44 0.33 otg_hs + ulpi 4.57 3.55 crc 0.07 0.06 bkpsram 0.11 0.08 dma1 6.15 4.75 dma2 6.24 4.8 eth_mac + eth_mac_tx eth_mac_rx eth_mac_ptp 3.28 2.54 ahb2 otg_fs 4.59 3.69 ma dcmi 1.04 0.80
electrical characteristics stm32f405xx, stm32f407xx 82/167 doc id 022152 rev 2 ahb3 fsmc 2.18 1.67 ma apb1 tim2 0.80 0.61 tim3 0.58 0.44 tim4 0.62 0.48 tim5 0.79 0.61 tim6 0.15 0.11 tim7 0.16 0.12 tim12 0.33 0.26 tim13 0.27 0.21 tim14 0.27 0.21 pwr 0.04 0.03 usart2 0.17 0.13 usart3 0.17 0.13 uart4 0.17 0.13 uart5 0.17 0.13 i2c1 0.17 0.13 i2c2 0.18 0.13 i2c3 0.18 0.13 spi2/i2s2 (2) 0.17/0.16 0.13/0.12 spi3/i2s3 (2) 0.16/0.14 0.12/0.12 can1 0.27 0.21 can2 0.26 0.20 dac 0.14 0.10 dac channel 1 (3) 0.91 0.89 dac channel 2 (4) 0.91 0.89 dac channel 1 and 2 (3)(4) 1.69 1.68 wwdg 0.04 0.04 table 24. peripheral current consumption (continued) peripheral (1) 168 mhz 144 mhz unit
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 83/167 5.3.7 wakeup time from low-power mode the wakeup times given in ta bl e 2 5 is measured on a wakeup phase with a 16 mhz hsi rc oscillator. the clock source used to wake up the device depe nds from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 1 . apb2 sdio 0.64 0.54 ma tim1 1.47 1.14 tim8 1.58 1.22 tim9 0.68 0.54 tim10 0.45 0.36 tim11 0.47 0.38 adc1 (5) 2.20 2.10 adc2 (5) 2.04 1.93 adc3 (5) 2.10 2.00 spi1 0.14 0.12 usart1 0.34 0.27 usart6 0.34 0.28 1. hse oscillator with 4 m hz crysta) and pll are on. 2. i2smod bit set in spi_i2scfgr register, and then the i2se bit set to enable i2s peripheral. 3. en1 bit is set in dac_cr register. 4. en2 bit is set in dac_cr register. 5. adon bit set in adc_cr2 register. table 24. peripheral current consumption (continued) peripheral (1) 168 mhz 144 mhz unit table 25. low-power mode wakeup timings symbol parameter min (1) typ (1) max (1) unit t wusleep (2) wakeup from sleep mode - 1 - s t wustop (2) wakeup from stop mode (regulator in run mode) - 13 - s wakeup from stop mode (regulator in low power mode) - 17 40 wakeup from stop mode (regulator in low power mode and flash memory in deep power down mode) -110- t wustdby (2)(3) wakeup from standby mode 260 375 480 s 1. based on characterization, not tested in production. 2. the wakeup times are measured from the wakeup event to the point in which the application c ode reads the first instruction. 3. t wustdby minimum and maximum values are given at 105 c and ?45 c, respectively.
electrical characteristics stm32f405xx, stm32f407xx 84/167 doc id 022152 rev 2 5.3.8 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 2 6 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 1 1 . low-speed external user clock generated from an external source the characteristics given in ta b l e 2 7 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 1 1 . table 26. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) 1850mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design, not tested in production. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 27. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -5-pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design, not tested in production.
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 85/167 figure 27. high-speed external clock source ac timing diagram figure 28. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 8 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). a i1752 8 o s c_in extern a l s tm 3 2f clock s o u rce v h s eh t f(h s e) t w(h s e) i l 90 % 10 % t h s e t t r(h s e) t w(h s e) f h s e_ext v h s el a i17529 o s c 3 2_in extern a l s tm 3 2f clock s o u rce v l s eh t f(l s e) t w(l s e) i l 90 % 10 % t l s e t t r(l s e) t w(l s e) f l s e_ext v l s el
electrical characteristics stm32f405xx, stm32f407xx 86/167 doc id 022152 rev 2 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 29 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available fr om the st website www.st.com. figure 29. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 9 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 28. hse 4-26 mhz oscillator characteristics (1) (2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization , not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 - 26 mhz r f feedback resistor - 200 - k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 -15-pf i 2 hse driving current v dd = 3.3 v, v in =v ss with 30 pf load --1ma g m oscillator transconductance startup 5 - - ma/v t su(hse (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms a i175 3 0 o s c_ou t o s c_in f h s e c l1 r f s tm 3 2f 8 mh z re s on a tor re s on a tor with integr a ted c a p a citor s bi as controlled g a in r ext (1) c l2
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 87/167 note: for c l1 and c l2 it is recommended to use high-quality external ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 30 ). c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 30. typical application with a 32.768 khz crystal table 29. lse oscillator characteristics (f lse = 32.768 khz) (1)(2) 1. based on characterization , not tested in production. 2. tbd stands for ?to be defined?. symbol parameter conditions min typ max unit r f feedback resistor - tbd - m c (3) 3. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (4) 4. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value for example msiv-tin32.768khz. refer to crystal manufacturer for more details r s = 30 k --tbdpf i 2 lse driving current v dd = 3.3 v, v in = v ss --tbda g m oscillator transconductance tbd - - a/v t su(lse) (5) 5. t su(lse) is the startup time measured from the mom ent it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard cr ystal resonator and it can vary significantly with t he crystal manufacturer startup time v dd is stabilized - tbd - s a i175 3 1 o s c 3 2_ou t o s c 3 2_in f l s e c l1 r f s tm 3 2f 3 2.76 8 kh z re s on a tor re s on a tor with integr a ted c a p a citor s bi as controlled g a in c l2
electrical characteristics stm32f405xx, stm32f407xx 88/167 doc id 022152 rev 2 5.3.9 internal clock source characteristics the parameters given in ta bl e 3 0 and ta b l e 3 1 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 1 . high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator table 30. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 16 - mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibrat ion? available from the st website www.st.com. --1% factory- calibrated t a = ?40 to 105 c ?8 - 4.5 % t a = ?10 to 85 c ?4 - 4 % t a = 25 c ?1 - 1 % t su(hsi) (3) 3. guaranteed by design, not tested in production. hsi oscillator startup time -2.24 s i dd(hsi) hsi oscillator power consumption -6080a table 31. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization , not tested in production. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 89/167 figure 31. acc lsi versus temperature 5.3.10 pll characteristics the parameters given in ta bl e 3 2 and ta b l e 3 3 are derived from tests performed under temperature and v dd supply voltage conditions summarized in ta b l e 1 1 . -36 .ormalizeddeviati on 4e m p e r at u r e ?# max avg min table 32. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) 0.95 (2) 12.10mhz f pll_out pll multiplier output clock 24 - 168 mhz f pll48_out 48 mhz pll multiplier output clock -48 -mhz f vco_out pll vco output 192 - 432 mhz t lock pll lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300
electrical characteristics stm32f405xx, stm32f407xx 90/167 doc id 022152 rev 2 jitter (3) cycle-to-cycle jitter system clock 120 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - main clock output (mco) for rmii ethernet cycle to cycle at 50 mhz on 1000 samples -32 - main clock output (mco) for mii ethernet cycle to cycle at 25 mhz on 1000 samples -40 - bit time can jitter cycle to cycle at 1 mhz on 1000 samples -330 - i dd(pll) (4) pll power consumption on vdd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to obtain the specified pll input clock va lues. the m factor is shared between pll and plli2s. 2. guaranteed by design, not tested in production. 3. the use of 2 plls in parallel could degraded the jitter up to +30%. 4. based on characterization, not tested in production. table 32. main pll characteristics (continued) symbol parameter conditions min typ max unit table 33. plli2s (audio pll) characteristics (1) symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (2) 0.95 (3) 12.10mhz f plli2s_out plli2s multiplier output clock - - 216 mhz f vco_out plli2s vco output 192 - 432 mhz t lock plli2s lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (4) master i2s clock jitter cycle to cycle at 12,343 mhz on 48khz period, n=432, p=4, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12,343 mhz n = 432, p = 4, r = 5 on 256 samples tbd - tbd ps ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples - 400 - ps
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 91/167 i dd(plli2s) (5) plli2s power consumption on v dd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (5) plli2s power consumption on v dda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. tbd stands for ?to be defined?. 2. take care of using the appropriate division factor m to have the specified pll input clock values. 3. guaranteed by design, not tested in production. 4. value given with main pll running. 5. based on characterization, not tested in production. table 33. plli2s (audio pll) characteristics (1) (continued) symbol parameter conditions min typ max unit
electrical characteristics stm32f405xx, stm32f407xx 92/167 doc id 022152 rev 2 5.3.11 pll spread spectrum clock generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 40: emi characteristics ). it is available only on the main pll. equation 1 the frequency mo dulation period (modeper) is gi ven by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation depth (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and f vco_out = 240 (in mhz): an amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: the error in modulation depth is consequently: 2.0 - 1.99954 = 0.00046%. table 34. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - 2 15 ? 1- 1. guaranteed by design, not tested in production. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 25 == incstep round 2 15 1 ? () md f vco_out () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2 240 () 100 5 25 () ? [] 1258md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () f vco_out () ? = md quantized % 25 1258 100 5 () 2 15 1 ? () 240 () ? 1.99954%(peak) ==
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 93/167 figure 32 and figure 33 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 32. pll output clock waveforms in center spread mode figure 33. pll output clock waveforms in down spread mode 5.3.12 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. &requency0,,?/54 4ime & tmode
tmode md ai md &requency0,,?/54 4ime & tmode
tmode
md ai table 35. flash memory characteristics (1) symbol parameter conditions min max unit i dd supply current read mode f hclk = 168 mhz with 5 wait states, v dd = 3.3 v -100ma write / erase modes f hclk = 168 mhz, v dd = 3.3 v -tbdma
electrical characteristics stm32f405xx, stm32f407xx 94/167 doc id 022152 rev 2 1. tbd stands for ?to be defined?. table 36. flash memory programming symbol parameter conditions min (1) typ max (1) 1. based on characterization , not tested in production. unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) 2. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -1632 s program/erase parallelism (psize) = x 16 -1121 program/erase parallelism (psize) = x 32 -816 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.8 - 3.6 v
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 95/167 table 38. flash memory endurance and data retention 5.3.13 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. table 37. flash memory programming with v pp (1) 1. tbd stands for ?to be defined?. symbol parameter conditions min (1) typ max (2) 2. guaranteed by design, not tested in production. unit t prog double word programming t a = 0 to +40 c - 16 100 (3) 3. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time - tbd - t erase64kb sector (64 kb) erase time - tbd - t erase128kb sector (128 kb) erase time - tbd - t me mass erase time - 6.8 - v prog programming voltage 2.7 - 3.6 v v pp v pp voltage range 7 - 9 v i pp minimum current sunk on the v pp pin 10 - - ma t vpp (4) 4. v pp should only be connected du ring programming/erasing. cumulative time during which v pp is applied - - 1 hour symbol parameter conditions value unit min (1) 1. based on characterization , not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20
electrical characteristics stm32f405xx, stm32f407xx 96/167 doc id 022152 rev 2 a device reset allows normal operations to be resumed. the test results are given in ta b l e 3 9 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 39. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp176, t a = +25 c, f hclk = 168 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp176, t a = +25 c, f hclk = 168 mhz, conforms to iec 61000-4-2 4a
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 97/167 electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc ? code, is running. this emission te st is compliant wi th sae iec61967-2 standard which specifies the test board and the pin loading. 5.3.14 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 40. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 25/168 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running from flash with art accelerator enabled 0.1 to 30 mhz 32 dbv 30 to 130 mhz 25 130 mhz to 1ghz 29 sae emi level 4 - v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running from flash with art accelerator and clock dithering enabled 0.1 to 30 mhz 19 dbv 30 to 130 mhz 16 130 mhz to 1ghz 18 sae emi level 3.5 - table 41. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to jesd22-a114 2 2000 (2) v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to jesd22-c101 ii 500 1. based on characterization results, not tested in production. 2. on v bat pin, v esd(hbm) is limited to 1000 v.
electrical characteristics stm32f405xx, stm32f407xx 98/167 doc id 022152 rev 2 static latchup two complementary static tests are required on six parts to assess the latchup performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. 5.3.15 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). the test results are given in ta b l e 4 3 . table 42. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 43. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on all ft pins ?5 +0 ma injected current on any other pin ?5 +5
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 99/167 5.3.16 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 4 4 are derived from tests performed under the conditions summarized in ta b l e 1 1 . all i/os are cmos and ttl compliant. table 44. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage ttl ports 2.7 v v dd 3.6 v v ss ?0.3 - 0.8 v v ih (1) tta/tc (2) i/o input high level voltage 2.0 - v dd +0.3 ft (3) i/o input high level voltage 2.0 - 5.5 v il input low level voltage cmos ports 1.8 v v dd 3.6 v v ss ?0.3 - 0.3v dd v ih (1) tta/tc i/o input high level voltage 0.7v dd -3.6 (4) ft i/o input high level voltage -5.2 (4) cmos ports 2.0 v v dd 3.6 v -5.5 (4) v hys i/o schmitt trigger voltage hysteresis (5) -200- mv io ft schmitt trigger voltage hysteresis (5) 5% v dd (4) - - i lkg i/o input leakage current (6) v ss v in v dd -- 1 a i/o ft input leakage current (6) v in = 5v - - 3 r pu weak pull-up equivalent resistor (7) all pins except for pa10 and pb12 v in = v ss 30 40 50 k pa10 and pb12 81115 r pd weak pull-down equivalent resistor all pins except for pa10 and pb12 v in = v dd 30 40 50 pa10 and pb12 81115 c io (8) i/o pin capacitance 5 pf 1. if v ih maximum value cannot be respected, the inject ion current must be limited externally to i inj(pin) maximum value. 2. tta = 3.3 v tolerant i/o directly connected to adc; tc = standard 3.3 v i/o. 3. ft = 5 v tolerant. 4. with a minimum of 100 mv. 5. hysteresis voltage between schmitt trigger switching leve ls. based on characterization, not tested in production. 6. leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 7. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) . 8. guaranteed by design, not tested in production.
electrical characteristics stm32f405xx, stm32f407xx 100/167 doc id 022152 rev 2 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 . in particular: the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 9 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 9 ). output voltage levels unless otherwise specified, the parameters given in ta bl e 4 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 1 1 . all i/os are cmos and ttl compliant. table 45. output voltage characteristics (1) 1. pc13, pc14, pc15 and pi8 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these i/os must not be used as a current source (e.g. to drive an led). symbol parameter conditions min max unit v ol (2) 2. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 9 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time ttl port i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 9 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 - v ol (2) output low level voltage for an i/o pin when 8 pins are sunk at same time cmos port i io =+ 8ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 - v ol (2)(4) 4. based on characterization data, not tested in production. output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 - v ol (2)(4) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v -0.4 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 -
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 101/167 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 34 and ta bl e 4 6 , respectively. unless otherwise specified, the parameters given in ta bl e 4 6 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 1 . table 46. i/o ac characteristics (1)(2)(3) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (4) c l = 50 pf, v dd > 2.70 v - - 2 mhz c l = 50 pf, v dd > 1.8 v - - 2 c l = 10 pf, v dd > 2.70 v - - tbd c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, v dd = 1.8 v to 3.6 v --tbd ns t r(io)out output low to high level rise time --tbd 01 f max(io)out maximum frequency (4) c l = 50 pf, v dd > 2.70 v - - 25 mhz c l = 50 pf, v dd > 1.8 v - - 12.5 (5) c l = 10 pf, v dd > 2.70 v - - 50 (5) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 50 pf, v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd 10 f max(io)out maximum frequency (4) c l = 40 pf, v dd > 2.70 v - - 50 (5) mhz c l = 40 pf, v dd > 1.8 v - - 25 c l = 10 pf, v dd > 2.70 v - - 100 (5) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, 2.4 < v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 50 pf, 2.4 < v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd
electrical characteristics stm32f405xx, stm32f407xx 102/167 doc id 022152 rev 2 figure 34. i/o ac characteristics definition 11 f max(io)out maximum frequency (4) c l = 30 pf, v dd > 2.70 v - - 100 (5) mhz c l = 30 pf, v dd > 1.8 v - - 50 (5) c l = 10 pf, v dd > 2.70 v - - 200 (5) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 20 pf, 2.4 < v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 20 pf, 2.4 < v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd -t extipw pulse width of external signals detected by the exti controller 10 - - ns 1. based on characterization data, not tested in production. 2. the i/o speed is configured using the ospeedry[1:0] bi ts. refer to the stm32f20/21xxx reference manual for a description of the gpiox_speedr gpio port output speed register. 3. tbd stands for ?to be defined?. 4. the maximum frequency is defined in figure 34 . 5. for maximum frequencies above 50 mhz, the compensation cell should be used. table 46. i/o ac characteristics (1)(2)(3) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50pf t t r(io)out
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 103/167 5.3.17 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 4 4 ). unless otherwise specified, the parameters given in ta bl e 4 7 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 1 . figure 35. recommended nrst pin protection 2. the reset network protects t he device against par asitic resets. 3. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 47 . otherwise the reset is not taken into account by the device. table 47. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 - 0.8 v v ih(nrst) (1) nrst input high level voltage 2 - v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse - - 100 ns v nf(nrst) (1) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s aic 34-&xxx 2 05 .234 6 $$ &ilter )nternal2eset ?& %xternal resetcircuit
electrical characteristics stm32f405xx, stm32f407xx 104/167 doc id 022152 rev 2 5.3.18 tim time r characteristics the parameters given in ta bl e 4 8 and ta b l e 4 9 are guaranteed by design. refer to section 5.3.16: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 48. characteristics of timx connected to the apb1 domain (1) 1. timx is used as a general term to refer to the tim2, tim3, tim4, tim5, tim6, tim7, and tim12 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb1 prescaler distinct from 1, f timxclk = 84 mhz 1- t timxclk 11.9 - ns ahb/apb1 prescaler = 1, f timxclk = 42 mhz 1- t timxclk 23.8 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 84 mhz apb1= 42 mhz 0 f timxclk /2 mhz 042mhz res tim timer resolution - 16/32 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk 0.0119 780 s 32-bit counter clock period when internal clock is selected 1- t timxclk 0.0119 51130563 s t max_count maximum possible count - 65536 65536 t timxclk -51.1 s
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 105/167 5.3.19 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 5 0 are derived from tests performed under the ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta bl e 1 1 . the stm32f405xx and stm32f407xx i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 5 0 . refer also to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 49. characteristics of timx connected to the apb2 domain (1) 1. timx is used as a general term to refer to the tim1, tim8, tim9, tim10, and tim11 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb2 prescaler distinct from 1, f timxclk = 168 mhz 1- t timxclk 5.95 - ns ahb/apb2 prescaler = 1, f timxclk = 84 mhz 1- t timxclk 11.9 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 168 mhz apb2 = 84 mhz 0 f timxclk /2 mhz 084mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk t max_count maximum possible count - 32768 t timxclk
electrical characteristics stm32f405xx, stm32f407xx 106/167 doc id 022152 rev 2 table 50. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1)(2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. -0 (4) 4. the device must internally provide a hold time of at least 300ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 107/167 figure 36. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 51. scl frequency (f pclk1 = 42 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee aib 34!24 3$ ! k )#bus k 6 $$ 6 $$ 34-&xx 3$! 3#, t f3$! t r3$! 3#, t h34! t w3#,( t w3#,, t su3$! t r3#, t f3#, t h3$! 3 4!242%0%!4%$ 34!24 t su34! t su34/ 34/0 t w34/34!
electrical characteristics stm32f405xx, stm32f407xx 108/167 doc id 022152 rev 2 i 2 s - spi interface characteristics unless otherwise specified, the parameters given in ta bl e 5 2 for spi or in ta bl e 5 3 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 1 1 . refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 52. spi characteristics (1)(2) 1. remapped spi1 characteristics to be determined. 2. tbd stands for ?to be defined?. symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 37.5 mhz slave mode - 37.5 t r(scl) t f(scl) spi clock rise and fall time capacitive load: c = 30 pf - 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (3) 3. based on characterization , not tested in production. nss setup time slave mode 4t pclk - ns t h(nss) (3) nss hold time slave mode 2t pclk - t w(sclh) (3) t w(scll) (3) sck high and low time master mode, f pclk = tbd mhz tbd tbd t su(mi) (3) t su(si) (3) data input setup time master mode 5 - slave mode 5 - t h(mi) (3) t h(si) (3) data input hold time master mode 5 - slave mode 4 - t a(so) (3)(4) 4. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 20 mhz 0 3 t pclk t dis(so) (3)(5) 5. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (3)(1) data output valid time slave mode (after enable edge) - 25 t v(mo) (3)(1) data output valid time master mode (after enable edge) - 5 t h(so) (3) data output hold time slave mode (after enable edge) 15 - t h(mo) (3) master mode (after enable edge) 2 -
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 109/167 figure 37. spi timing diagram - slave mode and cpha = 0 figure 38. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
electrical characteristics stm32f405xx, stm32f407xx 110/167 doc id 022152 rev 2 figure 39. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 111/167 table 53. i 2 s characteristics (1) 1. tbd stands for ?to be defined?. symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master tbd tbd mhz slave 0 tbd t r(ck) t f(ck) i 2 s clock rise and fall time capacitive load c l = 50 pf - tbd ns t v(ws) (2) 2. based on design simulation and/or characte rization results, not tested in production. ws valid time master tbd - t h(ws) (2) ws hold time master tbd - t su(ws) (2) ws setup time slave tbd - t h(ws) (2) ws hold time slave tbd - t w(ckh) (2) t w(ckl) (2) ck high and low time master f pclk = tbd, presc = tbd tbd - t su(sd_mr) (2) t su(sd_sr) (2) data input setup time master receiver slave receiver tbd tbd - t h(sd_mr) (2)(3) t h(sd_sr) (2)(3) 3. depends on f pclk . for example, if f pclk =8 mhz, then t pclk = 1/f plclk =125 ns. data input hold time master receiver slave receiver tbd tbd - t h(sd_mr) (2) t h(sd_sr) (2) data input hold time master f pclk = tbd slave f pclk = tbd tbd tbd - t v(sd_st) (2)(3) data output valid time slave transmitter (after enable edge) - tbd f pclk = tbd - tbd t h(sd_st) (2) data output hold time slave transmitter (after enable edge) tbd - t v(sd_mt) (2)(3) data output valid time master transmitter (after enable edge) - tbd f pclk = tbd tbd tbd t h(sd_mt) (2) data output hold time master transmitter (after enable edge) tbd -
electrical characteristics stm32f405xx, stm32f407xx 112/167 doc id 022152 rev 2 figure 40. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 41. i 2 s master timing diagram (philips protocol) (1) 1. based on characterization , not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2)
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 113/167 usb otg fs characteristics this interface is present in both the usb otg hs and usb otg fs controllers. table 54. usb otg fs startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb otg fs transceiver startup time 1 s table 55. usb otg fs dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg fs operating voltage 3.0 (2) 2. the stm32f405xx and stm32f407xx usb otg fs functi onality is ensured down to 2.7 v but not the full usb otg fs electrical c haracteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6v v di (3) 3. guaranteed by design, not tested in production. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg fs drivers --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v dd 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55
electrical characteristics stm32f405xx, stm32f407xx 114/167 doc id 022152 rev 2 figure 42. usb otg fs timings: definiti on of data signal rise and fall time table 56. usb otg fs electrical characteristics (1) 1. guaranteed by design, not tested in production. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v table 57. usb fs clock timing parameters (1)(2) 1. guaranteed by design, not tested in production. 2. tbd stands for ?to be defined?. parameter symbol min nominal max unit f hclk value to guarantee proper operation of usb fs interface - 14.2 mhz frequency (first transition) 8-bit 10% f start_8bit tbd tbd tbd mhz frequency (steady state) 500 ppm f steady tbd tbd tbd mhz duty cycle (first transition) 8-bit 10% d start_8bit tbd tbd tbd % duty cycle (steady state) 500 ppm d steady tbd tbd tbd % time to reach the stea dy state frequency and duty cycle after the first transition t steady --tbdms clock startup time after the de-assertion of suspendm peripheral t start_dev --tbd ms host t start_host --- phy preparation time after the first transition of the input clock t prep ---s ai14137 t f differen tial data lines v ss v cr s t r crossover points
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 115/167 usb hs characteristics ta bl e 5 8 shows the usb hs operating voltage. figure 43. ulpi timing diagram table 58. usb hs dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd ethernet operating voltage 2.7 3.6 v table 59. usb hs clock timing parameters (1) 1. guaranteed by design, not tested in production. parameter symbol min nominal max unit f hclk value to guarantee proper operation of usb hs interface 30 mhz frequency (first transition) 8-bit 10% f start_8bit 54 60 66 mhz frequency (steady state) 500 ppm f steady 59.97 60 60.03 mhz duty cycle (first transition) 8-bit 10% d start_8bit 40 50 60 % duty cycle (steady state) 500 ppm d steady 49.975 50 50.025 % time to reach the stea dy state frequency and duty cycle after the first transition t steady --1.4ms clock startup time after the de-assertion of suspendm peripheral t start_dev --5.6 ms host t start_host --- phy preparation time after the first transition of the input clock t prep ---s #lock #ontrol)n 5,0)?$)2 5,0)?.84 data)n bit #ontrolout 5,0)?340 dataout bit t $$ t $# t ($ t 3$ t (# t 3# aic t $#
electrical characteristics stm32f405xx, stm32f407xx 116/167 doc id 022152 rev 2 ethernet characteristics ta bl e 6 1 shows the ethernet operating voltage. ta bl e 6 2 gives the list of ethernet mac signals for the smi (station management interface) and figure 44 shows the corresponding timing diagram. figure 44. ethernet smi timing diagram table 60. ulpi timing parameter symbol value (1) 1. v dd = 2.7 v to 3.6 v and t a = ?40 to 85 c. unit min. max. control in (ulpi_dir) setup time t sc -2.0 ns control in (ulpi_nxt) setup time - 1.5 control in (ulpi_dir, ulpi_nxt) hold time t hc - data in setup time t sd -2.0 data in hold time t hd 0- control out (ulpi_stp) se tup time and hold time t dc -9.2 data out available from clock rising edge t dd - 10.7 table 61. ethernet dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd ethernet operating voltage 2.7 3.6 v table 62. dynamics characteristics: ethernet mac signals for smi (1) 1. tbd stands for ?to be defined?. symbol rating min typ max unit t mdc mdc cycle time (1.71 mhz, ahb = 72 mhz) tbd tbd tbd ns t d(mdio) mdio write data valid time tbd tbd tbd ns t su(mdio) read data setup time tbd tbd tbd ns t h(mdio) read data hold time tbd tbd tbd ns eth_mdc eth_mdio(o) eth_mdio(i) t mdc t d(mdio) t su (mdio) t h(mdio) a i15666c
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 117/167 ta bl e 6 3 gives the list of ethernet mac signals for the rmii and figure 45 shows the corresponding timing diagram. figure 45. ethernet rmii timing diagram ta bl e 6 4 gives the list of ethernet mac signals for mii and figure 45 shows the corresponding timing diagram. figure 46. ethernet mii timing diagram table 63. dynamics characteristics: ethernet mac signals for rmii symbol rating min typ max unit t su(rxd) receive data setup time 2 - - ns t ih(rxd) receive data hold time 1 - - ns t su(crs) carrier sense set-up time 0.5 - - ns t ih(crs) carrier sense hold time 2 - - ns t d(txen) transmit enable valid delay time 8 9.5 11 ns t d(txd) transmit data valid delay time 8.5 10 11.5 ns rmii_ref_clk rmii_tx_en rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv t d(txen) t d(txd) t su(rxd) t su(crs) t ih(rxd) t ih(crs) ai15667 mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er t d(txen) t d(txd) t su(rxd) t su(er) t su(dv) t ih(rxd) t ih(er) t ih(dv) ai15668 mii_tx_clk mii_tx_en mii_txd[3:0]
electrical characteristics stm32f405xx, stm32f407xx 118/167 doc id 022152 rev 2 can (controller area network) interface refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (cantx and canrx). 5.3.20 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 6 5 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 1 1 . table 64. dynamics characteristics: ethernet mac signals for mii (1) 1. tbd stands for ?to be defined?. symbol rating min typ max unit t su(rxd) receive data setup time tbd tbd tbd ns t ih(rxd) receive data hold time tbd tbd tbd ns t su(dv) data valid setup time tbd tbd tbd ns t ih(dv) data valid hold time tbd tbd tbd ns t su(er) error setup time tbd tbd tbd ns t ih(er) error hold time tbd tbd tbd ns t d(txen) transmit enable valid delay time 13.4 15.5 17.7 ns t d(txd) transmit data valid delay time 12.9 16.1 19.4 ns table 65. adc characteristics (1) symbol parameter conditions min typ max unit v dda power supply 1.8 (2) -3.6v v ref+ positive reference voltage 1.8 (2)(3)(4) -v dda v f adc adc clock frequency v dda = 1.8 (2)(4) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v (4) 0.6 30 36 mhz f trig (5) external trigger frequency f adc = 30 mhz - - tbd khz --171/f adc v ain conversion voltage range (6) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (5) external input impedance see equation 1 for details --50k r adc (5)(7) sampling switch resistance - - 6 k c adc (5) internal sample and hold capacitor -4-pf t lat (5) injection trigger conversion latency f adc = 30 mhz - - 0.100 s --3 (8) 1/f adc t latr (5) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (8) 1/f adc
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 119/167 t s (5) sampling time f adc = 30 mhz 0.100 - 16 s 3 - 416 1/f adc t stab (5) power-up time - 2 3 s t conv (5) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.416 - 12.95 s f adc = 30 mhz 10-bit resolution 0.360 - 12.89 s f adc = 30 mhz 8-bit resolution 0.305 - 12.84 s f adc = 30 mhz 6-bit resolution 0.250 - 12.79 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc f s (5) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc --2msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode --6msps i vref+ (5) adc v ref dc current consumption in conversion mode f adc = 30 mhz 3 sampling time 12-bit resolution - 300 500 a f adc = 30 mhz 480 sampling time 12-bit resolution --tbda i dda (5) adc v dda dc current consumption in conversion mode f adc = 30 mhz 3 sampling time 12-bit resolution -1.61.8 ma f adc = 30 mhz 480 sampling time 12-bit resolution --tbd 1. tbd stands for ?to be defined?. 2. if an inverted reset signal is applied to pdr_on, this value can be lowered to 1.7 v when the device operates in a reduced temperature range (0 to 70 c). 3. it is recommended to maintain the voltage difference between v ref+ and v dda below 1.8 v. 4. v dda -v ref+ < 1.2 v. 5. based on characterization, not tested in production. 6. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 7. r adc maximum value is given for v dd =1.8 v, and minimum value for v dd =3.3 v. 8. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 65 . table 65. adc characteristics (1) (continued) symbol parameter conditions min typ max unit
electrical characteristics stm32f405xx, stm32f407xx 120/167 doc id 022152 rev 2 equation 1: r ain max formula the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. a note: adc accuracy vs. negative injection current: injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. any positive injectio n current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.16 does not affect the adc accuracy. table 66. adc accuracy at f adc = 30 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 60 mhz, f adc = 30 mhz, r ain < 10 k , v dda = 1.8 (3) to 3.6 v 3. if an inverted reset signal is applied to pdr_on, th is value can be lowered to 1.7 v when the device operates in a reduced temper ature range (0 to 70 c). 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 r ain k0.5 ? () f adc c adc 2 n 2 + () ln -------------------------------------------------------------- r adc ? =
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 121/167 figure 47. adc accura cy characteristics 1. see also ta b l e 6 6 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum dev iation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual tr ansition and the end point correlation line. figure 48. typical connection diagram using the adc 1. refer to ta b l e 6 5 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion ac curacy. to remedy this, f adc should be reduced. % / % ' , 3" )$%!, % 4 % $ % , 6 $$! 6 33! aic 6 2%& ordependingonpackage = 6 $$! ;,3" )$%!, a i175 3 4 s tm 3 2f v dd ainx i l 1 a 0.6 v v t r ain (1) c p a r as itic v ain 0.6 v v t r adc (1) c adc (1) 12- b it converter sa mple a nd hold adc converter
electrical characteristics stm32f405xx, stm32f407xx 122/167 doc id 022152 rev 2 general pcb design guidelines power supply decoupling should be performed as shown in figure 49 or figure 50 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 49. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176. v ref+ is also available on lqfp100, lqfp144, and lqfp176. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . figure 50. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176. v ref+ is also available on lqfp100, lqfp144, and lqfp176. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . v ref+ s tm 3 2f v dda v ss a /v ref- 1 f // 10 nf 1 f // 10 nf a i175 3 5 ( s ee note 1) ( s ee note 1) v ref+ /v dda s tm 3 2f 1 f // 10 nf v ref? /v ss a a i175 3 6 ( s ee note 1) ( s ee note 1)
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 123/167 5.3.21 temperature sen sor characteristics 5.3.22 v bat monitoring characteristics 5.3.23 embedded reference voltage the parameters given in ta bl e 6 9 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 1 1 . table 67. ts characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 mv/c v 25 (1) voltage at 25 c - 0.76 v t start (2) startup time - 6 10 s t s_temp (3)(2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. based on characterization, not tested in production. 2. guaranteed by design, not tested in production. 3. shortest sampling time can be determined in the application by multiple iterations. table 68. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) error on q ?1 - +1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design, not tested in production. 2. shortest sampling time can be determined in the application by multiple iterations. table 69. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage 10 - - s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3 v - 3 5 mv t coeff (2) temperature coefficient - 30 50 ppm/c t start (2) startup time - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design, not tested in production.
electrical characteristics stm32f405xx, stm32f407xx 124/167 doc id 022152 rev 2 5.3.24 dac electrical characteristics table 70. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 1.8 (1) -3.6 v v ref+ reference supply voltage 1.8 (1) -3.6vv ref+ v dda v ssa ground 0 - 0 v r load (2) resistive load with buffer on 5 - - k r o (2) impedance output with buffer off -- 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.8 v dac_out max (2) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (2) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off --v ref+ ? 1lsb v i vref+ (3) dac dc v ref current consumption in quiescent mode (standby mode) - 170 240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs -50 75 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda (3) dac dc vdda current consumption in quiescent mode (standby mode) - 280 380 a with no load, middle code (0x800) on the inputs - 475 625 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (3) differential non linearity difference between two consecutive code-1lsb) -- 0.5 lsb given for the dac in 10-bit configuration. -- 2 lsb given for the dac in 12-bit configuration.
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 125/167 inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) -- 1 lsb given for the dac in 10-bit configuration. -- 4 lsb given for the dac in 12-bit configuration. offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) -- 10 mv given for the dac in 12-bit configuration -- 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v -- 12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (3) gain error - - 0.5 % given for the dac in 12-bit configuration t settling (3) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 4lsb -3 6 s c load 50 pf, r load 5 k thd (3) total harmonic distortion buffer on -- - db c load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1 ms/s c load 50 pf, r load 5 k t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) -6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - ?67 ?40 db no r load , c load = 50 pf 1. if an inverted reset signal is applied to pdr_on, this value can be lowered to 1.7 v when the device operates in a reduced temperature range (0 to 70 c). 2. guaranteed by design, not tested in production. 3. guaranteed by characterizati on, not tested in production. table 70. dac characteristics (continued) symbol parameter min typ max unit comments
electrical characteristics stm32f405xx, stm32f407xx 126/167 doc id 022152 rev 2 figure 51. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 5.3.25 fsmc characteristics asynchronous waveforms and timings figure 52 through figure 55 represent asynchronous waveforms and ta b l e 7 1 through ta bl e 7 4 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: addresssetuptime = 1 addressholdtime = 0x1 datasetuptime = 0x1 busturnaroundduration = 0x0 in all timing tables, the t hclk is the hclk clock period. r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 127/167 figure 52. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 71. asynchronous non-multiplexed sram/psram/nor read timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 2t hclk ?0.5 2 t hclk +1 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 0.5 3 ns t w(noe) fsmc_noe low time 2t hclk ?2 2t hclk + 2 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 4.5 ns t h(a_noe) address hold time after fsmc_noe high 4 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1.5 ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0 - ns t su(data_ne) data to fsmc_nex high setup time t hclk +4 - ns t su(data_noe) data to fsmc_noex high setup time t hclk +4 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 2 ns t w(nadv) fsmc_nadv low time - t hclk ns $ata &3-#?.% &3-#?.",;= &3-#?$;= t v",?.% t h$ata?.% &3-#?./% !ddress &3-#?!;= t v!?.% &3-#?.7% t su$ata?.% t w.% aic w./% t t v./%?.% t h.%?./% t h$ata?./% t h!?./% t h",?./% t su$ata?./% &3-#?.!$6 t v.!$6?.% t w.!$6
electrical characteristics stm32f405xx, stm32f407xx 128/167 doc id 022152 rev 2 figure 53. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 72. asynchronous non-multiplexed sram/psram/nor write timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk 3t hclk + 4 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk ?0.5 t hclk +0.5 ns t w(nwe) fsmc_nwe low time t hclk ?1 t hclk +2 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ?1 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t h(a_nwe) address hold time after fsmc_nwe high t hclk ? 2 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1 - ns t v(data_ne) data to fsmc_nex low to data valid - t hclk +3 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk ?1 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 2 ns t w(nadv) fsmc_nadv low time - t hclk +0.5 ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:0] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(data_ne) t w(ne) ai14990 fsmc_nadv (1) t v(nadv_ne) t w(nadv)
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 129/167 figure 54. asynchronous multiplexed psram/nor read waveforms table 73. asynchronous multiplexed psram/nor read timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk ?1 3t hclk +1 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 2t hclk ?0.5 2t hclk +0.5 ns t w(noe) fsmc_noe low time t hclk ?1 t hclk +1 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 3 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 1 2 ns t w(nadv) fsmc_nadv low time t hclk ? 2 t hclk +1 ns t h(ad_nadv) fsmc_ad(adress) valid hold time after fsmc_nadv high) t hclk -ns t h(a_noe) address hold time after fsmc_noe high t hclk ?1 - ns t h(bl_noe) fsmc_bl time after fsmc_noe high 0 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 2 ns t su(data_ne) data to fsmc_nex high setup time t hclk +4 - ns t su(data_noe) data to fsmc_noe high setup time t hclk +4 - ns t h(data_ne) data hold time afte r fsmc_nex high 0 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns nbl data fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_ne) address fsmc_a[25:16] t v(a_ne) fsmc_nwe t v(a_ne) ai14892b address fsmc_nadv t v(nadv_ne) t w(nadv) t su(data_ne) t h(ad_nadv) fsmc_ne fsmc_noe t w(ne) t w(noe) t v(noe_ne) t h(ne_noe) t h(a_noe) t h(bl_noe) t su(data_noe) t h(data_noe)
electrical characteristics stm32f405xx, stm32f407xx 130/167 doc id 022152 rev 2 figure 55. asynchronous multiplexed psram/nor write waveforms table 74. asynchronous multiplexed psram/nor write timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(ne) fsmc_ne low time 4t hclk ?0.5 4t hclk +3 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk ?0.5 t hclk -0.5 ns t w(nwe) fsmc_nwe low tim e 2t hclk ?0.5 2t hclk +3 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk -ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 1 2 ns t w(nadv) fsmc_nadv low time t hclk ? 2 t hclk + 1 ns t h(ad_nadv) fsmc_ad(adress) valid hold time after fsmc_nadv high) t hclk ?2 - ns t h(a_nwe) address hold time after fsmc_nwe high t hclk -ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ?2 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1.5 ns t v(data_nadv) fsmc_nadv high to data valid - t hclk ?0.5 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk -ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14891b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv)
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 131/167 synchronous waveforms and timings figure 56 through figure 59 represent synchronous waveforms and ta bl e 7 6 through ta bl e 7 8 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: burstaccessmode = fsmc_burstaccessmode_enable; memorytype = fsmc_memorytype_cram; writeburst = fsmc_writeburst_enable; clkdivision = 1; (0 is not supported, see the stm32f40xxx/41xxx reference manual) datalatency = 1 for nor flash; datalatency = 0 for psram in all timing tables, the t hclk is the hclk clock period (with maximum fsmc_clk = 60 mhz). figure 56. synchronous multiplexed nor/psram read timings &3-#?#,+ &3-#?.%x &3-#?.!$6 &3-#?!;= &3-#?./% &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+, !)6 t d#,+, ./%, t d#,+, ./%( t d#,+, !$6 t d#,+, !$)6 t su!$6 #,+( t h#,+( !$6 t su!$6 #,+( t h#,+( !$6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 aig
electrical characteristics stm32f405xx, stm32f407xx 132/167 doc id 022152 rev 2 table 75. synchronous multiplexed nor/psram read timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 2 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 2 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 2 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 0 - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - 0 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 2 - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - 4.5 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 - ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high 6 - ns t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high 0 - ns
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 133/167 figure 57. synchronous multiplexed psram write timings table 76. synchronous multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 1 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 0 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 0 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 8 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 0.5 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 0 - ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 - ns t d(clkl-data) fsmc_a/d[15:0] valid data after fsmc_clk low - 3 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 0 - ns &3-#?#,+ &3-#?.%x &3-#?.!$6 &3-#?!;= &3-#?.7% &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, .",( t d#,+, !$6 t d#,+, !$)6 t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aig t d#,+, $ata &3-#?.",
electrical characteristics stm32f405xx, stm32f407xx 134/167 doc id 022152 rev 2 figure 58. synchronous non-multiplexed nor/psram read timings table 77. synchronous non-multiplexed nor/psram read timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk ?0.5 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 0 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 2 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 3 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 2 - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - 0.5 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1.5 - ns t su(dv-clkh) fsmc_d[15:0] valid data before fsmc_clk high 6 - ns t h(clkh-dv) fsmc_d[15:0] valid data after fsmc_clk high 3 - ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?./% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+, ./%, t d#,+, ./%( t su$6 #,+( t h#,+( $6 t su$6 #,+( t h#,+( $6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 aif &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6(
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 135/167 figure 59. synchronous non-multiplexed psram write timings table 78. synchronous non-multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. based on characterization , not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 1 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 7 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 6 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 6 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 2 - ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low - 3 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 3 - ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?.7% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aig &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( t d#,+, $ata &3-#?.", t d#,+, .",(
electrical characteristics stm32f405xx, stm32f407xx 136/167 doc id 022152 rev 2 pc card/compactflash controller waveforms and timings figure 60 through figure 65 represent synchronous waveforms, and ta bl e 7 9 and ta b l e 8 0 provide the corresponding timings. the results shown in this table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x04; com.fsmc_waitsetuptime = 0x07; com.fsmc_holdsetuptime = 0x04; com.fsmc_hizsetuptime = 0x00; att.fsmc_setuptime = 0x04; att.fsmc_waitsetuptime = 0x07; att.fsmc_holdsetuptime = 0x04; att.fsmc_hizsetuptime = 0x00; io.fsmc_setuptime = 0x04; io.fsmc_waitsetuptime = 0x07; io.fsmc_holdsetuptime = 0x04; io.fsmc_hizsetuptime = 0x00; tclrsetuptime = 0; tarsetuptime = 0. in all timing tables, the t hclk is the hclk clock period. figure 60. pc card/compactflash controller waveforms for common memory read access 1. fsmc_nce4_2 remains high (inactive during 8-bit access. fsmc_nwe t w(noe) fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 (1) fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nce4_1-noe) t su(d-noe) t h(noe-d) t v(ncex-a) t d(nreg-ncex) t d(niord-ncex) t h(ncex-ai) t h(ncex-nreg) t h(ncex-niord) t h(ncex- niowr ) ai14895b
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 137/167 figure 61. pc card/compactflash controller waveforms for common memory write access t d(nce4_1-nwe) t w(nwe) t h(nwe-d) t v(nce4_1-a) t d(nreg-nce4_1) t d(niord-nce4_1) t h(nce4_1-ai) memxhiz =1 t v(nwe-d) t h(nce4_1-nreg) t h(nce4_1-niord) t h(nce4_1-niowr) ai14896b fsmc_nwe fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) t d(d-nwe) fsmc_nce4_2 high
electrical characteristics stm32f405xx, stm32f407xx 138/167 doc id 022152 rev 2 figure 62. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). t d(nce4_1-noe) t w(noe) t su(d-noe) t h(noe-d) t v(nce4_1-a) t h(nce4_1-ai) t d(nreg-nce4_1) t h(nce4_1-nreg) ai14897b fsmc_nwe fsmc_noe fsmc_d[15:0] (1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(noe-nce4_1) high
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 139/167 figure 63. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hi-z). figure 64. pc card/compactflash controller waveforms for i/o space read access t w(nwe) t v(nce4_1-a) t d(nreg-nce4_1) t h(nce4_1-ai) t h(nce4_1-nreg) t v(nwe-d) ai14898b fsmc_nwe fsmc_noe fsmc_d[7:0](1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) high t d(nce4_1-nwe) t d(niord-nce4_1) t w(niord) t su(d-niord) t d(niord-d) t v(ncex-a) t h(nce4_1-ai) ai14899b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord
electrical characteristics stm32f405xx, stm32f407xx 140/167 doc id 022152 rev 2 figure 65. pc card/compactflash controller waveforms for i/o space write access t d.#%? .)/72 t w.)/72 t v.#%x ! t h.#%? !) t h.)/72 $ !44x(): t v.)/72 $ aic &3-#?.7% &3-#?./% &3-#?$;= &3-#?!;= &3-#?.#%? &3-#?.#%? &3-#?.2%' &3-#?.)/72 &3-#?.)/2$ table 79. switching characteristics for pc card/cf read and write cycles in attribute/common space (1)(2) symbol parameter min max unit t v(ncex-a) fsmc_ncex low to fsmc_ay valid - 0 ns t h(ncex_ai) fsmc_ncex high to fsmc_ax invalid 4 - ns t d(nreg-ncex) fsmc_ncex low to fsmc_nreg valid - 3.5 ns t h(ncex-nreg) fsmc_ncex high to fsmc_nreg invalid t hclk +4 - ns t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk +0.5 ns t d(ncex-noe) fsmc_ncex low to fsmc_noe low - 5t hclk +0.5 ns t w(noe) fsmc_noe low width 8t hclk ?1 8t hclk +1 ns t d(noe_ncex) fsmc_noe high to fsmc_ncex high 5t hclk +2.5 - ns t su (d-noe) fsmc_d[15:0] valid data before fsmc_noe high 4.5 - ns t h(n0e-d) fsmc_n0e high to fsmc_d[15:0] invalid 3 - ns t w(nwe) fsmc_nwe low width 8t hclk ?0.5 8t hclk + 3 ns t d(nwe_ncex) fsmc_nwe high to fsmc_ncex high 5t hclk ?1 -ns t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk + 1 ns t v(nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - 0 ns t h (nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 8t hclk ?1 - ns t d (d-nwe) fsmc_d[15:0] valid before fsmc_nwe high 13t hclk ?1 - ns 1. c l = 30 pf. 2. based on characterization, not tested in production.
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 141/167 nand controller waveforms and timings figure 66 through figure 69 represent synchronous waveforms, and ta bl e 8 1 and ta b l e 8 2 provide the corresponding timings. the results shown in this table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x01; com.fsmc_waitsetuptime = 0x03; com.fsmc_holdsetuptime = 0x02; com.fsmc_hizsetuptime = 0x01; att.fsmc_setuptime = 0x01; att.fsmc_waitsetuptime = 0x03; att.fsmc_holdsetuptime = 0x02; att.fsmc_hizsetuptime = 0x01; bank = fsmc_bank_nand; memorydatawidth = fsmc_memorydatawidth_16b; ecc = fsmc_ecc_enable; eccpagesize = fsmc_eccpagesize_512bytes; tclrsetuptime = 0; tarsetuptime = 0. in all timing tables, the t hclk is the hclk clock period. table 80. switching characteristics for pc card/cf read and write cycles in i/o space (1)(2) symbol parameter min max unit t w(niowr) fsmc_niowr low width 8t hclk ?1 - ns t v(niowr-d) fsmc_niowr low to fsmc_d[15:0] valid - 5t hclk ? 1 ns t h(niowr-d) fsmc_niowr high to fsmc_d[15:0] invalid 8t hclk ? 2 - ns t d(nce4_1-niowr) fsmc_nce4_1 low to fsmc_niowr valid - 5t hclk + 2.5 ns t h(ncex-niowr) fsmc_ncex high to fsmc_niowr invalid 5t hclk ?1.5 - ns t d(niord-ncex) fsmc_ncex low to fsmc_niord valid - 5t hclk + 2 ns t h(ncex-niord) fsmc_ncex high to fsmc_niord) valid 5t hclk ? 1.5 - ns t w(niord) fsmc_niord low width 8t hclk ?0.5 - ns t su(d-niord) fsmc_d[15:0] valid before fsmc_niord high 9 - ns t d(niord-d) fsmc_d[15:0] valid after fsmc_niord high 0 - ns 1. c l = 30 pf. 2. based on characterization, not tested in production.
electrical characteristics stm32f405xx, stm32f407xx 142/167 doc id 022152 rev 2 figure 66. nand controller waveforms for read access figure 67. nand controller waveforms for write access &3-#?.7% &3-#?./%.2% &3-#?$;= t su$ ./% t h./% $ aic !,%&3-#?! #,%&3-#?! &3-#?.#%x t d!,% ./% t h./% !,% t h.7% $ t v.7% $ aic &3-#?.7% &3-#?./%.2% &3-#?$;= !,%&3-#?! #,%&3-#?! &3-#?.#%x t d!,% .7% t h.7% !,%
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 143/167 figure 68. nand controller waveforms for common memo ry read access figure 69. nand controller waveforms for common memory write access table 81. switching characteristics for nand flash read cycles (1) 1. c l = 30 pf. symbol parameter min max unit t w(n0e) fsmc_noe low width 4t hclk ? 0.5 4t hclk + 3 ns t su(d-noe) fsmc_d[15-0] valid data before fsmc_noe high 10 - ns t h(noe-d) fsmc_d[15-0] valid data after fsmc_noe high 0 - ns t d(ale-noe) fsmc_ale valid before fsmc_noe low - 3t hclk ns t h(noe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk ? 2 - ns &3-#?.7% &3-#?. /% &3-#?$;= t w./% t su$ ./% t h./% $ aic !,%&3-#?! #,%&3-#?! &3-#?.#%x t d!,% ./% t h./% !,% t w.7% t h.7% $ t v.7% $ aic &3-#?.7% &3-#?. /% &3-#?$;= t d$ .7% !,%&3-#?! #,%&3-#?! &3-#?.#%x t d!,% ./% t h./% !,%
electrical characteristics stm32f405xx, stm32f407xx 144/167 doc id 022152 rev 2 5.3.26 camera interface (dcmi) timing specifications 5.3.27 sd/sdio mmc ca rd host interface (sdio) characteristics unless otherwise specified, the parameters given in ta bl e 8 4 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta b l e 1 1 . refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (d[7:0], cmd, ck). figure 70. sdio high-speed mode table 82. switching characterist ics for nand flash write cycles (1) 1. c l = 30 pf. symbol parameter min max unit t w(nwe) fsmc_nwe low width 4t hclk ?1 4t hclk + 3 ns t v(nwe-d) fsmc_nwe low to fsmc_d[15-0] valid - 0 ns t h(nwe-d) fsmc_nwe high to fsmc_d[15-0] invalid 3t hclk ?2 - ns t d(d-nwe) fsmc_d[15-0] valid before fsmc_nwe high 5t hclk ?3 - ns t d(ale-nwe) fsmc_ale valid before fsmc_nwe low - 3t hclk ns t h(nwe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk ?2 - ns table 83. dcmi characteristics symbol parameter conditions min max unit frequency ratio dcmi_pixclk/ f hclk (1) 1. maximum value of dcmi_pixclk = 54 mhz. 0.4 t w(ckh) ck d, cmd (output) d, cmd (input) t c t w(ckl) t ov t oh t isu t ih t f t r ai14887
stm32f405xx, stm32f407xx electrical characteristics doc id 022152 rev 2 145/167 figure 71. sd default mode 5.3.28 rtc characteristics table 84. sd / mmc characteristics (1) 1. tbd stands for ?to be defined?. symbol parameter conditions min max unit f pp clock frequency in data transfer mode c l 30 pf tbd tbd mhz - sdio_ck/f pclk2 frequency ratio - - tbd - t w(ckl) clock low time, f pp = 16 mhz c l 30 pf tbd - ns t w(ckh) clock high time, f pp = 16 mhz c l 30 pf tbd - t r clock rise time c l 30 pf - tbd t f clock fall time c l 30 pf - tbd cmd, d inputs (referenced to ck) t isu input setup time c l 30 pf tbd - ns t ih input hold time c l 30 pf tbd - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time c l 30 pf - tbd ns t oh output hold time c l 30 pf tbd - cmd, d outputs (referenced to ck) in sd default mode (2) 2. refer to sdio_clkcr, the sdi clock control register to control the ck output. t ovd output valid default time c l 30 pf - tbd ns t ohd output hold default time c l 30 pf tbd - ck d, cmd (output) t ovd t ohd ai14888 table 85. rtc characteristics symbol parameter conditions min max unit - f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4--
package characteristics stm32f405xx, stm32f407xx 146/167 doc id 022152 rev 2 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stm32f405xx, stm32f407xx package characteristics doc id 022152 rev 2 147/167 figure 72. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline (1) figure 73. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. a a2 a1 c l1 l e e1 d d1 e b ai14398b 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 86. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 12.000 0.4724 d1 10.000 0.3937 e 12.000 0.4724 e1 10.000 0.3937 e 0.500 0.0197 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f405xx, stm32f407xx 148/167 doc id 022152 rev 2 figure 74. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline (1) figure 75. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 table 87. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 12.000 0.4724 e 15.80v 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 12.000 0.4724 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f405xx, stm32f407xx package characteristics doc id 022152 rev 2 149/167 figure 76. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline (1) figure 77. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 a 1 36 37 72 73 108 109 144 table 88. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.874 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 17.500 0.689 e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 17.500 0.6890 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f405xx, stm32f407xx 150/167 doc id 022152 rev 2 figure 78. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline 1. drawing is not to scale. s e a ting pl a ne c a2 a4 a 3 c ddd a1 a a b e f d f e e r eee m cab c fff (176 ba ll s ) ? b m ? ? a0e7_me b a ll a1 a 15 1 table 89. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data symbol millimeters inches (1) min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.002 0.0031 0.0043 a2 0.400 0.450 0.500 0. 0157 0.0177 0.0197 a3 0.130 0.0051 a4 0.270 0.320 0.370 0. 0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 0.600 0.650 0.700 0.0236 0.0256 0.0276 f 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f405xx, stm32f407xx package characteristics doc id 022152 rev 2 151/167 figure 79. lqfp176 24 x 24 mm, 144-pin low-profile quad flat package outline 1. drawing is not to scale. ccc c s e a ting pl a ne c aa2 a1 c 0.25 mm g au ge pl a ne hd d a1 l l1 k 8 9 88 ehe 45 44 e 1 176 pin 1 identific a tion b 1 33 1 3 2 1t_me zd ze table 90. lqfp176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 a2 1.350 1.450 0.0531 0.0060 b 0.170 0.270 0.0067 0.0106 c 0.090 0.200 0.0035 0.0079 d 23.900 24.100 0.9409 0.9488 e 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 hd 25.900 26.100 1.0200 1.0276 he 25.900 26.100 1.0200 1.0276 l 0.450 0.750 0.0177 0.0295 l1 1.000 0.0394 zd 1.250 0.0492 ze 1.250 0.0492 ccc 0.080 0.0031 k0 7 0 7 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f405xx, stm32f407xx 152/167 doc id 022152 rev 2 6.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org. table 91. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 46 c/w thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 43 thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 40 thermal resistance junction-ambient lqfp176 - 24 24 mm / 0.5 mm pitch 38 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.65 mm pitch 39
stm32f405xx, stm32f407xx part numbering doc id 022152 rev 2 153/167 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 92. ordering information scheme example: stm32 f 405 r e t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 405 = stm32f40x, connectivity, usb otg fs/hs, 407= stm32f40x, connectivity, usb otg fs/hs, camera interface, ethernet pin count r = 64 pins or 66 pins v = 100 pins z = 144 pins i = 176 pins flash memory size c = 256 kbytes of flash memory e = 512 kbytes of flash memory f = 768 kbytes of flash memory g = 1024 kbytes of flash memory package t = lqfp h = ufbga temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and reel
application block diagrams stm32f405xx, stm32f407xx 154/167 doc id 022152 rev 2 appendix a application block diagrams a.1 main applications versus package ta bl e 9 3 gives examples of configurations for each package. table 93. main applications versus package for stm32f407xx microcontrollers (1) 64 pins 100 pins 144 pins 176 pins config 1 config 2 config 3 config 1 config 2 config 3 config 4 config 1 config 2 config 3 config 4 config 1 config 2 usb 1 otg fs xxxxxx - x x x fs xxxxxxxxxxxx usb 2 hs ulpi ---x---xx xx otgfs---x xx xx fs - - - xxxxxxxxxx ethernet mii -----xx xxxx rmii---- xxxxxxxxx spi/i2s2 spi/i2s3 - x - - xxxxxxxxx sdio sdio sdio or dcmi sdio or dcmi - sdio or dcmi sdio or dcmi sdio or dcmi x sdio or dcmi x sdio or dcmi xxx dcmi 8bits data - x x xxx 10bits data - x x xxx 12bits data - x x xxx 14bits data ------- x xxx fsmc nor/ ram muxed - - - xxxxxxxxxx nor/ ram - - - xxxxxx nand - - - x x x* 22 x* 19 xx* 19 x* 22 x* 19 x* 22 x* 22 cf ------- xxxxxx can - xx - xxx - - xx - x 1. x* y : fsmc address limited to ?y?.
stm32f405xx, stm32f407xx application block diagrams doc id 022152 rev 2 155/167 a.2 application exampl e with regulator off figure 80. regulator off/internal reset on 1. this mode is available only on ufbga176 package. figure 81. regulator off/internal reset off 1. this mode is available only on ufbga176 package. "90!33?2%' 6#!0? ai 6#!0? 0! .234 !pplicationresetsignal optional 6 6 $$ 0ower downresetrisen after6#!0?6#!0?stabilization "90!33?2%' 6#!0? 6#!0? 0! 6 6 $$ 0ower downresetrisen before6#!0?6#!0?stabilization .234 6$$ 6$$ !pplicationreset signaloptional 6 #!0?monitoring %xtresetcontrolleractive when6 #!0? 6 0$2?/. 0$2?/. "90!33?2%' 6#!0? ai 6#!0? .234 6 6$$ 6$$ 6 $$ monitoring %xtresetcontrolleractive when6 $$ 6 or6 #!0? 6 #!0? 6 6$$ 0$2?/. 6$$ 0!
application block diagrams stm32f405xx, stm32f407xx 156/167 doc id 022152 rev 2 a.3 usb otg full speed (f s) interface solutions figure 82. usb controller configured as peripheral-only and used in full speed mode 1. external voltage regulator only needed when building a v bus powered device. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. figure 83. usb controller configured as host-only and used in full speed mode 1. the current limiter is required only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. 34-&xx 6to6 $$ 6olatgeregulator 6 $$ 6"53 $0 6 33 0!0" 0!0" 0!0" 53" 3td " connector $- /3#?). /3#?/54 -36 34-&xx 6 $$ 6"53 $0 6 33 53" 3td ! connector $- '0)/)21 '0)/ %. /vercurrent 60wr /3#?). /3#?/54 -36 #urrentlimiter powerswitch 0!0" 0!0" 0!0"
stm32f405xx, stm32f407xx application block diagrams doc id 022152 rev 2 157/167 figure 84. usb controller configured in dual mode and used in full speed mode 1. external voltage regulator only needed when building a v bus powered device. 2. the current limiter is required only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 3. the id pin is required in dual role only. 4. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. 34-&xx 6 $$ 6"53 $0 6 33 0!0" 0!0" 0!0" 53" micro !"connector $- '0)/)21 '0)/ %. /vercurrent 60wr 6to6 $$ voltageregulator 6 $$ )$ 0!0" /3#?). /3#?/54 -36 #urrentlimiter powerswitch
application block diagrams stm32f405xx, stm32f407xx 158/167 doc id 022152 rev 2 a.4 usb otg high speed (hs) interface solutions figure 85. usb controller configured as peripheral, host, or dual-mode and used in high speed mode 1. it is possible to use mco1 or mco2 to save a crys tal. it is however not mandato ry to clock the stm32f40x with a 24 or 26 mhz crystal when using usb hs. the above figure only shows an example of a possible connection. 2. the id pin is required in dual role only. $0 34-&xx $- 6 "53 6 33 $- $0 )$ 53" 53"(3 /4'#trl &30(9 5,0) (ighspeed /4'0(9 5,0)?#,+ 5,0)?$;= 5,0)?$)2 5,0)?340 5,0)?.84 notconnected connector -#/or-#/ or-(z84 0,, 84 8) -36
stm32f405xx, stm32f407xx application block diagrams doc id 022152 rev 2 159/167 a.5 complete audio player solutions two solutions are offe red, illustrated in figure 86 and figure 87 . figure 86 shows storage media to audio dac/amplifier streaming using a software codec. this solution implements an audio crystal to provide audio class i 2 s accuracy on the master clock (0.5% error maximum, see the serial peripheral interface section in the reference manual for details). figure 86. complete audio player solution 1 figure 87 shows storage media to audio codec/amplifier streaming with sof synchronization of input/output audio streaming using a hardware codec. figure 87. complete audio player solution 2 #ortex -&core upto-(z /4' host mode 0(9 30) 30) '0)/ )3 84!, -(z or-(z 53" -ass storage device --# 3$#ard ,#$ touch screen #ontrol buttons $!# !udio ampli &ile 3ystem 0rogrammemory !udio #/$%# 5ser application 34-&xx -36 #ortex -&core upto-(z /4' 0(9 30) 30) '0)/ )3 53" -ass storage device --# 3$#ard ,#$ touch screen #ontrol buttons !udio ampli &ile 3ystem 0rogrammemory !udio #/$%# 5ser application 34-&xx -36 3/& 3/&synchronizationofinputoutput audiostreaming 84!, -(z or-(z
application block diagrams stm32f405xx, stm32f407xx 160/167 doc id 022152 rev 2 figure 88. audio player solution using pll, plli2s, usb and 1 crystal figure 89. audio pll (plli2s) providing accurate i2s clock /4' -(z 0(9 84!, -(z or-(z 34-&xx -36 )3 accuracy $!# !udio ampli -#,+out 3#,+ -#/ -#/ 0,,)3 x. 0,, x. /3# $iv by- $iv by0 $iv by1 #ortex -&core upto-(z $iv by2 -#,+ in -#/02% -#/02% i2 s ctl i2 s _mck = 256 f s audio 11.2 8 96 mhz for 44.1 khz 12.2 88 0 mhz for 4 8 .0 khz i2 s _mck plli2 s /m m=1,2, 3 ,..,64 1 mhz 192 to 4 3 2 mhz n=192,194,..,4 3 2 i2 s com_ck ph as ec vco /n /r clkin ph as e lock detector r=2, 3 ,4,5,6,7 i2 s d=2, 3 ,4.. 129 a i16041 b
stm32f405xx, stm32f407xx application block diagrams doc id 022152 rev 2 161/167 figure 90. master clock (mck) used to drive the external audio dac 1. i2s_sck is the i2s serial clock to the exter nal audio dac (not to be confused with i2s_ck). figure 91. master clock (mck) not used to drive the external audio dac 1. i2s_sck is the i2s serial clock to the exter nal audio dac (not to be confused with i2s_ck). i2 s _ck i2 s controller i2 s _mck = 256 f s audio = 11.2 8 96 mhz for f s audio = 44.1 khz = 12.2 88 0 mhz for f s audio = 4 8 .0 khz /(2 x 16) / 8 /i2 s d f s audio i2 s _ s ck (1) = i2 s _mck/ 8 for 16- b it s tereo for 16- b it s tereo /(2 x 3 2) /4 for 3 2- b it s tereo f s audio 2, 3 ,4,..,129 = i2 s _mck/4 for 3 2- b it s tereo a i16042 i2 s com_ck i2 s controller /(2 x 16) /i2 s d f s audio i2 s _ s ck (1) for 16- b it s tereo /(2 x 3 2) for 3 2- b it s tereo f s audio a i16042
application block diagrams stm32f405xx, stm32f407xx 162/167 doc id 022152 rev 2 a.6 ethernet interface solutions figure 92. mii mode using a 25 mhz crystal 1. f hclk must be greater than 25 mhz. 2. pulse per second when using ieee1588 ptp optional signal. figure 93. rmii with a 50 mhz oscillator 1. f hclk must be greater than 25 mhz. -#5 %thernet -!# %thernet 0(9 0,, (#,+ 84 0(9?#,+-(z -))?28?#,+ -))?28$;= -))?28?$6 -))?28?%2 -))?48?#,+ -))?48?%. -))?48$;= -))?#23 -))?#/, -$)/ -$# (#,+ 003?/54 84!, -(z 34- /3# 4)- 4imestamp comparator 4imer input trigger )%%%040 -)) pins -))-$# pins -36 -#/-#/ -#5 %thernet -!# %thernet 0(9 0,, (#,+ 84 0(9?#,+-(z 2-))?28$;= 2-))?#28?$6 2-))?2%&?#,+ 2-))?48?%. 2-))?48$;= -$)/ -$# (#,+ 34- /3# -(z 4)- 4imestamp comparator 4imer input trigger )%%%040 2-)) pins 2-))-$# pins -36 or synchronous or-(z -(z -(z
stm32f405xx, stm32f407xx application block diagrams doc id 022152 rev 2 163/167 figure 94. rmii with a 25 mhz crystal and phy with pll 1. f hclk must be greater than 25 mhz. 2. the 25 mhz (phy_clk) must be derived directly from the hse oscillator , before the pll block. -#5 %thernet -!# %thernet 0(9 0,, (#,+ 84 0(9?#,+-(z 2-))?28$;= 2-))?#28?$6 2-))?2%&?#,+ 2-))?48?%. 2-))?48$;= -$)/ -$# (#,+ 34-& 4)- 4imestamp comparator 4imer input trigger )%%%040 2-)) pins 2-))-$# pins -36 or synchronous or-(z -(z 84!, -(z /3# 0,, 2%&?#,+ -#/-#/
revision history stm32f405xx, stm32f407xx 164/167 doc id 022152 rev 2 8 revision history table 94. document revision history date revision changes 15-sep-2011 1 initial release. 24-jan-2012 2 added wlcsp90 package on cover page. renamed usart4 and usart5 into uart4 and uart5, respectively. updated number of usb otg hs and fs in table 2: stm32f405xx and stm32f407xx: features and peripheral counts . updated figure 3: compatible board design between stm32f10xx/stm32f2xx/stm3 2f4xx for lqfp144 package and figure 4: compatible board design between stm32f2xx and stm32f4xx for lqfp176 package , and removed note 1 and 2. updated section 2.2.9: flexible static memory controller (fsmc) . modified i/os used to reprogram the flash memory for can2 and usb otg fs in section 2.2.13: boot modes . updated note in section 2.2.14: power supply schemes . pdr_on no more available on lqfp100 package. updated section 2.2.16: voltage regulator . updated condition to obtain a minimum supply voltage of 1.7 v in the whole document. renamed usart4/5 to uart4/5 and added lin and irda feature for uart4 and uart5 in table 4: usart feature comparison . removed support of i2c for otg phy in section 2.2.29: universal serial bus on-the-go full-speed (otg_fs) . added table 5: legend/abbreviations used in the pinout table . table 6: stm32f40x pin and ball definitions : replaced v ss _3, v ss _4, and v ss _8 by v ss ; reformatted table 6: stm32f40x pin and ball definitions to better highlight i/o structure, and alternate functions versus additional functions; signal corresponding to lqfp100 pin 99 changed from pdr_on to v ss ; eventout added in the list of alternate functions for all i/os; adc3_in8 added as alternate function for pf10; fsmc_cle and fsmc_ale added as alternate functions for pd11 and pd12, respectively; ph10 alternate function tim15_ch1_etr renamed tim5_ch1; updated pa4 and paa5 pin type. removed otg_hs_scl, otg_hs_sda, otg_fs_intn, otg_fs_sda, otg_fs_scl alternate functions in table 6: stm32f40x pin and ball definitions and table 7: alternate function mapping . changed tcm data ram to ccm data ram in figure 15: memory map . added i vdd and i vss maximum values in ta bl e 9 : c u r r e n t characteristics . added note 1 related to f hclk , updated note 2 in table 11: general operating conditions , and added maximum power dissipation values. updated table 12: limitations depending on the operating power supply range .
stm32f405xx, stm32f407xx revision history doc id 022152 rev 2 165/167 24-jan-2012 2 (continued) added v12 in table 16: embedded reset and power control block characteristics . updated table 17: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) and table 18: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled) or ram . added figure , figure 22 , figure 23 , anhd figure 24 . updated table 19: typical and maximum current consumption in sleep mode and removed note 1. updated table 20: typical and maximum current consumptions in stop mode and table 21: typical and maximum current consumptions in standby mode , table 22: typical and maximum current consumptions in v bat mode , and table 23: switching output i/o current consumption . section : on-chip peripheral current consumption : modified conditions, and updated table 24: peripheral current consumption and note 2 . changed f hse_ext to 50 mhz and t r(hse) /t f(hse) maximum value in table 26: high-speed external user clock characteristics . added c in(lse) in table 27: low-speed external user clock characteristics . updated maximum pll input clock frequency, removed related note, and deleted jitter for mco for rmii ethernet typical value in table 32: main pll characteristics . updated maximum plli2s input clock frequency and removed related note in table 33: plli2s (audio pll) characteristics . updated section : flash memory to specify that the devices are shipped to customers with the flash memory erased. updated table 35: flash memory characteristics , and added t me in table 36: flash memory programming . updated table 39: ems characteristics , and table 40: emi characteristics . updated table 53: i 2 s characteristics updated figure 43: ulpi timing diagram and table 60: ulpi timing . added t counter and t max_count in table 48: characteristics of timx connected to the apb1 domain and table 49: characteristics of timx connected to the apb2 domain . updated table 63: dynamics characteristics: ethernet mac signals for rmii . removed usb-if certification in section : usb otg fs characteristics . table 94. document revision history (continued) date revision changes
revision history stm32f405xx, stm32f407xx 166/167 doc id 022152 rev 2 24-jan-2012 2 (continued) updated table 57: usb fs clock timing parameters and table 59: usb hs clock timing parameters updated table 65: adc characteristics . updated table 66: adc accuracy at f adc = 30 mhz . updated note 1 in table 70: dac characteristics . section 5.3.25: fsmc characteristics : updated ta b l e 7 1 to ta bl e 8 2 , changed c l value to 30 pf, and modified fsmc configuration for asynchronous timings and waveforms. updated figure 57: synchronous multiplexed psram write timings . updated table 91: package thermal characteristics . appendix a.3: usb otg full speed (fs) interface solutions : modified figure 82: usb controller configured as peripheral-only and used in full speed mode added note 2 , updated figure 83: usb controller configured as host-only and used in full speed mode and added note 2 , changed figure 84: usb controller configured in dual mode and used in full speed mode and added note 3 . appendix a.4: usb otg high speed (hs) interface solutions : removed figures usb otg hs device-only connection in fs mode and usb otg hs host-only connection in fs mode, and updated figure 85: usb controller configured as peri pheral, host, or dual-mode and used in high speed mode and added note 2 . added appendix a.6: ethernet interface solutions . table 94. document revision history (continued) date revision changes
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