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1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av october 1999 rev. 2 description the wedc syncburst - sram family employs high-speed, low- power cmos designs that are fabricated using an advanced cmos process. wedc?s 16mb syncburst srams integrate two 512k x 18 srams into a single bga package to provide 512k x 36 configuration. all synchronous inputs pass through registers controlled by a positive - edge-triggered single-clock input (clk). the synchronous inputs include all addresses, all data inputs, active low chip enable (ce), burst control inputs (adsc, adsp, adv), byte write enables (bw 0-3 ) and global write (gw). asyn- chronous inputs include the output enable (oe), clock (clk) and snooze enable (zz). there is also a burst mode input (mode) that selects between interleaved and linear burst modes. write cycles can be from one to four bytes wide, as controlled by the write control inputs. burst operation can be initiated with either address status processor (adsp) or address status controller (adsc) inputs. subsequent burst addresses can be internally generated as controlled by the burst advance input (adv). * this data sheet describes a product under development, not fully characterized, and is subject to change without notice. 512kx36 synchronous pipeline burst sram preliminary* features n fast clock speed: 200, 166, 150 & 133mhz n fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns n fast oe access times: 2.5ns, 3.5ns, 3.8ns 4.0ns n available with 1.5ns setup and 0.5ns hold times or 1.0ns setup and hold times. n single +3.3v power supply (v dd ) n seperate +3.3v or +2.5v isolated output buffer supply (v ddq ) n snooze mode for reduced-power standby n single-cycle deselect n common data inputs and data outputs n individual byte write control and globa write n clock-controlled and registered addresses, data i/os and control signals n burst control (interleaved or linear burst) n packaging: 119-bump bga package n low capacitive bus loading n available in either single ce or three ce configuration n ieee 1149.1 jtag compatible boundary scan (available on single ce version only) fig. 1 block diagram pin configuration (top view) 123 4 5 67 a v ddq sa sa adsp sa sa v ddq b nc sa sa adsc sa sa nc c nc sa sa v dd sa sa nc/ce 2 * d dq c dqp c v ss nc v ss dqp b dq b e dq c dq c v ss ce v ss dq b dq b f v ddq dq c v ss oe v ss dq b v ddq g dq c dq c bw c adv bw b dq b dq b h dq c dq c v ss gw v ss dq b dq b j v ddq v dd nc v dd nc v dd v ddq k dq d dq d v ss clk v ss dq a dq a l dq d dq d bw d nc bw a dq a dq a m v ddq dq d v ss bwe v ss dq a v ddq n dq d dq d v ss sa1 v ss dq a dq a p dq d dqp d v ss sa0 v ss dqp a dq a r nc sa mode v dd nc sa nc/ce 2 * t nc nc sa sa sa nc zz u v ddq tmd tdi tck tdo nc v ddq dq b , dqp b dq a , dqp a gw adv sa clk adsp adsc oe bwe ce mode zz bw a bw b 512k x 18 ssram dq d , dqp d dq c , dqp c 512k x 18 ssram bw c bw d * enable on pins c7 and r7 are options for the three ce density only.
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av pin description x36 symbol type description clk input pulse the system clock input. all of the ssram inputs are sampled on the rising edge of the clock. 4p sa 0 input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of 4n sa 1 clk. 2a, 2c, 2r, 2b sa 3a, 3b, 3c, 3t 4t, 5a, 5b, 5c, 5t, 6a, 6b, 6c, 6r 5l bwa input synchronous byte write enables: these active low inputs allow individual bytes to be written and must meet the setup 5g bwb and hold times around the rising edge of clk. a byte write enable is low for a write cycle and high for a read cycle. 3g bwc 3l bwd bwa controls dqa?s and dqpa; bwb controls dqb?s and dqpb; bwc controls dqc?s and dqpc; bwd controls dqd?s and dqpd. 4m bwe input byte write enable: this active low input permits byte write operations and must meet the setup and hold times around the rising edge of clk. 4h gw input global write: this active low input allows a full 36- bit write to occur independent of the bwe and bwx lines and must meet the setup and hold times around the rising edge of clk. 4k clk input clock: this signal registers the address, data, chip enable, byte write enables and burst control inputs on its risin g edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. 4e ce input synchronous chip enable: this active low input is used to enable the device and conditions the internal use of adsp. ce is sampled only when a new external address is loaded. 7t zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when active, all other inputs are ignored. 4f oe input output enable: this active low, asynchronous input enables the data i/o output drivers. 4g adv input synchronous address advance: this active low input is used to advance the internal burst counter, controlling burst access after the external address is loaded. a high on adv effectively causes wait states to be generated (no address advance). to ensure use of correct address during a write cycle, adv must be high at the rising edge of the first clock after an adsp cycle is initiated. 4a adsp input synchronous address status processor: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read is performed using the new address, independent of the byte write enables and adsc, but dependent upon ce, ce 2 and ce 2 . adsp is ignored if ce is high. powerdown state is entered if ce 2 is low or ce 2 is high . 4b adsc input synchronous address status controller: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read or write is performed using the new address if ce is low. adsc is also used to place the chip into power-down state when ce is high. 3r mode input mode: this input selects the burst sequence. a low on mode selects linear burst. nc or high on this input selects interleaved burst. do not alter input state while device is operating. (a) 6k, 6l, 6m, 6n, dqa input/ sram data i/os: byte a is dqa?s; byte b is dqb?s; byte c is dqc?s; 7k, 7l, 7n, 7p output byte d is dqd?s. input data must meet setup and hold times around rising edge of clk. (b) 6e, 6f, 6g, 6h, dqb 7d, 7e, 7g, 7h (c) 1d, 1e, 1g, 1h dqc 2e, 2f, 2g, 2h (d) 1k, 1l, 1n, 1p, dqd 2k, 2l, 2m, 2n 6p dqpa input/ byte a parity is dqpa; byte b parity is dqpb; byte c parity is dqpc; 6d dqpb output byte d parity is dqpd. 2d dqpc 2p dqpd 2j, 4c, 4j, 4r, 5r, v dd supply power supply: see dc electrical characteristics and operating conditions for range. 6j 1a, 1f, 1j, 1m 1u v ddq supply isolated output buffer supply: see dc electrical characteristics and operating 7a, 7f, 7j, 7m, 7u conditions for range. 3d, 3e, 3f, 3h, 3k, v ss supply ground: gnd. 3m, 3n, 3p, 5d, 5e, 5f, 5h, 5k, 5m, 5n, 5p 2u tms input scan test mode select 3u tdi input scan test data in 4u tdo output scan test data out 5u tck input scan test clock
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av interleaved burst table (mode = nc or high) first address second address third address fourth address external internal internal internal x...x00 x...x01 x...x10 x...x11 x...x01 x....x00 x...x11 x...x10 x...x10 x...x11 x...x00 x...x01 x...x11 x...x10 x...x01 x...x00 interleaved burst table (mode = low) first address second address third address fourth address external internal internal internal x...x00 x...x01 x...x10 x...x11 x...x01 x....x10 x...x11 x...x00 x...x10 x...x11 x...x00 x...x01 x...x11 x...x00 x...x01 x...x10 truth table function address ce ce 2 ce 2 zz adsp adsc adv write oe clk dq used deselected cycle,power-down none h x x l x l x x x l-h high-z deselected cycle,power-down none l x l l l x x x x l-h high-z deselected cycle,power-down none l h x l l x x x x l-h high-z deselected cycle,power-down none l x l l h l x x x l-h high-z deselected cycle,power-down none l h x l h l x x x l-h high-z snooze mode,power-down none x x x h x x x x x x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle begin burst external l l h l h l x l x l-h d read cycle begin burst external l l h l h l x h l l-h q read cycle begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h hhhhl-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x hhhhl-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes : 1. x means don?t care. ?? means active low. h means logic high. l means logic low. 2. for write, l means any one or more byte write enable signals (bwa, bwb, bwc or bwd) and bwe are low or gw is low. write = h f or all bwx, bwe, gw high. 3. bwa enables writes to dqa?s and dqpa. bwb enables writes to dqb?s and dqpb. bwc enables writes to dqc?s and dqpc. bwd enables writes to dqd?s and dqpd. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high throughout t he input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk a write is performed by setting one or more byte write enab le signals and bwe low or gw low for the subsequent l-h edge of clk. refer to write timing diagram for clarification.
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av absolute maximum ratings* voltage on v dd supply relative to v ss -0.5v to +4.6v voltage on v ddq supply relative to v ss -0.5v to +4.6v vin (dqx) -0.5v to v ddq +0.5v vin (inputs) -0.5v to v dd +0.5v storage temperature (bga) +55 c to +125 c short circuit output current 100 ma *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics description symbol conditions min max units notes input high (logic 1)voltage v ih 2.0 v dd +0.3 v 1 input low (logic 0) voltage v il -0.3 0.8 v 1 input leakage current i li 0v v in v dd -1.0 1.0 ma 2 ouptut leakage current i lo output(s) disabled, 0v v in v dd -1.0 1.0 ma output high voltage v oh i oh = -4.0ma 2.4 v 1 output low voltage v ol i ol = 8.0ma 0.4 v 1 supply voltage v dd 3.135 3.6 v 1 isolated output buffer supply v ddq 3.134 3.6 v notes: 1. all voltages referenced to vss (gnd). 2. mode has an internal pull-up, and input leakage = 10lia. description conditions symbol typ max units notes control input capacitance t a = 25 c; f = 1mhz c i 34 pf1 input/output capacitance (dq) t a = 25 c; f = 1mhz c o 45 pf1 address capacitance t a = 25 c; f = 1mhz c a 35 pf1 clock capacitance t a = 25 c; f = 1mhz c ck 2.5 4 pf 1 notes: 1. this parameter is sampled. bga capacitance partial truth table - write commands function gw bwe bwa bwb bwc bwd read h h x x x x read h l h h h h write byte a h l l h h h write all bytes h l l l l l write all bytes l x x x x x note: using bwe and bwa through bwd, any one or more bytes may be written. description symbol conditions typ 200* 166 150 133 units notes mhz mhz mhz mhz power supply device selected; all inputs v il or 3 v ih ; cycle time 3 t kc min; current: operating i dd v dd = max; outputs open tbd 700 620 560 ma 1,2,3 device deselected; v dd = max; all inputs v ss + 0.2 cmos standby i sb2 or v dd - 0.2; all inputs static; clk frequency = 0 10 20 20 20 20 ma 2,3 device deselected; v dd = max; all inputs v il or v ih ; ttl standby i sb3 all inputs static; cld frequency = 0 20 40 40 40 40 ma 2,3 device deselected; v dd = max; all inputs v ss + 0.2 clock running i sb4 or v dd -0.2; cycle time 3 t kc min 80 tbd 180 160 140 ma 2,3 * advanced information notes: 1. i dd is specified with no output current and increases with faster cycle times. idd increases with faster cycle times and greater o utput loading. 2. device deselected means device is in power-down mode as defined in the truth table. device selected means device is activ e (not in power-down mode). 3. typical values are measured at 3.3v, 250 c and 10ns cycle time. dc characteristics
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av ac characteristics (wed2dl36513v) symbol 200mhz 166mhz 150mhz 133mhz parameter min max min max min max min max units clock clock cycle time t kc 5.0 6.0 6.6 7.5 ns clock frequency t kf 200 166 150 133 mhz clock high time t kh 2.0 2.4 2.6 2.6 ns clock low time t kl 2.0 2.4 2.6 2.6 ns output times clock to output valid t kq 2.5 3.5 3.8 4.0 ns clock to output invalid (2) t kqx 1.5 1.25 1.25 1.5 ns clock to output on low-z (2,3,4) t kqlz 0000ns clock to output in high-z (2,3,4) t kqhz 3.0 3.5 3.8 4.0 ns oe to output valid (5) t oeq 2.5 3.5 3.8 4.0 ns oe to output in low-z (2,3,4) t oelz 0000ns oe to output in high z (2,3,4) t oehz 2.5 3.5 3.8 4.0 ns setup times address (6,7) t as 1.5 1.5 1.5 1.5 ns address status (adsc, adsp) (6,7) t adss 1.5 1.5 1.5 1.5 ns address advance (adv) (6,7) t aas 1.5 1.5 1.5 1.5 ns write signals (bwa-bwd, bwe, gw) (6,7) t ws 1.5 1.5 1.5 1.5 ns data-in (6,7) t ds 1.5 1.5 1.5 1.5 ns chip enables (ce, ce 2 , ce 2 ) (6,7) t ces 1.5 1.5 1.5 1.5 ns hold times address (6,7) t ah 0.5 0.5 0.5 0.5 ns address status (adsc, adsp) (6,7) t adsh 0.5 0.5 0.5 0.5 ns address advance (adv) (6,7) t aah 0.5 0.5 0.5 0.5 ns write signals (bwa-bwd, bwe, gw) (6,7) t wh 0.5 0.5 0.5 0.5 ns data-in (6,7) t dh 0.5 0.5 0.5 0.5 ns chip enables (ce, ce 2 , ce 2 ) (6,7) t ceh 0.5 0.5 0.5 0.5 ns notes: 1. test conditions as specified with the output loading as shown in figure 1 for 3.3v 1/0 and figure 3 for 2.5v 1/0 unless other wise noted. 2. this parameter is measured with output load as shown in figure 2 for 3.3v 1/0 and figure 4 for 2.5v 1/0. 3. this parameter is sampled. 4. transition is measured 500mv from steady state voltage. 5. oe is a dont care when a byte write enable is sampled low. 6. a write cycle is defined by at least one byte write enable low and adsp high for the required setup and hold times. a read cy cle is defined by all byte write enables high and adsc or adv low or adsp low for the required setup and hold times. 7. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when eit her adsp or adsc is low and chip enabled. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when either adsp or adsc is low to remain enabled. output loads ac test conditions 50 w vt = 1.5v output z0 = 50 w z0 = 50 w parameter 3.3v i/o 2.5v i/o unit input pulse levels v ss to 3.0 v ss to 2.5 v input rise and fall times 1 1 ns input timing reference levels 1.5 1.25 v output timing reference levels 1.5 1.25 v output load see figure, at left ac output load equivalent vt = 1.5v for 3.3v i/o vt = 1.25v for 2.5v i/o
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av ac characteristics (wed2dl36513av) symbol 200mhz 166mhz 150mhz 133mhz parameter min max min max min max min max units clock clock cycle time t kc 5.0 6.0 6.6 7.5 ns clock frequency t kf 200 166 150 133 mhz clock high time t kh 2.0 2.4 2.6 2.6 ns clock low time t kl 2.0 2.4 2.6 2.6 ns output times clock to output valid t kq 2.5 3.5 3.8 4.0 ns clock to output invalid (2) t kqx 1.25 1.25 1.25 1.5 ns clock to output on low-z (2,3,4) t kqlz 0000ns clock to output in high-z (2,3,4) t kqhz 3.0 3.5 3.8 4.0 ns oe to output valid (5) t oeq 2.5 3.5 3.8 4.0 ns oe to output in low-z (2,3,4) t oelz 0000ns oe to output in high z (2,3,4) t oehz 2.5 3.5 3.8 4.0 ns setup times address (6,7) t as 1.0 1.0 1.0 1.0 ns address status (adsc, adsp) (6,7) t adss 1.0 1.0 1.0 1.0 ns address advance (adv) (6,7) t aas 1.0 1.0 1.0 1.0 ns write signals (bwa-bwd, bwe, gw) (6,7) t ws 1.0 1.0 1.0 1.0 ns data-in (6,7) t ds 1.0 1.0 1.0 1.0 ns chip enables (ce, ce 2 , ce 2 ) (6,7) t ces 1.0 1.0 1.0 1.0 ns hold times address (6,7) t ah 1.0 1.0 1.0 1.0 ns address status (adsc, adsp) (6,7) t adsh 1.0 1.0 1.0 1.0 ns address advance (adv) (6,7) t aah 1.0 1.0 1.0 1.0 ns write signals (bwa-bwd, bwe, gw) (6,7) t wh 1.0 1.0 1.0 1.0 ns data-in (6,7) t dh 1.0 1.0 1.0 1.0 ns chip enables (ce, ce 2 , ce 2 ) (6,7) t ceh 1.0 1.0 1.0 1.0 ns notes: 1. test conditions as specified with the output loading as shown in figure 1 for 3.3v 1/0 and figure 3 for 2.5v 1/0 unless other wise noted. 2. this parameter is measured with output load as shown in figure 2 for 3.3v 1/0 and figure 4 for 2.5v 1/0. 3. this parameter is sampled. 4. transition is measured 500mv from steady state voltage. 5. oe is a dont care when a byte write enable is sampled low. 6. a write cycle is defined by at least one byte write enable low and adsp high for the required setup and hold times. a read cy cle is defined by all byte write enables high and adsc or adv low or adsp low for the required setup and hold times. 7. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when eit her adsp or adsc is low and chip enabled. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when either adsp or adsc is low to remain enabled.
7 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av snooze mode snooze mode is a low-current, power-down mode in which the device is deselected and current is reduced to i sb2z . the duration of snooze mode is dictated by the length of time zz is in a high state. after the device enters snooze mode, all inputs except zz become gated inputs and are ignored. zz is an asynchronous, active high input that causes the device to enter description conditions symbol min max units notes current during snooze mode zz 3 vih i sb2z 10 ma zz active to input ignored t zz 2(t kc )ns 1 zz inactive to input sampled t rzz 2(t kc )ns1 zz active to snooze current t zzi 2(t kc )ns 1 zz inactive to exit snooze current t rzzi ns 1 snooze mode snooze mode. when zz becomes a logic high, i sb2z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is notguaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending operations are completed. fig. 2 snooze mode timing diagram zz i supply clock all inputs (except zz) output (q) t zz t zzi t rzz t rzzi high-z deselect or read only i isb2z don't care
8 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av fig. 3 read timing diagram adsp adsc address bwx, gw ce (note 2) t adss t adsh adv oe clock a 2 a 1 t as t ah q t aas t aah q(a 2 )q(a 2+1 ) t kh t kl t kc t kq q(a 2+3 ) q(a 2+1 ) q(a 1 ) q(a 2+2 ) t kqlz t oelz t kq t oeq t oehz single read burst read q(a 2 ) t kqhz (note 3) a 3 don? care undefined deselect cycle (note 4) adv suspends burst t css t csh t ws t wa burst continued with new base address burst wraps around to its initial state (note 1) high-z t kqx notes: 1. q (a 2 ) refers to output from address a 2 . q (a 2 + 1 ) refers to output from the next internal burst address following a 2 . 2. ce 2 and ce 2 have timing identical to ce. on this diagram, when ce is low, ce 2 is low and ce 2 is high. when ce is high, ce 2 is high and ce 2 is low. 3. timing is shown assuming that the device was not enabled before entering into this sequence. oe does not cause q to be driven until after the following clock rising edge. 4. outputs are disabled within one clock cycle after deselect.
9 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av fig. 4 write timing diagram adsp adsc address bwx ce (note 2) t adss t adsh adv oe clock a 2 a 1 t as t ah q t aas t aah t kh t kl t kc t oehz burst read single write burst write extended burst write (note 5) a 3 don? care undefined (note 3) adv suspends burst t css t csh t ws t wa adsc extends burst byte write signals are ignored for first cycle when adsp initiates burst. (note 1) d d(a 1 ) d(a 2 ) d(a 2+1 ) d(a 2+1 ) d(a 2+2 )d(a 2+3 )d(a 3 )d(a 3+1 ) high-z t adss t adsh gw t wh (note 3) (note 5) t ws (note 4) d(a 3+2 ) t ds t dh notes: 1. d (a 2 ) refers to output from address a 2 . d (a 2 + 1 ) refers to output from the next internal burst address following a 2 . 2. ce 2 and ce 2 have timing identical to ce. on this diagram, when ce is low, ce 2 is low and ce 2 is high. when ce is high, ce 2 is high and ce 2 is low. 3. oe must be high before the input data setup and held high throughout the data hold time. this prevents input/output data cont entin for the time period prior to the byte write enable inputs being sampled. 4. adv must be high to permit a write to the load address. 5. full-width write can be initiated by gw low, or gw high and bwe, bwa, - bwd low. timing is shown assuming that the device was not enabled before entering into its sequence. oe does not cause q to be driven until after the following clock rising edge.
10 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av fig. 5 read/write timing diagram adsp adsc address bwx (note 4) ce (note 2) t adss t adsh adv oe clock a 2 t as t ah q t kh t kl t kc t oelz q(a 4+2 ) q(a 4 ) q(a 1 ) q(a 4+1 ) q(a 4+3 ) t kqlz t kq t oehz back-to-back reads (note5) single write back-to-back writes burst read q(a 2 ) (note 3) a 5 a 6 don? care undefined t css t csh t ws t wh (note 1) high-z d high-z a 1 a 3 a 4 (note 4) d(a 3 ) d(a 5 ) d(a 6 ) t ds t dh notes: 1. q (a 4 ) refers to output from address a 4 . q (a 4 + 1 ) refers to output from the next internal burst address following a 4 . 2. ce 2 and ce 2 have timing identical to ce. on this diagram, when ce is low, ce 2 is low and ce 2 is high. when ce is high, ce 2 is high and ce 2 is low. 3. the data bus q remains in high-z following a write cycle unless adsp, adsc or adv cycle is performed. 4. gw is high. 5. back-to-back reads may be controlled by either adsp or adsc.
11 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av package dimension: 119 bump pbga 2.79 (0.110) max 0.711 (0.028) max 1.27 (0.050) typ 1.27 (0.050) typ a b c d e f g h j k l m n p r t u 14.00 (0.551) typ a1 corner 20.32 (0.800) typ 22.00 (0.866) typ 7.62 (0.300) typ r 1.52 (0.060) max (4x) all linear dimensions are millimeters and parenthetically in inches
12 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com wed2dl36513v wed2dl36513av ordering information 512kx36, single ce part number config. t kq clock package (ns) (mhz) no. commercial temp range (0 c to 70 c) wed2dl36513av25bc 512kx36 2.5 200 435 wed2dl36513av35bc 512kx36 3.5 166 435 wed2dl36513av38bc 512kx36 3.8 150 435 WED2DL36513AV40bc 512kx36 4.0 133 435 industrial temp range (-40 c to +85 c)* wed2dl36513av38bi 512kx36 3.8 150 435 WED2DL36513AV40bi 512kx36 4.0 133 435 * advanced information 512kx36, three ce part number config. t kq clock package (ns) (mhz) no. commercial temp range (0 c to 70 c) wed2dl36514av25bc 512kx36 2.5 200 435 wed2dl36514av35bc 512kx36 3.5 166 435 wed2dl36514av38bc 512kx36 3.8 150 435 wed2dl36514av40bc 512kx36 4.0 133 435 industrial temp range (-40 c to +85 c) wed2dl36514av38bi 512kx36 3.8 150 435 wed2dl36514av40bi 512kx36 4.0 133 435 * advanced information 512kx36, single ce part number config. t kq clock package (ns) (mhz) no. commercial temp range (0 c to 70 c) wed2dl36513v25bc 512kx36 2.5 200 435 wed2dl36513v35bc 512kx36 3.5 166 435 wed2dl36513v38bc 512kx36 3.8 150 435 wed2dl36513v40bc 512kx36 4.0 133 435 industrial temp range (-40 c to +85 c)* wed2dl36513v38bi 512kx36 3.8 150 435 wed2dl36513v40bi 512kx36 4.0 133 435 * advanced information 512kx36, three ce part number config. t kq clock package (ns) (mhz) no. commercial temp range (0 c to 70 c) wed2dl36514v25bc 512kx36 2.5 200 435 wed2dl36514v35bc 512kx36 3.5 166 435 wed2dl36514v38bc 512kx36 3.8 150 435 wed2dl36514v40bc 512kx36 4.0 133 435 industrial temp range (-40 c to +85 c) wed2dl36514v38bi 512kx36 3.8 150 435 wed2dl36514v40bi 512kx36 4.0 133 435 * advanced information

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