your ? electronic ? engineering ? resource ? ? xrt91l30 sts12-stm4 or sts3-stm1 sonet-sdh transceiver general description: the xrt91l30 is a fully integrated sonet/sdh transceiver for sonet/sdh 622.08 mbps sts-12/stm-4 or 155.52 mbps sts-3/stm-1 applications. the transceiver includes an on-chip clock multiplier unit (cmu), which uses a high frequency phase- locked loop (pll) to generate the high-speed transmit serial clock from a slower external clock reference. it also provides clock and data recovery (cdr) function by sy nchronizing its on-chip voltage controlled oscillator (vco) to the incoming serial data stream. the internal cdr unit can be disabled and bypassed in lieu of an externally recovered received clock from the optical module. either the internally recovered clock or the externally re covered clock can be used for loop timing applications. the chip provides serial-to-parallel and parallel-to -serial converters using an 8-bit wide lvttl system interface in both receive and transmit directions. the tr ansmit section includes an option to accept a parallel clock signal from the framer/mapper to synchronize t he transmit section timing. the device can internally monitor loss of signal (los) condition and automat ically mute received data upon los. an on-chip sonet/sdh frame byte and boundary detector and fr ame pulse generator offers the ability recover sonet/sdh framing and to byte align the receive serial data stream into the 8-bit parallel bus. key features: ? targeted for sonet sts-12/sts-3 and sdh stm-4/stm-1 applications ? selectable full duplex operation between sts-12/stm-4 standard rate of 622.08 mbps or sts-3/stm-1 155.52 mbps ? single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (cmu), serialto-parallel converter, clock data recovery (cdr) functions, and a sonet/sdh frame and byte boundary detection circuit ? ability to disable and bypass onchip cdr for exter nal based received reference clock recovery thru differential lvpecl input pins xrxclkip/n legal disclaimer: the content of the pages of this website is for your general information and use only . it is subject to change without notice. from time to time, this website may also include links to other websites. these links are provided for your convenience to provide further information. they do not signify that we endorse the website(s). we have no responsibility for the content of the linked we bsite(s). your use of any information or materials on this website is entirely a t your own risk, for which we shall not be liable. it shall be your own responsibility to ensure that any products, services or information availa ble through this website meet your specif ic requirements.
your ? electronic ? engineering ? resource ? ? ? 8-bit lvttl parallel data bus paths running at 77.76 mbps in sts-12/stm-4 or 19.44 mbps in sts-3/stm-1mode of operation ? uses differential lvpecl or single-ended lvttl cmu reference clock frequencies of either 19.44 mhz or 77.76 mhz for both sts-12/stm-1 or sts-3/stm-1 operations ? optional use of 77.76 mhz single-ended lvttl input for independent cdr reference clock operation ? able to detect and recover sonet/sdh fram e boundary and byte align received data on the parallel bus ? diagnostics features include los monito ring and automatic received data mute upon los ? provides local, remote and split loop-back modes as well as loop timing mode ? optional flexibility to re-configure the transmit para llel bus clock output to a clock input and accept timing signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the transceiver transmit timing ? meets telcordia, ansi and itu-t g.783 and g.825 sdh jitter requirements including t1.105.03 ? 2002 sonet jitter tolerance specification, bellcore tr-nwt-000253 and gr-253-core, gr-253 ilr sonet jitter specifications ? complies with ansi/tia/eia-644 and ieee p 1596.3 3.3v lvds standard , 3.3v lvpecl, and jesd 8-b lvttl and lvcmos standard ? operates at 3.3v core with 3.3v i/o ? less than 660mw in sts-3/stm-1 mode or 800mw in sts-12/stm-4 mode typical power dissipation ? package: 10 x 10 x 2.0 mm 64-pin qfp applications: ? sonet/sdh-based transmission systems ? add/drop multiplexers ? cross connect equipment ? atm and multi-service switches, routers and ? switch/routers ? dslams ? sonet/sdh test equipment ? dwdm termination equipment related products information: mfr part # farnell # newark # description XRT91L30IQ-F 1798688 24r1992 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver - 64-pin qfp package xrt91l32iq-f 1798689 73r5147 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver - 100-pin qfp package legal disclaimer: the content of the pages of this website is for your general information and use only . it is subject to change without notice. from time to time, this website may also include links to other websites. these links are provided for your convenience to provide further information. they do not signify that we endorse the website(s). we have no responsibility for the content of the linked we bsite(s). your use of any information or materials on this website is entirely a t your own risk, for which we shall not be liable. it shall be your own responsibility to ensure that any products, services or information availa ble through this website meet your specif ic requirements.
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