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acpl-782t automotive isolation amplifier with r 2 coupler? isolation data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the acpl-782t isolation amplifier was designed for voltage and current sensing in electronic motor drives and battery system monitoring. in a typical implementa- tion, and motor currents flow through an external resistor and the resulting analog voltage drop is sensed by the acpl-782t. a differential output voltage is created on the other side of the acpl-782t optical isolation barrier. this differential output voltage is proportional to the motor current and can be converted to a single-ended signal by using an op-amp as shown in the recommended ap- plication circuit. since common-mode voltage swings of several hundred volts in tens of nanoseconds are common in modern switching inverter motor drives, the acpl-782t was designed to ignore very high common- mode transient slew rates (of at least 10 kv/ s). the high cmr capability of the acpl-782t isolation amplifier provides the precision and stability needed to ac- curately monitor motor current and dc rail voltage in high noise motor control environments, providing for smoother control (less torque ripple) in various types of motor control applications. the product can also be used for general analog signal isolation applications requiring high accuracy, stability, and linearity under similarly severe noise conditions. the acpl-782t utilizes sigma delta ( ) analog-to-digital converter technology, chopper stabilized amplifiers, and a fully differential circuit topology. together, these features deliver unequaled isolation- mode noise rejection, as well as excellent offset and gain accuracy and stability over time and temperature. this performance is delivered in a compact, auto-insert- able, industry standard 8-pin dip package that meets worldwide regulatory safety standards. (a gull-wing surface mount option -300e is also available). avago r 2 coupler isolation products provide the rein- forced insulation and reliability needed for critical in auto- motive and high temperature industrial applications. features 2% gain tolerance @ 25c 15 kv/ s common-mode rejection at v cm = 1000v 30ppm/c gain drift vs. temperature 0.3 mv input offset voltage 100 khz bandwidth 0.004% nonlinearity compact, auto-insertable standard 8-pin dip package worldwide safety approval: C ul 1577 (3750 v rms /1 min.) and C csa C iec 60747-5-5, din en 60747-5-2(vde 0884 teil 2) qualified to aec-q100 test guidelines automotive operating temperature -40 to 125c advanced sigma-delta ( ) a/d converter technology fully differential circuit topology applications automotive motor inverter current/voltage sensing automotive ac/dc and dc/dc converter current/ voltage sensing automotive battery ecu automotive motor phase current sensing isolation interface for temperature sensing general purpose current sensing and monitoring functional diagram lead (pb) free rohs 6 fully compliant ro hs 6 f u lly c omp l iant options avai l a bl e ; -xxxe d enotes a l ea d-f ree pro d u c t the connection of a 0.1 f bypass capacitor between pins 1 and 4, pins 5 and 8 is recommended. 1 2 3 4 8 7 6 5 i dd1 v dd1 v in+ v in- gnd1 i dd2 v dd2 v out+ v out- gnd2 + - + - shield
2 part number option (rohs compliant) package surface mount gullwing tape & reel acpl-782t -000e 300mil dip-8 -300e x x -500e x x x to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example: acpl-782t-500e to order product of gullwing smt dip-8 package in tape and reel packaging with rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. package outline drawings ACPL-782T-000E standard dip package 9. 8 0 0. 25 (0. 386 0.010) 1. 78 (0.0 7 0) max. 1.19 (0.0 47 ) max. a 782 t yyww ee d ate c od e exte nd e d d ate c od e 1.0 8 0 0. 32 0 (0.0 43 0.01 3 ) 2 . 54 0. 25 (0.100 0.010) 0. 5 1 (0.0 2 0) mi n . 0. 65 (0.0 25 ) max. 4 . 7 0 (0.1 85 ) max. 2 .9 2 (0.11 5 ) mi n . dimensions in millimeters and (inches). note: floating lead protrusion is 0.5 mm (20 mils) max. 5 6 7 8 4 3 2 1 5 typ. 0. 2 0 (0.00 8 ) 0. 33 (0.01 3 ) 7 . 62 0. 25 (0. 3 00 0.010) 6 . 35 0. 25 (0. 25 0 0.010) 3 . 56 0.1 3 (0.1 4 0 0.00 5 )
3 gull wing surface mount option 300e and 500e 0. 635 0. 25 (0.0 25 0.010) 1 2 no m. 9. 65 0. 25 (0. 38 0 0.010) 0. 635 0.1 3 0 (0.0 25 0.00 5 ) 7 . 62 0. 25 (0. 3 00 0.010) 5 6 7 8 4 3 2 1 9. 8 0 0. 25 (0. 386 0.010) 6 . 35 0 0. 25 (0. 25 0 0.010) 1.01 6 (0.0 4 0) 1. 27 (0.0 5 0) 10.9 (0. 43 0) 2 .0 (0.0 8 0) la nd patter n rec o mme nd ati on 1.0 8 0 0. 32 0 (0.0 43 0.01 3 ) 3 . 56 0.1 3 (0.1 4 0 0.00 5 ) 1. 78 0 (0.0 7 0) max. 1.19 (0.0 47 ) max. 2 . 54 (0.100) b s c note: floating lead protrusion is 0.5 mm (20 mils) max. dimensions in millimeters (inches). tolerances (unless otherwise specified): xx.xx = 0.01 xx.xxx = 0.005 a 782 t yyww ee lea d c o pla n arity maxim u m: 0.10 2 (0.00 4 ) 0. 2 0 (0.00 8 ) 0. 33 (0.01 3 ) ul ul 1577, component recognition program up to v iso = 3750 v rms csa approved under csa component acceptancenotice #5, file ca 88324. iec/din iec 60747-5-5 din en 60747-5-2(vde 0884 teil 2) regulatory information the ACPL-782T-000E is approved by the following organizations: recommended pb-free ir profile recommended reflow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used.
4 iec 60747-5-5, din en 60747-5-2(vde 0884 teil 2) insulation characteristics description symbol characteristic unit installation classification per din vde 0110/1.89, table 1 for rated mains voltage 300 vrms for rated mains voltage 450 vrms for rated mains voltage 600 vrms i-iv i-iii i-ii climatic classification 55/125/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 891 v peak input to output test voltage, method b [2] v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 1670 v peak input to output test voltage, method a [2] v iorm x 1.6 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc v pr 1426 v peak highest allowable overvoltage (transient overvoltage t ini = 60 sec) v iotm 6000 v peak safety-limiting valuesmaximum values allowed in the event of a failure. case temperature input current [3] output power [3] t s i s,input p s,output 175 400 600 c ma mw insulation resistance at t s , v io = 500 v r s >10 9 notes: 1. insulation characteristics are guaranteed only within the saf ety maximum ratings which must be ensured by protective circui ts within the application. surface mount classification is class a in accordance with cecc00802. 2. refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulatio ns section, (iec 60747-5-5/din en 60747-5-2) for a detailed description of method a and method b partial discharge test profiles. 3. refer to the following figure for dependence of ps and is on ambient temperature. out p ut p owe r - p s , in p ut c u rr ent - i s 0 0 t a - ca se te mp e ra tu r e - c 2 00 5 0 4 00 125 25 75 1 00 15 0 6 00 8 00 2 00 1 00 3 00 5 00 7 00 175 p s (mw) i s (m a )
5 insulation and safety related specifications parameter symbol value units conditions minimum external air gap (clearance) l(101) 7.4 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 8.0 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti >175 volts din iec 112/vde 0303 part 1 isolation group (din vde0109) iiia material group (din vde 0110) absolute maximum ratings parameter symbol min. max. units storage temperature t s -55 130 c operating temperature t a -40 125 c supply voltage v dd1 , v dd2 0 5.5 volts steady-state input voltage v in+ , v in- -2.0 v dd1 + 0.5 volts 2 second transient input voltage -6.0 volts output voltage v out -0.5 v dd2 + 0.5 volts solder reflow temperature profile see package outline drawings section recommended operating conditions parameter symbol min. max. units notes ambient operating temperature t a -40 125 c power supply voltage v dd1 , v dd2 4.5 5.5 volts input voltage (accurate & linear) v in+ , v in- -200 200 mv 1 input voltage (functional) v in+ , v in- -2 2 v
6 dc electrical specifications unless otherwise noted, all typical and figures are at the nominal operating conditions of v in+ = 0, v in- = 0 v, v dd1 = v dd2 = 5 v and t a = 25c; all min. /max. specifications are within the recommended operating conditions. parameter symbol min. typ.* max. units test conditions fig. note input offset voltage v os -2.0 0.3 2.0 mv t a =25c 1,2 -4.0 4.0 mv -40c < t a < +125c, -4.5v < (v dd1 , v dd2 ) < 5.5v magnitude of input offset change vs. temperature | v os / t a | 3.0 10.0 v/c 32 gain g 7.84 8.00 8.16 v/v -200 mv < v in+ < 200 mv, t a = 25c, 4,5,6 3 magnitude of v out gain change vs. temperature | g/ g/ t a | 30 ppm/c 4 v out 200 mv nonlinearity nl 200 0.0037 0.35 % -200 mv < v in+ < 200 mv 7,8 5 magnitude of v out 200mv nonlinearity change vs. temperature | nl 200 / t| 0.0002 %/c v out 100 mv nonlinearity nl 100 0.0027 0.2 % -100 mv < v in+ < 100mv 6 maximum input voltage before v out clipping |v in+ |max 308.0 mv 9 input supply current i dd1 10.86 16.0 ma v in+ = 400 mv 10 7 output supply current i dd2 11.56 20.0 ma v in+ = -400 mv 8 input current i in+ -5 -0.5 a 11 9 magnitude of input bias current vs. temperature coefficient | i in / t| 0.45 na/c output low voltage v ol 1.29 v 10 output high voltage v oh 3.80 v output common-mode voltage v ocm 2.2 2.545 2.8 v output short-circuit current |i osc | 18.6 ma 11 equivalent input imped- ance r in 500 k v out output resistance r out 15 input dc common-mode rejection ratio cmrr in 76 db 12
7 ac electrical specifications unless otherwise noted, all typicals and figures are at the nominal operating conditions of v in+ = 0, v in- = 0 v, v dd1 = v dd2 = 5 v and t a = 25c; all min./max. specifications are within the recommended operating conditions. parameter symbol min. typ.* max. units test conditions fig. note v out bandwidth (-3 db) sine wave. bw 50 100 khz v in+ = 200mvpk-pk 12,13 v out noise n out 6mv rms v in+ = 0.0 v 13 v in to v out signal delay (50 C 10%) t pd10 2.03 3.3 s measured at output of mc34081on figure 15. 4,15 v in to v out signal delay (50 C 50%) t pd50 3.47 5.6 s v in+ = 0 mv to 150mv step. v in to v out signal delay (50 C 90%) t pd90 4.99 9.9 s v out rise/ fall time (10 C 90%) t r/f 2.96 6.6 s common mode transient immunity cmti 10.0 15.0 kv/ s v cm = 1 kv, t a = 25c 16 14 power supply rejection psr 170 mv rms with recommended application circuit. 15 package characteristics parameter symbol min. typ.* max. units test conditions fig. note input-output momentary withstand voltage v iso 3750 v rms rh < 50%, t = 1 min. t a = 25c 16,17 resistance (input-output) r i-o >10 9 v i-o = 500 v dc 18 capacitance (input-output) c i-o 1.2 pf ? = 1 mhz 18
8 notes: general note: typical values represent the mean value of all characterization units at the nominal operating conditions. typical drift specifications are determined by calculating the rate of change of the specified parameter versus the drift parameter (at nominal operating conditions) for each characterization unit, and then averaging the individual unit rates. the corresponding drift figures are normalized to the nominal operating conditions and show how much drift occurs as the par-ticular drift parameter is varied from its nominal value, with all other parameters held at their nominal operating values. note that the typical drift specifications in the tables below may differ from the slopes of the mean curves shown in the corresponding figures. 1. avago technologies recommends operation with v in- = 0 v (tied to gnd1). limiting v in+ to 100 mv will improve dc nonlinearity and nonlinearity drift. if v in- is brought above v dd1 C 2 v, an internal test mode may be activated. this test mode is for testing led coupling and is not intended for customer use. 2. this is the absolute value of input offset change vs. temperature. 3. gain is defined as the slope of the best-fit line of differential output voltage (v out+ Cv out- ) vs. differential input voltage (v in+ Cv in- ) over the specified input range. 4. this is the absolute value of gain change vs. temperature in ppm level. 5. nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a percentage of the full-scale differential output voltage. 6. nl100 is the nonlinearity specified over an input voltage range of 100 mv. 7. the input supply current decreases as the differential input voltage (v in+ Cv in- ) decreases. 8. the maximum specified output supply current occurs when the differential input voltage (v in+ Cv in- ) = -200 mv, the maximum recommended operating input voltage. however, the output supply current will continue to rise for differential input voltages up to approximately -300 mv, beyond which the output supply current remains constant. 9. because of the switched-capacitor nature of the input sigma-delta converter, time-averaged values are shown. 10. when the differential input signal exceeds approximately 308 mv, the outputs will limit at the typical values shown. 11. short circuit current is the amount of output current generated when either output is shorted to v dd2 or ground. 12. cmrr is defined as the ratio of the differential signal gain (signal applied differentially between pins 2 and 3) to the common-mode gain (input pins tied together and the signal applied to both inputs at the same time), expressed in db. 13. output noise comes from two primary sources: chopper noise and sigma-delta quantization noise. chopper noise results from chopper stabilization of the output op-amps. it occurs at a specific frequency (typically 400 khz at room temperature), and is not attenuated by the internal output filter. a filter circuit can be easily added to the external post-amplifier to reduce the total rms output noise. the internal output filter does eliminate most, but not all, of the sigma- delta quantization noise. the magnitude of the output quantization noise is very small at lower frequencies (below 10khz) and increases with increasing frequency. 14. cmti (common mode transient immunity or cmr, common mode rejection) is tested by applying an exponentially rising/falling voltage step on pin 4 (gnd1) with respect to pin 5 (gnd2). the rise time of the test waveform is set to approximately 50 ns. the amplitude of the step is adjusted until the differential output (v out+ C v out- ) exhibits more than a 200 mv deviation from the average output voltage for more than 1 s. the acpl-782t will continue to function if more than 10 kv/ s common mode slopes are applied, as long as the breakdown voltage limitations are observed. 15. datasheet value is the differential amplitude of the transient at the output of the acpl-782t when a 1 v pk-pk , 1 mhz square wave with 40 ns rise and fall times is applied to both v dd1 and v dd2 . 16. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, ii-o 5 a). this test is performed before the 100% production test for partial discharge (method b) shown in iec 60747-5-5/din en 60747-5-2 insulation characteristic table. 17. the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refers to the iec 60747-5-5/din en 60747-5-2 insulation characteristics table and your equipment level safety specification. 18. this is a two-terminal measurement: pins 1C4 are shorted together and pins 5C8 are shorted together.
9 t a - te mp e ra tu r e - c 0. 6 0. 5 0. 3 -25 0. 8 35 9 5 0. 2 0. 7 -55 125 0. 4 565 v os - in p ut offset volt a ge - mv v dd - su pp ly volt a ge - v 0. 37 0. 36 0. 3 9 4 . 75 5 .0 0. 33 vs . v dd1 4 . 55 . 5 5 . 25 vs . v dd2 0. 34 0. 38 0. 35 v os - in p ut offset volt a ge - mv g - g a in - v/v t a - te mp e ra tu r e - c 8 .0 25 8 .0 2 8 .0 15 -35 8 .0 35 25 85 8 .0 1 8 .0 3 -55 125 545 1 0 5 -15 65 figure 3. input offset voltage vs. supply. figure 4. gain vs. temperature. figure 1. input offset voltage test circuit. figure 2. input offset voltage vs. temperature. 0. 1 f v dd2 v out 8 7 6 1 3 acp l-782t 5 2 4 0. 1 f 1 0 k 1 0 k v dd1 +15 v 0. 1 f 0. 1 f -15 v + - a d624 c d g a in = 1 00 0. 47 f 0. 47 f
10 g - g a in - v/v v dd - su pp ly volt a ge - v 8 .0 28 8 .0 32 4 . 75 5 .0 8 .0 24 4 . 55 . 5 5 . 25 8 .0 3 8 .0 26 vs . v dd1 vs . v dd2 nl - nonline ar ity - % t a - te mp e ra tu r e - c 0.0 2 0.0 15 0.00 5 -25 0.0 3 35 9 5 0 0.0 25 -55 125 0.0 1 565 nl - nonline ar ity - % v dd - su pp ly volt a ge - v 0.00 5 4 . 75 5 .0 0.00 2 4 . 55 . 5 5 . 25 0.00 4 0.00 3 vs . v dd1 vs . v dd2 v o - out p ut volt a ge - v v in - in p ut volt a ge - v 2 . 6 1 . 8 - 0. 3 4 . 2 - 0. 1 0. 1 0. 3 1 .0 3 . 4 - 0. 5 0. 5 v o p v o r figure 5. gain and nonlinearity test circuit. 0. 1 f v dd2 8 7 6 1 3 acp l-782t 5 2 4 0.0 1 f 1 0 k 1 0 k +15 v 0. 1 f 0. 1 f -15 v + - a d624 c d g a in = 4 0. 47 f 0. 47 f v dd1 13 . 2 4 0 4 v in v out +15 v 0. 1 f 0. 1 f -15 v + - a d624 c d g a in = 1 0 1 0 k 0. 47 f 0. 1 f figure 6. gain vs. supply. figure 7. nonlinearity vs. temperature. figure 8. nonlinearity vs. supply. figure 9. output voltage vs. input voltage.
11 i dd - su pp ly c u rr ent - m a v in - in p ut volt a ge - v 7 - 0. 3 13 - 0. 1 0. 1 0. 3 4 1 0 - 0. 5 0. 5 i dd1 i dd2 i in - in p ut c u rr ent - a v in - in p ut volt a ge - v -3 - 0. 4 0 - 0. 2 0. 2 0. 4 -5 -1 - 0. 6 0. 6 -2 -4 0 g a in - d b f r equen c y (hz) -2 1 -4 0 1 0 1 00000 -1 -3 1 000 1 00 1 0000 p h a se - deg r ees f r equen c y (hz) -1 00 5 0 -3 00 0 1 0 1 00000 -5 0 -15 0 1 000 -2 00 -25 0 1 00 1 0000 p d - pr o pa g a tion del a y - s t a - te mp e ra tu r e - c 3 . 1 -25 5 . 5 565 9 5 1 . 5 4 . 7 -55 125 3 .9 2 . 3 35 tpd 1 0 tpd 5 0 tpd 90 trise figure 12. gain vs. frequency. figure 13. phase vs. frequency. figure 14. propagation delay vs. temperature. figure 10. supply current vs. input voltage. figure 11. input current vs. input voltage.
12 figure 15. propagation delay test circuits. figure 16. cmti test circuits. 0. 1 f v dd2 v out 8 7 6 1 3 acp l-782t 5 2 4 2 k 2 k +15 v 0. 1 f 0. 1 f -15 v - + mc 34 0 81 0. 1 f 1 0 k 1 0 k 0.0 1 f v dd1 v in v in i mp ed a n c e less th a n 1 0 w . 0. 1 f v dd2 v out 8 7 6 1 3 acp l-782t 5 2 4 2 k 2 k 78l 0 5 +15 v 0. 1 f 0. 1 f -15 v - + mc 34 0 81 15 0 pf in out 0. 1 f 0. 1 f 9 v p ulse gen . v cm + - 1 0 k 1 0 k 15 0 pf
13 application information power supplies and bypassing the recommended supply connections are shown in figure 17. a floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 v using a simple zener diode (d1); the value of resistor r4 should be chosen to supply sufficient current from the existing floating supply. the voltage from the current sensing resistor (rsense) is applied to the input of the acpl-782t through an rc anti-aliasing filter (r2 and c2). although the application circuit is relatively simple, a few recommenda- tions should be followed to ensure optimal performance. the power supply for the acpl -782t is most often obtained from the same supply used to power the power transis- tor gate drive circuit. if a dedicated supply is required, in many cases it is possible to add an additional winding on an existing transformer. otherwise, some sort of simple isolated supply can be used, such as a line powered trans- former or a high-frequency dc-dc converter. an inexpensive 78l05 three-terminal regulator can also be used to reduce the floating supply voltage to 5 v. to help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass filter with the regulators input bypass capacitor. as shown in figure 18, 0.1 f bypass capacitors (c1, c2) should be located as close as possible to the pins of the acpl-782t. the bypass capacitors are required because of the high-speed digital nature of the signals inside the acpl-782t. a 0.01f bypass capacitor (c2) is also rec- ommended at the input due to the switched-capacitor nature of the input circuit. the input bypass capacitor also forms part of the anti-aliasing filter, which is recom- mended to prevent high-frequency noise from aliasing down to lower frequencies and interfering with the input signal. the input filter also performs an important reliability functionit reduces transient spikes from esd events flowing through the current sensing resistor. acpl-782t c1 0.1 f r2 39 gate drive circuit floating power supply * * * hv+ * * * hv- * * * - + r sense motor c2 0.01 f d1 5.1 v - + r1 figure 17. recommended supply and sense resistor connections.
14 0.1 f +5 v v out 8 7 6 1 3 u2 5 2 4 r1 2.00 k +15 v c8 0.1 f 0.1 f -15 v - + mc34081 r3 10.0 k acpl-782t c4 r4 10.0 k c6 150 pf u3 u1 78l05 in out c1 c2 0.01 f r5 68 gate drive circuit positive floating supply hv+ * * * hv- - + r sense motor c5 150 pf 0.1 f 0.1 f c3 c7 r2 2.00 k * * * * * * figure 18. recommended application circuit. figure 19. example printed circuit board layout. pc board layout the design of the printed circuit board (pcb) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. in addition, the layout of the pcb can also affect the isolation transient immunity (cmti) of the acpl-782t, due primarily to stray capacitive coupling between the input and the output circuits. to obtain optimal cmti performance, the layout of the pc board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the pc board does not pass directly below or extend much wider than the body of the acpl-782t. c 3 c 2 c 4 r 5 to r sense+ to r sense- to v dd1 to v dd2 v out+ v out-
15 current sensing resistors the current sensing resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). choosing a particular value for the resistor is usually a compromise between minimiz- ing power dissipation and maximizing accuracy. smaller sense resistance decreases power dissipation, while larger sense resistance can improve circuit accuracy by utilizing the full input range of the acpl -782t. the first step in selecting a sense resistor is determining how much current the resistor will be sensing. the graph in figure 20 shows the rms current in each phase of a three- phase induction motor as a function of average motor output power (in horsepower, hp) and motor drive supply voltage. the maximum value of the sense resistor is deter- mined by the current being measured and the maximum recommended input voltage of the isolation amplifier. the maximum sense resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the sense resistor should see during normal operation. for example, if a motor will have a maximum rms current of 10 a and can experience up to 50% overloads during normal operation, then the peak current is 21.1 a (=10 x 1.414 x 1.5). assuming a maximum input voltage of 200 mv, the maximum value of sense re- sistance in this case would be about 10 m . the maximum average power dissipation in the sense resistor can also be easily calculated by multiplying the sense resistance times the square of the maximum rms current, which is about 1 w in the previous example. if the power dissipation in the sense resistor is too high, the re- sistance can be decreased below the maximum value to decrease power dissipation. the minimum value of the sense resistor is limited by precision and accuracy require- figure 20. motor output horsepower vs. motor phase current and supply voltage. ments of the design. as the resistance value is reduced, the output voltage across the resistor is also reduced, which means that the offset and noise, which are fixed, become a larger percentage of the signal amplitude. the selected value of the sense resistor will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specific design. when sensing currents large enough to cause significant heating of the sense resistor, the temperature coefficient (tempco) of the resistor can introduce nonlinearity due to the signal dependent temperature rise of the resistor. the effect increases as the resistor-to-ambient thermal resis- tance increases. this effect can be minimized by reducing the thermal resistance of the current sensing resistor or by using a resistor with a lower tempco. lowering the thermal resistance can be accomplished by reposition- ing the current sensing resistor on the pc board, by using larger pc board traces to carry away more heat, or by using a heat sink. for a two-terminal current sensing resistor, as the value of resistance decreases, the resistance of the leads become a significant percentage of the total resistance. this has two primary effects on resistor accuracy. first, the effective resistance of the sense resistor can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the leads during assembly (these issues will be discussed in more detail shortly). second, the leads are typically made from a material, such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco overall. both of these effects are eliminated when a four-terminal current sensing resistor is used. a four- terminal resistor has two additional terminals that are kelvin-connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. because of the kelvin connec- tion, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. when laying out a pc board for the current sensing resistors, a couple of points should be kept in mind. the kelvin con- nections to the resistor should be brought together under the body of the resistor and then run very close to each other to the input of the acpl-782t; this minimizes the loop area of the connection and reduces the possibility of stray magnetic fields from interfering with the measured signal. if the sense resistor is not located on the same pc board as the acpl-782t circuit, a tightly twisted pair of wires can accomplish the same thing. m oto r p h a se c u rr ent - a (rms) 15 5 4 0 1 0 25 3 0 0 35 0 35 25 1 0 2 0 44 0 v 38 0 v 22 0 v 12 0 v 3 0 2 0 5 15 m oto r out p ut p owe r - ho r se p owe r
16 also, multiple layers of the pc board can be used to increase current carrying capacity. numerous plated- through vias should surround each non-kelvin terminal of the sense resistor to help distribute the current between the layers of the pc board. the pc board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 a. note: please refer to avago technologies application note 1078 for additional information on using isolation amplifiers. sense resistor connections the recommended method for connecting the acpl-782t to the current sensing resistor is shown in figure 18. v in+ (pin 2 of the apcl-782t) is connected to the positive terminal of the sense resistor, while vin- (pin 3) is shorted to gnd1 (pin 4), with the power-supply return path func- tioning as the sense line to the negative terminal of the current sense resistor. this allows a single pair of wires or pc board traces to connect the acpl-782t circuit to the sense resistor. by referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the resistor are seen as a common-mode signal and will not interfere with the cur- rent-sense signal. this is important because the large load currents flowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and offsets that are rela- tively large compared to the small voltages that are being measured across the current sensing resistor. if the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very important that the connection from gnd1 of the acpl-782t to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. the only direct connection between the acpl-782t circuit and the gate drive circuit should be the positive power supply line. output side the op-amp used in the external post-amplifier circuit should be of sufficiently high precision so that it does not contribute a significant amount of offset or offset drift relative to the contribution from the isolation amplifier. generally, op-amps with bipolar input stages exhibit better offset performance than op-amps with jfet or mosfet input stages. in addition, the op-amp should also have enough bandwidth and slew rate so that it does not adversely affect the response speed of the overall circuit. the post- amplifier circuit includes a pair of capacitors (c5 and c6) that form a single-pole low-pass filter; these capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isolation amplifier. many different op-amps could be used in the circuit, including: tl032a, tl052a, and tlc277 (texas instruments), lf412a (national semiconductor). the gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate cmrr and adequate gain tolerance for the overall circuit. resistor networks can be used that have much better ratio tolerances than can be achieved using discrete resistors. a resistor network also reduces the total number of components for the circuit as well as the required board space. figure 21. recommended circuit for voltage sensing application. line 1 1 2 3 4 8 7 6 5 acp l-782t +5 v +15 v 0.0 1 f 0. 1 f 0. 1 f 0. 1 f 1 0.0 k 15 0 pf 2 .0 k 2 .00 k -15 v tl 0 32 a + - v out 0. 1 f + su pp ly 15 0 pf 78l 0 5 in out 0. 1 f line 2 6 5 8 4 7 1 0.0 k 3 9 + 5 v r a r b note for the voltage divider : v (line) x [ r b / ( r a+ r b) ] <= 2 00 mv
17 voltage sensing for dc rail measurement acpl-782t is a suitable device to measure the dc rail voltage over different potentials. in a dc rail voltage sensing application, the line1 and line2 in figure 21 are the dc lines to be measured. dividing ratio error due to the tolerances of the resistors from a differential calculation, the error in the voltage divider of ra and rb is expressed as a/a = ra/(ra + rb) * ( rb/rb C ra/ra) (1) where a is the ratio of the resistor divider consisting of ra and rb. since the errors of the resistors, rb/rb and ra/ra are independent to each other, we need to take absolute values in equation (1) to know the maximum possible gain error of the divider and it gives a/a = ra/(ra + rb) * ( | rb/rb| + | ra/ra|) (2) figure 22 is the plot of the equation (2) when the resistors have 1% tolerance expressing the relationship between the ratio of ra to (ra+rb) and the possible maximum error of the dividing ratio. dividing error when 1% resistors are used(%) 0 0. 5 1 1 . 5 2 0. 5 0. 6 0. 7 0. 8 0.9 1 .0 r a/( r a+ r b) dividererror (%) figure 22: divider error % vs resistors divider note on the thermistor and the rl: v dd x [rl/(rth + rl)] x [ r3/(r2 + r3)] <= 200 mv, assuming r2+r3 >> r1 rth: resistance of thermistor rl: linearizing resistor value = r1//(r2+r3) 1 2 3 4 8 7 6 5 acp l-782t +5 v +15 v 1 f 0. 1 f 0. 1 f 0. 1 f 1 0.0 k 15 0 pf 2 .0 k 2 .0 -15 v tl 0 32 a + - v out 0. 1 f + su pp ly 15 0 pf 78l 0 5 in out 0. 1 f 6 5 8 4 7 1 0.0 k 3 9 +5 v r 1 semitec e c 2f1 0 3 a 2-4 0 113 thermistor ig b t attaching type th r l = r 1//( r 2+ r 3) r 3 r 2 k figure 23. recommended circuit for temperature sensing application.
for pro d u c t in f ormation an d a c omplete list o f d istri b utors, please go to our we b site: www.avagotech.com avago, avago te c hnologies, the a logo an d r 2 coupler? are tra d emarks o f avago te c hnologies in the unite d s tates an d other c ountries. data su b je c t to c hange. cop y right ? 2005 - 2011 avago te c hnologies. all rights reserve d . av02 - 15 6 5en - mar c h 23, 2011 isolated temperature sensing using thermistor thermistor is widely used to measure temperatures in most systems application. a galvanic isolation between the potential of the thermistor and that of the analog- to-digital is often required when they are mounted in locations such as high voltage potential, electrically noisy environments, poorly grounded environments, where lack of isolation causes either safety or emi issues. rl = r1//(r2+r3)=r1(r2+r3)/(r1+r2+r3) r2 and r3 divides the voltage across rl so that the voltage fed into acpl-782t does not exceed +200 mv. the high impedance characteristic of the input terminals of acpl- 782t helps in determining those resistors value since one can select relatively high resistance of r2 and r3 and r1 can be determined easily. if r2+r3 >> r1, rl ~ r1 dividing ratio ~ r3/(r2+r3) as can be seen from the circuit, one might eliminate r1 and rl~(r2+r3) in this case. an application example with a thermistor designed for measuring igbts surface temperatures is shown in figure 23. where th is the thermistor and the rl is a resistor for linearization. suitable rl value is determined from the thermistor characteristic and the temperature range to measure. please note that the rl value is the compound value of r1, r2 and r3.

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