revision 2.0 september 2004 K1S3216BCC - 1 - u t ram document title 2mx16 bit page mode uni-transistor random access memory the attached datasheets are provided by samsu ng electronics. samsung electronics co., ltd. reserve the right to change the spe cifications and products. samsung electronics will answer to your questions about device. if you have any questio ns, please contact the samsung branch offices. revision history revision no. 1.0 2.0 remark final final history revised - corrected toh from 5ns to 3ns. draft date february 25, 2004 september 20, 2004
revision 2.0 september 2004 K1S3216BCC - 2 - u t ram product family product family operating temp. vcc range speed (t rc ) power dissipation pkg type standby (i sb1 , max.) operating (i cc2 , max.) K1S3216BCC-i industrial(-40~85 c) 1.7~2.1v 70ns 100 a 35ma 48-fbga-6.00x8.00 2m x 16 bit page mode uni-transistor cmos ram general description the K1S3216BCC is fabricated by samsung s advanced cmos technology using one transi stor memory cell. the device support 4 page mode operation, industrial temperature range and 48 ball chip scale package for user flexibility of system design. the device also supports deep power down mode for low standby current. features ? process technology: cmos ? organization: 2m x16 bit ? power supply voltage: 1.7~2.1v ? three state outputs ? compatible with low power sram ? support 4 page read mode ? package type: 48-fbga-6.00x8.00 pin description 1) reserved for future use name function name function cs 1,cs2 chip select inputs vcc power oe output enable input vss ground we write enable input ub upper byte(i/o 9 ~ 16 ) a 0 ~a 20 address inputs lb lower byte(i/o 1 ~ 8 ) i/o 1 ~i/o 16 data inputs/outputs nc no connection 1) 48-fbga: top view(ball down) lb oe a0 a1 a2 cs2 i/o9 ub a3 a4 cs 1 i/o1 i/o10 i/o11 a5 a6 i/o2 i/o3 vss i/o12 a17 a7 i/o4 vcc vcc i/o13 nc a16 i/o5 vss i/o15 i/o14 a14 a15 i/o6 i/o7 i/o16 a19 a12 a13 we i/o8 a18 a8 a9 a10 a11 a20 1 23456 a b c d e f g h samsung electronics co., ltd. reserves the right to change produc ts and specifications without notice . functional block diagram clk gen. row select i/o 1 ~i/o 8 data cont data cont data cont i/o 9 ~i/o 16 vcc vss precharge circuit. memory array i/o circuit column select we oe ub cs1 lb control logic cs2 row addresses column addresses
revision 2.0 september 2004 K1S3216BCC - 3 - u t ram power up sequence 1. apply power. 2. maintain stable power(vcc min.=1.7v) for a minimum 200 s with cs 1=high.or cs2=low. min. 200 s timing waveform of power up(1) (cs 1 controlled) timing waveform of power up(2) (cs 2 controlled) power up(2) 1. after v cc reaches v cc (min.), wait 200 s with cs 2 low. then the device gets into the normal operation. v cc cs 1 cs 2 v cc(min) power up(1) 1. after v cc reaches v cc (min.), wait 200 s with cs 1 high. then the device gets into the normal operation. min. 200 s v cc cs 1 cs 2 v cc(min) normal operation power up mode normal operation power up mode
revision 2.0 september 2004 K1S3216BCC - 4 - u t ram absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ra tings" may cause permanent damage to the device. functional ope ration should be restricted to be used under recommended operating condition. expo sure to absolute maximum rating conditions longer than 1 secon d may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v v voltage on vcc supply relative to vss v cc -0.2 to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c functional description 1. x means don t care.(must be low or high state) cs 1 cs2 oe we lb ub i/o 1~8 i/o 9~16 mode power h x 1) x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) x 1) x 1) x 1) h h high-z high-z deselected standby lhhhl x 1) high-z high-z output disabled active lhhh x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active lh x 1) l l h din high-z lower byte write active lh x 1) l h l high-z din upper byte write active lh x 1) l l l din din word write active
revision 2.0 september 2004 K1S3216BCC - 5 - u t ram dc and operating characteristics 1. typical values are tested at v cc =2.9v, t a =25 c and not guaranteed. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to vcc -1 - 1 a output leakage current i lo cs =v ih, zz =v ih , oe =v ih or we =v il , v io =vss to vcc -1 - 1 a average operating current i cc1 cycle time=1 s, 100% duty, i io =0ma, cs 0.2v, zz vcc-0.2v, v in 0.2v or v in v cc -0.2v --5ma i cc2 cycle time=t rc +3t pc , i io =0ma, 100% duty, cs =v il , zz =v ih, v in =v il or v ih -35ma output low voltage v ol i ol =2.1ma - - 0.2 v output high voltage v oh i oh =-1.0ma 1.4 - - v standby current(cmos) i sb1 2) cs vcc-0.2v, zz vcc-0.2v, other inputs=vss to vcc - - 100 a recommended dc operating conditions 1) 1. t a =-40 to 85 c, otherwise specified. 2. overshoot: vcc+1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 1.7 1.8/2.0 2.1 v ground vss 0 0 0 v input high voltage v ih 1.4 - vcc+0.3 2) v input low voltage v il -0.2 3) -0.4v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf product list industrial temperature product(-40~85 c) part name function K1S3216BCC-fi70 K1S3216BCC-fi85 48-fbga, 70ns, 1.8/2.0v 48-fbga, 85ns, 1.8/2.0v
revision 2.0 september 2004 K1S3216BCC - 6 - u t ram ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.2 to vcc-0.2v input rising and falling time: 5ns input and output reference voltage: 0.5 x v cc output load (see right): c l =50pf c l 1. including scope and jig capacitance dout ac characteristics (vcc=1.7~2.1v, t a =-40 to 85 c) 1. t wp (min)=70ns for continuous write operation over 50 times. parameter list symbol speed bins units 70ns 85ns min max min max read read cycle time t rc 70 - 85 - ns address access time t aa - 70 - 85 ns chip select to output t co - 70 - 85 ns output enable to valid output t oe - 35 - 40 ns ub , lb access time t ba - 70 - 85 ns chip select to low-z output t lz 10 - 10 - ns ub , lb enable to low-z output t blz 10 - 10 - ns output enable to low-z output t olz 5- 5 - ns chip disable to high-z output t hz 0 25 0 25 ns ub , lb disable to high-z output t bhz 0 25 0 25 ns output disable to high-z output t ohz 0 25 0 25 ns output hold from address change t oh 3- 3 - ns page cycle t pc 25 - 25 - ns page access time t pa - 20 - 20 ns write write cycle time t wc 70 - 85 - ns chip select to end of write t cw 60 - 70 - ns address set-up time t as 0- 0 - ns address valid to end of write t aw 60 - 70 - ns ub , lb valid to end of write t bw 60 - 70 - ns write pulse width t wp 55 1) - 60 1) -ns write recovery time t wr 0- 0 - ns write to output high-z t whz 0 25 0 25 ns data to write time overlap t dw 30 - 35 - ns data hold from write time t dh 0- 0 - ns end write to output low-z t ow 5- 5 - ns
revision 2.0 september 2004 K1S3216BCC - 7 - u t ram address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs =oe =v il , we= v ih , ub or/and lb =v il ) timing waveform of read cycle(2) (we =v ih ) t aa t rc t oh (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the op en circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given devic e and from device to device interconnection. 3. t oe (max) is met only when oe becomes enabled after t aa (max). 4. if invalid address signals shorter than min. t rc are continuously repeated for over 4u s, the device needs a normal read timing(t rc ) or needs to sustain standby state for min. t rc at least once in every 4us. data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t co address ub , lb oe data out timing waveform of page cycle(read only) data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa high z a20~a2 a1~a0 dq15~dq0 oe t ohz t oe t co t aa cs 1 cs 2 cs 1 cs 2
revision 2.0 september 2004 K1S3216BCC - 8 - u t ram timing waveform of write cycle(2) (cs 1 controlled) address data valid ub , lb we data in data out high-z t wc t cw t aw t bw t wp t dh t dw t wr t as cs 1 cs 2 timing waveform of write cycle(1) (we controlled) address cs 1 data undefined ub , lb we data in data out t wc t cw t wr t aw t bw t wp t as t dh t dw t whz t ow high-z high-z data valid cs 2
revision 2.0 september 2004 K1S3216BCC - 9 - u t ram address data valid ub , lb we data in data out high-z timing waveform of write cycle(4) (ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs 1 and low we . a write begins when cs 1 goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest tran- sition when cs 1 goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs 1 or we going high. t wc t cw t bw t wp t dh t dw t wr t aw t as cs 1 cs 2 timing waveform of write cycle(3) (cs 2 controlled) address data valid ub , lb we data in data out high-z t wc t cw t aw t bw t wp(1) t dh t dw t wr t as cs 1 cs 2
revision 2.0 september 2004 K1S3216BCC - 10 - u t ram package dimension 654321 a b c d e f g h c b c1 b c bottom view top view d e1 e c side view a y detail a min typ max a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 7.90 8.00 8.10 c1 - 5.25 - d 0.40 0.45 0.50 e - 1.00 e1 0.25 y- -0.10 b1 #a1 notes. 1. bump counts: 48(8 row x 6 column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are 0.050 unless specified beside figures. 4. typ : typical 5. y is coplanarity unit: millimeters 48 ball fine pitch bga(0.75mm ball pitch) e1
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