asahi kasei [AK2546] 2002/5 1 AK2546 7 channel t1 transceiver feature ? 7ch short haul t1 transceiver ? jitter tolerance: compliant with gr-499 category i, ii ? transmitter pulse shape: compliant with gr-499 ? loss of signal detection ? selectable signal polarity ? local/remote loopback ? parallel microprocessor interface ? single 3.3v5% operation ? low power consumption (105mw/ch: typ) ? pin-to-pin compatible with ak2548 (7 channel e1 transceiver) ? small plastic package 144pin lqfp block diagram transceiver 1 transceiver 2-7 7 channel t1 transceiver block diagram recover clkgen mclk mclk mclk mclk rtip1 rtip1 rtip1 rtip1 rring1 rring1 rring1 rring1 as(ale) a s ( ale ) as ( ale ) a s(ale) rclk1 rclk1 rclk1 rclk1 rpos1 rpos1 rpos1 rpos1 rneg1 rneg1 rneg1 rneg1 los1 los1 los1 los1 rtip2 rtip2 rtip2 rtip2- - - -7 7 7 7 rring2 rring2 rring2 rring2- - - -7 7 7 7 los2 los2 los2 los2- - - -7 7 7 7 rclk2 rclk2 rclk2 rclk2- - - -7 7 7 7 rpos2 rpos2 rpos2 rpos2- - - -7 7 7 7 rneg2 rneg2 rneg2 rneg2- - - -7 7 7 7 tclk2 tclk2 tclk2 tclk2- - - -7 7 7 7 tpos2 tpos2 tpos2 tpos2- - - -7 7 7 7 tneg2 tneg2 tneg2 tneg2- - - -7 7 7 7 ds(rd) ds ( rd ) ds ( rd ) ds(rd) test1 test1 test1 test1- - - -5 5 5 5 shaper ttip1 ttip1 ttip1 ttip1 tring1 tring1 tring1 tring1 tneg1 tneg1 tneg1 tneg1 tpos1 tpos1 tpos1 tpos1 tclk1 tclk1 tclk1 tclk1 control ttip2 ttip2 ttip2 ttip2- - - -7 7 7 7 tring2 tring2 tring2 tring2- - - -7 7 7 7 ad7 a d7 ad7 a d7- - - -ad0 ad0 ad0 ad0 local loopback reset reset reset reset r /w (wr) r /w ( wr ) r /w ( wr ) r /w (wr) cs cs cs cs bts bts bts bts int int int int los clk clk clk clksel sel sel sel remote loopback
asahi kasei [AK2546] 2002/5 2 general description the AK2546 is the 7 channel short haul t1 transceiver for a sonet mux, m13 mux, etc. it includes seven independent transmitters, clock and data recovery, los detector, control circuit in one lqfp-144 package which saves space, power consumption and the board design time. internally generated transmit pulse provides the appropriate pulse shape for line length ranging from 0 to 655 feet from a dsx-1 cross connect. pin assignments tclk1 tpos1 tneg1 rclk1 rpos1 rneg1 tclk2 tpos2 tneg2 rclk2 rpos2 rneg2 iovdd1 iovss1 tavdd1 tavss1 tclk3 tpos3 tneg3 rclk3 rpos3 rneg3 davss1 dvss1 dvdd1 tclk4 tpos4 tneg4 rclk4 rpos4 rneg4 los1 los2 los3 los4 ravdd1 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 tclk7 tpos7 tneg7 rclk7 rpos7 rneg7 tclk6 tpos6 tneg6 rclk6 rpos6 rneg6 iovdd2 iovss2 tavdd2 tavss2 tclk5 tpos5 tneg5 rclk5 rpos5 rneg5 davss2 dvss2 dvdd2 los7 los6 los5 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 avss8 ttip7 tvss7 tvdd7 tring7 avss7 ttip6 tvss6 tvdd6 tring6 avss6 ttip5 tvss5 tvdd5 tring5 avss5 ttip4 tvss4 tvdd4 tring4 avss4 ttip3 tvss3 tvdd3 tring3 avss3 ttip2 tvss2 tvdd2 tring2 avss2 ttip1 tvss1 tvdd1 tring1 avss1 r/w(wr) as(ale) ds(rd) cs int pvdd mcl k pvss ravss2 ravdd2 reset rring7 rtip7 bts rring6 rtip6 test5 rring5 rtip5 test4 bvss bgref bvdd test3 rring4 rtip4 test2 rring3 rtip3 clksel rring2 rtip2 test1 rring1 rtip1 ravss1 (top view)
asahi kasei [AK2546] 2002/5 3 pin condition pin no. pin name i/o pin type ac load dc load comments 1 tclk7 i cmos 2 tpos7 i cmos 3 tneg7 i cmos 4 rclk7 o cmos 15pf 5 rpos7 o cmos 15pf 6 rneg7 o cmos 15pf 7 tclk6 i cmos 8 tpos6 i cmos 9 tneg6 i cmos 10 rclk6 o cmos 15pf 11 rpos6 o cmos 15pf 12 rneg6 o cmos 15pf 13 iovdd2 i power 14 iovss2 i power 15 tavdd2 i power 16 tavss2 i power 17 tclk5 i cmos 18 tpos5 i cmos 19 tneg5 i cmos 20 rclk5 o cmos 15pf 21 rpos5 o cmos 15pf 22 rneg5 o cmos 15pf 23 davss2 i power 24 dvss2 i power 25 dvdd2 i power 26 los7 o cmos 15pf 27 los6 o cmos 15pf 28 los5 o cmos 15pf 29 ad0 i/o cmos 50pf 30 ad1 i/o cmos 50pf 31 ad2 i/o cmos 50pf 32 ad3 i/o cmos 50pf 33 ad4 i/o cmos 50pf 34 ad5 i/o cmos 50pf 35 ad6 i/o cmos 50pf 36 ad7 i/o cmos 50pf
asahi kasei [AK2546] 2002/5 4 pin no. pin name i/o pin type ac load dc load comments 37 r/w(wr) i cmos 38 as(ale) i cmos 39 ds(rd) i cmos 40 cs i cmos 41 int o open drain pmos open drain 42 pvdd i power 43 mclk i cmos 44 pvss i power 45 ravss2 i power 46 ravdd2 i power 47 reset i cmos 48 rring7 i analog 49 rtip7 i analog 50 bts i cmos 51 rring6 i analog 52 rtip6 i analog 53 test5 i cmos note1) 54 rring5 i analog 55 rtip5 i analog 56 test4 i cmos note1) 57 bvss i power 58 bgref o analog 12k ? 1% accuracy 59 bvdd i power 60 test3 i cmos note1) 61 rring4 i analog 62 rtip4 i analog 63 test2 i cmos note2) 64 rring3 i analog 65 rtip3 i analog 66 clksel i cmos 67 rring2 i analog 68 rtip2 i analog 69 test1 i cmos note1) 70 rring1 i analog 71 rtip1 i analog 72 ravss1 i power
asahi kasei [AK2546] 2002/5 5 pin no. pin name i/o pin type ac load dc load comments 73 ravdd1 i power 74 los4 o cmos 15pf 75 los3 o cmos 15pf 76 los2 o cmos 15pf 77 los1 o cmos 15pf 78 rneg4 o cmos 15pf 79 rpos4 o cmos 15pf 80 rclk4 o cmos 15pf 81 tneg4 i cmos 82 tpos4 i cmos 83 tclk4 i cmos 84 dvdd1 i power 85 dvss1 i power 86 davss1 i power 87 rneg3 o cmos 15pf 88 rpos3 o cmos 15pf 89 rclk3 o cmos 15pf 90 tneg3 i cmos 91 tpos3 i cmos 92 tclk3 i cmos 93 tavss1 i power 94 tavdd1 i power 95 iovss1 i power 96 iovdd1 i power 97 rneg2 o cmos 15pf 98 rpos2 o cmos 15pf 99 rclk2 o cmos 15pf 100 tneg2 i cmos 101 tpos2 i cmos 102 tclk2 i cmos 103 rneg1 o cmos 15pf 104 rpos1 o cmos 15pf 105 rclk1 o cmos 15pf 106 tneg1 i cmos 107 tpos1 i cmos 108 tclk1 i cmos
asahi kasei [AK2546] 2002/5 6 pin no. pin name i/o pin type ac load dc load comments 109 avss1 i power 110 tring1 o analog driver output 111 tvdd1 i power 112 tvss1 i power 113 ttip1 o analog driver output 114 avss2 i power 115 tring2 o analog driver output 116 tvdd2 i power 117 tvss2 i power 118 ttip2 o analog driver output 119 avss3 i power 120 tring3 o analog driver output 121 tvdd3 i power 122 tvss3 i power 123 ttip3 o analog driver output 124 avss4 i power 125 tring4 o analog driver output 126 tvdd4 i power 127 tvss4 i power 128 ttip4 o analog driver output 129 avss5 i power 130 tring5 o analog driver output 131 tvdd5 i power 132 tvss5 i power 133 ttip5 o analog driver output 134 avss6 i power 135 tring6 o analog driver output 136 tvdd6 i power 137 tvss6 i power 138 ttip6 o analog driver output 139 avss7 i power 140 tring7 o analog driver output 141 tvdd7 i power 142 tvss7 i power 143 ttip7 o analog driver output 144 avss8 i power note1 ) should be connected to vss externally. note2 ) should be connected to vdd externally
asahi kasei [AK2546] 2002/5 7 pin descriptions pin name i/o function comment t1 transceiver ttip1-7 tring1-7 o o transmit tip/ring output bipolar output over transmit transformer tpos1-7 tneg1-7 i i transmit positive/negative data input input on the falling edge of tclk tclk1-7 i transmit clock input rtip1-7 rring1-7 i i receive tip/ring input bipolar input over receive transformer rpos1-7 rneg1-7 o o receive positive/negative data output output on the falling edge of rclk rclk1-7 o receive clock output recovered from receive data input los1-7 o loss of signal output output ?high? when detect loss of signal losx output is not masked by mlosx register. tvdd1-7 positive power supply for the transmit driver tvss1-7 negative power supply for the transmit driver avss1-8 analog ground common block mclk i 1.544mhz or 24.704mhz external reference clock input as(ale) i address select(address latch enable) input int o interrupt output(pmos open drain, should be tied to gnd through a resistor), active high, int output goes ?high? when the alarm is reported to any one of losx, lotcx or lomc registers. this pin can be masked by mlosx, mlotcx or mlomc registers. ds(rd) i data strobe(read enable) input r/w (wr) i read/write(write enable) input cs i chip select input bts i bus type select input bts=?h? : motorola mode bts=?l? : intel mode ad0-ad7 i/o address/data input/output used for read/write internal registers. clksel i mclk select input clksel=?h?:1.544mhz clksel=?l?:24.704mhz reset i reset input active ?low? input pulse over 200ns initializes the internal circuit and forces rposx/rnegx output ?low? and losx output ?high?.
asahi kasei [AK2546] 2002/5 8 pin name i/o function comment common block test1,3-5 i factory use. should be connected to vss externally. test2 i factory use. should be connected to vdd externally. tavdd1,2 positive power supply for the analog circuitry in the transmitters tavss1,2 negative power supply for the analog circuitry in the transmitters ravdd1,2 positive power supply for the digital circuitry in the transmitters ravss1,2 negative power supply for the digital circuitry in the transmitters dvdd1,2 positive power supply for digital dvss1,2 negative power supply for digital davss1,2 ground for digital iovdd1,2 positive power supply for i/o iovss1,2 negative power supply for i/o bvdd positive power supply for reference circuit bvss negative power supply for reference circuit pvdd positive power supply for pll pvss negative power supply for pll bgref bandgap reference output. 12k ? 1% external register should be connected across this pin and vss.
asahi kasei [AK2546] 2002/5 9 absolute maximum ratings parameter symbol min typ max units condition dc supply vdd -0.3 6.5 v vin1 -0.3 vdd+0.3 v apply to except for rtipx, rringx input voltage vin2 -3 vdd+0.3 v apply to rtipx, rringx input current iin 10 ma storage temperature tstg -55 130 c note) all voltages with respect to ground. : all negative voltage pins = 0v. vdd apply to all positive voltage pins. recommended operating conditions parameter symbol min typ max units condition dc supply vdd 3.135 3.3 3.465 v 3.3v5% ambient operating temperature ta -40 25 +85 c note) all voltages with respect to ground. : all negative voltage pins = 0v. vdd apply to all positive voltage pins. electorical characteristics dc characteristics parameter symbol min typ max units condition power consumption(/ch) pd 105 260 mw note1 digital high-level output voltage voh 0.9vdd v ioh=-40a digital low-level output voltage vol 0.4 v iol=500a digital high-level input voltage vih 0.7vdd v digital low-level input voltage vil 0.3vdd v input leak current ii 10 a output current iol 1.0 ma int pin note1: typ : 50% mark, room temp., vdd 3.3v, line length 399feet, load 100 ? max: 100% mark, temp./vdd in all range, line length 655feet, load 100 ? not include any other load (ex. external pull up register) except lines.
asahi kasei [AK2546] 2002/5 10 receiver receiver characteristics are guaranteed on the conditions as shown below. vdd=3.3v5%, vss, gnd=0v, ta=-40~85c, mclk frequency: 1.544mhz100ppm, 24.704mhz100ppm, bipolar input frequency: 1.544mhz130ppm(reference input level: 3v 0p 20%) parameter symbol min typ max units condition sensitivity -6 db note1 loss of signal threshold 0.35 0.5 0.7 v note2 allowable consecutive zero before los 170 175 180 bits s/x tolerance 12 db note3 generated jitter 30 nspp note4 low pulse density immunity 1/16 mark jitter tolerance gr-499 category i,ii note1: relative value to the reference level. compare at 772khz with all mark pattern. note2: level at the chip side of transformer. loss of signal is logical and between an analog loss of signal monitors input level and a digital loss of signal check recovered data stream. note3: pn20 and ami 1/8 mark pattern input. noise frequency is 770khz. note4: pn20 pattern input. jitter tolerance 0.01 0.1 1 10 100 1 10 100 1000 10000 100000 jiiter frequency(hz) jitter amplitude(uipp) gr-499 category ii gr-499 category i
asahi kasei [AK2546] 2002/5 11 transmitter transmitter characteristics are guaranteed on the conditions as shown below. vdd=3.3v5%, vss, gnd=0v,ta=-40~85c, mclk frequency: 1.544mhz100ppm, 24.704mhz100ppm parameter symbol min typ max units condition output pulse shape gr-499, note1 output pulse amplitude 2.5 3.0 3.5 v 0p note1, note2 output pulse imbalance 0.4 db output jitter 10hz-8khz 10hz-40khz 8khz-40khz broad band 0.02 0.025 0.025 0.05 uipp power levels@772khz 12.6 15 17.9 dbm note3 power levels @1.544mhz -29 db note3, note4 note1: measured at the dsx terminated with 100 ? . note2: amplitude at the pulse center to normalize to unity. turns ratio and dcr are recommended value. note3: measured in a 2khz band width around the specified frequency. transmit all mark pattern. note4: compare to the power at 772khz isolated pulse mask (gr-499) normalized amplitude -1 -0.5 0 0.5 1 1.5 -1-0.500.511.5 time, in unit intervals
asahi kasei [AK2546] 2002/5 12 ac characteristics (clock/data) parameter symbol min typ max units condition clock frequency mclk fci 1.543846 24.70153 1.544000 24.70400 1.544154 24.70647 mhz 100ppm clock pulse width mclk tclk t pwhi t pwli 324 ns refer to fig.2 clock pulse width rclk t pwho t pwlo 324 ns refer to fig.1 duty cycle rclk tclk 50 % note1 setup/hold time rclk rpos rneg t su1 t h1 150 ns refer to fig.1 setup/hold time tclk tpos tneg t su2 t h2 50 ns refer to fig.2 rise time rclk rpos rneg t r 100 ns refer to fig.3 note2 fall time tclk tpos tneg t f 40 ns refer to fig.3 note2 note1) duty cycle:(t pwho /( t pwho +t pwlo ))100% note2) drive 15pf load capacitance
asahi kasei [AK2546] 2002/5 13 fig.1 receiver timing fig.2 transmitter timing fig.3 rise and fall times (rclk, rpos, rneg, tclk, tpos, tneg) t pwho t pwlo t sur t hr rclk rpos/rneg 50% 50% 50% 50% t r t f 10% 10% 90% 90% t sut t ht t pwhi t pwli 50% 50% 50% 50% tclk tpos/tneg
asahi kasei [AK2546] 2002/5 14 ac characteristics (parallel port) parameter symbol min typ max units condition read/write cycle tcyc 250 ns motorola mode address setup time t1 10 ? ? ns address hold time t2 10 ? ? ns as to ds delay time t3 20 ? ? ns ds to as delay time t4 20 ? ? ns read data delay time t5 ? ? 40 ns read data hold time t6 ? ? 20 ns r/w setup time t7 10 ? ? ns r/w hold time t8 10 ? ? ns cs setup time t9 10 ? ? ns cs hold time t10 15 ? ? ns write data setup time t11 40 ? ? ns write data hold time t12 20 ? ? ns ds pulse width t13 100 ? ? ns as pulse width t14 20 ? ? ns address invalid to ds delay time t15 0 ? ? ns intel mode address setup time t21 10 ? ? ns address hold time t22 10 ? ? ns ale to wr delay time t23 20 ? ? ns wr to ale delay time t24 20 ? ? ns rd to ale delay time t25 20 ? ? ns read data delay time t26 ? ? 40 ns read data hold time t27 ? ? 20 ns cs setup time t28 10 ? ? ns cs hold time t29 15 ? ? ns write data setup time t30 40 ? ? ns write data hold time t31 20 ? ? ns rd pulse width t32 100 ? ? ns wr pulse width t33 100 ? ? ns ale pulse width t34 20 ? ? ns address invalid to rd delay time t35 0 ? ? ns notes) cl= 50pf on ad0-ad7. all of the timing is specified at 50%vdd.
asahi kasei [AK2546] 2002/5 15 motorola mode(read) cs ds a s a d7-0 r/w a ddress data t1 t2 t13 t8 t6 t7 t9 t10 cs ds a s a d7-0 r/w a ddress data t1 t2 t3 t13 t12 t7 t9 t10 t8 motorola mode(write) t14 t11 t14 t5 t4 t4 t15
asahi kasei [AK2546] 2002/5 16 intel mode(read) cs wr a le a d7-0 rd a ddress data t21 t22 t34 t26 t27 t28 t29 cs wr a le a d7-0 rd a ddress data t21 t22 t31 t28 t29 t30 intel mode(write) t33 t24 t32 t25 t34 t23 t35
asahi kasei [AK2546] 2002/5 17 register description register map *a7-a4= ? 0? address function a3 a2 a1 a0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 status register (read only) 0 0 0 0 los7 (1) los6 (1) los5 (1) los4 (1) los3 (1) los2 (1) los1 (1) 0 0 0 0 1 lotc7 (1) lotc6 (1) lotc5 (1) lotc4 (1) lotc3 (1) lotc2 (1) lotc1 (1) lomc (1) mask control register (write/read) 0 0 1 0 mlos7 (1) mlos6 (1) mlos5 (1) mlos4 (1) mlos3 (1) mlos2 (1) mlos1 (1) rden (0) 0 0 1 1 mlotc7 (1) mlotc6 (1) mlotc5 (1) mlotc4 (1) mlotc3 (1) mlotc2 (1) mlotc1 (1) mlomc (1) channel control register (write/read) 0 1 1 0 leng31 (0) leng21 (0) leng11 (0) rloop1 (0) lloop1 (0) poln1 (1) msk1 (1) pd1 (1) 0 1 1 1 leng32 (0) leng22 (0) leng12 (0) rloop2 (0) lloop2 (0) poln2 (1) msk2 (1) pd2 (1) 1 0 0 0 leng33 (0) leng23 (0) leng13 (0) rloop3 (0) lloop3 (0) poln3 (1) msk3 (1) pd3 (1) 1 0 0 1 leng34 (0) leng24 (0) leng14 (0) rloop4 (0) lloop4 (0) poln4 (1) msk4 (1) pd4 (1) 1 0 1 0 leng35 (0) leng25 (0) leng15 (0) rloop5 (0) lloop5 (0) poln5 (1) msk5 (1) pd5 (1) 1 0 1 1 leng36 (0) leng26 (0) leng16 (0) rloop6 (0) lloop6 (0) poln6 (1) msk6 (1) pd6 (1) 1 1 0 0 leng37 (0) leng27 (0) leng17 (0) rloop7 (0) lloop7 (0) poln7 (1) msk7 (1) pd7 (1) *other address is reserved. * initial value is in ( ). *?<>? show i/o pin name. address a0-a3 should be input via ad0-ad3 pins.
asahi kasei [AK2546] 2002/5 18 status register symbol description losx (x=1 to 7) loss of signal alarm for channel x. read only register. when the loss of signal is detected, losx is set high. lotcx (x=1 to 7) loss of tclk alarm for channel x. read only register. when the loss of tclkx is detected, lotcx is set high. lomc loss of mclk alarm. read only register. when the loss of mclk is detected, lomc is set high. mask control symbol description mlosx (x=1 to 7) mask loss of signal alarm for channel x. mlosx is active-high to prevent losx from setting int output ?high?. it is possible to read losx register regardless of the status of mlosx. initial value is ?high?. mlotcx (x=1 to 7) mask loss of tclk alarm for channel x. mlotcx is active-high to prevent lotcx from setting int output ?high?. it is possible to read lotcx register regardless of the status of mlotcx. initial value is ?high?. mlomc mask loss of mclk alarm. mlomc is active-high to prevent lomc from setting int output ?high?. it is possible to read lomc register regardless of the status of mlomc. initial value is ?high?. when the loss of mclk is detected, losx register and losx pins are set ?high? at the same time. therefore all mlosx register must be set ?high? to prevent loss of mclk from setting int output. in this case, lomc can be read. channel control register symbol description lengyx the generated transmit pulse in channel x provides the appropriate pulse shape for line length from a dsx-1 cross connect through the setting of this register as shown below in table 1. rloopx/ lloopx loopback mode of channel x is activated through the setting of these registers as shown below in table 2. polnx this register as shown in table 3 controls tipx/ringx output polarity. initial value is ?high?. pdx pdx is active-high to set the corresponding transceiver in power down mode. the impedance between ttip and tring is set to 30k ? (typ). losx goes ?high? in power down mode. initial value is ?high?. mskx mskx is active-high to prevent losx or lotcx from setting int output ?high?. initial value is ?high?. rden rden is active-high to prevent rclk, rpos, and rneg output from forcing to ?low? or ?high? by the detection of loss of signal. initial value is ?low?.
asahi kasei [AK2546] 2002/5 19 table 1. pulse shape control leng3x leng2x leng1x line length 0 0 0 0-133feet (initial value) 0 0 1 133-266feet 0 1 0 266-399feet 0 1 1 399-533feet 1 0 0 533-655feet table 2. loopback mode select rloopx lloopx function 0 0 normal (initial value) 0 1 local loop back 1 0 remote loop back 1 1 inhibited table 3. tipx/ringx polarity control polnx posx/negx tipx/ringx 0 space 1 1 mark 0 mark 0 1 space
asahi kasei [AK2546] 2002/5 20 output control *: don?t care los: losx output and losx register reset, loss of mclk, power down loopback reset mclk pd local remot e p o l n r d e n t c l k receive signal ttip tring rclk rpos rneg los 0 * * * * * * * * 0(note 1) 0 0 1 1 loss * * * 1 * * * 0 0 0 1 1 loss * * * 0 * * * 0 0 1 1 1 clocked 1 * * 1 * * * 0(note 1) 0 0 1 1 clocked 1 * * 0 * * * 0(note 1) 0 1 1 normal operation(reset=1, mclk: clocked, pd=0) loopback local remote poln rden tclk receive signal ttip tring rclk rpos rneg los 0 0 1 * clocked in tpos tneg rclk rtip rring 0 0 0 1 0 clocked loss tpos tneg 0 0 1 0 0 1 * loss in 0 rclk rtip rring 0 0 0 1 0 loss loss 0 0 0 1 0 0 1 1 clocked loss tpos tneg rclk rtip rring 1 0 0 1 1 loss loss 0 rclk rtip rring 1 0 0 0 * clocked in tpos tneg rclk rtip rring 0 0 0 0 0 clocked loss tpos tneg 0 1 1 0 0 0 * loss in 0 rclk rtip rring 0 0 0 0 0 loss loss 0 0 1 1 0 0 0 1 clocked loss tpos tneg rclk rtip rring 1 0 0 0 1 loss loss 0 rclk rtip rring 1
asahi kasei [AK2546] 2002/5 21 remote loopback(reset=1, mclk: clocked, pd=0) loopback local remote poln rden tclk receive signal ttip tring rclk rpos rneg los 0 1 1 * * in rtip rring rclk rtip rring 0 0 1 1 0 * loss rtip rring 0 0 1 0 1 1 1 * loss rtip rring rclk rtip rring 1 0 1 0 * * in rtip rring rclk rtip rring 0 0 1 0 0 * loss rtiip rring 0 1 1 0 1 0 1 * loss rtip rring rclk rtip rring 1 local loopback(reset=1, mclk: clocked, pd=0) loopback local remote poln rden tclk receive signal ttip tring rclk rpos rneg los 1 0 1 * clocked in tpos tneg tclk (note 2) tpos tneg 0 1 0 1 * clocked loss tpos tneg tclk (note 2) tpos tneg 1 1 0 1 * loss in 0 0 0 0 1 0 1 * loss loss 0 0 0 1 1 0 0 * clocked in tpos tneg tclk (note 2) tpos tneg 0 1 0 0 * clocked loss tpos tneg tclk (note 2) tpos tneg 1 1 0 0 * loss in 0 0 1 0 1 0 0 * loss loss 0 0 1 1 note 1) the impedance between ttip and tring is 30k ? (typ). note 2) the phase of the tclk satisfies receive output timing.
asahi kasei [AK2546] 2002/5 22 theory of operation loss of signal loss of signal in channel x is reported by setting losx register ?high?. the receiver will indicate loss of signal upon receiving 175 consecutive zeros or detecting input level being below the threshold (alos). losx returns to ?low? when the received signal returns to 12.5% ones density and not including 100 consecutive zeros. (gr-820) when loss of signal is detected in channel x, losx register is set ?high? and losx pin becomes ?high?. when losx is set ?high?, interrupt will be issued on int pin if mlosx is ?low?. losx pin becomes high regardless of mlosx status. mlosx is active-high and masks losx interrupt. losx registers and losx pins represent the current status of received signal regardless of the mlosx status. loss of tclk loss of tclkx is reported by setting lotcx ?high?. when lotcx is set ?high?, int output becomes ?high? if mlotcx is ?low?. mlotcx is active-high and masks lotcx interrupt. lotcx represents the current status of tclkx and can be read regardless of mlotcx status. when loss of tclkx is detected, ttipx/tringx will be forced to ?0?. loss of mclk loss of mclk is reported by setting lomc ?high?. when lomc is set ?high?, int output becomes ?high? if mlomc is ?low?. mlomc is active-high and masks lomc interrupt. lomc represents the current status of mclk and can be read regardless of mlomc status. when the loss of mclk is detected, losx register and losx pin goes ?high? at the same time. therefore all mlosx register must be set to ?high? to prevent loss of mclk from setting int output int output int output becomes ?high? when the alarm is reported to any one of losx, lotcx or lomc registers. this pin can be masked by mlosx, mlotcx or mlomc registers. local loopback in local loopback mode, tposx, tnegx, tclkx signals are looped back to rposx, rnegx, rclkx output. rtipx, rringx inputs are ignored but loss of signal detection is active. the transmitter in channel x outputs ttipx, tringx normally. remote loopback in remote loopback mode, rtipx/rringx signals are looped back to ttipx/tringx output. the receiver in channel x output rposx, rnegx, rclkx normally and detect loss of signal. tposx, tnegx, tclkx inputs are ignored.
asahi kasei [AK2546] 2002/5 23 recommended external circuit transmit circuit received circuit recommended transformer specification dcr (max) turns ratio (typ) primary inductance (min) leakage inductance (max) interwinding capacitance (max) pri sec tx 1:2 720h 0.3h 30pf 0.6 ? 1.2 ? rx 1:2ct 720h 0.3h 30pf 0.6 ? 1.2 ? recommended transformers selection turns ratio manufacturer part number description tdk wbtt-0425 single, smt,1.5kv pulse engineering t1105, t1106 octal, smt,1.5kv 1:2ct* jpc 4101 single, smt,1.5kv a k2546 ttipx tringx c1 c1=0.47f r1=r2=68 ? r3=r4=130 ? vdd vdd 1:2 a k2546 rtipx rringx vdd r1 r3 r2 vdd 2ct:1 r4
asahi kasei [AK2546] 2002/5 24 reference current circuit to determine input reference current, connect 12k ? 1% resistor. power supply to attenuate the power supply noise, connect capacitors between vdd and vss respectively. the value of the capacitance AK2546 need depend on the condition of the power supply line. please decide the value of the capacitance after your evaluation. pin name c1 ravdd1-ravss1, ravdd2-ravss2, bvdd-bvss, tavdd1-tavss1, tavdd2-tavss2 1f tvdd1-tvss1, tvdd2-tvss2, tvdd3-tvss3, tvdd4-tvss4, tvdd5-tvss5, tvdd6-tvss6, tvdd7-tvss7, iovdd1-iovss1, iovdd2-iovss2, dvdd1-dvss1, dvdd2-dvss2, pvdd-pvss 0.01f bgref AK2546 r1 r1=12k ? 1% vdd AK2546 c1
asahi kasei [AK2546] 2002/5 25 ? recommended conditions for pcb board for the performance of noise and heat, the board design must be taken care. recommended conditions for pcb board is shown below. recommended conditions: multilayerboard with more than two vdd or gnd layer please design the rest of pattern for gnd
asahi kasei [AK2546] 2002/5 26 package 144pin lqfp output dimensions 22.0 1 36 37 72 73 108 109 144 20.0 0.50 0.20 0~10o 0.17 0.04 0.07 22.0 20.0 1.70 max 1.40 0.500.1 0.10 0.10 0.10 m AK2546 xxxxxxx japan
asahi kasei [AK2546] 2002/5 27 important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
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