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wide supply range, rail - to - rail output instrum entation amplifier ad8226 rev. b information furnished by analog devices is believed to be accurate and reliable. h owever, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 C 2011 analog devices, inc. all rights reserved. features gain set with 1 external resistor gain range: 1 to 1000 input voltage goes below ground inputs protected beyond supplies very w ide power supply range single supply: 2.2 v to 36 v dual s upp lies : 1. 35 v to 18 v b andwidth (g = 1) : 1 .5 m hz cmrr (g = 1) : 9 0 db minimum for br models i nput noise : 22 nv/ hz typical supply current: 350 a specified temperature : ? 40c to + 125c 8 - lead soic and msop packages applications industrial process controls bridge amplifiers medical instrumentation portable data acquisition multichannel systems pin configuration top view (not to scale) 07036-001 ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8226 f igure 1. table 1 . instrumentation amplifiers by category 1 general purpose zero drift military grade low power high speed pga ad8220 ad8231 ad620 ad627 ad8250 ad8221 ad8290 ad621 ad623 ad8251 ad8222 ad8293 ad524 ad8223 ad8253 ad8224 ad8553 ad526 ad8226 ad8228 ad8556 ad624 ad8227 ad8295 ad8557 ad8235 / ad8236 1 visit www.analog.com for the latest instrumentation amplifiers. general description t he ad8226 is a low cost , wide supply range instrumentation amplifier that requires only one exte rnal resistor to set any gain between 1 and 1000. the ad8226 is designed to work with a variety of signal voltages. a wide input range and rail - to - rail output allow the signal to make full use of the supply rails. because the input range also includes the ability to go below the negative supply, small signals near ground can be amplified wit hout requiring dual supplies. the ad8226 operates on supplies ranging from 1. 35 v to 18 v for dual supp lies and 2. 2 v to 36 v for single supply . the robust ad8226 in puts are designed to connect to real - world sensors. in addition to its wide operating range, the ad8226 can handle voltages beyond the rails. for example, with a 5 v supply, the part is guaranteed to withstand 35 v at the input with no damage. minimu m as well as maximum inp ut bias currents are specified to facilitate open wire det ection. the ad8226 is perfect for multichannel, space - constrained industrial applications. unlike other low cost, low power instrumentation amplifiers, the ad8226 is designed with a minimum gain of 1 and can easily handle 10 v signals. with its msop package and 1 2 5c temperature rating, the ad8226 thrives in tightly packed , zero airflow designs. the ad8226 is available in 8 - lead msop and soic packages , and is fully specifi ed for ? 40c to + 125c operation. for a device with a similar package and performance as the ad8226 but with gain settable from 5 to 1000, consider using the ad8227 .
ad8226 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin configuration ............................................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 19 architecture ................................................................................. 19 gain selection ............................................................................. 19 reference terminal .................................................................... 20 input voltage range ................................................................... 20 layout .......................................................................................... 20 input bias current return path ............................................... 21 input protection ......................................................................... 22 radio frequency interference (rfi) ........................................ 22 applications informatio n .............................................................. 23 differential drive ....................................................................... 23 precision strain gage ................................................................. 24 driving an a dc ......................................................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 3 /11 rev. a to rev. b added ad8 235/ad8236 to table 1 ............................................... 1 changes to endnote 1 , table 2 ........................................................ 4 change endnote 2 placement in total noise equation, table 3 ...... 5 added g > 1 brz, brmz max parameter .................................... 6 changes to endnote 1 , table 3 ........................................................ 6 changes to figure 18 ...................................................................... 11 changes to figure 37 ...................................................................... 14 changes to figure 42 ...................................................................... 15 updated outline dimensions ....................................................... 25 7 /09 rev. 0 to rev. a added brz and brm models .......................................... universal changes to features section ............................................................ 1 changes to table 1 ............................................................................ 1 changes to general description section ...................................... 1 changes to gain vs . temperature parameter , output parameter, and operati ng range parameter, table 2 ................................ .......... 4 changes to common - mode rejection ratio (cmrr) parameter and to input offset, v oso , average temperature coefficient parame ter, table 3 ........................................................................ 5 changes to gain vs . temperature parameter, table 3 ................. 6 changes to gain selection section ............................................... 1 9 changes to reference terminal section and input voltage range section .............................................................................. 20 changes to ordering guide .......................................................... 2 5 1 /0 9 revision 0 : initial versi on
ad8226 rev. b | page 3 of 28 specifications +v s = +15 v, ? v s = ? 15 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k , specifications referred to input , unless otherwise noted . table 2 . arz, armz brz, brmz parameter conditions min typ max min typ max unit common - mode rejection ratio (cmrr) v cm = ? 10 v to +10 v cmrr with dc to 60 hz g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db cmrr with dc at 5 khz g = 1 80 80 db g = 10 90 90 db g = 100 90 90 db g = 1000 100 100 db noise total nois e: e n = (e ni 2 + (e no /g) 2 ) voltage no ise 1 khz input voltage noise, e ni 22 24 22 24 nv/ hz output voltage noise, e no 120 125 120 125 nv/ hz rti f = 0.1 hz to 10 hz g = 1 2 2 v p - p g = 10 0.5 0.5 v p - p g = 100 to 1000 0.4 0.4 v p - p current noise f = 1 khz 100 100 fa/ hz f = 0.1 hz to 10 hz 3 3 pa p - p voltage offset total offset voltage: v os = v osi + (v oso /g) input offset, v osi v s = 5 v to 15 v 200 100 v average temperature coefficient t a = ?40c to +125c 0.5 2 0.5 1 v/ c output offset, v oso v s = 5 v to 15 v 1000 500 v average temperature coefficient t a = ?40c to +125c 2 10 1 5 v/c offset rti vs. supply (psr) v s = 5 v to 15 v g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db input current input bias current 1 t a = +25c 5 20 27 5 20 27 na t a = +125c 5 15 25 5 15 25 na t a = ?40c 5 30 35 5 30 35 na average temperature coefficient t a = ?40c to +125c 70 70 pa/c input offset current t a = +25c 1.5 0.5 na t a = +125c 1.5 0.5 na t a = ?40c 2 0.5 na average temperature coefficient t a = ?40c to +125c 5 5 pa/c reference input r in 100 100 k i in 7 7 a voltage range ?v s +v s ?v s +v s v referen ce gain to output 1 1 v/v reference gain error 0.01 0.01 % dynamic response small - signal ? 3 db bandwidth g = 1 1500 1500 khz g = 10 160 160 khz g = 100 20 20 khz g = 1000 2 2 khz
ad8226 rev. b | page 4 of 28 arz, armz brz, brmz parameter conditions min typ max min typ max unit settling time 0.01% 10 v step g = 1 25 25 s g = 10 15 15 s g = 100 40 40 s g = 1000 350 350 s slew rate g = 1 0.4 0.4 v/s g = 5 to 100 0.6 0.6 v/s gain g = 1 + (49.4 k /r g ) gain range 1 1000 1 1000 v/v gain error v out 10 v g = 1 0.04 0.01 % g = 5 to 1000 0.3 0.1 % gain nonlinearity v out = ? 10 v to +10 v g = 1 to 10 r l 2 k 10 10 ppm g = 100 r l 2 k 75 75 ppm g = 1000 r l 2 k 750 750 ppm gain vs. temperature 2 g = 1 t a = ?40c to +85c 5 1 ppm/c t a = 85c to 125c 5 2 ppm/c g > 1 t a = ?40c to +125c ? 100 ? 100 ppm/c input v s = 1.35 v to +36 v input impedance differential 0.8||2 0.8||2 g ||pf common mode 0.4||2 0.4||2 g ||pf input operating voltage range 3 t a = +25c ?v s ? 0.1 +v s ? 0.8 ?v s ? 0.1 +v s ? 0.8 v t a = +125c ?v s ? 0.05 +v s ? 0.6 ?v s ? 0.05 +v s ? 0.6 v t a = ? 40c ?v s ? 0.15 +v s ? 0.9 ?v s ? 0.15 +v s ? 0.9 v input overvoltage range t a = ?40c to +12 5c +v s ? 40 ?v s + 40 +v s ? 40 ?v s + 40 v output output swing r l = 2 k to ground t a = +25c ?v s + 0.4 +v s ? 0. 7 ?v s + 0.4 +v s ? 0. 7 v t a = +125c ?v s + 0.4 +v s C 1.0 ?v s + 0.4 +v s C 1.0 v t a = ? 40c ?v s + 1.2 +v s C 1.1 ?v s + 1. 2 +v s C 1.1 v r l = 10 k to ground t a = +25c ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v t a = +125c ?v s + 0.3 +v s ? 0.3 ?v s + 0.3 +v s ? 0.3 v t a = ? 40c ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v r l = 100 k to ground t a = ? 40c to +125c ?v s + 0.1 +v s ? 0.1 ?v s + 0.1 +v s ? 0.1 v short - circuit current 13 13 ma power supply operating range dual - supply operation 1. 35 18 1. 35 18 v quiescent current t a = +25c 350 425 350 425 a t a = ? 40c 250 325 250 325 a t a = +85c 450 525 450 525 a t a = +125c 525 600 525 600 a temperature range ?40 +125 ?40 +125 c 1 the input s tage uses pnp transistors ; therefore, input bias current always flows out of the part. 2 the values specified for g > 1 do not include the effects of the external gain - setting resistor, r g . 3 input voltage range of the ad8226 input stage. the input range d epends on the common - mode voltage, the differential voltage, the gain, and the reference voltage. see the input voltage range section for more information.
ad8226 rev. b | page 5 of 28 +v s = 2.7 v , ? v s = 0 v , v ref = 0 v, t a = 25 c, g = 1, r l = 10 k , specifications referred to input, unless otherwise no ted. table 3 . arz, armz brz, brmz parameter conditions min typ max min typ max unit common - mode rejection ratio (cmrr) v cm = 0 v to 1.7 v cmrr with dc to 60 hz g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db cmrr with dc at 5 khz g = 1 80 80 db g = 10 90 90 db g = 100 90 90 db g = 1000 100 100 db noise total nois e: e n = (e ni 2 + (e no /g ) 2 ) voltage noise 1 khz input voltage noise, e ni 22 24 22 24 nv/ hz output voltage noise, e no 120 125 120 125 nv/ hz rti f = 0.1 hz to 10 hz g = 1 2.0 2.0 v p - p g = 10 0.5 0.5 v p - p g = 100 to 1 000 0.4 0.4 v p - p current noise f = 1 khz 100 100 fa/ hz f = 0.1 hz to 10 hz 3 3 pa p - p voltage offset total offset voltage: v os = v osi + (v oso /g) input offset, v osi 200 100 v average temperature coefficient t a = ?40c to + 125c 0.5 2 0.5 1 v/c output offset, v oso 1000 500 v average temperature coefficient t a = ?40c to +125c 2 10 1 5 v/c offset rti vs. supply (psr) v s = 0 v to 1.7 v g = 1 80 90 db g = 10 100 105 db g = 100 105 1 10 db g = 1000 105 1 10 db input current input bias current 1 t a = +25c 5 20 27 5 20 27 na t a = +125c 5 15 25 5 15 25 na t a = ?40c 5 30 35 5 30 35 na average temperature coefficient t a = ?40c to +125c 70 70 pa/c input offset curr ent t a = +25c 1.5 0.5 na t a = +125c 1.5 0.5 na t a = ?40c 1 0.1 na average temperature coefficient t a = ? 40c to +125c 5 5 pa/c reference input r in 100 100 k i in 7 7 a voltage range ?v s +v s ?v s +v s v refe rence gain to output 1 1 v/v reference gain error 0.01 0.01 % dynamic response small - signal ? 3 db bandwidth g = 1 1500 1500 khz g = 10 160 160 khz g = 100 20 20 khz g = 1000 2 2 khz
ad8226 rev. b | page 6 of 28 arz, armz brz, brmz parameter conditions min typ max min typ max unit settling time 0.01% 2 v step g = 1 6 6 s g = 10 6 6 s g = 100 35 35 s g = 1000 350 350 s slew rate g = 1 0.4 0.4 v/s g = 5 to 100 0.6 0.6 v/s gain g = 1 + (49.4 k /r g ) gain range 1 1000 1 1000 v/v gain error g = 1 v out = 0.8 v to 1.8 v 0.04 0.01% % g = 5 to 1000 v out = 0.2 v to 2.5 v 0.3 0.1% % gain vs. temperature 2 g = 1 t a = ?40c to +85c 5 1 ppm/c t a = +85c to +125c 5 2 ppm/c g > 1 t a = ?40c to +125c ?100 ?100 ppm /c input ?v s = 0 v, +v s = 2.7 v to 36 v input impedance differential 0.8||2 0.8||2 g ||pf common mode 0.4||2 0.4||2 g ||pf input operating voltage range 3 t a = +25c ?0.1 +v s ? 0.7 ?0.1 +v s ? 0.7 v t a = ? 40c ?0.15 +v s ? 0.9 ?0.15 +v s ? 0.9 v t a = +125c ?0.05 +v s ? 0.6 ?0.05 +v s ? 0.6 v input overvoltage range t a = ?40c to +125c +v s ? 40 ?v s + 40 +v s ? 40 ?v s + 40 output output swing r l = 10 k to 1.35 v, t a = ?40c to +125c 0.1 +v s ? 0.1 0.1 +v s ? 0.1 v short - circuit current 13 13 ma power supply operating range single - supply operation 2.2 36 2.2 36 v quiescent current t a = +25c, ?v s = 0 v, +v s = 2.7 v 325 400 325 400 a t a = ?40c, ?v s = 0 v, +v s = 2.7 v 250 325 250 325 a t a = +85c, ?v s = 0 v, +v s = 2.7 v 425 500 425 500 a t a = +125c, ?v s = 0 v, +v s = 2.7 v 475 550 475 550 a temperature range ? 40 +125 ? 40 +125 c 1 input stage uses pnp transistors ; therefore, input bias current always f lows out of the part. 2 the values specified for g > 1 do not include the effects of the external gain - setting resistor, r g . 3 input voltage range of the ad8226 input stage. the input range depends on the common - mode voltage, the differential voltage, the gain, and the reference voltage. see the input voltage range section for more information.
ad8226 rev. b | page 7 of 28 absolute maximum rat ings table 4 . parameter rating supply voltag e 18 v output short - circuit current indefinite maximum voltage at ?in or +in ?v s + 40 v minimum voltage at ?in or +in +v s ? 40 v ref voltage v s storage temperature range ?65c to +150c specified temperature range ?40c to +125c maximum junction temperature 140c esd human body model 1.5 kv charge device model 1 .5 kv machine model 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of t he device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for a device in free air. table 5 . thermal resistance package ja unit 8 - lead msop, 4 - layer jedec board 135 c/w 8 - lead soic, 4 - layer jedec board 121 c/w esd caution
ad8226 rev. b | page 8 of 28 pin configuration an d function des criptions top view (not to scale) 07036-002 ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8226 figure 2 . pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 ?in negative input. 2, 3 r g gain - setting pins . place a gain resistor between these two pins. 4 + in positive input. 5 ?v s negative supply. 6 ref reference. this pin m ust be driven by low impedance. 7 v out output. 8 +v s positive supply.
ad8226 rev. b | page 9 of 28 typical performance characteristics t = 25c, v s = 15 v, r l = 10 k ?, unless otherwise noted. 160 140 120 100 80 60 40 20 0 ?900 ?600 ?300 0 300 600 900 v oso @ 15v (v) hits 07036-031 n: 2203 mean: 35.7649 sd: 229.378 figure 3 . typical distribution of output offset voltage 240 210 180 150 120 90 60 30 0 ?9 ?6 ?3 0 3 6 9 v oso drift (v) hits 07036-032 mean: ?0.57 sd: 1.5762 figure 4 . typical distribution of output offset voltage drift 350 300 250 200 150 100 50 0 ?400 ?200 0 200 400 v osi @ r g pins @ 15v (v) hits 07036-033 mean: ?3.67283 sd: 51.1 figure 5 . typical distribution of input offset voltage 250 200 150 100 50 0 ?1.2 ?0.9 ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 v osi drift (v) hits 07036-034 mean: 0.041 sd: 0.224 figu re 6 . typical distribution of input offset voltage drift, g = 100 180 150 120 90 30 60 0 18 20 22 24 26 positive i bias current @ 15v (na) hits 07036-035 mean: 21.5589 sd: 0.624 figure 7 . typical distribution of input bias current 300 250 200 150 100 50 0 ?0.9 ?0.6 ?0.3 0 0.3 0.6 0.9 v osi @ 15v (na) hits 07036-036 mean: 0.003 sd: 0.075 figure 8 . typical distribution of input offset curren t
ad8226 rev. b | page 10 of 28 +0.02v, +2.0v +0.02v, ?0.4v +2.4v, +0.8v +1.35v, +1.9v +0.02v, +1.3v +0.02v, +0.3v +1.35v, ?0.4v +2.68v, +0.3v +2.68v, +1.2v ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 common-mode voltage (v) output voltage (v) v re f = 0v v re f = +1.35v 07036-037 figure 9 . input common - mode voltage vs. output voltage, single supply , v s = +2.7 v, g = 1 +0.02v, +4.3v +0.02v, ?0.4v +4.7v, +1.9v +2.5v, +4.3v +0.02v, +3.0v +0.02v, +0.8v +2.5v, ?0.4v +4.98v, +0.8v +4.98v, +3.0v ?1 0 1 2 3 4 5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 common-mode voltage (v) output voltage (v) v re f = 0v 07036-038 v re f = +1.35v figure 10 . input common - mode voltage vs. output voltage, single supply , v s = +5 v, g = 1 0v, +4.3v ?4.97v, +1.8v ?4.97v, ?3.0v 0v, ?5.4v +4.96v, ?0.3v +4.96v, +1.8v ?6 ?4 ?2 0 2 4 6 ?6 ?4 ?2 0 2 4 6 common-mode voltage (v) output voltage (v) 07036-039 figure 11 . input common - mode voltage vs. output voltage, dual supplies , v s = 5 v, g = 1 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 output voltage (v) +0.02v, +2.0v +0.02v, ?0.3v +2.4v, +0.8v +1.35v, +1.9v +0.02v, +1.3v +0.02v, +0.4v +1.35, ?0.3v +2.67v, +0.4v +2.67v, +1.3v 0 0.5 ?0.5 1.0 1.5 2.0 2.5 common-mode voltage (v) v re f = 0v 07036-040 v re f = +1.35v figure 12 . input common - mode voltage vs. output voltage, single supply , v s = +2.7 v, g = 100 +0.02v, +4.3v +0.02v, ?0.3v +4.7v, +1.9v +2.5v, +4.2v +0.02v, +3.0v +0.02v, +0.7v +2.5v, ?0.3.v +4.96v, +0.7v +4.96v, +3.0v ?1 0 1 2 3 4 5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 common-mode voltage (v) output voltage (v) v re f = 0v 07036-041 v re f = +2.5v figure 13 . input common - mode voltage vs. output voltage, single supply , v s = +5 v, g = 100 0v, +4.2v ?4.96v, +1.7v ?4.96v, ?3.1v 0v, ?5.3v +4.96v, ?3.1v +4.96v, +1.7v ?6 ?4 ?2 0 2 4 6 ?6 ?4 ?2 0 2 4 6 output voltage (v) 07036-042 common-mode voltage (v) figure 14 . input common - mode voltage vs. output voltage, dual supplies , v s = 5 v, g = 100
ad8226 rev. b | page 11 of 28 +14.96v, +6.8v ?14.96v, ?7.9v +11.95v, +5.3v +11.95v, ?6.4v 0v, +14.3v 0v, +11.3v ?11.95v, +5.3v ?11.95v, ?6.4v 0v, ?15.4v 0v, ?12.4v +14.94v, ?7.9v +14.94v, +6.8v ?20 ?15 ?10 ?5 0 10 5 15 20 common-mode voltage (v) output voltage (v) v s = 15v 07036-043 20 15 10 5 0 ?5 ?10 ?20 ?15 v s = 12v figure 15 . in put common - mode voltage vs. output voltage, dual supplies , v s = 15 v, g = 1 2.25 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 input voltage (v) output voltage (v) input current (ma) 07036-044 v s = 2.7v g = 1 ?v in = 0v v out i in figure 16 . input overvoltage performance , g = 1, v s = 2.7 v 16 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 14 12 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 input voltage (v) output voltage (v) input current (ma) 07036-045 v s = 15v g = 1 ?v in = 0v v out i in figure 17 . input overvoltage performance, g = 1, v s = 15 v ?14.95v, +6.7v ?14.95v, ?8.0v +11.95v, +5.2v +11.95v, ?6.5v 0v, +14.2v 0v, +11.2v ?11.95v, +5.2v ?11.95v, ?6.5v 0v, ?15.4v 0v, ?12.3v +14.95v, ?8.0v +14.95v, +6.7v ?20 ?15 ?10 ?5 0 10 5 15 20 common-mode voltage (v) output voltage (v) v s = 15v 07036-046 20 15 10 5 0 ?5 ?10 ?20 ?15 v s = 12v figure 18 . input common - mode voltage vs. output voltage, dual supplies , v s = 15 v, g = 100 2.25 2.50 2.75 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 input voltage (v) output voltage (v) input current (ma) 07036-047 v s = 2.7v g = 100 ?v in = 0v v out i in figure 19 . input overvoltage performance, g = 100, v s = 2.7 v 16 0.5 0.6 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 14 12 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 input voltage (v) output voltage (v) input current (ma) 07036-048 v s = 15v g = 100 ?v in = 0v v out i in figure 20 . in put overvoltage performance, g = 100, v s = 15 v
ad8226 rev. b | page 12 of 28 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 common-mode voltage (v) input bias current (na) 07036-049 +4.22v ?0.15v figure 21 . input bias current vs. common - mode voltage, v s = +5 v 50 45 40 35 30 25 20 15 10 5 0 ?5 ?16 ?12 ?8 ?4 0 4 8 12 16 common-mode voltage (v) input bias current (na) 07036-050 ?15.13v +14.18v figure 22 . input bias current vs. common - mode voltage, v s = 15 v 160 140 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k 1m frequency (hz) positive psrr (db) 07036-013 gain = 1000 gain = 100 gain = 10 gain = 1 figure 23 . positive psrr vs. frequency, rti 160 140 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k 1m frequency (hz) negative psrr (db) 07036-014 gain = 1000 gain = 100 gain = 10 gain = 1 figure 24 . negative psrr vs. frequency 70 60 50 40 30 20 10 0 ?10 ?20 ?30 100 1k 10k 100k 1m 10m frequency (hz) gain (db) 07036-015 v s = 15v gain = 1000 gain = 100 gain = 10 gain = 1 figure 25 . gain vs. frequency, v s = 15 v 70 60 50 40 30 20 10 0 ?10 ?20 ?30 100 1k 10k 100k 1m 10m frequency (hz) gain (db) 07036-016 v s = 2.7v gain = 1000 gain = 100 gain = 10 gain = 1 figure 26 . gain vs. frequency, 2. 7 v single supply
ad8226 rev. b | page 13 of 28 160 140 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k frequency (hz) cmrr (db) 07036-017 gain = 1000 gain = 100 gain = 10 gain = 1 bandwidth limited figure 27 . cmrr vs. frequency, rti 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k frequency (hz) cmrr (db) 07036-018 gain = 1000 gain = 1 gain = 100 gain = 10 bandwidth limited figure 28 . cmrr vs. frequency, rti, 1 k source imbalance 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 0 10 20 30 40 50 60 70 80 90 100 110 120 warm-up time (seconds) change in input offset voltage (v) 07036-011 figure 29 . change in input offset voltage vs. warm - up time 35 30 25 20 15 10 150 125 100 75 50 25 0 5 ?45 ?30 ?15 0 15 30 45 60 75 90 105 120 135 temperature (c) input bias current (na) input offset current (pa) 07036-012 v s = 15v v ref = 0v ?in bias current +in bias current offset current figure 30 . input bias current and input offset current vs. temperature 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) gain error (v/v) 07036-051 normalized at 25c ?0.4ppm/c ?0.3ppm/c ?0.6 ppm/c figure 31 . gain er ror vs. temperature, g = 1 20 10 0 ?10 ?20 ?30 ?40 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature (c) cmrr (v/v) 07036-052 representative data normalized at 25c 0.2ppm/c ?0.35ppm/c figure 32 . cm r r vs. temperature, g = 1
ad8226 rev. b | page 14 of 28 +v s ?0.2 ?0.4 ?0.6 ?0.8 ?v s ?0.2 ?0.4 ?0.6 ?0.8 2 4 6 8 10 12 14 16 18 supply voltage (v s ) input voltage (v) referred to supply voltages 07036-053 ?40c +25c +85c +105c +125c figure 33 . input voltage limit vs. supply voltage +v s ?0.1 ?0.2 ?0.3 ?0.4 ?v s +0.3 +0.2 +0.1 +0.4 2 4 6 8 10 12 14 16 18 supply voltage (v s ) output voltage swing (v) referred to supply voltages 07036-054 ?40c +25c +85c +105c +125c figure 34 . output voltage swing vs. supply voltage, r l = 10 k +v s ?0.8 ?1.0 ?1.2 ?0.2 ?0.4 ?0.6 ?v s +0.4 +0.2 +1.0 +0.8 +0.6 +1.2 2 4 6 8 10 12 14 16 18 supply voltage (v s ) output voltage swing (v) referred to supply voltages 07036-055 ?40c +25c +85c +105c +125c figure 35 . output voltage swing vs. supply voltage , r l = 2 k 15 10 5 0 ?5 ?10 ?15 100 1k 10k 100k load resistance ( ?) output voltage swing (v) 07036-056 ?40c +25c +85c +105c +125c figure 36 . output voltage swing vs. load resistance +v s ?v s ?0.2 +0.2 ?0.4 +0.4 ?0.6 +0.6 ?0.8 +0.8 10 100 1m 10m output current (a) output voltage swing (v) referred to supply voltages 07036-057 ?40c +25c +85c +105c +125c figure 37 . output voltage swing vs. output current, g = 1 8 g = 1 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 output voltage (v) nonlinearity (2ppm/div) 07036-019 figure 38 . gain nonlinearity, g = 1, r l 2 k
ad8226 rev. b | page 15 of 28 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 output voltage (v) nonlinearity (2ppm/div) 07036-020 g = 10 figure 39 . gain nonlinearity, g = 10, r l 2 k 80 60 40 20 0 ?20 ?40 ?60 ?80 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 output voltage (v) nonlinearity (20ppm/div) 07036-021 g = 100 figure 40 . gain nonlinearity, g = 100, r l 2 k 800 600 400 200 0 ?200 ?400 ?600 ?800 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 output voltage (v) nonlinearity (100ppm/div) 07036-022 g = 1000 figure 41 . gain nonlinearity, g = 1000, r l 2 k 1k 100 10 1 10 100 1k 10k 100k frequency (hz) noise (nv/ hz) 07036-023 gain = 1000 gain = 100 gain = 10 gain = 1 bandwidth limited figure 42 . voltage noise spectral density vs. frequency 07036-024 1s/div gain = 1000, 200nv/div gain = 1, 1v/div figure 43 . 0.1 hz to 10 hz rti voltage noise, g = 1, g = 1000 1k 100 10 1 10 100 1k 10k frequency (hz) noise (fa/ hz) 07036-058 figure 44 . current noise spectral density vs. frequency
ad8226 rev. b | page 16 of 28 07036-025 1s/div 1.5pa/div figure 45 . 0.1 hz to 10 hz current noise 0 3 6 9 12 15 18 21 24 27 30 10 0 1 k 10 k 100 k 1 m output voltage (v p-p) frequ e nc y (hz) v s = 15v v s = +5v 07036-059 figure 46 . large - signal frequency response 07036-060 40s/div 25.38s to 0.01% 26.02s to 0.001% 0.002%/div 5v/div figure 47 . large - signal pu lse response and settling time, g = 1, 10 v step , v s = 15 v 07036-061 40s/div 15.46s to 0.01% 17.68s to 0.001% 0.002%/div 5v/div figure 48 . large - signal pu lse response and settling time, g = 10 , 10 v step , v s = 15 v 07036-062 100s/div 39.64s to 0.01% 58.04s to 0.001% 0.002%/div 5v/div figure 49 . large - signal pulse respon s e and settling time, g = 100, 10 v step , v s = 15 v 07036-063 400s/div 349.6s to 0.01% 529.6s to 0.001% 0.002%/div 5v/div figure 50 . large - signal pulse re sponse and settling time, g = 1000, 10 v ste p , v s = 15 v
ad8226 rev. b | page 17 of 28 07036-026 20mv/div 4s/div figure 51 . small - signal response, g = 1, r l = 10 k , c l = 100 pf 07036-027 20mv/div 4s/div figure 52 . small - signal response, g = 10, r l = 10 k , c l = 100 pf 07036-028 20mv/div 20s/div figure 53 . small - signal response, g = 100, r l = 10 k , c l = 100 pf 07036-029 20mv/div 100s/div figure 54 . small - sign al response, g = 1000, r l = 10 k , c l = 100 pf
ad8226 rev. b | page 18 of 28 07036-030 20mv/div r l = 147pf r l = 100pf r l = 47pf no load 4s/div figure 55 . small - signal response with various capacitive loads , g = 1, r l = 07036-064 2 60 50 40 30 20 10 0 4 6 8 10 ste p size (v) settling time (s) 12 14 16 18 20 settled t o 0.01% settled t o 0.001% figure 56 . settling time vs. step size , v s = 15 v dual suppl ies 340 330 320 310 300 290 0 2 4 6 8 10 12 14 16 18 supply voltage (v s ) supply current (a) 07036-066 fig ure 57 . supply current vs. supply voltage
ad8226 rev. b | page 19 of 28 theory of operation a3 r2 24.7k ? r1 24.7k ? a1 a2 q2 q1 ?in +in +v s ?v s r3 50k? r4 50k? r5 50k? r b r b +v s ?v s v out ref 07036-003 node 1 node 2 r g v bias +v s ?v s +v s ?v s node 4 node 3 r6 50k? difference amplifier s t age gain s t age esd and ove r volt age protection esd and ove r volt age protection ?v s figure 58 . simplified schematic architecture the ad8226 is based on the classic 3 - op - amp topology. this topology has two stages: a prea mplifier to provide differential amplification, followed by a difference amplifier to remove the common - mode voltage. figure 58 shows a simplified schematic of the ad8226. the first stage works as follows : in ord er to maintain a constant voltage across the bias r esistor r b , a1 must keep n ode 3 a con - stant diode drop above the positive input voltage. similarly, a2 keeps n ode 4 at a constant diode drop above the negative input voltage. therefore, a replica of the di fferential input vo ltage is placed across the gain - setting resistor, r g . the current that flows across this resistance must also flow through the r1 and r2 resistors, creating a gained differential signal between the a2 and a1 outputs. note that, in addi tion to a gained differential signal, the original common - mode signal, shifted a diode drop up , is also still present. the second stage is a difference amplifier, composed of a3 and four 50 k ? resistors. the purpose of this stage is to remove the common - m ode signal from the amplified differential signal. the transfer function of the ad8226 is v out = g ( v in+ ? v in ? ) + v ref where: g r g k 49.4 1 + = gain selection placing a resistor across the r g terminals sets the gain of the ad8226, which can be calc ulated by referring to table 7 or by using the following gain eq uation: 1 k 49.4 ? = g r g table 7 . gains achieved using 1 resistors 1% standard table value of r g ( ?) calculated gain 4 9.9 k 1.990 12.4 k 4.984 5.49 k 9.998 2.61 k 19.93 1.00 k 50.40 499 100.0 249 199.4 100 495.0 49.9 991.0 the ad8226 defaults to g = 1 when no gain resistor is used. the tolerance and gain drift of the r g resistor should be added to the ad8226 spe cifications to determine the total gain accu - racy of the system. when the gain resistor is not used, gain error and gain drift are minimal. if a gain of 5 is required and minimal gain drift is important, consider using the ad8227 . the ad8227 has a default gain of 5 that is set with internal resistors. because all resistors are internal , the gain drift is extremely low (<5 ppm/ c maximum ).
ad8226 rev. b | page 20 of 28 reference terminal the outp ut voltage of the ad8226 is developed with respect to the potential on the reference terminal. this is useful when the output signal needs to be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level - shift th e output so that the ad8226 can drive a single - supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.3 v. for the best performance, source impedance to the ref terminal should be kept below 2 ?. as show n in figure 58, the reference terminal, ref, is at one end of a 50 k resistor. additional impedance at the ref terminal adds to this 50 k resistor and results in amplification of the signal connected to the posit ive input. the amplification from the additional r ref can be computed by 2(50 k + r ref )/ ( 100 k + r ref ) . only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades cmrr. incorrect v correct ad8226 op1177 + ? v 07036-004 ref ad8226 ref figure 59 . driving the reference pin input voltage range figure 9 through figure 15 and figure 18 show the allowable common - mode inpu t voltage ranges for various output voltages and supply voltages. the 3 - o p - amp architecture of the ad8226 applies gain in the first stage before removing common - mode voltage with the difference amplifier stage . i nternal nodes between the first and second s tages ( n ode 1 and node 2 in figure 58) experience a combination of a gained signal, a c ommon - mode signal, and a diode drop . this combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited . for most applications, figure 9 through figure 15 and figure 18 provide sufficient informatio n to achieve a good design. for applications where a more detailed understanding is needed, equation 1 to equation 3 can be used to understand how the gain (g) , common - mode input voltage (v cm ), differential input voltage (v diff ) , and reference voltage (v re f ) interact. the values for the constants , v ? limit , v +limit , and v ref_limit , are shown in table 8 . these three formulas, along with the input and output range specifications in table 2 and table 3 , set the operating boundaries of the part . limit s diff cm v v g v v ? + ? > ? 2 ) )( ( (1) limit s diff cm v v g v v + ? + < + 2 ) )( ( (2) limit ref s ref cm diff v v v v g v _ 2 2 ) )( ( ? + < + + (3) table 8 . input voltage range constants for various temperatures temperature v ? l imit v +limit v ref_limit ? 40c ? 0.55 v 0.8 v 1. 3 v + 25c ? 0.3 5 v 0 . 7 v 1. 1 5 v + 85c ? 0.1 5 v 0. 65 v 1. 05 v + 125c ? 0 .0 5 v 0.6 v 0 . 9 v performance across temperature t he common - mode input range shifts upwa rd with temper - ature. at cold te mperatures, the part requires extra headroom from the positive supply, and operation near the ne gative supply has more margin. conversely, hot temperatures require less headroom from the pos itive supply, but are the worst - case conditions for input voltages near the negati ve supply. recommendation for best performance a typical part functions up to the boundaries describe d in this section . however , for best performance, designing with a few hundred millivolts extra margin is recommend ed . as signals approach the boundary, i nternal transistors begin to saturate, which can affect frequency and linearity performance. if the application requirements exceed the boundaries, one solution is to apply less gain with the ad8226, and then apply additional gain later in the signal chai n. another option is to use the pin - compatible ad8227 . layout to ensure optimum performance of the ad8226 at the pcb level, care must be taken in the design of the board layout. the ad822 6 pins are arranged in a logical manner to aid in this task. 8 7 6 5 1 2 3 4 ?in r g r g +v s v out ref ?v s +in t op view (not to scale) ad8226 07036-005 figure 60 . pinout diagram
ad8226 rev. b | page 21 of 28 common - mode rejection ratio over frequency poor layout can cause some of the common - mode signal s to be converted to differential signal s before reaching the in - a mp. such conversions occur when one input path has a frequency response that is different from the other. to keep cmrr across frequency high, the input source impedance and capacitance of each path should be closely matched. additional source resistance in the input path (for example, for input protection) should be placed close to the in - amp inputs, which minimizes their interaction with parasitic capacitance from the pcb traces. pa rasitic capacitance at the gain - setting pins can also affect cmrr over freq uency. if the board design has a component at the gain - setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as small as possible. power supplies a stable dc voltage should be used to power the inst rumentation amplifier. n ote that n oise on the supply pins can adversely affect perform ance. for more information, see the psrr performance curves in figure 23 and figure 24. a 0.1 f capacitor should be placed as close as possible to each supply pin. as shown in figure 61 , a 10 f tantalum capacitor can be used farther away from the part. in most cases, it can be shared by other precision integrated circuits. ad8226 +v s +in ?in load ref 0.1 f 10 f 0.1 f 10 f ?v s v out 07036-006 figure 61 . supply decoupling, ref, and output referred to local ground references the output voltage of the ad822 6 is developed with respect to the potential on the reference terminal. care should b e taken to tie ref to the appropriate local ground. input bias current r eturn path the input bias current of the ad8226 must have a return path to ground . when the source, such as a thermocouple, cannot provide a return current path, one should be create d, as shown in figure 62. thermocouple +v s ref ?v s ad8226 capacitively coupled +v s ref c c ?v s ad8226 transformer +v s ref ?v s ad8226 incorrect capacitively coupled +v s ref c r r c ?v s ad8226 1 f high-pass = 2rc thermocouple +v s ref ?v s 10m ? ad8226 transformer +v s ref ?v s ad8226 correct 07036-007 figure 62 . creating an i bias path
ad8226 rev. b | page 22 of 28 input protection the ad8226 has very robust inputs and typically does not need additional inp ut protection. input voltages c an be up to 40 v from the opposite supply rail. for example, with a +5 v positive supply and a ? 8 v negative supply, the part can safely withstand voltages from ? 35 v to 32 v. u nlike some other instrumentation amplifiers, the part can handle large differen - tial input voltages even when the part is in high gain. figure 16, figure 17, figure 19 , and figure 20 show the behavior of the par t under overvoltage conditions. the rest of the ad8226 terminals shoul d be kept within the supplies. all terminals of the ad8226 are protected against esd. for applications where the ad822 6 encounters voltages b eyond the allowed limits, external current - limiting resistors and low - leakage diode clamps such as the bav199l, the fjh1100s, or the sp720 should be used. radio frequency inte rference (rfi) rf rectification is often a problem when amplifiers are used in a pplications having strong rf signals. the disturbance can appear as a small dc offset voltage. high frequency signals can be filtered with a low - pass rc network placed at the input of the instru - mentation amplifier, as shown in figure 63 . the filter li mits the input signal bandwidth according to the following relationship: ) 2 ( 2 1 c d diff c c r uency filterfreq + = c cm rc uency filterfreq 2 1 = where c d 10 c c . r r ad8226 +v s +in ?in 0.1f 10f 10f 0.1f ref v out ?v s r g c d 10nf c c 1nf c c 1nf 4.02k ? 4.02k ? 07036-008 figure 63 . rfi suppression c d affects the difference signal and c c affects the common - mode signal. values of r and c c should be chosen to minimize rfi. mismatch between the r c c at the positive input and the r c c at the negative input degrades the cmrr of the ad822 6 . by using a value of c d that is one m agnitude larger than c c , the ef fect of the mismatch is reduced and performance is improved.
ad8226 rev. b | page 23 of 28 applications information differential drive +in ?in ref ad8226 v bias r + ? op amp +out ?out 07036-009 r recommended o p amps: ad8515, ad8641, ad820. recommended r v alues: 5k ? to 20k?. figure 64 . differential output using an op amp figure 64 shows how to configure the ad822 6 for differ - ential output. the differential output is set by the following equation: v diff_out = v out+ ? v out ? = gain ( v in + ? v in ? ) t he common - mode output is set by the following equation: v cm_out = ( v o ut + ? v out ? )/2= v bias the advantage of this circuit is that the dc differential accuracy depends on the ad822 6 , not on the op amp or the resistors. in addition, t his circuit takes advantage of the precise control that the ad8226 has of its output voltage rel ativ e to the reference voltage. although the dc performance and resistor matching of the op amp affect the dc common - mode output accuracy , such errors are likely to be rejected by the next device in the signal chain and therefore typically have little effect o n overall system accuracy . tips for best differential output performance for best ac performance, an op amp with at least a 2 mhz gain bandwidth and a 1 v/s slew rate is recommended. good choices for op amps are the ad8641 , ad8515 , and ad820 . keep trace length s from the resistors to the inverting terminal of th e op amp as short as possible. excessive capacitance at this node can cause the circuit to be unstable. if capacitance cannot be avoided, use lower value resistors. for best linearity and ac performance, a minimum positive supply voltage (+v s ) is required. table 9 shows the minimum supply voltage required for optimum performance . in this mode, v cm_max indicates the maximum common - mode voltage expect ed at the input of the ad8226. table 9 . minimum positive supply voltage temperature equation less than ? 10c +v s > (v cm_max + v bias )/ 2 + 1.4 v ? 10c to 25c +v s > (v cm_max + v bias )/2 + 1.25 v m ore than 25c +v s > (v cm_max + v bias )/2 + 1.1 v
ad8226 rev. b | page 24 of 28 precision strain gag e the low offset and high cmrr over frequency of the ad8226 make it an excellent cand idate fo r performing bridge measure - ments. t he bridge can be connected directl y to the inputs of the amplifier (see figure 65) . 5v 2.5v 10f 0.1f ad8226 +in ?in r g 350? 350? 350? 350? + ? 07036-010 figure 65 . precision strain gage driving a n adc figure 66 shows several methods for driving an adc. the aduc7026 microcontroller was chosen for this example because it contains adcs with an unbuffered, charge - sampling architecture th at is typical of most modern adcs. this type of architecture typically requires an rc buffer stage between the adc an d amplifier to work correctly. o ption 1 shows the minimum configuration required to drive a charge - sampling adc . the capacitor provides c harg e to the adc sampling capacitor while the resistor shields the ad8226 from the capacitance. to keep the ad8226 stable , the rc time constant of the resistor and capacitor needs to stay above 5 s. t his circuit is mainly useful for low er frequency signal s. option 2 shows a circuit for driving higher speed signals. i t uses a precision op amp ( ad8616 ) with relatively high bandwidth and output drive . this amplifier can drive a resistor and capacitor with a much higher time constant and is therefore suited for higher frequency applications. option 3 is useful for application s where the ad8226 needs to run off a large v oltage supply but drive a single - su pply adc. in normal operation, the ad8226 output stays withi n the adc range, and the ad8616 simply buffers it. however , i n a fault condition, the output of the ad8226 may go outside the supply range o f both the ad8616 and th e adc. this is not an issue in the circu it, however, because the 1 0 k resistor between the tw o amplifie rs limits the current into the ad8616 to a safe level. ad8226 ref 100nf 100? 10k? 10? 10nf adc0 adc1 adc2 agnd 3.3v 3.3v 3.3v option 1: driving low frequenc y signals option 2: driving high frequenc y signals option 3: protecting adc from large vo lt ages 3.3v ad8226 ad8616 aduc7026 ref 3.3v 10? 10nf ad8226 ad8616 ref +15v ?15v a v dd 07036-065 figure 66 . driving a n adc
ad8226 rev. b | page 25 of 28 outline dimensions compl iant to jedec standa rds mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0. 40 0.25 1.10 max 3.20 3.00 2.80 copla narit y 0. 10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 ident ifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07- 2009-b figure 67 . 8- lead mini small outline package [msop] (rm - 8) dimensions shown in millimeters controlli ng dimensions are in millimeters; inch dimensions (in p arenthe ses) are rounded-o ff millimeter equiv alents for r eference onl y and are not appropria te for use in des ign. compliant t o jedec st andards ms-012-aa 012407 -a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) sea ting plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.24 41) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarit y 0.10 figure 68 . 8 - lead standard small outline package [soic_n] narrow body (r - 8) dimensions shown in millimeters and (inches) ordering gu ide model 1 temperature range package description package option branding ad8226 armz ? 40c to +12 5c 8 - lead msop rm - 8 y1 8 ad8226 armz -rl ? 40c to +12 5c 8 - lead msop, 13" tape and reel rm - 8 y1 8 ad8226 armz -r7 ? 40c to +12 5c 8 - lead msop, 7" tape and reel rm - 8 y1 8 ad8226 arz ? 40c to +12 5c 8 - lead soic_n r -8 ad8226 arz - rl ? 40c to +12 5c 8 - lead soic_n, 13" tape and reel r -8 ad8226 arz - r7 ? 40c to +12 5c 8 - lead soic_n, 7" tape and reel r -8 ad8226brmz ? 40c to +125c 8 - lead msop rm - 8 y19 ad8226brmz -rl ? 40 c to +125c 8 - lead msop, 13" tape and reel rm - 8 y19 ad8226brmz -r7 ? 40c to +125c 8 - lead msop, 7" tape and reel rm - 8 y19 ad8226brz ? 40c to +125c 8 - lead soic_n r -8 ad8226brz - rl ? 40c to +125c 8 - lead soic_n, 13" tape and reel r -8 ad8226brz - r7 ? 40c to +125c 8 - lead soic_n, 7" tape and reel r -8 1 z = rohs compliant part.
ad8226 rev. b | page 26 of 28 notes
ad8226 rev. b | page 27 of 28 notes
ad8226 rev. b | page 28 of 28 notes ? 2009 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07036 - 0 - 3/11(b)

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