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| ? maps ds3 (44.736 mbit/s) or e3 (34.368 mbit/s) line formats into sdh/sonet formats as follows: - ds3 to/from stm-1/tug-3 - ds3 to/from sts-3/sts-1 spe or sts-1 spe - e3 to/from stm-1/tug-3 only sdh/sonet bus access: - drop/add data byte access (with clock, c1j1, spe, and parity) - add bus interface timing derived from drop bus, add bus, or external timing path overhead byte processing: - microprocessor or external interface - b3 generation and detection with test mask - b3 performance counter (16-bit) and block error counter (8-bit) - c2 mismatch and unequipped detection - g1 processing - febe count by block or bits (16-bit counter) microprocessor access: - motorola or intel compatible (selected via a lead) - hardware/software interrupt capability line interface - transmit and receive nrz or rail operation with split operation capability testing functions: - sonet, facility, or line loopback - transmit and receive 2 15 -1 or 2 23 -1 generators and shared analyzer - boundary scan capability (ieee 1149.1) 144-lead plastic quad flat package (pqfp) or 208-lead plastic ball grid array package (pbga) the l3m maps a ds3 line signal into an stm-1 tug-3 or sts-3/ sts-1 spe or sts-1 spe sdh/sonet signal. an e3 line signal is mapped into an stm-1 tug-3 signal only. the l3m provides a tug-3 formatted signal for stm-1 operation, or an sts spe for sts-3 or sts-1 operation. the sdh/sonet signal is transmitted via an add bus with timing derived from the drop side, add side or from external timing (sts-1 only). an option is provided to gener- ate the a1, a2 framing pattern, c1 byte and h1, h2 pointer towards the add bus when external timing mode is selected. individual poh bytes for the transmitted sdh/sonet signal are mapped from the l3m memory map or an external inter- face. an option is provided to generate an unequipped status or tug-3 path ais signal. external accesses are provided for the communications channel ?o?-bits and alarms for ring oper- ation. the received signal is desynchronized from drop bus stm-1/tug-3, sts-3/sts-1 spe, or sts-1 signals. internal pointer processing is performed for the tug-3 signal. all poh bytes are provided for the microprocessor. add/drop multiplexers digital cross-connect systems broadband switching systems transmission equipment l3m device level 3 mapper txc-03452b document number: txc-03452b-mb ed. 4, september 1999 poh interface i/o alarm level 3 mapper l3m microprocessor control ?o?-bits alarms add bus nrz clock, nrz, rail input vcxo sdh/sonet side ext port i/o i/o line side data (monitor) scan boundary nrz, rail output drop bus txc-03452b u.s. patents no.: 4,967,405; 5,040,170; 5,157,655; 5,265,096 u.s. and/or foreign patents issued or pending copyright ? 1999 transwitch corporation txc and transwitch are registered trademarks of transwitch corporation data sheet applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
-2 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet table of contents section page list of figures ....................................................................................................... 3 block diagram ..................................................................................................... 5 block diagram description .................................................................................. 6 lead diagram for 144-lead plastic quad flat package .................................... 11 lead diagram for 208-lead plastic ball grid array package ........................... 12 lead descriptions ............................................................................................. 13 absolute maximum ratings and environmental limitations ............................. 24 thermal characteristics .................................................................................... 24 power requirements ......................................................................................... 24 input, output and i/o parameters ..................................................................... 25 timing characteristics ....................................................................................... 27 operation .......................................................................................................... 49 l3m power-up reset sequence ................................................................ 49 pll filter connection to vcxo ................................................................. 51 testing ........................................................................................................ 53 boundary scan ........................................................................................... 55 memory map ..................................................................................................... 61 memory map descriptions ................................................................................ 63 package information ......................................................................................... 86 standards documentation sources .................................................................. 88 ordering information ......................................................................................... 90 related products ............................................................................................... 90 list of data sheet changes .............................................................................. 91 documentation update registration form* ................................................. 95 * please note that transwitch provides documentation for all of its products. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. -3 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet list of figures figure page 1. l3m txc-03452b block diagram .......................................................... 5 2. l3m multiplexing structure ..................................................................... 6 3. itu-tss tug-3 build format ................................................................ 8 4. sonet au-3/sts-1 spe build format ................................................. 9 5. lead diagram for l3m txc-03452b 144-lead plastic quad flat package .............................................................................. 11 6. lead diagram foe l3m txc-03452b 208-lead plastic ball grid array package ....................................................................... 12 7. line side transmit timing ................................................................... 27 8. line side receive timing .................................................................... 28 9. stm-1 add bus derived interface timing ............................................ 29 10. sts-3 add bus derived interface timing ............................................ 30 11. sts-1 add bus derived interface timing ............................................ 31 12. stm-1 drop bus interface timing ........................................................ 32 13. sts-3 drop bus interface timing ........................................................ 33 14. sts-1 drop bus interface timing ........................................................ 34 15. sts-1 add bus interface timing using an external clock .................. 35 16. stm-1 add/drop bus interface timing ................................................ 36 17. sts-3 add/drop bus interface timing ................................................. 37 18. sts-1 add/drop bus interface timing ................................................. 38 19. transmit path overhead timing .......................................................... 39 20. receive path overhead timing ........................................................... 40 21. transmit alarm indication port timing ................................................. 41 22. receive alarm indication port timing .................................................. 42 23. transmit overhead communications channel timing ........................ 42 24. receive overhead communications channel interface timing .......... 43 25. intel microprocessor read cycle timing ............................................. 44 26. intel microprocessor write cycle timing .............................................. 45 27. motorola microprocessor read cycle timing ...................................... 46 28. motorola microprocessor write cycle timing ...................................... 47 29. boundary scan timing ......................................................................... 48 30. l3m power-up reset sequence .......................................................... 49 31. physical design for analog power distribution ................................... 50 32. pll connection to external vcxo ...................................................... 51 33. jitter results for sts-3/ds3 and tug-3/e3 mappings ....................... 52 34. loopbacks, test generator & analyzers ............................................. 54 35. external circuit to maintain clock input to tx prbs generator .......... 54 36. boundary scan schematic ................................................................... 56 37. l3m txc-03452b 144-lead plastic quad flat package ..................... 86 38. l3m txc-03452b 208-lead small outline plastic ball grid array package ........................................................... 87 -4 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet this page intentionally left blank. -5 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet block diagram figure 1. l3m txc-03452b block diagram motorola tpos tneg/los tclk p i/o intel d7 - d0 a7 - a0 sel rd wr rdy reset int moto ramci aisclk d7 - d0 a7 - a0 sel rd/wr dtack reset irq alarm interface port raipd taipd taipc taipf output block rpos rclk rnrzd rnrzc rneg ctrl xosci desync block destuff block ram path overhead i/o overhead comm channel i/o build block add block aclk ac1j1 aspe add adata(7-0) apar 8 8 input block stuff/ sync block 8 tochc tochd rochc rochd tpohc tpohd tpohf rpohc rpohd rpohf stai istat pais dclk dc1j1 dspe ddata(7-0) dpar dc1 xc1 xclke xclki ampinn drop block ds3/e3 ais gen 8 transmit sdh/sonet side line side tri internal amplifier ampinp ampout boundary scan (for vcxo) tms tck tdi trs tdo fifoerr decode block receive -6 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet block diagram description transmit and receive paths, overhead communications, alarms and control a simplified block diagram of the l3m device is shown in figure 1. the portion of the itu-t sdh multiplexing structure implemented by the l3m device is shown in figure 2. in the transmit direction, positive/negative (p/ n) rail data and clock input signals, or nrz data and clock input signals, operating at 44.736 mbit/s (ds3) or 34.368 mbit/s (e3), are connected to the input block. the transmit line input consists of positive rail/nrz signal lead (tpos), negative rail signal lead (tneg), and input clock (tclk). a control bit is provided in software that inverts the clock signal if required. the input block performs either an hdb3 or b3zs decoder function if the input line termination is a rail signal. separate nrz data (rnrzd) and clock (rnrzc) output signals are pro- vided for external performance monitoring circuits. illegal coding violations are counted in a 16-bit performance counter. when the line termination is nrz, the negative rail signal lead (tneg) can be used to clock in an external loss of signal indication. the transmit signal and clock are both monitored for operation, and alarms are reported for failure conditions. control bits are provided that enable the l3m device to send a line ais when either signal or clock failure is detected. the input block also monitors the line signal for an e3 ais and it has a 2 15 -1 or 2 23 -1 pseudo-random binary sequence (prbs) test generator for testing. figure 2. l3m multiplexing structure stm-n aug au-4 vc-4 au-3 vc-3 c-4 tug-3 vc-4 tu-3 vc-3 tug-2 tu-2 vc-2 c-2 tu-12 vc-12 c-12 tu-11 vc-11 c-11 c-3 pointer processing multiplexing aligning mapping same as sts-3 itu-t sdh multiplexing structure 139264 kbit/s (note 1) 6312 kbit/s (note 1) 2048 kbit/s (note 1) 1544 kbit/s (note 1) 44736 kbit/s (note 1) x n x 1 x 3 x 1 x 3 x 7 x 7 x 1 x 4 x 3 l3m note 1: g.702 tributaries associated with containers c-x are shown. other signals (e.g., atm) can also be accommodated. l3m portion or 34368 kbit/s -7 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet the stuff/sync block and build blocks work together for mapping a ds3 signal into a tug-3 or sts-1 spe or an e3 signal into a tug-3. the mapped formats are shown in figures 3 and 4. the stuffing algorithm for the ds3 signal format uses one set of five control bits (c-bits) with one stuff opportunity bit (s-bit) for frequency justification, per subframe (9 subframes). the e3 format uses five pairs of control bits (c1, c2 bits) to control two stuff opportunity bits (s1 and s2) per subframe (one subframe per three rows for a total of three subframes per frame). a read clock and timing indications are given by the build block for reading the transmit fifo. a fifo overflow or underflow alarm indication is provided. should an underflow/overflow condition occur, the fifo is immediately reset to the start-up preset value. the transmit fifo also tracks the incoming line signal that can have an average frequency error as high as +/- 20 ppm, and simultaneously accepts this signal with up to 5 ui peak-to-peak jitter (where ui = 1/f). the build block, with signals exchanged between itself and the stuff/sync block, constructs one of two 87 col- umn by 9 row formats: an itu-tss tug-3 signal (figure 3) or a sonet sts-1 (for sts-3) signal (figure 4). the l3m generates a stuff byte in column 0 when control bit nopoh is set to 0, to fill out the 87 columns of the spe such that three l3m devices will provide inputs for a vc-4 of 261 columns, as shown in figure 2. this col- umn position is overwritten with the vc-4 poh when the device is mapped into the first tug-3, while fixed stuff is used for the second and third tug-3s. a fixed pointer value of 6800h is used as the initial value when build- ing a tug-3 format. there are two levels of pointer movements in tug-3 mapping. when the tug-3 mode is selected in drop timing mode, the transmit tug-3 pointer value will change when there is a receive stm-1 au- 4 pointer increment or decrement. however, this feature may be disabled. pointer movements on the stm-1 bus, which are detected using the c1j1 and spe bus signals, are compensated by creating a tug-3 pointer movement in the opposite direction. an ? o ? -bit serial interface, or two bits in ram, are used for mapping the two ? o ? -bits into the ds3 sonet format subframes. the ? o ? -bit interface consists of an output clock (tochc) and an input data lead (tochd). the nine path overhead bytes are mapped individually into the sonet for- mat from either the poh interface (except the b3 byte), from microprocessor-written ram positions, or from internal logic (such as the path rdi state in bit 5 of g1). the poh interface consists of an output clock (tpohc), a framing pulse (tpohf) and an input data lead (tpohd). a control bit enables the poh interface bytes to be written into ram when transmitted. enable bits are provided for controlling the febe and path rdi states as a result of local alarms or remote status information received during ring operation. a b3 test mask or fixed byte can also be transmitted. control bits are provided for generating a tug-3 path ais, or an unequipped status condition (payload and poh bytes are equal to zero). an alarm interface provides febe and path rdi (ferf) input indications from a mate l3m device for ring operation. the alarm interface leads consist of input data (taipd), framing pulse (taipf), and clock signal (taipc). the add block uses an external byte rate clock signal (xclki), or the add or drop bus clock and the spe and c1j1 timing signals, for building and adding a tug-3, sts-3/sts-1 spe, or sts-1 spe to the add bus. the add block supports the stm-1/sts-3 bus signaling rate of 19.44 mhz and the sts-1 signaling rate of 6.48 mhz. the external clock is enabled by placing a high on the external clock enable lead (xclke), and is intended for sts-1 operation. the external clock generates the add bus clock (aclk), c1j1 indication (ac1j1), and spe indication (aspe). the output data to the bus is 3-state, active true. a software control bit enables the transport overhead a1, a2, c1, and h1/h2 bytes to be generated. the h1 and h2 bytes will carry the value of 6000h and the c1 byte carries the value of 01h. an optional c1 signal (xc1 signal lead) can be applied to the l3m device to align the start of the frame (a1, a2 bytes). -8 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 3. itu-tss tug-3 build format p o h c c c c c ab8i 24i 24i 2 41 86 e3 34.368 mbit/s subframe format (1 of 3) rrrrooc1c2 rrrroorr rrrrrrrs1 s2iiiiiii ab 24i 1r 3 11 15 20 28 36 40 24i 24i 24i 24i 24i 24i 24i 24i c 19 24 32 41 rrrrrrrr 24i 45 49 53 57 62 66 78 82 24i 24i 24i 24i 24i 24i 24i 24i 61 70 74 86 24i 2 1 rrrrrrc1c2 poh 8r 8r rrc 5i 200i 8r ccrrrrrr 208i 8r ccrroors 208i ds3 44.736 mbit/s subframe format (1 of 9) 234 31 32 59 60 86 1 k3 n1 j1 b3 c2 g1 f2 h4 f3 86 h1 h2 h3 tug-3 format (86 x 9) 1 9 0 0 0 01 -9 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 4. sonet au-3/sts-1 spe build format when add bus timing is selected, the clock (aclk), c1j1 indication (ac1j1), and spe indication (aspe) become input signals from the add bus. when drop timing is selected, the l3m device supports dc1j1 pointer movements on the drop bus, and adjusts the pointer value in the tug-3s accordingly. an active low add indi- cator (add ) is also provided to indicate the location of all time slots that are added to the bus by the l3m device (e.g., tug-3 a, b or c). in tug-3 mode, the vc-4 path overhead bytes are optionally sent as output to the bus when control bit nopoh (address ca, bit 5) is set to 0. the selected clock is monitored for operation, and an odd parity signal (apar) is calculated for the bus data, including the spe and c1j1 signals when these signals are outputs (i.e., in external timing mode). the drop block supports the stm-1/sts-3 bus signaling rate of 19.44 mhz and the sts-1 signaling rate of 6.48 mhz. the drop block uses the clock (dclk), c1j1 indication (dc1j1) and a separate dc1 signal if required, and spe indication (dspe) from a drop bus for determining the location of the path overhead j1 byte in the vc-4, the three j1 bytes in the three sts-1 spes in the sts-3 signal, and the single spe for sts- 1 operation. the c1 pulse is required, and is synchronous with the first c1 byte in the stm-1 section over- head bytes, or in the sts-3 or sts-1 transport overhead bytes. the c1 pulse provides a framing indication for determining the location of the bytes corresponding to the tug-3 or sts-1 selected, and is also used by the desynchronizer as a frame reference. the c1 pulse can be present in the dc1j1 signal or provided as a separate signal (dc1). the drop spe (dspe) is active during the poh and payload byte times. the drop bus clock and composite c1j1 signal are monitored for operation, and odd parity is calculated and compared against the incoming parity bit. the decode block contains the logic for performing pointer interpretation and tracking for the selected tug-3 signal, removing the path overhead bytes and overhead communication bits, and detecting the e1 byte for an upstream ais detection. the e1 byte carries an ais indication from an associated transwitch sot-3 or sot-1 device. the sot-3 or sot-1 generates an ais signal in one e1 byte for tug-3 mode, or in each of the three e1 bytes for the three sts-1s, when a loss of frame, loss of pointer, loss of signal, or line ais is detected. this indication is used by the l3m device to generate a path rdi indication, and for generating a received ds3 or e3 ais. in place of the e1 byte ais, the l3m device also supports an alarm indication provided on the istat and pais signal leads. the tug-3 pointer is monitored for loss of pointer, new data flag, and path ais. per- formance counters are provided for monitoring pointer movements. all poh bytes are written into ram loca- tions and are also provided at the poh interface. the poh interface consists of an output data lead (rpohd), j1 b3 c2 g1 f2 h4 z3 z4 z5 poh 8r 8r rrc 5i 200i 8r 8r ccrrrrrr 208i 8r 8r ccrroors 208i ds3 44.736 mbit/s subframe format (1 of 9) 123 3031 32 5960 61 87 1305987 au-3/sts-1 spe format (87 x 9) 1 9 - 10 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet framing pulse (rpohf), and clock signal (rpohc). the l3m device also provides a microprocessor-written location for performing c2 mismatch detection, and unequipped detection based on ansi and itu-tss stan- dards. the received ? o ? -bits are available at an external interface and a 2-bit ram location for these bits is updated each frame. the ? o ? -bit interface consists of a data lead (rochd) and clock signal (rochc). an alarm indication port is provided for ring operation. the alarm indication port consists of a data lead (raipd), which is used with the poh interface framing pulse (rpohf) and clock signal (rpohc). the signal on the data lead (raipd) consists of the febe count and a path rdi (ferf) status indication. the desynchronize block removes the effect on the output ds3 or e3 signals of systemic jitter due to signal mapping and pointer movements. the output has an average frequency equal to the source frequency, and has jitter characteristics that meet itu-tss and ansi standards. the desynchronize block consists of two cir- cuits, a pointer leak circuit and a phase-locked loop circuit. the function of the pointer leak circuit is to absorb the immediate effect of up to eight consecutive pointer movements (any combination of spe or tug-3 pointer movements) in either direction, and filter them out in time. a single pointer adjustment is an 8 unit inter- val (ui) phase step. the pointer leak circuit turns the phase step into eight 1-ui steps, widely spaced in time, allowing the phase-locked loop circuit to track. in normal operation, the output is one data bit and one clock cycle for each input bit. when a negative stuff occurs 8 extra bits are pulled from the signal and absorbed. fol- lowing this operation, the normal operation of one bit in for one bit out continues except that one extra bit is pulled from the fifo every n frames. in this way, the pointer step is leaked out in 8 x n frames. the value of n is programmed via the microprocessor. the phase-locked loop (pll) circuit of the desynchronize block is externally connected to a line-frequency voltage controlled crystal oscillator (vcxo) via a filter. details of the external circuit for the pll are provided in the operation section of this data sheet under the heading ? pll filter connection to vcxo ? . in the receive direction, the output block provides either a positive (rpos) and negative (rneg) rail line sig- nal or a nrz line signal (rpos), and a clock signal (rclk). the hdb3/b3zs coder operates independently of the transmitter. for interface flexibility, a control bit is provided for inverting the output clock. the receive data and clock outputs can be forced to a high impedance state for the purpose of tying two l3m devices together for ring operation or redundancy. an additional 2 15 -1 or 2 23 -1 pseudo-random test generator is provided. the output block and the input block share a 2 15 -1 or 2 23 -1 analyzer that can compare the desynchronizer output or transmit data against a fixed pattern. an alarm is provided when the analyzer and incoming data are not synchronous. errors are counted in the 16-bit coding violation counter. loopbacks between the input and out- put blocks facilitate board and network debugging. all of the control registers and performance counters, and the status and alarm indications, are accessible through the l3m device ? s compatible microprocessor bus interface in the microprocessor i/o block. the l3m device supports both intel and motorola microprocessor bus interfaces, with both hardware and software inter- rupt capability. the motorola compatible microprocessor interface is selected by placing a high on the moto signal lead. the boundary scan block provides a mechanism for external access to the input and output leads of the device, so that they may be observed and tested. the structure and operation of this block are described in the operation section. - 11 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet lead diagram for 144-lead plastic quad flat package figure 5. lead diagram for l3m txc-03452b 144-lead plastic quad flat package (top view) l3m 2 4 10 12 20 22 30 34 112 100 94 90 86 80 74 140 136 130 128 120 114 110 40 46 50 56 60 66 70 nc vdd tpos tri rneg vdd tpohc tpohf adata7 gnd vdd gnd aisclk vdd adata5 adata6 vdd gnd a0 trs a2 tms ddata7 ddata6 gnd gnd rpohc rpohf ddata5 rpohd tneg/los tdo a3 a4 a5 a6 a7 gnd wr rd or rd/wr sel gnd vdd gnd rdy/dtack int/irq ramci gnd moto d0 fifoerr gnd ddata4 apar adata4 tcap reset d2 xosci nc raipd gnd nc nc vdd gnd rochd rochc tpohd nc nc gnd apwr agnd agnd2 rcap apwr2 apwr agnd nc ampout ampinp ampinn gnd gnd ctrl rpos gnd rclk vdd d7 d6 d5 d4 d1 d3 apwr2 agnd2 istat pa i s stai rnrzc rnrzd tochd tochc gnd vdd gnd ta i p d ta i p f ta i p c nc gnd xclke xclki xc1 gnd adata2 adata0 adata1 adata3 aclk add ac1j1 aspe gnd vdd gnd dspe ddata3 ddata2 ddata1 ddata0 dc1 dpar dclk dc1j1 gnd 6 8 14 16 18 24 28 26 32 38 36 42 44 48 54 52 58 64 62 68 72 78 82 76 84 88 92 98 96 102 104 106 108 118 116 122 124 126 132 134 138 142 144 tdi tck apwr agnd tclk a1 txc-03452b note: see figure 37 for package information. - 12 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet lead diagram for 208-lead plastic ball grid array package figure 6. lead diagram for l3m txc-03452b 208-lead plastic ball grid array package 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 trp mlkjhgfedcb 1 2 4 3 6 7 10 12 14 16 17 18 19 20 22 23 26 27 28 30 31 32 34 35 36 37 38 41 42 43 45 46 47 48 49 50 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 71 72 73 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 114 115 116 118 117 121 120 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 140 143 144 192 194 197 198 199 200 notes: this is the bottom view. the leads are solder balls. see figure 38 for package information. some signal symbols have been abbreviated to fit the space available. the symbols are shown in full in the lead descriptions section. 16 a 5 9 195 n 142 145 146 147 148 149 150 151 152 153 154 155 156 157 159 161 162 163 164 165 166 168 167 170 171 172 174 175 176 180 181 182 184 185 186 188 190 191 51 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd rneg rpos nc nc nc nc d2 d5 gnd wr nc nc a0 tclk tneg nc nc nc gnd amout apwr apwr nc gnd nc gnd rpohf vdd nc nc nc nc aisclk xosci ampinp nc gnd rcap nc nc raipd rpohc nc nc nc vdd rclk nc ctrl nc fifo nc agnd2 nc vdd rochc rpohd gnd nc nc gnd vdd d7 ampinn agnd nc agnd nc apwr2 nc rochd gnd ddata5 nc ddata7 ddata6 d6 d4 nc nc ddata3 nc ddata4 d3 d1 d0 ddata0 nc ddata2 ddata1 moto ramci nc dc1j1 dclk dc1 dpar vdd nc dspe gnd int rdy gnd nc vdd nc nc gnd aspe apar nc rd sel ac1j1 nc aclk add addata7 nc adata5 adata6 a5 a6 a7 a2 a3 a4 nc adata4 nc adata3 nc gnd a1 tdo agnd istat rnrzd tochd gnd taipc tpohc xclki adata2 adata1 nc nc tpos tms tdi nc agnd2 rnrzc tochc reset nc gnd vdd nc gnd adata0 nc nc trs tck nc tcap pa i s vdd nc tpohf xc1 nc nc nc nc nc vdd tri nc apwr apwr2 stai gnd vdd tpohd xclke gnd nc nc vdd - 13 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet lead descriptions power supply, ground and no connects symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p* type** name/function vdd 23,34,38,55, 72,73,88, 108,126,141 b4, c9, c16, k3, j15, n1, n8, n14, t2, t16 p vdd: +5 volts, 5% power supply. apwr 10,14,101 f1, f16, g1, p analog vdd: +5 volts, 5% power supply. apwr2 18,98 g16, j4 p analog vdd2: +5 volts, 5% power supply. gnd 4,13,20,24, 27,29,33,37, 39,48,54,56, 62,71,74,78, 87,89,112, 121,125, 127,132 a9, c13, d1, d8, g2, g7, g8, g9, g10, h7, h8, h9, h10, j1, j7, j8, j9, j10, j16, k7, k8, k9, k10, k13, l1, m4, m14, n3, n16, p9, r14, t3, t8 p ground: 0 volts reference. agnd 9,15,100 e4, f13, g4 p analog ground: 0 volts reference. agnd2 17,97 g14, h3 p analog ground2: 0 volts reference. nc 8,12,19 21,22,35 36,82 a3, a4, a7, a8, a11, a12, a16, b1, b2, b9, b10, b13, b14, b15, b16, c1, c3, c15, d5, d7, d9, e3, e16, f2, f4, f14, f15, g3, h1, h4, j2, j3, k1, k2, k4, l14, n2, n5, n9, n12, n15, p1, p2, p3, p4, p6, p8, p10, p11, p14, p15, p16, r1, r2, r3, r5, r12, r15, r16, t1, t13, t15 no connect: nc leads are not to be connected, not even to another nc lead, but must be left float- ing. connection of these leads may impair perfor- mance or cause damage to the device. *note: i = input; o = output; p = power; t = tri-state **note: see input, output and i/o parameters section below for the type definitions. - 14 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet line interface symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function rnrzd 92 h13 o cmos 4ma receive line nrz data: output provided for an optional external performance monitoring circuit. this serial nrz output is provided after the decoder (transmit direction), independent of whether the input is nrz or rail. data is always clocked out on positive transitions of clock (rnrzc). this lead goes to a high impedance state when control bit l3z is set to 1. rnrzc 93 h14 o cmos 4ma receive line clock: nrz data on lead rnrzd is clocked out of the l3m device on positive transitions of this clock. this lead goes to a high impedance state when control bit l3z is set to 1. tpos 109 c14 i cmos transmit nrz line data/positive rail data: serial nrz input for the 44.736 or 34.368 mbit/s asynchronous line data. this lead also provides the positive rail data input for an internal decoder. tneg/ los 110 a15 i cmos transmit negative rail data: when operating in the p/n rail mode, this lead provides a negative rail input for the internal decoder. when operating in the nrz mode, a high on this lead instead indicates an external loss of signal alarm, so that the lead must be tied to ground if it is not used for input of an external loss of signal indication. tclk 111 a14 i cmos transmit line clock: nrz or rail data is clocked into the l3m device using the tpos/tneg signal leads on positive transitions of this clock when control bit invci is set to 0. nrz or rail data is clocked in on negative transitions when control bit invci is set to 1. tclk is used as the input clock for the transmit prbs generator and it must be present to generate a test pattern. rclk 142 b3 o cmos 4ma receive line clock: line data present on the rpos/ rneg signal leads (44.736 or 34.368 mbit/s) is clocked out of the l3m device on negative transitions of this clock when control bit invco is set to 0. nrz or rail data is clocked out on positive transitions of this clock when control bit invco is set to 1. this lead goes to a high impedance state when control bit l3z is set to 1. rpos 143 a2 o cmos 4ma receive line nrz data/positive rail data: serial nrz output for the 44.736 or 34.368 mbit/s asynchronous line data. this lead also provides the positive rail output when the rail interface is selected. this lead goes to a high impedance state when control bit l3z is set to 1. rneg 144 a1 o cmos 4ma receive negative rail data: this lead provides a negative rail interface from the internal coder. this lead goes to a high impedance state when control bit l3z is set to 1. when the nrz interface is selected, this lead outputs a 0. - 15 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet microprocessor interface symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function a(7-0) 120 - 113 d11, c11, b11, d12, c12, b12, d13, a13 ittl address bus: these are address line inputs that are used by the microprocessor for accessing the l3m ram for a read/write cycle. a0 is defined as the least significant bit. high is logic 1. wr 122 a10 i ttl write (i mode): intel mode - an active low signal generated by the micro- processor for writing to the l3m ram locations. motorola mode - not used. rd rd/wr 123 c10 i ttl read (i mode) or read/write (m mode): intel mode - an active low signal generated by the micro- processor for reading the l3m ram locations. motorola mode - a high signal generated by the microprocessor for reading the l3m ram locations. a low signal is used for writing to l3m ram locations. sel 124 d10 i ttlp select: a low enables data transfers between the micro- processor and the l3m device during a read/write cycle. rdy/ dtack 128 c8 o(t) ttl8ma ready (i mode) or data transfer acknowledge (m mode): intel mode - a high is an acknowledgment from the addressed ram location that the transfer can be com- pleted. a low indicates that the l3m has not completed the transfer cycle, and the microprocessor must wait before latching read data or completing the write cycle. motorola mode - during a read bus cycle, a low signal indi- cates the information on the data bus is valid. during a write bus cycle, a low signal acknowledges the acceptance of data. int/irq 129 b8 o(t) ttl4ma interrupt: intel mode - a high on this output lead signals an interrupt request to the microprocessor. the off state is low when control bit intz (bit 2, register c2) is 0, and 3-state when intz is 1. motorola mode - a low on this lead signals an interrupt request to the microprocessor. the off state is high when intz is 0, and 3-state when intz is 1. ramci 130 c7 i cmos ram clock input: clock input for the internal ram. this clock allows an outside clock to provide an arbitrator func- tion for accessing the internal ram structure. this clock must operate between 12 and 25 mhz with a duty cycle of 50 +/- 10 percent. this clock and the microprocessor timing signals may operate asynchronously with respect to each other. moto 131 b7 i ttl motorola/intel microprocessor select: a high selects the motorola microprocessor compatible bus interface. a low selects the intel microprocessor compatible bus interface. - 16 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet drop bus interface d(7-0) 140 - 133 c4, b5, a5, c5, b6, a6, c6, d6 i/o ttl8ma data bus: bi-directional data lines used for transferring data between the l3m device and an external microproces- sor. d0 is defined as the least significant bit. high is logic 1. symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function ddata (7-0) 40 - 47 r4, t4, n4, t5, p5, r6, t6, n6 ittl drop data byte: byte data that corresponds to the stm-1/ sts-3/sts-1 signal from the drop bus. the first bit received corresponds to bit 7. dc1 49 r7 i ttl drop c1 pulse: external positive c1 pulse that may be provided on this lead instead of in the dc1j1 signal. this signal is ored internally with the dc1j1 signal to form a composite c1j1 signal. if this lead is not used it must be grounded. this lead is used for special applications. dpar 50 t7 i ttl drop bus parity bit: this is an odd parity input for each data byte, the dspe signal, and the composite dc1j1 pulses. the status bit buserr (bit 5 in registers b0 and b1) indicates when this input differs from an internally-gen- erated odd parity for these signals, but no other action is taken upon occurrence of this drop bus parity error. dclk 51 p7 i ttl drop bus clock: this clock operates at 19.44 mhz for stm-1/sts-3 operation, and at 6.48 mhz for sts-1 bus operation. drop bus byte-wide data (ddata7-0), parity (dpar), payload indicator (dspe), and c1/j1 (dc1j1 and dc1) are clocked into the l3m device on negative transi- tions of this clock. dc1j1 52 n7 i ttl drop bus c1 and j1 indicator: the c1 pulse is an active high, one clock cycle wide timing pulse that indicates the location of the first c1 time slot in the stm-1 or sts-3 frame. if the c1 pulse is not present in this signal, it must be provided at the dc1 lead. a j1 pulse, also one clock cycle wide, identifies the location of the j1 byte. dspe 53 r8 i ttl drop bus spe indicator: a signal that is high during the stm-1 vc-4, and the sts-3/sts-1 spe period. symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function - 17 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet add bus interface symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function apar 57 t9 o(t) ttl4ma add bus parity bit: this output bit represents the odd par- ity calculation for each data byte in the add timing and drop timing modes. in the external timing mode, the parity calcu- lation also includes the aspe and ac1j1 signals which become outputs. this lead is forced to a high impedance state when the control bit addz is set to 1, or when add is inactive (high). aspe 58 r9 i/o(t) ttl4ma add bus spe indicator: an input signal that is high during the stm-1 vc-4 period, and sts-3/sts-1 spe period. when enabled by the external clock enable (xclke) con- trol lead, this signal becomes an output. this lead is forced to a high impedance state when the control bit addz is set to 1, or when the drop timing mode is selected. ac1j1 59 n10 i/o(t) ttl4ma add bus c1 and j1 indicator: the c1 pulse is an active high, one clock cycle wide input timing pulse that identifies the location of the first c1 time slot in the stm-1 or sts-3 frame. a j1 pulse, also one clock cycle wide, identifies the location of the j1 byte. when enabled by the external clock enable (xclke) control lead, this signal becomes an out- put. this lead goes to a high impedance state when control bit addz is set to 1, or when the drop timing mode is selected. add 60 t10 o ttl4ma add indicator: an active low signal that identifies the posi- tion of the data time slots being mapped onto the add bus. this signal will be high when - data is not present - reset is present - add bus loss of clock occurs - when control bit addz is set to 1. - until the first two c1 pulses are received in either the add bus or drop bus timing mode. this avoids bus contention during start up. this signal will be a high impedance when the tri lead is low. aclk 61 r10 i/o ttl4ma add bus clock: this clock operates at 19.44 mhz for stm-1/sts-3 operation, and at 6.48 mhz for sts-1 bus operation. the add clock is used for build block timing and for sourcing the add bus byte-wide data (adata(7-0)), par- ity (apar), and add indicator (add ). when enabled by the external clock enable (xclke) control lead, this signal becomes an output. this lead goes to a high impedance state when control bit addz is set to 1. - 18 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet overhead communications channel interface adata (7-0) 63 - 70 n11, t11, r11, p12, t12, p13, r13, t14 o(t) ttl4ma add data byte: byte-wide data that corresponds to the stm-1/sts-3/sts-1 time slots that are placed on the add bus. bit 7 corresponds to bit 1 in the stm-1/sonet trans- mission format. this bus is forced to a high impedance state when the control bit addz is set to 1, or when a dd is inactive (high). symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function rochd 25 l4 o ttl4ma receive overhead comm channel data: unaligned data output for the overhead communications channel ? o ? -bits from the ds3 or e3 formats. the ? o ? -bits are clocked out of the l3m device on negative transitions of the rochc clock signal. rochc 26 l3 o ttl4ma receive overhead comm channel clock: a gapped 720 khz output clock with an average frequency of 144 khz for clocking out the transmit overhead communications channel bits to external circuitry. tochc 90 j14 o ttl4ma transmit overhead comm channel clock: a gapped 720 khz output clock with an average frequency of 144 khz for sourcing the transmit overhead communications channel bits from external circuitry. tochd 91 j13 ittl transmit overhead comm channel data: data input for the overhead communications channel in the ds3 or e3 for- mats. data is clocked into the l3m device on positive transi- tions of the tochc clock signal. the bits are multiplexed into the ? o ? -bit positions unaligned regarding bit position and subframe number. this input is enabled by the exoo control bit. when enabled, the lead must be grounded if it is desired to insert zeroes in the corresponding fixed stuff locations. symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function - 19 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet path overhead interface symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function rpohd 30 m3 o ttl4ma receive path overhead data: the serial output for the nine path overhead bytes. the poh bytes are clocked out on negative transitions of the clock signal (rpohc). rpohf 31 m1 o ttl4ma receive path overhead framing: a positive one clock cycle (rpohc) wide output framing pulse that is synchro- nous with the j1 data of rpohd. this signal is also used as the framing pulse for the receive alarm indication port data (raipd). rpohc 32 m2 o ttl4ma receive path overhead clock: a gapped clock used for clocking out the path overhead bytes, and receive alarm indication port data (raipd). tpohc 79 m13 o ttl4ma transmit path overhead clock: a gapped clock used for clocking the path overhead bytes from an external circuit into the l3m device. tpohf 80 l15 o ttl4ma transmit path overhead framing: a positive one clock cycle (tpohc) wide output framing pulse that determines the start of the j1 byte in tpohd. tpohd 81 l16 ittl transmit path overhead data: a serial input for the fol- lowing path overhead bytes: j1, c2, g1, f2, h4, z3, z4, and z5 bytes. the poh bytes are clocked into the l3m device on positive transitions of the tpohc clock signal. eight bits are clocked in during the b3 byte time, but they are ignored by the l3m device. - 20 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet alarm indication port additional signals symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function raipd 28 l2 o ttl4ma receive alarm indication port data: a serial output that provides the 4-bit febe count (b3 error count) and path rdi alarm indication to a mate l3m device for ring opera- tion. this lead is normally connected to the taipd lead at the mate l3m device. the rpohc signal is used to clock this signal out of the l3m device. the rpohf signal pro- vides the frame reference signal. the bits are sent in the following format: bit 1 is the msb and is sent first in the bit stream. ta i p c 8 3 l13 ittl transmit alarm indication port clock: this clock input is normally connected to the rpohc clock lead at the mate l3m device for ring operation. transmit alarm data (taipd) is clocked into the l3m device on positive transitions of the rpohc clock. ta i p f 8 4 k15 ittl transmit alarm indication port framing pulse: normally connected to rpohf lead at the mate l3m device for ring operation. used to indicate the first bit in the first byte for the external alarm indications. ta i p d 8 5 k16 ittl transmit alarm indication port data: this serial input lead is normally connected to the raipd lead at the mate l3m device for ring operation. provides an input for the four bit febe count (b3 error count), and path rdi alarm indica- tion (as shown above for raipd). symbol 144-lead qfp lead no. 208- lead bga lead no. i/o/p type name/function aisclk 1 c2 icmos ais clock input: clock input for the l3m device ? s ais gen- erator. this clock must be present for the ais generator to function. the clock must have the operating line rate of either 44.736 or 34.368 mhz, and have a frequency stabil- ity of +/- 20 ppm. xclki 75 n13 ittl external clock input: used to derive output timing and data for the add bus. enabled by placing a high on the lead labeled xclke. a byte clock frequency of 6.48 mhz is required for sts-1 operation. this clock is monitored for loss of clock when the external timing mode is selected. 1 2 3 4 5 6 7 8 b3 count rdi 0 0 1 bits - 21 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet xc1 76 m15 ittl external c1 input: optional c1 input signal used to syn- chronize the frame start when the external timing mode is selected for the add bus. this lead must be held low when the external timing mode is not used. xclke 77 m16 ittl external clock enable: a high on this lead enables add bus timing to be derived from the xckli lead (external clock signal). the aspe, ac1j1, and aclk signal leads become output leads. reset 86 k14 i ttlp hardware reset: a low clears all counters and initiates reframing in the transmit direction upon its release. this lead is provided with an internal pull-up resistor. the reset signal must be low for a minimum of 200 nanoseconds. the bus clocks, line clocks, microprocessor clock and vcxo clock must be present during the reset signal. the add bus outputs are held in a high impedance state during the reset period. the add bus high impedance state is released on the occurrence of the c1 pulse. fifoerr 11 f3 o ttl8ma od fifo reset indication: this lead requires an external 4.7 k ? pull-up resistor to +5v. a high on this lead indicates that the receive side fifos have been reset. the reset condi- tion occurs after a hardware reset (rese t , lead 86 or k14) or a software reset (control bit rxrst), or after a fifo error (underflow or overflow). after the hardware or soft- ware reset, or the fifo error, clears, fifoerr stays high for a minimum of 125 microseconds and a maximum of 250 microseconds before returning to its normal low level. stai 94 h16 ittl sts network alarm indication: a high on this lead will generate a count of 9 in bits 1 through 4 of g1 when control bit febe9en is equal to 1. an indication is also provided as the xstai status bit. the lead is normally grounded. pa i s 9 5 h15 ittl external path ais indication: a high on this lead may be used to indicate an external path ais has occurred. it causes the xpais status bit to be set to 1. this lead is enabled when control bit xalm2ais is a 1. when enabled, the in-band upstream ais indication provided via the toh e1 byte is disabled. istat 96 g13 ittl external sts-1 alarm indication: a high on this lead may be used to indicate an external sonet/sdh alarm has occurred. it causes the xistat status bit to be set to 1. tri 107 d16 i ttlp high impedance enable: a low causes all l3m device dig- ital outputs and bi-directional leads to be set to a high impedance state for test purposes. this lead is provided with an internal pull-up resistor. symbol 144-lead qfp lead no. 208- lead bga lead no. i/o/p type name/function - 22 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet receive and transmit phase locked loops receive desynchronizer symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function rcap 16 h2 ianalog receiver internal phase locked loop capacitor: optional capacitor used for an internal receive phase locked loop. this lead must be left floating. tcap 99 g15 ianalog transmitter internal phase locked loop capacitor: optional capacitor used for an internal transmit phase locked loop. this lead must be left floating. symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function xosci 2 d2 i cmos external oscillator input: this input is connected to the output of the external vcxo, as shown in the pll connec- tions diagram (figure 32). ctrl 3 d3 o ttl8ma phase detector output : normally connected to the exter- nal low pass filter consisting of external components and the internal amplifier. ampinn 5 d4 i analog internal amplifier - negative port input: negative port of an internal amplifier which can be used in the desynchro- nizer loop filter. ampinp 6 e2 i analog internal amplifier - positive port input: positive port of an internal amplifier which can be used in the desynchro- nizer loop filter. ampout 7 e1 o analog internal amplifier - output: output of an internal ampli- fier which can be used in the desynchronizer loop filter. - 23 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet boundary scan testing symbol 144-lead qfp lead no. 208-lead bga lead no. i/o/p type name/function tdo 102 e13 o(t) ttl4ma boundary scan test data output: serial data clocked out on negative transitions of tck. tdi 103 e14 i ttl boundary scan test data input: serial data input for boundary scan test messages. tck 104 e15 i ttl boundary scan test clock: the input clock for boundary scan testing. the tdi and tms states are clocked in on positive transitions. tms 105 d14 i ttlp boundary scan test mode select: the signal present on this lead is used to control test operations. trs 106 d15 i ttlp boundary scan test reset: this lead must be asserted low for at least 5 nanoseconds in order to reset the l3m device ? s test access port (tap) controller. the tap con- troller may also be reset by holding the tms signal lead high for at least five clock cycles of tck. in applications which will not be using the boundary scan feature, this lead must be tied low, thereby holding the tap controller reset. - 24 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the ? caution ? label on the drypack bag in which devices are supplied. 3. v in may not exceed the actual operating supply voltage (v dd ) by more than 0.5 volt. thermal characteristics power requirements parameter symbol min max unit conditions supply voltage v dd -0.3 +7.0 v note 1 dc input voltage v in -0.5 v dd + 0.5 v notes 1, 3 storage temperature range t s -55 150 o c note 1 ambient operating temperature t a -40 85 o c 0 ft/min linear airflow component temperature x time ti 270 x 5 o c x s note 1 moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd 2000 v per mil-std-883d method 3015.7 parameter min typ max unit test conditions 144-lead qfp thermal resis- tance: junction to ambient 34 o c/w 0 ft/min linear airflow 208-lead bga thermal resis- tance: junction to ambient 29.0 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd 4.75 5.00 5.25 v i dd 190 ma analog v dd 4.75 5.00 5.25 v analog i dd 30 ma analog v dd2 4.75 5.00 5.25 v analog i dd2 1ma p dd 1160 mw inputs switching - 25 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet input, output and i/o parameters input parameters for cmos input parameters for ttl input parameters for ttlp output parameters for cmos 4ma parameter min typ max unit test conditions v ih 3.15 v 4.75 < v dd < 5.25 v il 1.65 v 4.75 < v dd < 5.25 input leakage current -10 av dd = 5.25; v in = 0 input capacitance 3.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current -10 av dd = 5.25; v in = 0 input capacitance 3.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current -0.5 -1.4 ma v dd = 5.25; v in = 0 input capacitance 3.5 pf parameter min typ max unit test conditions v oh v dd(min) - 0.7 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 1.2 2.8 5.0 ns c load = 15pf t fa l l 0.9 2.0 4.1 ns c load = 15pf - 26 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet output parameters for cmos 8ma input/output parameters for ttl 4ma input/output parameters for ttl 8ma and ttl 8ma od (open drain) notes: 1. output drivers will output cmos logic levels into cmos loads. 2. v ol , i ol and t fall are the only parameters applicable to ttl 8ma od. parameter min typ max unit test conditions v oh v dd(min) - 0.7 v v dd = 4.75; i oh =-8.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 1.2 2.8 5.0 ns c load = 15pf t fa l l 0.9 2.0 4.1 ns c load = 15pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current -10 av dd = 5.25; v in = 0 input capacitance 3.5 pf v oh 2.4v v v dd = 4.75; i oh = -4.0 (note 1) v ol 0.4 v v dd = 4.75; i ol = 4.0 (note 1) i ol 4.0 ma i oh -4.0 ma t rise 2.5 5.5 10.0 ns c load = 15pf t fa l l 1.0 2.0 4.0 ns c load = 15pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current -10 av dd = 5.25; v in = 0 input capacitance 3.5 pf v oh 2.4v v v dd = 4.75; i oh = -8.0 (note 1) v ol (note 2) 0.4 v v dd = 4.75; i ol = 8.0 (note 1) i ol (note 2) 8.0 ma i oh -8.0 ma t rise 1.9 4.5 8.0 ns c load = 25pf t fa l l (note 2) 0.8 1.5 3.1 ns c load = 25pf - 27 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet timing characteristics detailed timing diagrams for the l3m device are illustrated in figures 7 through 29, with values of the timing intervals tabulated below the diagrams. all output times are measured with a maximum 25 pf load capaci- tance. timing parameters are measured at voltage levels of (v ih + v il )/2 for input signals or (v oh + v ol )/2 for output signals. figure 7. line side transmit timing * 22.35 ns (ds3) or 29.10 ns (e3). parameter symbol min typ max unit tclk clock period t cyc(1) *ns tclk duty cycle, t pwh(1) /t cyc(1) -- 40 50 60 % tpos/tneg input set-up time to tclk t su 4.0 ns tpos/tneg input hold time after tclk t h 2.0 ns rnrzc clock period t cyc(2) *ns rnrzc duty cycle, t pwh(2) /t cyc(2) -- 40 50 60 % rnrzd output delay after rnrzc t od -2.0 5.0 ns tclk tpos t cyc(1) t pwh(1) t su t h (input) (input) (input) tpos/tneg (input) t su t h t su t h los indication (nrz mode) rnrzc t cyc(2) t pwh(2) (ouput) t od rnrzd (output) nrz interface rail interface note: shown for invci equal to 0; data is clocked in on the negative edge when invci equals 1. rnrzd is always clocked out on the positive transitions of rnrzc. the delay between the input clock tclk and output clock rnrzc is not specified. tneg(los indication) - 28 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 8. line side receive timing *22.35 ns (ds3) or 29.10 ns (e3). parameter symbol min typ max unit rclk clock period t cyc *ns rclk high time t pwh t cyc /2 ns rclk low time t pwl t cyc /2 ns rclk duty cycle, t pwh /t cyc ---455055% rpos/rneg data output delay after rclk t od -2.0 5.0 ns rclk rpos t cyc t pwh t pwl t od (output) (output) t od rpos/rneg (output) note : shown for invco equal to 0; data is clocked out on the positive edge when invco equals 1. the three signals are forced to a high impedance state when control bit l3z is set to 1. nrz interface rail interface - 29 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 9. stm-1 add bus derived interface timing parameter symbol min typ max unit aclk clock period t cyc 51.44 ns aclk duty cycle, t pwh /t cyc -- 40 50 60 % ac1j1 set-up time to aclk t su(1) 7.0 ns ac1j1 hold time after aclk t h(1) 3.0 ns aspe set-up time to aclk t su(2) 10.0 ns aspe hold time after aclk t h(2) 5.0 ns adata(7-0) data and apar output delay from aclk t od(1) 3.0 30 ns add low output delay from aclk t od(2) 3.0 25 ns adata(7-0) and apar tri-state delay from aclk t od(3) 12 25 ns add high output delay from aclk t od(4) 12 25 ns aclk t su(1) t h(1) t h(2) t od(1) h1 t su(2) t od(2) stuff byte data c1(1) j1 (input) aspe (input) ac1j1 (input) adata (7-0) apar add (output) t pwh t cyc note : the relationship between j1 and the spe signal is shown for illustration purposes only. for the stm-1 format, there will be one j1 pulse which indicates the start of the vc-4 that carries the three tug-3s. the tug-3 added to the bus is shown for the tug-3 designated as a. tug-3 b will occur one clock cycle later. there is always a one byte delay between the output adata and ac1j1/aspe inputs. for j1 tug-3 (outputs) t od(3) t od(4) - 30 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 10. sts-3 add bus derived interface timing parameter symbol min typ max unit aclk clock period t cyc 51.44 ns aclk duty cycle, t pwh /t cyc -- 40 50 60 % ac1j1 set-up time to aclk t su(1) 7.0 ns ac1j1 hold time after aclk t h(1) 3.0 ns aspe set-up time to aclk t su(2) 10.0 ns aspe hold time after aclk t h(2) 5.0 ns adata(7-0) data and apar output delay from aclk t od(1) 3.0 30 ns add low output delay from aclk t od(2) 3.0 25 ns adata(7-0) and apar tri-state delay from aclk t od(3) 12 25 ns add high output delay from aclk t od(4) 12 25 ns aclk t su(1) t h(1) t h(2) t od(1) j1 sts1#1 t su(2) data c1(1) j1 for (input) aspe (input) ac1j1 (input) adata(7-0) apar add (output) t pwh t cyc note : the relationship between j1 and the spe signal is shown for illustration purposes only. for the sts-3 format, there will be three j1 pulses which indicate the start of each of the sts-1 spes. the sts-1 spe added to the bus is shown for sts-1 num- ber 1. sts-1 number 2 will occur one clock cycle later. there is always a one byte delay between the output adata and ac1j1/aspe inputs. sts-1 #1 sts-1#1 data sts-1#1 t od(2) (outputs) t od(3) t od(4) - 31 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 11. sts-1 add bus derived interface timing parameter symbol min typ max unit aclk clock period t cyc 154.32 ns aclk duty cycle, t pwh /t cyc -- 40 50 60 % ac1j1 set-up time to aclk t su(1) 7.0 ns ac1j1 hold time after aclk t h(1) 3.0 ns aspe set-up time to aclk t su(2) 10.0 ns aspe hold time after aclk t h(2) 5.0 ns adata(7-0) data and apar output delay from aclk t od(1) 3.0 30 ns add low output delay from aclk t od(2) 3.0 25 ns adata(7-0) and apar tri-state delay from aclk t od(3) 12 25 ns add high delay from aclk t od(4) 12 25 ns aclk t su(1) t h(1) t h(2) t od(1) j1 t su(2) t od(2) c1 j1 (input) aspe (input) ac1j1 (input) adata(7-0) apar add (output) t pwh t cyc note : the relationship between j1 and the spe signal is shown for illustration purposes only. there is always a one byte delay between the output adata and ac1j1/aspe inputs. data data data (outputs) t od(4) t od(3) - 32 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 12. stm-1 drop bus interface timing parameter symbol min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle, t pwh /t cyc -- 40 50 60 % ddata(7-0) data/dpar/dc1j1 set-up time to dclk t su 7.0 ns ddata(7-0) data/dpar/dc1j1 hold time after dclk t h 3.0 ns note : the relationship between j1 and the spe signals is shown for illustration pur- poses only, and will be a function of the pointer offset. for the stm-1 format, there will be one j1 pulse which indicates the start of the vc-4 that carries the three tug-3s. the c1 pulse is shown dotted because the c1 pulse may be provided on the dc1 signal lead. if the dc1 signal lead is not used, it must be grounded. t cyc t h t su c1(1) j1 dclk (input) dspe (input) dc1j1 (input) t pwh t h t su c1(2) c1(3) j1 fixed stuff fixed stuff h1(1) c1(1) ddata(7-0) dpar tug-3 h1(2) tug-3 (inputs) - 33 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 13. sts-3 drop bus interface timing parameter symbol min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle, t pwh /t cyc -- 40 50 60 % ddata(7-0) data/dpar/dc1j1 set-up time to dclk t su 7.0 ns ddata(7-0) data/dpar/dc1j1 hold time after dclk t h 3.0 ns note : the relationship between j1 and the spe signals is shown for illustration purposes only, and will be a function of the pointer offset. for the sts-3 format, there will be three j1 pulses which indicate the start of each of the sts-1 spes. the c1 pulse is shown dotted because the c1 pulse may be provided on the dc1 signal lead. if the dc1 signal lead is not used, it must be grounded. t cyc t h t su c1(1) j1 for c1(2) c1(3) j1 spe sts-1 #2 spe sts-1 #3 data sts-1 #1 dclk (input) ddata(7-0) dpar dspe (input) dc1j1 (input) t pwh t h t su sts-1 #1 c1(1) sts-1#1 (inputs) - 34 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 14. sts-1 drop bus interface timing parameter symbol min typ max unit dclk clock period t cyc 154.32 ns dclk duty cycle, t pwh /t cyc -- 40 50 60 % ddata(7-0) data/dpar/dc1j1 set-up time to dclk t su 7.0 ns ddata(7-0) data/dpar/dc1j1 hold time after dclk t h 3.0 ns note : the relationship between j1 and the spe signals is shown for illustration pur- poses only, and will be a function of the pointer offset. for the sts-1 format, there will be one j1 pulse which indicates the start of the sts-1 spe. the c1 pulse is shown dotted because the c1 pulse may be provided on the dc1 sig- nal lead. if the dc1 signal lead is not used, it must be grounded. t cyc t h t su c1 j1 data data j1 data data dclk (input) ddata(7-0) dpar dspe (input) dc1j1 (input) t pwh t h t su data c1 (inputs) - 35 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 15. sts-1 add bus interface timing using an external clock parameter symbol min typ max unit xclki clock period t cyc(1) 154.32 ns xclki duty cycle, t pwh(1) /t cyc(2) -- 40 50 60 % aclk clock period t cyc(2) 154.32 ns aclk duty cycle, t pwh(2) /t cyc(2) -- 40 50 60 % ac1j1/aspe delay after aclk t od(1) 0.0 5.0 ns adata(7-0) data and apar delay after aclk t od(2) 0.0 12 ns aclk clock delay after xclki t od(3) 3.0 25 ns note : timing is shown for sts-1 signal. pointer value is transmitted with a value equal to 0. when the tohout bit is set to 1, the a1, a2, c1, h1, and h2 bytes are generated. different from add/drop mode, output ac1j1/aspe and adata are synchronous in the external clock mode. t cyc(1) t od(2) t od(1) c1 j1 a2 c1 = 01 h1 h2 xclki (input) aclk (output) aspe (output) ac1j1 (output) t pwh(1) data a1 data h3 j1 t cyc(2) t pwh(2) t od(1) add (output) adata(7-0) apar r=00 r=00 xc1 (input) t su min = 7 ns t h min = 3 ns t od min = 7 ns max = 25 ns (outputs) (low) t od(3) - 36 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 16. stm-1 add/drop bus interface timing parameter symbol min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle, t pwh /t cyc -- 40 50 60 % ddata(7-0) data/dpar/dc1j1 set-up time to dclk t su(1) 7.0 ns ddata(7-0) data/dpar/dc1j1 hold time after dclk t h(1) 3.0 ns dspe set-up time to dclk t su(2) 10.0 ns dspe hold time after dclk t h(2) 5.0 ns adata(7-0) data and apar delay after dclk t od(1) 3.0 30 ns add indicator delayed after dclk t od(2) 3.0 25 ns adata(7-0) data and apar tri-state after dclk t od(3) 12 25 ns ad d high after dclk t od(4) 12 25 ns note : the relationship between j1 and the spe signals is shown for illustration purposes only, and will be a function of the pointer offset. for the stm-1 format, there will be one j1 pulse which indicates the start of the vc-4 that carries the three tug-3s. the c1 pulse is shown dotted because the c1 pulse may be provided on the dc1 signal lead. if the dc1 signal lead is not used, it must be grounded. shown is tug-3 a being added to the add bus. t cyc t h(1) t su(1) c1(1) j1 c1(2) c1(3) j1 fixed h1(2) h1(1) dclk (input) ddata(7-0) dpar dspe (input) dc1j1 (input) t pwh t h(1) t su(1) t od(2) data adata(7-0) (outputs) add (output) data data d ata fixed t h(2) t su(2) t od(1) stuff stuff c1(1) fixed stuff tug-3 tug-3 for j1 (inputs) apar t od(4) t od(3) - 37 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 17. sts-3 add/drop bus interface timing parameter symbol min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle, t pwh /t cyc -- 40 50 60 % ddata(7-0) data/dpar/dc1j1 set-up time to dclk t su(1) 7.0 ns ddata(7-0) data/dpar/dc1j1 hold time after dclk t h(1) 3.0 ns dspe set-up time to dclk t su(2) 10.0 ns dspe hold time after dclk t h(2) 5.0 ns adata(7-0) data and apar delay after dclk t od(1) 3.0 30 ns add indicator delayed after dclk t od(2) 3.0 25 ns adata(7-0) data and apar tri-state after dclk t od(3) 12 25 ns ad d indicator high after dclk t od(4) 12 25 ns note : the relationship between j1 and the spe signals is shown for illustration purposes only, and will be a function of the pointer offset. for the sts-3 format, there will be three j1 pulses with each j1 pulse indicating the start of an sts-1. the c1 pulse is shown dotted because the c1 pulse may be provided on the dc1 signal lead. if the dc1 signal lead is not used, it must be grounded. shown is sts-1 number 1 being added to the add bus. t cyc t h(1) t su(1) c1(1) j1 c1(2) c1(3) j1 fixed dclk (input) ddata(7-0) dpar dspe (input) dc1j1 (input) t pwh t h(1) t su(1) t od(2) data adata(7-0) (outputs) add (output) data data d ata fixed t h(2) t su(2) t od(1) c1(1) stuff stuff j1 data (inputs) apar t od(4) t od(3) - 38 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 18. sts-1 add/drop bus interface timing parameter symbol min typ max unit dclk clock period t cyc 154.32 ns dclk duty cycle, t pwh /t cyc -- 40 50 60 % ddata(7-0) data/dpar/dc1j1 set-up time to dclk t su(1) 7.0 ns ddata(7-0) data/dpar/dc1j1 hold time after dclk t h(1) 3.0 ns dspe set-up time to dclk t su(2) 10.0 ns dspe hold time after dclk t h(2) 5.0 ns adata(7-0) data and apar delay after dclk t od(1) 3.0 30 ns add indicator delayed after dclk t od(2) 3.0 25 ns adata(7-0) data and apar tri-state after dclk t od(3) 12 25 ns ad d indicator high after dclk t od(4) 12 25 ns note : the relationship between j1 and the spe signals is shown for illustration purposes only, and will be a function of the pointer offset. for the sts-1 format, there will be one j1 pulse which indicates the start of the sts-1. the c1 pulse is shown dotted because the c1 pulse may be provided on the dc1 signal lead. if the dc1 signal lead is not used, it must be grounded. t cyc t h(1) t su(1) c1(3) j1 j1 spe dclk (input) ddata(7-0) dpar dspe (input) dc1j1 (input) t pwh t h(1) t su(1) spe c1 j1 spe spe add (output) adata(7-0) (outputs) t od(1) t od(2) spe t h(2) t su(2) spe (inputs) apar t od(4) t od(3) - 39 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 19. transmit path overhead timing parameter symbol min typ max unit tpohc high time t pwh 617 3395 ns tpohc low time t pwl 771.7 ns tpohf output delay after tpohc t d -2.0 5.0 ns tpohd set-up time to tpohc t su 7.0 ns tpohd data hold time after tpohc t h 3.0 ns tpohf pulse width t pw 1388.9 ns tpohc tpohf t pwl t pwh (output) (output) tpohd (input) t su t h note: the clock cycle that corresponds to bit 8 in each overhead byte is stretched. bit 1 j1 t pw t d bit 2 j1 bit 3 j1 bit 4 j1 bit 5 j1 bit 6 j1 bit 7 j1 bit 8 j1 bit 1 b3 t pwh - 40 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 20. receive path overhead timing parameter symbol min typ max unit rpohc low time t pwl 617 3395 ns rpohc high time t pwh 771.7 ns rpohf output delay after rpohc t d(1) -2.0 5.0 ns rpohd output delay after rpohc t d(2) -2.0 5.0 ns rpohf pulse width t pw 1388.9 ns rpohc rpohf t pwl t pwh (output) (output) rpohd (output) t d(2) note: the clock cycle that corresponds to bit 8 in each overhead byte is stretched. t pw t d(1) bit 8 j1 bit 1 b3 bit 7 j1 bit 6 j1 bit 5 j1 bit 4 j1 bit 3 j1 bit 2 j1 bit 1 j1 bit 8 z5 t pwl - 41 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 21. transmit alarm indication port timing parameter symbol min typ max unit taipc low time t pwl 617 3395 ns taipc high time t pwh 771.7 ns taipf set-up time to taipc t su(1) 7.0 ns taipf hold time after taipc t h(1) 3.0 ns taipd set-up time to taipc t su(2) 7.0 ns taipd set-up time after taipc t h(2) 3.0 ns note : alarm indication byte consists of eight bits and is repeated nine times. bit 8 in each byte is stretched. the first four bits correspond to the febe count (bits 1 through 4 in g1), bit 5 is the path rdi value, and bits 6 and 7 are set to 0, while bit 8 is set to 1. ta i p c ta i p f t pwl t pwh (input) (input) ta i p d (input) t su(2) t h(2) bit 1 t h(1) t su(1) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 t pwl byte1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 - 42 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 22. receive alarm indication port timing figure 23. transmit overhead communications channel timing parameter symbol min typ max unit rpohc low time t pwl 617 3395 ns rpohc high time t pwh 771.7 ns rpohf output delay after rpohc t d(1) -2.0 5.0 ns raipd output delay after rpohc t d(2) -2.0 5.0 ns rpohf pulse width t pw 1388.9 ns parameter symbol min typ max unit tochc high time t pwh 617 11729 ns tochc low time t pwl 771.2 ns tochd set-up time to tochc t su 7.0 ns tochd hold time after tochc t h 3.0 ns note: alarm indication byte consists of eight bits and is repeated nine times. bit 8 in each byte is stretched. the first four bits correspond to the febe count (bits1 through 4 in g1), bit 5 is the path rdi value, and bits 6 and 7 are set to 0, while bit 8 is set to 1. rpohc rpohf t pwl t pwh (output) (output) raipd t d(2) t pw t d(1) t pwl bit 8 byte 1 bit 1 byte 2 bit 7 byte 1 bit 6 byte 1 bit 5 byte 1 bit 4 byte 1 bit 3 byte 1 bit 2 byte 1 bit 1 byte 1 bit 8 byte 9 (output) tochc tochd t pwl t pwh (output) (input) t su t h - 43 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 24. receive overhead communications channel interface timing parameter symbol min typ max unit rochc high time t pwh 617 11729 ns rochc low time t pwl 771.2 ns rochd output delay after rochc t d -2.0 5.0 ns rochc rochd t pwl t pwh (output) (output) t d - 44 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 25. intel microprocessor read cycle timing * note: rdy goes low when the address being read corresponds to a ram location but remains high during status or control register access. rcyc is the period, in nanoseconds, of the ram clock (ramci) (e.g., ramci @ 25mhz yields t pw(2) = 1.92 s max) parameter symbol min typ max unit a(7-0) address hold time after rd t h(1) 3.0 ns a(7-0) address set-up time to sel t su(1) 0.0 ns d(7-0) data valid delay after rdy t d(1) 7.0 ns d(7-0) data float time after rd t f(1) 6.0 ns rd pulse width t pw(1) 40.0 ns sel set-up time to rd t su(2) 10.0 ns se l hold time after rd t h(2) 0.0 ns rdy delay after sel t d(2) 10.0 ns rdy delay after rd t d(3) 16.0 ns rdy pulse width * t pw(2) 0.0 48 * rcyc s rdy float time after sel t f(2) 10.0 ns d(7-0) se l rd rdy t h(2) t f(1) t d(1) t pw(2) t d(3) t su(2) t su(1) t pw(1) t h(1) t f(2) a (7-0) t d(2) - 45 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 26. intel microprocessor write cycle timing * note: rdy goes low when the address being written to corresponds to a ram location but remains high dur- ing status or control register access. rcyc is the period, in nanoseconds, of the ram clock (ramci) (e.g., ramci @ 25mhz yields: t su(4) =-80ns min, t pw(2) = 1.92 s max) parameter symbol min typ max unit a(7-0) address hold time after wr t h(1) 3.0 ns a(7-0) address set-up time to sel t su(1) 0.0 ns d(7-0) data valid set-up time to wr t su(2) 8.0 ns d(7-0) data hold time after wr t h(2) 6.0 ns sel set-up time to wr t su(3) 10.0 ns wr pulse width t pw(1) 40.0 ns rdy delay after sel t d(1) 10.0 ns rdy delay after wr t d(2) 16.0 ns rdy pulse width * t pw(2) 0.0 48 * rcyc ns rdy float time after sel t f 10.0 ns ram cycle d(7-0) valid set-up time to wr t su(4) -2 * rcyc ns d(7-0) se l wr rdy t h(2) t su(1) t pw(2) t d(2) t su(3) t pw(1) t su(2) t h(1) a(7-0) t su(4) t d(1) t f - 46 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 27. motorola microprocessor read cycle timing note: rcyc is the period, in nanoseconds, of the ram clock (ramci) (e.g., ramci @ 25 mhz yields t pw(2) = 1.92 s max). parameter symbol min typ max unit a(7-0) address hold time after sel t h(1) 3.0 ns a(7-0) address valid set-up time to sel t su(1) 10.0 ns d(7-0) data valid delay after dtack t d(1) 5.0 ns d(7-0) data float time after sel t f(1) 6.0 ns sel pulse width t pw(1) 40.0 ns rd/wr set-up time to sel t su(2) 5.0 ns rd/w r hold time after sel t h(3) 3.0 ns dtack delay after sel t d(2) 16.0 ns dtack pulse width t pw(2) 0.0 48 * rcyc s dtack float time after sel t f(2) 10.0 ns d(7-0) se l rd / wr dtack t f(2) t f(1) t d(1) t pw(2) t su(2) t su(1) t pw(1) t d(2) t h(1) t h(3) a(7-0) - 47 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 28. motorola microprocessor write cycle timing note: rcyc is the period, in nanoseconds, of the ram clock (ramci) (e.g., ramci @ 25mhz yields: t su(4) =-80ns min, t pw(2) = 1.92 s max). parameter symbol min typ max unit a(7-0) address hold time after sel t h(1) 3.0 ns a(7-0) address valid set-up time to sel t su(1) 10.0 ns d(7-0) data valid set-up time to sel t su(2) 8.0 ns d(7-0) data hold time after sel t h(2) 6.0 ns sel pulse width t pw(1) 40.0 ns rd/wr set-up time to sel t su(3) 5.0 ns rd/w r hold time after sel t h(3) 3.0 ns dtack delay after sel t d 15.0 ns dtack pulse width t pw(2) 0.0 48 * rcyc ns dtack float time after sel t f 10.0 ns ram cycle d(7-0) valid set-up time to sel t su(4) -2 * rcyc ns d(7-0) se l rd / wr t f t pw(2) t su(1) t su(3) dtack t su(2) t h(2) t pw(1) t d t h(1) t h(3) a(7-0) t su(4) - 48 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 29. boundary scan timing parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time to tck t su(1) 3.0 - ns tms hold time after tck t h(1) 2.0 - ns tdi setup time to tck t su(2) 3.0 - ns tdi hold time after tck t h(2) 2.0 - ns tdo output delay after tck t d -7.0ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl - 49 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet operation l3m power-up reset sequence the l3m requires that the clocks are valid and stable for a minimum of 200 nanoseconds in order for a reset to take effect (refer to hardware reset function, reset , lead 86 or k14). the sequence shown in figure 30 is recommended on l3m power-up: 1. when a system reset is initiated, the l3m input leads reset and tri are set low at the same time. 2. the l3m reset lead is held low for a minimum of 200 nanoseconds after the system reset has been com- pleted and all of the l3m clocks have become stable. 3. the l3m tri lead then remains low to hold the l3m outputs with tri-state capability in the tri-state condi- tion until the tug-3 position in register c0h has been programmed. 4. once the l3m is programmed for the assigned tug-3 in register c0h, the tri lead is set high and the l3m will lock to the c1 pulse and map data to and from the positions selected by the dposn and aposn settings. figure 30. l3m power-up reset sequence for application circuit boards that require the capability for hot insertion, a suitable circuit must be included to ensure that the l3m reset and tri input leads are forced low until the l3m power supply leads have all reached the normal operating voltage range. it is important to remember that, when reading the latched registers in the l3m, the contents should be read a second time before determining the current status. system reset sys reset l3m reset l3m tri 200 ns (min.) l3m configuration reg. c0h should be programmed during this time. - 50 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 31. physical design for analog power distribution separate power islands should be used for apwr and apwr2, as shown in figure 31. traces should be kept as short as possible when connecting the emi filter to the analog power planes. place the 0.01 microfarad decoupling capacitors as close as possible to the associated device lead and on the same board side as the l3m. place the 10 microfarad capacitors close to the emi filters. leads 1, 36, 37, 72, 73, 108, 109 and 144 are shown for reference only, they are not connected to the apwr or apwr2 power islands. similar design considerations apply to the pbga package. ? l3m pqfp top view ? ? ? + 5v emi 25-120 mhz digi-key part no. p9809 digi-key part no. p9809 emi 25-120 mhz 110 14 18 36 37 72 73 98 101 108 109 144 apwr2 leads 18,98 ? ? apwr leads 10,14,101 0.01 f 10 f ? ? 10 f 0.01 f 0.01 f + 5v ? (3 places) note: the 10 f capacitors may be polarized types. - 51 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet pll filter connection to vcxo the desynchronize block in the receive line side path contains a phase-locked loop (pll) circuit, which must be connected to an external voltage-controlled crystal oscillator (vcxo) via an external filter. this arrangement is designed to meet limits for jitter on the asynchronous line output signal, which is due to signal mapping and pointer movements. figure 32 shows the external filter circuit that is recommended for connecting the l3m pll circuit to the vcxo. figure 33 shows the jitter results obtained with the circuit shown in figure 32. figure 32. pll connection to external vcxo notes: 1. the vcxo pll filter design is a 2-pole integrator that is designed to supply reliable jitter performance and cap- ture range with good margins for implementation in high volume production applications. due to the characteris- tics of the filter network the signal at ampout will go to a rail in the absence of a ds3/e3 signal in the sonet/ sdh payload. in systems that experience extended loss of signal in the tug-3/sts payload, this characteristic can cause long capture times, which can exceed 30 seconds. 2. this filter arrangement can be used for tug-3/ds3, tug-3/e3, sts-1/ds3 and sts-3/sts-1/ds3 mapping modes. it provides a bandwidth of 0.3 hz for ds3 and 0.23 hz for e3. 3. all resistance ( ? ) and capacitance ( f) values must be within 5% and 10%, respectively, of the values shown to meet the requirements of figure 33. two components in series or parallel may be used, where needed. 4. all capacitors must be high quality, non-polarized ceramic types. 5. termination resistor r4 must be chosen to suit the physical design adopted (e.g., 75 or 50 ohms). 6. inverter u1 is a signetics 74hct04 or equivalent. 7. vcxo x1 is a fordahl dfv 14-mhr 44.736 mhz v14112 or dfv 14-khr 34.368 mhz v14111 or equivalent, depending on the application signal rate. 8. setting the div4 bit (bit 4 in register c7) controls the gain of the phase detector. this bit must be set to 1. 9. setting the invctrl bit (bit 3 in register c7) controls the polarity of the ctrl signal on lead 3 or d3. this bit must be set to 0 for the circuit shown, which provides the results tabulated in figure 33. control bit invctrl allows the use of an external ciruit that does not include the inverter u1, if invctrl is set to 1. 10. please contact the transwitch applications engineering department if questions arise concerning the pll filter design and characteristics. l3m device txc-03452b x1 vcxo (see note 7) 1k r4 (see note 5) termination c1 0.1 gnd 13, g2 xosci 3, d2 - + internal op amp c3 3.2 c2 0.01 r1 806k r2 3m ampinn 5, d4 u1 ctrl 3, d3 ampout 7, e1 inverter (see notes 6, 9) ampinp 6, e2 r3 - 52 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 33. jitter results for sts-3/ds3 and tug-3/e3 mappings l3m jitter results for sts-3/ds3 mapping bellcore, gr-253-core, rev. 2, jan 1999 maximum measured jitter (ui p-p) maximum jitter specified by gr-253-core (ui p-p) mapping jitter 0.16 0.4 single pointer adjustment 0.12 a0 + 0.3 pointer adjustment burst 0.38 1.3 phase transient pointer adjustment burst 0.19 1.2 periodic pointer adjustments without added or canceled pointer adjustments 0.47 (t = 34 ms) 1.0 0.13 (t = 10 s) periodic pointer adjustments with added or canceled pointer adjustments 0.54 (t = 34 ms) 1.3 0.16 (t = 10 s) periodic pointer adjustments continuous pattern 0.08 (t = 34 ms) 1.0 0.14 (t = 10 s) periodic pointer adjustments continuous pattern with added or canceled pointer adjustment 0.17 (t = 34 ms) 1.3 0.24 (t = 10 s) l3m jitter results for tug-3/e3 mapping pa sequence specified by etsi document ets-de/tm-1015-1:nov-93 maximum measured jitter (ui p-p) maximum allowed jitter (ui p-p) specified by ets-de/tm-1015-1:nov-93 hp1/lp hp2/lp hp1/lp hp2/lp a 0.021 0.012 0.075 b 0.024 0.016 0.4 0.75 c 0.028 0.016 0.75 0.75 d 0.026 0.016 0.4 0.75 e 0.026 0.016 0.4 0.75 - 53 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet testing loopbacks three loopback capabilities are provided: facility, line and sdh/sonet. diagrams illustrating the three types of loopback are provided in the memory map descriptions section, address c1, bits 2-0. writing a 1 to control bit flbk enables facility loopback. facility loopback and line loopback operations are shown in figure 34. when facility loopback is enabled, the internal ds3/e3 transmit signal becomes the inter- nal receive signal. either interface may be used, p/n rail or nrz. line loopback is enabled by writing a 1 to control bit l3lbk. the ds3/e3 receive output becomes the transmit line input. the receive output may be p/n rail or nrz. writing a 1 to control bit slbk enables a sdh/sonet loopback. sdh/sonet loopback disables the stm-1/ sts-3/sts-1 signal input on the drop bus, and enables the add signals to become the drop bus signals. the add signals are provided at the add bus. test generators and analyzers two pseudo-random binary sequence (prbs) test generators are provided, as shown in figure 34. each gen- erator can provide a 2 15 -1 or 2 23 -1 pseudo-random pattern. the test sequence of 2 23 -1 is selected when a 1 is written into control bit pat23. when pat23 is 0, the pattern is 2 15 -1. the transmit test generator is enabled by writing a 1 to control bit tprbs. when enabled, the transmit test generator transmits the pseudo-random pattern in place of transmit nrz data. the transmit test generator must have a clock signal provided at the transmit line clock (tclk) input lead in order to generate a test pat- tern. for applications where no transmit line clock is present and the system is required to generate a transmit prbs signal, a loss of clock detection circuit and a circuit to multiplex the transmit line clock and the aisclk should be used externally to maintain a valid clock, as shown in figure 35. the receive test generator is enabled by writing a 1 to control bit rprbs. when enabled, the receive test gen- erator inserts the pseudo-random test pattern in place of the received desynchronized nrz data. the test analyzer is enabled by writing a 1 to control bit enana. the test sequence of 2 23 -1 is selected when a 1 is written into control bit pat23. receive nrz data is analyzed when a 0 is written to control bit txana. when a 1 is written to control bit txana, the transmit nrz data path is monitored. the selection of the test analyzer disables the decoder cv output to the 16-bit counter. the 16-bit counter now counts received errors from the test analyzer, when the analyzer is in lock. - 54 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 34. loopbacks, test generator & analyzers figure 35. external circuit to maintain clock input to tx prbs generator los det tx prbs generator hdb3/ b3zs decoder counter hdb3/ b3zs coder prbs analyzer rx prbs generator line in (tx ds3/e3) 0 1 l3lbk enana flbk rprbs line out (rx ds3/e3) 0 1 cvs errors 1 0 txana 1 0 tprbs 0 1 from desynchronizer 0 1 to facility loopback line loopback tclk raisgn 1 0 ais generator 1 0 tlaisgn ais generator aisclk synchronizer tx prbs generator l3m aisclk tclk detect tclk tclk input lead - 55 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet boundary scan introduction the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. as shown in figure 36, one cell of a bound- ary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). the boundary scan capability is based on a test access port (tap) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. the boundary scan test bus interface consists of four input signals (test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs )) and a test data output (tdo) output signal. boundary scan signal timing is shown in figure 29. the tap controller receives external control information via a test clock (tck) signal and a test mode select (tms) signal, and sends control signals to the internal scan paths. the tap controller is reset by asserting the trs lead low for a minimum of 5 nanoseconds. detailed information on the operation of this state machine can be found in the ieee 1149.1 standard. the serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. these three serial registers are connected in parallel between the test data input (tdi) and test data output (tdo) signals, as shown in figure 36. the boundary scan function will be reset and disabled by holding lead trs low. when boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the l3m device ? s internal logic. during boundary scan testing, the boundary scan register may dis- able the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. boundary scan operation the maximum frequency the l3m device will support for boundary scan is 10 mhz. the timing diagrams for the boundary scan interface leads are shown in figure 29. the instruction register contains three bits. the l3m device performs the following three boundary scan test instructions: the extest test instruction (000) provides the ability to test the connectivity of the l3m device to external cir- cuitry. the sample test instruction (010) provides the ability to examine the boundary scan register contents without interfering with device operation. the bypass test instruction (111) provides the ability to bypass the l3m boundary scan and instruction regis- ters. during the capture - ir state, a fixed value (101) is loaded into the instruction register. - 56 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 36. boundary scan schematic tap controller bypass register instruction register tdi tdo in out controls boundary scan serial test data core logic of l3m boundary scan register 3 device signal input and output leads (solder balls on bottom surface of pbga package) - 57 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet boundary scan chain there are 104 scan cells in the l3m boundary scan chain. bidirectional signals require two scan cells. addi- tional scan cells are used for direction control as needed. a boundary scan description language (bsdl) source file for each package type is available via the products page of the transwitch world wide web site (www.transwitch.com). the following table shows the listed order of the scan cells and their function. scan cell no. input/output pqfp (pbga) lead no. symbol comments 103 input 107 (d16) tri see note 1 (at end of table). 102 --- --- (l3 out ctrl) when low, leads 92 (h13), 93 (h14), 142 (b3), 143 (a2) and 144 (a1) are set to a high impedance state. see note 1. 101 input 109 (c14) tpos 100 input 110 (a15) tneg 99 input 111 (a14) tclk 98 input 113 (a13) a0 97 input 114 (d13) a1 96 input 115 (b12) a2 95 input 116 (c12) a3 94 input 117 (d12) a4 93 input 118 (b11) a5 92 input 119 (c11) a6 91 input 120 (d11) a7 90 input 122 (a10) wr 89 input 123 (c10) rd or rd/wr 88 --- --- (rdy ctrl) when low, lead 128 (c8) is set to a high impedance state. see note 1. 87 input 124 (d10) sel 86 output (3-state) 128 (c8) rdy/dtack 85 output (3-state) 129 (b8) int/irq 84 --- --- ( p d(7-0) ctrl) when low, leads 133 thru 140 (c4, b5, a5, c5, b6, a6, c6 and d6) are set to a high impedance state. see note 1. 83 input 130 (c7) ramci 82 --- --- (int/irq ctrl) when low, lead 129 (b8) is set to a high impedance state. see note 1. - 58 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet 81 input 131 (b7) moto 80 output (3-state) 133 (d6) d0 (out) 79 input 133 (d6) d0 (in) 78 output (3-state) 134 (c6) d1 (out) 77 input 134 (c6) d1 (in) 76 output (3-state) 135 (a6) d2 (out) 75 input 135 (a6) d2 (in) 74 output (3-state) 136 (b6) d3 (out) 73 input 136 (b6) d3 (in) 72 output (3-state) 137 (c5) d4 (out) 71 input 137 (c5) d4 (in) 70 output (3-state) 138 (a5) d5 (out) 69 input 138 (a5) d5 (in) 68 output (3-state) 139 (b5) d6 (out) 67 input 139 (b5) d6 (in) 66 output (3-state) 140 (c4) d7 (out) 65 input 140 (c4) d7 (in) 64 output (3-state) 143 (a2) rpos 63 output (3-state) 144 (a1) rneg 62 input 1 (c2) aisclk 61 input 2 (d2) xosci 60 output (2-state) 3 (d3) ctrl 59 output (2-state) 8 (e3) nc not used 58 output (2-state) 11 (f3) fifoerr 57 output (2-state) 21 (j2) nc not used 56 output (2-state) 22 (k4) nc not used 55 output (2-state) 25 (l4) rochd 54 output (2-state) 26 (l3) rochc 53 output (2-state) 28 (l2) raipd 52 output (2-state) 30 (m3) rpohd scan cell no. input/output pqfp (pbga) lead no. symbol comments - 59 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet 51 output (2-state) 31 (m1) rpohf 50 output (2-state) 32 (m2) rpohc 49 output (2-state) 35 (n2) nc not used 48 output (2-state) 36 (p1) nc not used 47 input 40 (r4) ddata7 46 input 41 (t4) ddata6 45 input 42 (n4) ddata5 44 input 43 (t5) ddata4 43 input 44 (p5) ddata3 42 input 45 (r6) ddata2 41 input 46 (t6) ddata1 40 input 47 (n6) ddata0 39 input 49 (r7) dc1 38 input 50 (t7) dpar 37 input 51 (p7) dclk 36 input 52 (n7) dc1j1 35 input 53 (r8) dspe 34 output (3-state) 57 (t9) apar 33 output (3-state) 58 (r9) aspe 32 input 58 (r9) aspe 31 output (3-state) 59 (n10) ac1j1 30 input 59 (n10) ac1j1 29 output (2-state) 60 (t10) add 28 output (3-state) 61 (r10) aclk 27 input 61 (r10) aclk 26 output (3-state) 63 (n11) adata7 25 output (3-state) 64 (t11) adata6 24 output (3-state) 65 (r11) adata5 23 output (3-state) 66 (p12) adata4 22 output (3-state) 67 (t12) adata3 scan cell no. input/output pqfp (pbga) lead no. symbol comments - 60 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet note 1: all outputs are disabled when the high impedance enable input (tri , lead 107 (d16)) is low, except during extest, when the direction control scan cells (numbers 16 (h2), 18 (j4), 82 (l14), 84 (k15), 88 (j15), 102 (e13) and 103 (e14)) take precedence. 21 output (3-state) 68 (p13) adata2 20 output (3-state) 69 (r13) adata1 19 output (3-state) 70 (t14) adata0 18 --- --- (apar, adata(7-0) ctrl) when low, leads 57 (t9), 63 thru 70 (n11, t11, r11, p12, t12, p13, r13 and t14) are set to a high impedance state. see note 1. 17 input 75 (n13) xclki 16 --- --- (spe ctrl) when low, leads 58 (r9), 59 (n10), and 61 (r10) are set to a high impedance state. see note 1. 15 input 76 (m15) xc1 14 input 77 (m16) xclke 13 output (2-state) 79 (m13) tpohc 12 output (2-state) 80 (l15) tpohf 11 input 81 (l16) tpohd 10 input 83 (l13) taipc 9 input 84 (k15) taipf 8 input 85 (k16) taipd 7 input 86 (k14) reset 6 output (2-state) 90 (j14) tochc 5 input 91 (j13) tochd 4 output (3-state) 92 (h13) rnrzd 3 output (3-state) 93 (h14) rnrzc 2 input 94 (h16) stai 1 input 95 (h15) pais 0 input 96 (g13) istat scan cell no. input/output pqfp (pbga) lead no. symbol comments - 61 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet memory map please note that all control registers (c0h to cah) and the fifo leak rate register (a0h) must be initialized to 00h value unless otherwise specified below or required by the application. control bits status bits *r/w: read/write; r: read only; r/w(l): read/write - latched register. **even addresses contain unlatched status bits. odd addresses contain latched status bits. interrupt mask bits address (hex) mode* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0 r/w tug3 sts3 dpos1 dpos0 apos1 apos0 test ds3 c1 r/w decode code invci invco ring flbk l3lbk slbk c2 r/w alm2ais alm2fb9 tlaisgn tpaisgn tpais00 intz addz l3z c3 r/w exz5 exz4 exz3 exh4 exf2 exg1 exc2 exj1 c4 r/w exoo febe9en ramrdi febeen xalm2ais test tloc2ais tlos2ais c5 r/w cor test dropt poh2ram raisgn raisen wgdec psl2ais c6 r/w fastptr tohout h4ctr pat23 enana txana tprbs rprbs c7 r/w testb3 fixptr test div4 invctrl txrst rxrst resetc c8 r/w c2 compare c9 r/w test rdi5 febeblk ca r/w test nopoh test address (hex)** mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b0 r dloc dloj1 buserr e1ais lop pais pslerr c2eq0 b1 r/w(l) dloc dloj1 buserr e1ais lop pais pslerr c2eq0 b2 r rdi l3los l3loc tovfl l3ais ramloc aloc aloj1 b3 r/w(l) rdi l3los l3loc tovfl l3ais ramloc aloc aloj1 b4 r sint febe9 new tug3new rovfl xstai xistat xpais b5 r/w(l) reserved febe9 new tug3new rovfl xstai xistat xpais b6 r l3err lovfl rfrst tfrst vcxoloc tploc rploc ool b7 r/w(l) l3err lovfl rfrst tfrst vcxoloc tploc rploc ool address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ba r/w dloc dloj1 buserr e1ais lop pais pslerr c2eq0 bb r/w rdi l3los l3loc tovfl l3ais ramloc aloc aloj1 bc r/w hint febe9 new tug3new rovfl xstai xistat xpais bd r/w l3err lovfl rfrst tfrst vcxoloc tploc rploc ool - 62 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet transmit poh bytes & ? o ? -bits receive poh bytes, tug-3 h1/h2 bytes & ? o ? -bits performance counters & fifo leak rate device identification the device identification (id) is based on the manufacturer identity, part-number and version codes described in ieee standard 1149.1 on boundary scan, using the manufacturer code assigned by the joint electron device engineering council (jedec). the serial format for this id is shown below: the device identification is not currently provided as a boundary scan message. however, the manufacturer identity and part-number are implemented with read-only capability for microprocessor read access. the man- ufacturer identity for transwitch devices is 107 (06b hex.). the part-number of the l3m device is 03452 (0d7c hex.). in addition, the read-only segment is expanded to include a 4-bit mask level field and a 4-bit future growth field, as shown below: j1 b3 error mask and test c2 g1 f2 h4 z3 (f3) z4 (k3) z5 (n1) not used ? o ? -bits 00-3f 40 41424344 45 46 47 48 49 bits 1-0 j1 b3 c2 g1 f2 h4 z3 (f3) z4 (k3) z5 (n1) h1 h2 ? o ? -bits 50-8f 90 91929394 95 96 97 9899 9a bits 1-0 rcv frame count not used fifo leak rate inc count dec count ndf count tug-3 inc count tug-3 dec count a0 a1 a2 a3 a4 a5 a6 a7 tug-3 new data flag count b3 block error count febe count b3 error count line cv/prbs error count common high byte (febe, b3, cvs) a8 a9 aa ac ae ff msb lsb version (tbd) part-number 0000 1101 0111 1100 manufacturer identity 000 0110 1011 fixed bit 1 4 bits 16 bits 11 bits 1 bit address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f4 r mask level - content tbd growth - content tbd f3 r revision (version) level - content tbd pn15=0 pn14=0 pn13=0 pn12=0 f2 r pn11=1 pn10=1 pn9=0 pn8=1 pn7=0 pn6=1 pn5=1 pn4=1 f1 r pn3=1 pn2=1 pn1=0 pn0=0 mi10=0 mi9=0 mi8=0 mi7=0 f0 r mi6=1 mi5=1 mi4=0 mi3=1 mi2=0 mi1=1 mi0=1 1 - 63 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet memory map descriptions control bits on power-up, the control bits will not be automatically initialized to a fixed default pattern. the microprocessor must write the control bits to the required system status. the control bits are not affected by either hardware or software resets. address bit symbol description c0 7, 6 tug3, sts3 bus format control bits: determine the bus format according to the table given below: tug3 sts3 mapping 00sts-1 01sts-3 10future use 11tug-3 5, 4 dpos1,0 drop positions 1 and 0: determine the locations of the tug-3s and au-3/sts-1 spes dropped from the stm-1/sts-3 according to the table given below: d pos1 dpos0 mapping 0 0 tug-3 position a (or sts-1 #1) 0 1 tug-3 position b (or sts-1 #2) 1 0 tug-3 position c (or sts-1 #3) 1 1 idle state. rx front end held in reset. 3, 2 apos1,0 add positions 1 and 0: determine the locations of the tug-3s and au-3/sts-1 spes to be added to the stm-1/sts-3 according to the table given below: a pos1 apos0 mapping 0 0 tug-3 position a (or sts-1 #1) 0 1 tug-3 position b (or sts-1 #2) 1 0 tug-3 position c (or sts-1 #3) 1 1 undefined 1test test : a 0 must be written into this location. 0ds3 ds3 mode: determines the mapping mode according to the table given below: d s3 mapping mode 0 e3 (34.368 mbit/s) 1 ds3 (44.736 mbit/s) c1 7 decode transmit decoder enabled: a 1 enables the transmit hdb3/ b3zs decoder (for rail operation). a 0 disables the decoder (for nrz operation). 6code receive coder enabled: a 1 enables the receive hdb3/b3zs coder (for rail operation). a 0 disables the coder (for nrz operation). 5invci invert transmit line clock input: when set to 0, the ds3 or e3 line sig- nals are clocked into the l3m device on positive transitions of the clock (tclk). a 1 enables the line signal to be clocked out of the l3m device on negative transitions of the clock. - 64 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c1 (cont.) 4invco invert receive line clock output: when set to 0, the ds3 or e3 line sig- nals are clocked out of the l3m device on negative transitions of the clock (rclk). a 1 enables the line signal to be clocked out on positive transitions of the clock. 3ring ring operating mode: a 1 enables the external alarm interface febe count and rdi alarm indication from another l3m device to be transmitted in the g1 byte. the outgoing g1 byte comes from the poh port if the external poh g1 byte is selected. the alarm conditions at the other l3m device that may cause rdi are shown below. the + symbol represents an or function, while & represents an and function. control bit states are given by the = sign. 2flbk facility loopback: a 1 enables the transmit line data and clock signals to be looped back as the receive line data and clock signals. 1l3lbk line e3/ds3 loopback: a 1 enables the receive line signal to be looped back as the transmit line signal. the receive data and clock are provided at the receive line interface. address bit symbol description & + lop (tug-3) pais (tug-3) tug3=1 dloj1 (alarm) e1ais (alarm) xalm2ais=0 istat lead high pais lead high xalm2ais=1 pslerr (alarm) c2eq0 (alarm) psl2ais=1 & + + send rdi & & + tx rx ds3/e3 a d sdh/sonet l3m facility loopback bus tx ds3/e3 a d sdh/sonet l3m line loopback rx bus - 65 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c1 (cont.) 0slbk sdh/sonet loopback: a 1 enables the add sdh/sonet signal to be looped back as the drop signal. the drop signals from the bus are dis- abled. add data and clock are provided at the bus interface. c2 7 alm2ais external alarm enable ais: a 1 enables an ais detected in an e1 byte (when control bit xalm2ais = 0) or a high on either the istat or pais leads (when control bit xalm2ais = 1) to generate a line ais in the receive direction when control bit raisen is a 1. see logic diagram for address c5, bit 2. 6alm2fb9 external alarm enable febe9: a 1 enables an ais detected in an e1 byte (when control bit xalm2ais = 0) or a high on either the istat or pais leads (when control bit xalm2ais = 1) to generate a count of 9 in bits 1 through 4 of the transmitted g1 byte when control bit febe9en is a 1. see logic diagram for address c4, bit 6. 5tlaisgn transmit line ais: a 1 written into this position generates and transmits a ds3 or e3 ais towards the sdh/sonet bus, independent of the state of control bit flbk (bit 2 in register c1h). see note 1 below. 4tpaisgn transmit zeros or path ais enable: a 1 enables the l3m device to trans- mit an spe with zeros (and valid pointer) or a tug-3 path ais towards the sdh/sonet bus, depending on the state of tpais00. the logic diagram for sending path ais is given below. the + symbol rep- resents an or function, while & represents an and function. control bit states are given by the = sign. unequip is sent instead if tpais00 = 1. 3tpais00 transmit spe with zeros: when enabled by writing a 1 to control bit tpaisgn, a 1 written into this location causes the spe (poh bytes and payload) to be transmitted with zeros, but with a valid pointer. a 0 causes a tug-3 ais to be transmitted towards the sdh/sonet bus. note 1: ds3 ais is defined as a valid m-frame with proper subframe structure. the data payload is a 1010... sequence starting with a 1 after each overhead bit. overhead bits are as follows: f0=0, f1=1, m0=0, m1=1; c-bits are set to 0; x-bits are set to 1; and p-bits are set for valid parity. e3 ais is an all ones pattern. address bit symbol description tx rx ds3/e3 d sdh/sonet l3m sdh/sonet loopback a bus tug3=1 tpaisgn=1 tpais00=0 send tug-3 path ais & tug3=1 tpaisgn=1 tpais00=1 send unequip & - 66 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c2 (cont.) 2intz interrupt high impedance enable : a 0 enables the interrupt int/irq (lead 129 or b8) to be either high (intel mode) with the off state low, or to be low (motorola mode), with the off state high. a 1 enables the off state to be high impedance. 1addz add bus high impedance enable: a 1 sets add bus data (adata(7-0)) and add parity (apar) leads to a high impedance state, and add high. if the external timing mode is selected, the clock (aclk), spe (aspe), and c1j1 (ac1j1) signals are also forced to a high impedance state. 0l3z receive output high impedance enable: a 1 forces the receive inter- face clock (rclk) and data signals (rpos and rneg), and nrz outputs (rnrzc and rnrzd) to a high impedance state. c3 7 exz5 transmit external interface z5 byte: a 1 enables the z5 byte from the poh i/o to be transmitted. a 0 enables the corresponding ram location to be transmitted. 6exz4 transmit external interface z4 byte: a 1 enables the z4 byte from the poh i/o to be transmitted. a 0 enables the corresponding ram location to be transmitted. 5exz3 transmit external interface z3 byte: a 1 enables the z3 byte from the poh i/o to be transmitted. a 0 enables the corresponding ram location to be transmitted. 4exh4 transmit external interface h4 byte: a 1 enables the h4 byte from the poh i/o to be transmitted. a 0 enables the corresponding ram location to be transmitted. 3exf2 transmit external interface f2 byte: a 1 enables the f2 byte from the poh i/o to be transmitted. a 0 enables the corresponding ram location to be transmitted. 2exg1 transmit external interface g1 byte: a 1 enables bits 1 through 8 in the g1 byte from the poh i/o to be transmitted. a 0 enables the correspond- ing ram location or internal logic/alarms to control the transmitted state of febe, rdi, and the unassigned bits. 1exc2 transmit external interface c2 byte: a 1 enables the c2 byte from the poh i/o to be transmitted. a 0 enables the corresponding ram location to be transmitted. 0 exj1 transmit external interface j1 bytes: a 1 enables the j1 bytes from the poh i/o to be transmitted. a 0 enables the corresponding ram segment (64 locations) to be transmitted. address bit symbol description - 67 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c4 7 exoo external ? o ? -bit select: a 1 selects the two overhead communication bits ( ? o ? -bits) from the external interface (lead tochd) as the two ? o ? -bits transmitted in each of the nine subframes of the ds3 format or each of the three subframes of the e3 format. a 0 enables the two ? o ? -bits from the corresponding ram location to be transmitted (to2, to1 at address 49h). 6 febe9en febe9 enable: enable bit for generating a febe count of 9 (this is a pro- prietary non-standard feature and lead febe9en should be disabled for standard compliance by holding it low). when exg1 is a 0 and febe9en is high, a febe count of 9 is generated when: - either the istat or pais input lead is high, and the external alarm enable control bit xalm2ais is a 1 and alm2fb9 is 1; - an ais is detected in the e1 byte, and xalm2ais is 0 and alm2fb9 is 1; - either the tug-3 pais or lop alarms occur; - the stai lead is high. the logic diagram for sending febe9 is given below. the + symbol repre- sents an or function, while & represents an and function. control bit states are given by the = sign. address bit symbol description lop (tug-3) pais (tug-3) tug3=1 stai lead high febe9en lead high e1ais (alarm) xalm2ais=0 istat lead high pais lead high xalm2ais=1 alm2fb9=1 send febe9 & & + exg1=0 & + & + & + (count of 9 in bits 1-4 of g1) - 68 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c4 (cont.) 5ramrdi remote defect indication (yellow alarm) enabled: enable bit for con- trolling the generation of path rdi (bit 5 in g1 byte). when control bits ring and exg1 are 0, and ramrdi is a 0, rdi is generated when the fol- lowing alarms or conditions occur: - drop bus loss of j1 (dloj1) - drop bus loss of clock (dloc) - loss of pointer (lop) (tug-3 operation) - path ais detected (pais) (tug-3 operation) - received e1 byte has a majority of 1s and control bit xalm2ais is 0 - either the istat or pais input lead is high and control bit xalm2ais is a 1 - pslerr or c2eq0 alarm, and control bit psl2ais is a 1 when control bit ring is a 1, exg1 is a 0, and ramrdi is a 0, the rdi state is controlled via the external alarm indication port. the microprocessor controls the rdi state when ramrdi is a 1 and exg1 is a 0. note: writing a 1 to the ramrdi bit will disable the local alarms and the alarm indication port rdi in the ring mode from controlling the state of the transmitted rdi bit. the logic diagram for sending path rdi is given below. the + symbol rep- resents an or function, while & represents an and function. control bit states are given by the = sign. address bit symbol description lop (tug-3) pais (tug-3) tug3=1 remote alm i/o ring=1 e1ais (alarm) xalm2ais=0 istat lead high pais lead high xalm2ais=1 dloj1 (alarm) send path & & + bit 5 of g1 from port & + & + & & rdi/ferf/ exg1=1 ring=0 pslerr (alarm) c2eq0 (alarm) psl2ais=1 dloc (alarm) ramrdi=0 ramrdi=1 ram rdi value exg1=0 & + & + & + & + yellow 5 in g1 byte) alarm (bit - 69 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c4 (cont.) 4 febeen febe enable: a 1 enables the local b3 count or remote b3 count to be inserted as the febe count. a 0 written into this position permits the microprocessor to control the febe count. the logic diagram for sending febe for all conditions is given below. the + symbol represents an or function, while & represents an and function. control bit states are given by the = sign. 3 xalm2ais external alarm ais lead enable: a 1 enables the external alarm leads (istat and pais) to affect alarm generation instead of ais in the e1 byte. a 0 causes alarm generation to be based on e1ais from the drop bus. 2test transwitch test mode : a 0 must be written into this location. 1tloc2ais transmit loss of clock (tlck) ais enable: a 1 enables the l3m device to send sonet/sdh ds3 ais or e3 ais automatically when a transmit line clock failure is detected. the logic diagram for transmitting a line ais is given below. the + symbol represents an or function, while & represents an and function. control bit states are given by the = sign. 0 tlos2ais transmit loss of signal (tpos/tneg) ais enable: a 1 enables the l3m device to send ds3 or e3 ais automatically when a transmit line sig- nal failure is detected. address bit symbol description febeen=1 send febe9=0 (internal) febeen=0 ram febe count send febe & exg1=1 & + count port g1 febe value & rx b3 count ring=0 remote alm febe count ring=1 exg1=0 & + & + & send ds3 or e3 ais & l3loc (alarm) tloc2ais=1 l3los (alarm) tlos2ais=1 tlaisgn=1 + & - 70 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c5 7 cor clear on read: a 0 enables all performance counters to become non- saturating with roll over capability. the contents of the counter are not affected by a read cycle. a 1 causes the performance counters to become saturating counters, which clear on read. 6test test: a 1 must be written into this location. 5dropt drop bus timing: drop timing can only be selected when the l3m lead xclke is low. a 1 selects drop bus timing for the add bus. a 0 selects tim- ing signals from the add bus. 4poh2ram path overhead bytes to ram: works in conjunction with the exbn con- trol bits (e.g., exf2). the following table summarizes the action taken by this bit and an exbn bit: 3 raisgn generate receive line ais: a 1 written into this position generates a ds3/e3 ais towards the line (rpos, rneg) independent of the state of the receive ais enable bit (raisen). see note below. note: ds3 ais is defined as a valid m-frame with proper subframe structure. the data payload is a 1010... sequence starting with a 1 after each overhead bit. overhead bits are as follows: f0=0, f1=1, m0=0, m1=1; c-bits are set to 0; x-bits are set to 1; and p-bits are set for valid parity. e3 ais is an all ones pattern. address bit symbol description poh2ram exbn (e.g., exf2) action 11 poh bn interface byte transmit- ted and written to ram location. 01 poh bn interface byte transmit- ted, ram location holds micro- processor-written value. x0 poh bn value written to ram location by the microprocessor is transmitted. - 71 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c5 (cont.) 2raisen receive ais enable: a 1 enables receive ais to be generated when the following alarms/conditions occur: - loss of drop bus clock (dloc) - loss of drop bus j1 (dloj1) - e1 ais (e1ais) and xalm2ais are 0, and alm2ais is a 1 - istat or pais (lead) and xalm2ais are 1, and alm2ais is a 1 - loss of pointer (lop) (tug-3) - path ais (pais) (tug-3) - pslerr or c2eq0 occurs, and path signal label error enable ais control bit (psl2ais) is a 1 the logic diagram for generating receive line ais is given below. the + symbol represents an or function, while & represents an and function. control bit states are given by the = sign. address bit symbol description lop (tug-3) pais (tug-3) tug3=1 raisen=1 e1ais (alarm) xalm2ais=0 istat lead high pais lead high xalm2ais=1 dloj1 (alarm) send receive ais & + alm2ais=1 & + raisgn=1 pslerr (alarm) c2eq0 (alarm) psl2ais=1 dloc (alarm) & + & + & + & + - 72 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c5 (cont.) 1wgdec test equipment bpv selection: a 1 enables the decoder to detect cod- ing violations as found in ? type 1 ? test equipment. a 0 enables the decoder to detect coding violations as found in ? ty p e 0 ? test equipment. the follow- ing tables summarize the two decoding procedures of coding violations: 0psl2ais path signal label error enable ais: a 1 enables the l3m device to send ds3 or e3 ais automatically towards the receive line, and path rdi (ferf) when a pslerr or c2eq0 alarm occurs. (see ramrdi and raisen for diagrams.) c6 7 fastptr fast pointer enabled: a 1 allows the l3m device to track pointer move- ments every frame instead of every other frame for tug-3 operation. 6 tohout transport overhead bytes out: a 1 enables the l3m device to generate the a1, a2, c1, and the h1, h2 bytes, in the external timing mode (sts-1 mode) only. the h1 and h2 bytes are transmitted with a fixed pointer value of 6000h. 5h4ctr h4 counter enable: normally set to 0. a 1 enables the h4 byte to be transmitted with a count generated by an internal 8-bit frame counter. 4 pat 2 3 2 23 -1 test pattern enable: a 0 selects the test pattern generators ? and analyzer ? s pattern to be 2 15 -1. a 1 selects the pattern generators ? and ana- lyzer ? s pattern to be 2 23 -1. 3enana enable analyzer: a 1 enables the 2 15 -1or 2 23 -1 analyzer. prbs errors are counted in a 16-bit counter in locations aeh and afh. 2txana transmit analyzer enable: a 1 enables the analyzer to sample the trans- mit nrz line (ds3/e3) signal after the decoder. a 0 causes the analyzer to sample the receive nrz line data prior to the coder function. a 1 must be written into enana for this bit to function (see figure 34). 1tprbs transmit test pattern generator enable: a 1 enables the transmit test pattern generator and disables the nrz decoder output. 0rprbs receive test pattern generator enable: a 1 enables the receive test pattern generator and disables the nrz coder input. address bit symbol description bpv for b3zs bpv for hdb3 bpv "type 1 ? equipment ? ty p e 0 ? equipment ++ or -- 000 (preceding bit(s) changed) 11 0bv or 000v 0000 011 or 0001 bb0v after odd 1000 1101 b00v after even 1000 1001 bpv "type 1 ? equipment ? ty p e 0 ? equipment ++ or -- 0000 (preceding bit(s) changed) 11 0bv or 0000v 00000 011 or 00001 bb00v after odd 10000 11001 b000v after even 10000 10001 - 73 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet c7 7 testb3 test b3 byte: a 1 transmits a b3 value written by the microprocessor in location 40h. a 0 enables the test byte to become a test mask. when con- figured as a test mask, a 1 in one or more bit positions causes those bits in the transmitted b3 byte to be inverted. 6fixptr tug-3 fixed pointer generation: a 1 forces a fixed pointer of 0 to be generated in the transmitted tug-3 regardless of any pointer movements (j1 in dc1j1) that may occur on the drop side when the drop timing mode is selected, or if a pointer movement (j1 in ac1j1) takes place when add bus timing is selected. when this bit is written with a 0, a pointer movement on the add or drop bus is compensated with an outgoing tug-3 pointer movement in the opposite direction. 5test test bit position: this bit must be set to 1. 4div4 phase detector gain: this control bit governs the gain of the phase detector, and it should be set as indicated in the operation section entitled ? pll filter connection to vcxo ? . 3 invctrl invert control: inverts the ctrl output lead (lead 3 or d3). when set to 0, the external loop filter must be non-inverting, which requires the use of an inverter in the loop (u1 in figure 32). when set to 1, an external invert- ing loop filter is necessary, and u1 is not required. 2txrst transmit reset: a 1 written into this position resets the transmit section (line to sdh/sonet) of the l3m device. this includes the transmit fifos and internal counters. the l3m device ? s transmitter will remain reset until the microprocessor writes a 0 into this location. 1rxrst receive reset: a 1 written into this position resets the receive section (sdh/sonet to line) of the l3m device. this includes the receive fifos and internal counters. the l3m device ? s receiver will remain reset until the microprocessor writes a 0 into this location. 0 resetc reset performance counters: a 1 written into this position resets all per- formance counters to 0. this bit is self clearing, and does not require the microprocessor to write a 0 into this location. c8 7-0 c2 compare path signal label compare: the bits in this location are written by the microprocessor, and are compared against the c2 byte received (register 91h) for a signal label mismatch condition. c9 7-2 test test bit positions: zeros must be written into these bits. 1 rdi5 rdi 5 consecutive enable: a 1 enables the detection/recovery of rdi (bit 5 in the g1 byte) to 5 consecutive matches/mismatches. a 0 enables the detection/recovery of rdi to 10 consecutive matches/mismatches. 0 febeblk febe counter block count enable: a 1 configures the febe counter (register locations aa and ab) to count one or more febe errors per received g1 byte as one error (block). a 0 configures the febe counter to count the number of errors detected (1 to 8). address bit symbol description - 74 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet ca 7-6 test test bit positions: these bits must be set 0. 5nopoh no path overhead: when this bit is set to 1, the vc-4 path overhead time slots of the add bus data signals adata(7-0) are set to a high impedance and the add signal is high during these time slots. when this bit is set to 0, adata(7-0) and add are active during these time slots. the adata (7-0) byte values are set to 00h during these time slots. 4-0 test test bit positions: these bits must be set 0. address bit symbol description - 75 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet status bits status bits report the condition of alarms. unlatched bit positions (even addresses) respond to transient alarm conditions. latched bit positions (odd addresses) are set upon occurrence of an alarm condition and then stay high until they are cleared by a read cycle. it is important to remember that, when reading the latched registers in the l3m, the contents should be read a second time before determining the current status. address bit symbol description b0 & b1 7 dloc drop bus loss of clock alarm: a loss of clock alarm occurs when the input drop clock is stuck high or low for 1000 500 nanoseconds. recovery occurs on the first clock transition. 6dloj1 drop bus loss of j1: a loss of j1 alarm occurs when: - 8 consecutive new j1 positions have been detected or - j1 is stuck low for 8 consecutive frames or - j1 is stuck high for 8 consecutive bytes or - 8 j1 pulses are received in one frame. recovery occurs when the j1 pulse is detected in the same location for 8 consecutive frames. 5buserr bus parity error: a 1 indicates a parity error has been detected on the drop bus. odd parity is calculated over the ddata, dspe, dc1j1 or dc1, and dpar leads. other than providing this alarm, no other action is taken. 4e1ais e1 byte ais detected: a 1 indicates that ais has been detected in the e1 byte corresponding to au-3/sts-3 sts-1. for tug-3 operation, the e1 in slot 0 is monitored. majority logic (5 out of 8 1s) is used for detection. the following alarms in the transwitch sot-3/sot-1 devices generate an e1 byte having an ais indication: loss of frame, loss of signal, loss of pointer, and line ais detected. internal pointer processing is performed for the tug- 3 signal according to etsi draft document pr ets 300 417-1, july 1994. 3lop loss of pointer alarm: valid for tug-3 pointer processing only. a loss of pointer alarm occurs when a new data flag (ndf) or an invalid pointer is detected for eight consecutive frames. recovery occurs when a valid pointer is received for three consecutive frames. 2pais path ais alarm: valid for tug-3 pointer processing only. a path alarm indication signal (ais) is detected when all ones are detected in the 16 bit pointer word (h1 and h2) for three consecutive frames. recovery occurs when a valid ndf is received, or a valid pointer is detected, for three con- secutive frames. 1 pslerr path signal label error: a 1 indicates that the comparison between the received c2 byte and the microprocessor-written c2 byte or certain fixed values did not match 5 times consecutively (i.e., the two mismatch test conditions are c2 value in register c8h and-gated with c2 01h, or c2 = 00h). recovery to 0 occurs when the comparison matches five times con- secutively. 0c2eq0 unequipped alarm: an unequipped alarm is detected (c2eq0 = 1) when the c2 byte is equal to 00h 5 times consecutively. alarm recovery to c2eq0 = 0 occurs when the c2 byte is not equal to 00h five times consec- utively. - 76 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet b2 & b3 7 rdi receive rdi (yellow) alarm: when rdi5 is set to 0, a 1 in rdi indicates that bit 5 in the g1 byte has been detected as a one for 10 consecutive frames. when rdi5 is set to 0, rdi recovers to 0 when a 0 has been detected for 10 consecutive frames. when rdi5 is a 1, detection and recov- ery of rdi occurs after 5 consecutive events instead of 10. 6 l3los mapper transmit loss of signal: for an e3 signal, a loss of signal alarm occurs when the positive/negative rail is stuck low for 256 bit times. recov- ery occurs when there are at least 32 transitions (both positive and negative rail) in a count of 256 clock cycles. for a ds3 signal, a loss of signal alarm occurs when either the positive or negative rail is stuck low for 200 bit times. recovery occurs on the first transition (both positive and negative rail). when the interface is configured for nrz operation, an active high on the tneg will be an external loss of signal indication and will cause a l3los indication. 5 l3loc mapper transmit loss of clock: a 1 indicates the incoming line clock (tclk) signal has been stuck high or low for 1000 500 nanoseconds. recovery occurs on the first clock transition. 4tovfl transmit fifo overflow/underflow: a 1 indicates that the transmit fifo has either underflowed or overflowed. when this happens, the fifo auto- matically resets to a preset position. 3 l3ais mapper e3 transmit ais detected: for an e3 signal, ais is detected when four or fewer zeros are detected in 1536 bits, twice in a row. recovery occurs when there are five or more zeros detected in 1536 bits two consec- utive times. 2ramloc loss of microprocessor ram clock: a 1 indicates that the ram clock (ramci) has been stuck high or low for 1000 500 nanoseconds. recov- ery occurs on the first clock transition. 1aloc add bus loss of clock: a loss of clock alarm occurs when the input add clock (aclk) is stuck high or low for 1000 500 nanoseconds. recovery occurs on the first clock transition. when the add bus clock is an output, the external byte clock (xclki) is monitored for loss of clock instead, and its loss is reported by this alarm. 0aloj1 add bus loss of j1: a loss of j1 alarm occurs when: - 8 consecutive new j1 positions have been detected or - j1 is stuck low for 8 consecutive frames or - j1 is stuck high for 8 consecutive bytes or - 8 j1 pulses are received in one frame. recovery occurs when the j1 pulse is detected in the same location for 8 consecutive frames. address bit symbol description - 77 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet b4 & b5 7 sint (b4 only) software interrupt: a software interrupt indication occurs when one or more bit locations in the interrupt mask locations is set to 1, and the corre- sponding latched alarm is active. the sint state is exited when the latched alarm causing the interrupt clears or its corresponding bit in the interrupt mask is cleared. 6febe9 febe count of 9 indication: an sts febe9 indication occurs when the code 1001 (count of 9) in bits 1-4 in the received g1 byte is detected for five consecutive frames. the alarm is terminated when any code other than the 1001 is detected in bits 1-4 for five consecutive frames. 5new new alarm: an indication that a new j1 location, other than those resulting from inc or dec, has been detected. 4tug3new tug-3 new alarm: a tug-3 new indication occurs when three consecu- tive new pointers, or an ndf and a match of the ss bits and the pointer off- set value is in range, has been detected. 3rovfl receive fifo overflow/underflow: a 1 indicates an underflow or overflow condition in the receive direction (sdh/sonet to line). when this happens, the fifo will automatically reset to a preset position and the fifoerr out- put (lead 11 or f3) will pulse high. 2xstai sdh/sonet network alarm indication: a 1 indicates that the input on the lead labeled stai is high. 1xistat external sts-1 alarm: a 1 indicates that the input on the lead labeled istat is a high. a 1 is equal to an external alarm condition (e.g., lop). 0xpais external path ais: a 1 indicates that the input on the lead labeled pais is a high. a 1 is equal to an external alarm condition (i.e., path ais). address bit symbol description - 78 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet b6 & b7 7 l3err analyzer error indication: a 1 indicates that the 2 15 -1 or 2 23 -1 analyzer has detected an error when enabled. a 1 written to enana (bit 3, location c6) enables the analyzer. this indication will be disabled during operation when control bit enana is a 0. 6lovfl leak fifo overflow/underflow alarm: a 1 indicates that the leak fifo has underflowed or overflowed. when this occurs, the fifo will automati- cally reset to a preset position and the fifoerr output (lead 11 or f3) will pulse high. 5rfrst receive fifo reset indication: a 1 indicates that either of the receive fifos has been reset. this may occur because of a fifo overflow/under- flow alarm, or when the receive section has been reset by writing a 1 to control bit rxrst, or upon hardware reset. 4 tfrst transmit fifo reset indication: a 1 indicates that the transmit fifo has been reset. this may occur because of a fifo overflow/underflow alarm, or when the transmit section has been reset by writing a 1 to control bit txrst, or upon hardware reset. 3vcxoloc loss of vcxo clock: a 1 indicates that the external vcxo clock has been stuck high or low for 1000 500 nanoseconds. recovery occurs on the first clock transition. 2tploc loss of transmit pll clock: a 1 indicates that the internal pll clock has been stuck high or low for 1000 500 nanoseconds. recovery occurs on the first clock transition. 1rploc loss of receive pll clock: a 1 indicates that the internal pll clock has been stuck high or low for 1000 500 nanoseconds. recovery occurs on the first clock transition. 0ool analyzer out of lock: a 1 indicates that the analyzer, when enabled, is out of lock. address bit symbol description - 79 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet interrupt mask bits a 1 written to any of the bits in the interrupt mask (except hint), and the occurrence of the corresponding alarm, causes a software interrupt (sint) to occur. if the hardware interrupt bit (hint) is also written with a 1, then a hardware interrupt also occurs. address bit symbol description ba 7 dloc drop bus loss of clock 6 dloj1 drop bus loss of j1 5 buserr bus parity error 4 e1ais e1 byte ais detected 3 lop loss of pointer (tug-3 operation) 2 pais path ais (tug-3 operation) 1 pslerr path signal label error 0 c2eq0 c2 equal to 0 alarm (unequipped) bb 7 rdi receive rdi (yellow) detected. 6 l3los transmit line loss of signal 5 l3loc transmit line loss of clock 4 tovfl transmit fifo error (underflowed or overflowed) 3 l3ais e3 transmit line ais detected 2 ramloc loss of microprocessor ram clock (ramci signal, lead 130 or c7) 1 aloc add bus loss of clock 0 aloj1 add bus loss of j1 bc 7 hint hardware interrupt enable 6 febe9 febe count of 9 indication 5 new new alarm - ndf and 3x new pointer events (tug-3 operation) 4 tug3new tug-3 new alarm - three new pointer events 3 rovfl receive fifo overflow/underflow 2 xstai sdh/sonet network alarm indication 1 xistat external sts-1 alarm (istat) signal detected as a 1 (if enabled) 0 xpais external path ais (pais) signal detected as a 1 (if enabled) bd 7 l3err internal analyzer bit error detected. 6 lovfl leak fifo overflow/underflow 5 rfrst receive fifo reset indication 4 tfrst transmit fifo reset indication 3 vcxoloc vcxo loss of clock 2 tploc transmit pll loss of clock 1 rploc receive pll loss of clock 0 ool analyzer out of lock. - 80 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet transmit path overhead bytes and ? o ? -bits the transmit path overhead bytes consist of the j1, b3, c2, g1, f2, h4, z3 (f3), z4 (k3), and z5 (n1) bytes, where z3, z4 and z5 are ansi designations. the poh bytes may be individually transmitted from the poh interface, or from ram locations written by the microprocessor. when poh2ram is a 1, the poh interface byte selected for transmission is written into the common ram location as transmitted. for example, if exc2 is set to 1, the transmit poh interface c2 byte is written into the assigned ram location, in addition to being transmitted. if exc2 is set to 0, the transmitted byte is the value written into the corresponding ram location by the microprocessor. when a 0 is written into the poh2ram control bit, the l3m device disables the capability of writing any of the selected poh interface bytes into their ram locations. however, individual bytes may still be transmitted from either the poh interface or the microprocessor-written ram location. this feature permits switching back and forth between a selected poh interface byte or a ram location for transmission, without having to re-initialize the ram location. the following table is a summary of this operation: * e.g., bn = c2. the relationship between a transmitted path overhead byte and the corresponding ram location is as follows: bits of ram location bits of transmitted poh byte poh2ram exbn* action 1 1 poh interface byte bn written into ram, and also transmit- ted. 0 1 poh interface byte bn transmitted, but not written into ram. microprocessor writes ram value as required. x 0 poh ram value of bn byte transmitted. 76543210 12345678 - 81 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet the ? o ? -bits consists of two overhead communication bits per subframe, for nine subframes, in the ds3 format, or for 3 subframes in the e3 format. the selection of the two bits per subframe, either from the ? o ? -bit interface or from ram, operates in the same way as the path overhead bytes, but ? o ? -bits from the transmit ? o ? -bit port are not written into ram. when sourced from the ram, the same ? o ? -bit pair will be sent throughout the entire sonet frame (i.e., the ? o ? -bit value from ram is accessed only once per frame). address bit symbol description 00 to 3f 7-0 j1 path trace: the bytes written into this location provide a repetitive 64 byte fixed length message for transmission. the bytes written into these posi- tions are either from the microprocessor or from the external poh i/o. 40 7-0 b3 error mask b3 error mask: when control bit testb3 is a 0, the bit columns written with a one represent the columns in the b3 byte in which errors are gener- ated. the b3 errors are sent until this position is rewritten with a 00h. when control bit testb3 is a 1, the value written into this location is the transmitted b3 byte. 41 7-0 c2 path signal label (microprocessor): the bits written into this position indicate the construction of the au-3, tug-3, or spe. 42 7-0 g1 transmit byte g1: this byte is used for sending the microprocessor-con- trolled states for febe, rdi, and the unassigned bits, according to states given in the tables below: tfebe trdi unassigned bits transmit g1 bit 1234 5 678 ram bit 7654 3 210 tfebe trdi unassigned exg1 febeen action 0 0 microprocessor-written value sent 0 1 internal or mate (ring mode) value sent 1 x external poh value sent exg1 ramrdi action 0 0 internal or mate (ring mode) value sent 0 1 microprocessor-written value sent 1 x external poh value sent exg1 action 0 microprocessor-written value sent 1 external poh value sent - 82 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet 43 7-0 f2 user channel: this location provides microprocessor- or i/o- written infor- mation between elements. 44 7-0 h4 h4 channel: this byte is not used in this mapping, and should be set to 00h by the microprocessor or i/o. writing a one to the h4ctr bit inserts an 8-bit counter into this byte. 45 46 47 7-0 7-0 7-0 z3 (f3) z4 (k3) z5 (n1) z3 (f3), z4 (k3), z5 (n1) bytes: the processing of these bytes is not sup- ported in the l3m. however, the microprocessor may write the transmit val- ues of these bytes in these registers. 48 7-0 not used. 49 7-2 not used. 1 0 to2 to1 trans mit ? o ? -bits: these two bits correspond to the two ? o ? -bits found in each of the nine subframes in the ds3 format or the three subframes in the e3 format. the ? o ? -bits are read once per frame and inserted into each of the subframes. address bit symbol description - 83 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet receive path overhead bytes, tug-3 h1/h2 bytes and ? o ? -bits the received bytes are written into the locations given below, and are also provided at the receive path over- head byte interface. the relationship between a received path overhead byte and the corresponding ram location is as follows: bits of ram location: bits of received poh byte: 76543210 12345678 address bit symbol description 50 to 8f 7-0 j1 path trace: the received j1 bytes are written in the 64 byte segment in a rotating fashion. there is no specific starting point. 90 7-0 b3 path b3: the value in this location is the received b3 parity byte. 91 7-0 c2 path signal label: these bits indicate the construction of the au-3, tug-3, or spe (e.g., unequipped). 92 7-0 g1 receive byte g1: this location provides the receive status of the febe bits, path rdi, and unassigned bits in the g1 byte. 93 7-0 f2 user channel: this location provides user information between elements. 94 7-0 h4 h4 byte: this byte is not specified for use in this application. it is provided for future use as required. 95 96 97 7-0 7-0 7-0 z3 (f3) z4 (k3) z5 (n1) path growth: the z3, z4 and z5 bytes are designated for future growth. the z5 byte has been assigned for tandem connection application. 98 99 7-0 h1 h2 received h1 and h2 pointer: the contents of the h1 and h2 pointer for a tug-3 are provided in the following bit order for a microprocessor read cycle. h1 h2 bit76543210 76543210 nnnnss id idididid 9a 1 0 ro2 ro1 receive ? o ? -bits: the received states of the two overhead communica- tion channel bits found in the nine subframes in the ds3 format or the three subframes in the e3 format. the two bits are updated once a frame from one of the subframes in the frame. receiveg1bit 1234 5 678 ram bit 7654 3 210 rfebe rrdi unassigned - 84 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet performance counters and fifo leak rate all 16-bit performance counters allow uninterrupted access, without the danger of one byte changing while the other byte is read. to perform a 16-bit read, the low order byte is read first. this causes the high order byte of the counter to be transferred to a common high order byte at location ffh. the common high order byte should be read next to complete the count transfer; if another performance counter low order byte is read first, the contents of the common high order byte will change to reflect the performance counter just read. counts that occur during the read cycle are held for the counter to be updated afterwards. all the performance counters can also be configured to be either saturating or non-saturating. when a 1 is writ- ten to control bit cor (clear on read), the performance counters are configured to be saturating, with the counters stopping at their maximum count. an 8-bit or 16-bit counter is reset on a microprocessor read cycle. when a 0 is written to control bit cor, the performance counters are configured to be non-saturating, and roll over to zero after the maximum count in the counter is reached. the counters are then not cleared on a read cycle. all the performance counters can be reset simultaneously by writing a 1 to control bit resetc. this bit is self clearing, and does not require writing a 0 into this location. all drop bus related performance counters are inhibited (i.e., will not increment) when one or more of the fol- lowing alarms occurs: - loss of drop bus clock (dloc) - loss of drop bus j1 (dloj1) - ais detected in the e1 byte (when xalm2ais = 0) - when either istat or pais lead is high (when xalm2ais = 1) - loss of pointer (tug-3) - path ais (tug-3) the performance counters can also be written by the microprocessor. however, when writing to a 16-bit counter (at locations n, n+1) it is recommended that the low order byte at location n should be written first. the high order byte can be written by addressing location n + 1. since the writes occur in separate cycles, care must be taken to prevent the low byte from carrying-out to the high byte before the high byte is initialized. writ- ing a low byte equal to 00h will provide the maximum time for the microprocessor to update the high byte. address bit symbol description a0 7-0 rcv frame cnt receive sdh/sonet frame count: counts the number of received sdh/sonet frames. a1 7-0 not used. a2 7-0 fifo leak rate fifo leak rate register: the number written into this location repre- sents the number of frames between consecutive leaked bits, in multiples of four frames (i.e., a value of x means that there are 4x frames between bit leaks). the recommended value of zero causes a bit to be leaked every other frame. a3 7-0 inc count positive justification counter: counts the number of positive (incre- ment) pointer movements in the aug/vc-4 or sts-3/sts-1 based on j1 movements. - 85 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet a4 7-0 dec count negative justification counter: counts the number of negative (decre- ment) pointer movements in the aug/vc-4 or sts-3/sts-1 based on j1 movements. a5 7-0 new count new data flag (ndf) counter: counts the number of j1 movements for the aug/vc-4 or sts-3/sts-1. a6 7-0 tug-3 inc count tug-3 positive justification counter: counts the number of positive (increment) pointer movements in the tug-3, based on interpretation of h1 and h2. a7 7-0 tug-3 dec count tug-3 negative justification counter: counts the number of negative (decrement) pointer movements in the tug-3, based on interpretation of h1 and h2. a8 7-0 tug-3 ndf count tug-3 new data flag (ndf) counter: counts the number of new data flags (ndfs) or new pointers in the tug-3 pointer (h1/h2). note: the tug-3 ndf counter will not register a count when the pointer is changed between certain sets of values (i.e., 192 to 194 or 193 to 195). the tug-3 ndf counter will register two counts for the inverse case, (i.e., 194 to 192 or 195 to 193). a9 7-0 b3 block count b3 blocks (in error) counter: counts the number of b3 blocks which are received in error. aa 7-0 febe count far end block error counter: counts the febe error count indication received in bits 1 through 4 of g1 when control bit febeblk is a 0. when febeblk is a 1, one or more errors per received g1 byte are counted as 1 error (block). location aah is the low order byte, while location abh is the high order byte of the 16-bit counter. after reading the low order byte from aah the corresponding high order byte (abh) should be read from ffh. ac 7-0 b3 counter b3 error counter: counts the number of b3 errors that occur between the incoming value and calculated value. location ach is the low order byte, while location adh is the high order byte of the 16-bit counter. after read- ing the low order byte from ach the corresponding high order byte (adh) should be read from ffh. ae 7-0 coding errors hdb3/b3zs coding error counter: counts the number of internal cod- ing violation errors detected when in p/n rail mode. location aeh is the low order byte while location afh is the high order byte of the 16-bit counter. when control bit enana is set to 1, prbs errors are counted when the internal analyzer is in lock (no ool alarm). after reading the low order byte from aeh the corresponding high order byte (afh) should be read from ffh. ff 7-0 common high byte count common high order byte: this location contains a copy of the high order byte that was associated with the low order byte of the 16-bit counter most recently read. address bit symbol description - 86 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet package information the l3m device is available in two package formats. one is a 144-lead plastic quad flat package suitable for sur- face mounting, as shown in figure 37. the other is a 208-lead small outline plastic ball grid array package suitable for surface mounting, as illustrated in figure 38. figure 37. l3m txc-03452b 144-lead plastic quad flat package TXC-03452-BIPQ 108 73 72 37 36 1 144 109 lead #1 index 22.75 sq 28.00 sq 31.90 0.25 sq 0.65 typ 0.30 typ 4.07(max) 0.25 (min) 3.42 see detail ? a ? 0.18 typ 0.80 typ 0 -7 degree typ detail ? a ? note: all linear dimension values are shown in millimeters and are nominal unless otherwise indicated. transwitch - 87 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet figure 38. l3m txc-03452b 208-lead small outline plastic ball grid array package 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 trpnmlkjhgfedcb b e e2 e d2 d note 2 d1/4 e1/4 -d1- -e1- a2 (a3) a a1 dimension (note 1) min max notes: 1. all dimensions are in millimeters. values shown are for reference only. 2. identification of the solder ball a1 corner is contained within this shaded zone. this package corner may be a 90 angle, or chamfered for a1 identification. 3. size of array: 16 x 16, jedec code mo-151-aaf-1 a a1 a2 1.35 0.30 0.75 1.75 0.50 0.85 a3 (ref.) 0.36 b 0.40 0.60 d17.00 d1 (bsc) 15.00 d2 15.00 15.70 e17.00 e1 (bsc) 15.00 e2 15.00 15.70 e (bsc) 1.00 bottom view transwitch txc-03452biog 16 a - 88 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet ordering information part number: TXC-03452-BIPQ 144-lead plastic quad flat package txc-03452biog 208-lead small outline plastic ball grid array package related products txc-02030, dart vlsi device (advanced e3/ds3 receiver/transmitter). dart performs the trans- mit and receive line interface functions required for transmission of e3 (34.368 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. txc-02302b, syn155c vlsi device (155-mbit/s synchronizer, clock and data output). transmits and receives at sts-3/stm-1 rates. provides the complete sts-3/stm-1 frame synchronization function. connects directly to optical fiber interface components. txc-03001/txc-03001b, sot-1 vlsi device (sonet sts-1 overhead terminator). this device performs section, line and path overhead processing for sts-1 sonet signals. has programmable sts-1 or sts-n modes. txc-03003/txc-03003b, sot-3 vlsi device (stm-1/sts-3/sts-3c overhead terminator). this device performs section, line and path overhead processing for stm-1/sts-3/sts-3c signals. compliant with ansi and itu-tss standards. txc-03301, m13 vlsi device (ds3/ds1 mux/demux). this single-chip multiplex/demultiplex device provides the complete interfacing function between a single ds3 signal and 28 independent ds1 signals. txc-03303, m13e vlsi device. extended feature version of the txc-03301 (m13). txc-03305, m13x vlsi device (ds3/ds1 mux/demux). this single-chip device provides the functions needed to multiplex and demultiplex 28 independent ds1 signals to and from a ds3 signal with either an m13 or c-bit frame format. it includes some enhanced features relative to the m13e device. txc-06103, phast-3n vlsi device (sonet/sdh stm-1, sts-3 or sts-3c overhead terminator) this phast-3n vlsi device provides a combus interface for downstream devices and operates from a power supply of 3.3 volts. txc-06125, xbert vlsi device (bit error rate generator receiver). programmable multi-rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface capability. txc-20153d, ds3/sts-1 line interface module (ds3lim-sn). complete and compact analog to digital interface serving b3zs encoded ds3 signals. - 89 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: 212-642-4900 11 west 42nd street fax: 212-302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: 650-949-6700 suite 304 fax: 650-949-6705 mountain view, ca 94040 web: www.atmforum.org atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium web: www.euroinfo@atmforum.ocm atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan web: www.apinfo@atmforum.com bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: 800-854-7179 (within u.s.a.) global engineering documents tel: 314-726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: 314-726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: 800-669-6857 (within u.s.a.) tel: 903-769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: 508-650-1375 washington, dc 20007 web: www.mvip.org - 90 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet itu-t (international): publication services of international telecommunication union tel: 22 730 5111 fax: 22 733 7256 telecommunication standardization sector web: www.itu.int place des nations, ch 1211 geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: 215-697-2179 building 4 / section d fax: 215-697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: 800-433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: 503-693-6232 (outside u.s.a.) hillsboro, or 97124 fax: 503-693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: 800-521-core (within u.s.a.) attention - customer service tel: 908-699-5800 (outside u.s.a.) 8 corporate place fax: 908-336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsucho - suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo - 91 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet list of data sheet changes this change list identifies those areas within this updated l3m txc-03452b data sheet that have significant differences relative to the previous and now superseded data sheet: updated l3m txc-03452b data sheet: edition 4, september 1999 previous l3m txc-03452b data sheet: edition 3, october 1997 the page numbers indicated below of this updated data sheet include changes relative to the superseded data sheet. page number of updated data sheet summary of the change all changed edition number and date. changed ? pin ? to ? lead ? throughout. 1 added 208-lead pbga package to features. 2-3 updated table of contents and list of figures. 6 deleted asterisk from text and associated footnote. 10 changed third paragraph. 12 added new figure 6 for the 208-lead pbga package and renumbered fol- lowing figures. 13-23 added 208-lead bga lead assignment column to lead description tables. 16 added last sentence to name/function for symbols dc1 and dpar. 21 changed name/function for symbols xc1, stai, pais and istat. 23 changed name/function for symbol trs . 24 added rows for parameters ? ambient operating temperature ? , ? relative humidity, during assembly ? and ? relative humidity, in-circuit ? to first table. modified note 2 and added note 3. added row for thermal resistance for 208-lead pbga package to second table. removed ambient operating temperature row from last table and changed its title. 25, 26 changed the input leakage current polarity (positive to negative) and test conditions in five tables. 29-31, 36-38 added t od(3) and t od(4) to tables and figures. 49 changed sentences 3 and 4 above figure 30. 50 added figure 31 and associated text. renumbered following figures. 51-52 extensively changed ? pll filter connection to vcxo ? section. 54 changed facility loopback in figure 34. - 92 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet 55 added second sentence to second paragraph. changed first sentence of third paragraph. 56 added reference to pbga package in figure 36. 57-60 added pbga lead number information to boundary scan chain table. 61 added text below memory map heading. 67 changed first sentence of description for symbol febe9en. 70 added note below table. 74 added last sentence to description for symbol nopoh. 75 changed first sentence of description for pslerr. 84 changed description for symbol fifo leak rate. 86 removed reference to socket mounting for pqfp package. 87 added new pbga package diagram as figure 38. 88 added new part number for pbga package to ordering information. added three items to related products. 89-90 updated standards documentation sources list. 91-92 updated list of data sheet changes. 95 updated documentation update registration form. page number of updated data sheet summary of the change - 93 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. - 94 - transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 - 95 - txc-03452b-mb ed. 4, september 1999 l3m txc-03452b data sheet documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: ________________________________________________________________________________ company: ______________________________________ title: _________________________________ dept./mailstop: __________________________________________________________________________ street: ________________________________________________________________________________ city/state/zip: __________________________________________________________________________ if located outside u.s.a., please add - country: _________________ postal code: ____________________ telephone: ________________________ ext.: _____________ fax: __________________________ e-mail: ________________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: ___________ ____________ ___________ ____________ ___________ ____________ ___________ ___________ ____________ ___________ ____________ ___________ ____________ ___________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required please complete the registration form on this back cover sheet, and mail or fax it, if you wish to receive updated documentation on selected transwitch products as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. engines for global connectivity |
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