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description the a6278 and a6279 devices are specifically designed for led display applications. each of these bicmos devices includes a cmos shift register, accompanying data latches, and npn constant-current sink drivers. the a6278 contains 8 sink drivers, while there are 16 in the a6279. the cmos shift register and latches allow direct interfacing with microprocessor-based systems. with a 3.3 or 5 v logic supply, typical serial data-input rates can reach up to 25 mhz. the led drive current is determined by the user?s selection of a single resistor. a cmos serial data output permits cascading between multiple devices in applications requiring additional drive lines. open led connections can be detected and signaled back to the host microprocessor through the serial data out pin. four package styles are provided: a qfn surface mount, 0.90 mm overall height nominal (a6279 only); a dip (type a) for through-hole applications; and for leaded surface-mount, an soic (type lw) and a tssop with exposed thermal pad (type lp). all package styles for the a6278 are electrically identical to each other, as are the a6279 package styles. all packages are lead (pb) free, with 100% matte tin plated leadframes. 6278-ds, rev. 10 features and benefits ? 3.0 to 5.5 v logic supply range ? ? schmitt trigger inputs for improved noise immunity ? power-on reset (por) ? up to 90 ma constant-current sinking outputs ? led open circuit detection ? low-power cmos logic and latches ? high data input rate ? 20 ns typical staggering delay on the outputs ? internal uvlo and thermal shutdown (tsd) circuitry serial-input constant-current latched led drivers with open led detection not to scale a6278 and a6279 packages: 28 pin qfn (suffix et) 16 and 24 pin dip (suffix a) 16 and 24 pin tssop (suffix lp) 16 and 24 pin soic (suffix lw) serial data out serial data in latch enable out0 out1 out7 (a6278) out15 (a6279) output enable uvlo logic supply i o regulator rext serial - parallel shift register control logic block v dd v dd clock output control drivers and open circuit detector gnd v led exposed pad (et and lp packages) l a t c h es functional block diagram
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number packing package type terminals led drive lines A6278EA-T 1 25 pieces per tube dip 16 8 a6278elptr-t 1 4000 pieces per 13-in. reel tssop with exposed thermal pad a6279elptr-t 4000 pieces per 13-in. reel tssop with exposed thermal pad 24 16 a6279elwtr-t 2 1000 pieces per 13-in. reel soicw a6279eettr-t 1500 pieces per 7-in. reel mlp surface mount 28 16 1 variant is in production but has been determined to be last time buy. this classification indicates that the variant is obsolet e and notice has been given. sale of the variant is currently restricted to existing customer applications. the variant should not be purcha sed for new design applications because of obsolescence in the near future. samples are no longer available. status date change november 1, 2010. deadline for receipt of last time buy orders is april 30, 2011. recommended substitute: a6279. 2 variant is in production but has been determined to be last time buy. this classification indicates that the variant is obsolet e and notice has been given. sale of the variant is currently restricted to existing customer applications. the variant should not be purcha sed for new design applications because of obsolescence in the near future. samples are no longer available. status date change may 3, 2010. deadl ine for receipt of last time buy orders is october 29, 2010. recommended substitute: a6279. parameter symbol conditions min. typ. max. units logic supply voltage range v dd ? ? 7.0 v load supply voltage range v led ?0.5 ? 17 v outx current (any single output) i o ? ? 90 ma ground current i gnd a6278 ? ? 750 ma a6279 ? ? 1475 ma logic input voltage range v i ?0.4 v dd + 0.4 v operating temperature range (e) t a ?40 ? 85 c junction temperature t j ? ? 150 c storage temperature range t s ?55 ? 150 c absolute maximum ratings
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 3 4 5 6 7 8 2 1 14 13 12 11 10 9 15 16 ep gnd serial data in clock latch enable out0 out1 out2 out3 logic supply rext serial data out output enable out7 out6 out5 out4 terminal list table package a, lw, lp 16-pin pin-out diagrams number name function a, lw, lp et a6278 a6279 a6279 1 1 5 gnd reference terminal for logic ground and power ground 2 2 6 serial data in serial-data input to the shift-register 3 3 7 clock clock input terminal; data is shifted on the rising edge of the clock. 4 4 9 latch enable data strobe input terminal; serial data is latched with a high-level input 5 to 12 5 to 20 10 to 26 out x current-sinking output terminals 13 21 27 output enable (active low) set low to enable output drivers; set high to turn off (blank) all output drivers 14 22 1 serial data out cmos serial-data output; for cascading to the next device (to that device serial data in pin); for reading ocd bits. 15 23 2 rext an external resistor at this terminal establishes the output current for all of the sink drivers. 16 24 3 logic supply (v dd ) logic supply voltage (typically 3.3 or 5.0 v) ?? 4, 8, 18, 28 nc no connection ? ? ? ep lp and et packages only; exposed thermal pad for heat dissipation ep 21 20 19 18 17 16 15 1 2 3 4 5 6 7 14 13 12 11 10 9 8 22 23 24 25 26 27 28 out10 out9 out8 nc out7 out6 out5 serial data out rext logic supply nc gnd serial data in clock out4 out3 out2 out1 out0 latch enable nc out11 out12 out13 out14 out15 output enable nc 3 4 5 6 7 8 2 1 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 11 ep gnd serial data in clock latch enable out0 out1 out2 out3 out4 out5 out6 out7 logic supply rext serial data out output enable out15 out14 out13 out12 out11 out10 out9 out8 package et package a, lw, lp 24-pin
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics characteristic symbol test conditions min. typ. max unit electrical characteristics valid at t a = 25 c, v dd = 3.0 to 5.5 v, unless otherwise noted logic supply voltage range v dd operating 3.0 5.0 5.5 v undervoltage lockout v dd(uv) v dd = 0.0 5.0 v 2.4 ? 2.85 v v dd = 5.0 0.0 v 2.15 ? 2.55 v output current (any single output) i o v ce = 0.7 v, r ext = 225 64.2 75.5 86.8 ma v ce = 0.7 v, r ext = 470 34.1 40.0 45.9 ma v ce = 0.6 v, r ext = 3900 4.25 5.0 5.75 ma output current matching (difference between any two outputs at the same v ce ) i o v ce(a) = v ce(b) = 0.7 v, r ext = 225 ? +1.0 +6.0 % v ce(a) = v ce(b) = 0.7 v, r ext = 470 ? +1.0 +6.0 % v ce(a) = v ce(b) = 0.6 v, r ext = 3900 ? +1.0 +6.0 % output leakage current i cex v oh = 15 v ? 1.0 5.0 a logic input voltage v ih 0.7v dd ?v dd v v il gnd ? 0.3v dd v logic input voltage hysteresis v ihys all digital inputs 200 ? 400 mv serial data out voltage v ol i ol = 500 a ? ? 0.4 v v oh i oh = ?500 av dd ? 0.4 ? ? v input resistance r i output enable input, pull up 150 300 600 k latch enable input, pull down 100 200 400 k logic supply current i dd(off) r ext = open, v oe = 5 v ? ? 1.4 ma r ext = 470 , v oe = 5 v ? ? 5.0 ma r ext = 225 , v oe = 5 v ? ? 8.0 ma i dd(on) r ext = 3900 , v oe = 0 v ? ? 3.0 ma r ext = 470 , v oe = 0 v ? ? 18.0 ma r ext = 225 , v oe = 0 v ? ? 32.0 ma thermal shutdown temperature t jtsd temperature increasing ? 165 ? c thermal shutdown hysteresis t jtsdhys ?15? c open led detection threshold v ce(odc) i o > 5 ma, v ce 0.6 v ? 0.30 ? v switching characteristics valid at t a = 25 c, v dd = v ih = 3.0 to 5.5 v, v ce = 0.7 v, v il = 0 v, r ext = 470 , i o = 40 ma, v led = 3 v, r led = 58 , c led = 10 pf, unless otherwise noted clock pulse width t high, t low normal mode 20 ? ? ns serial data in setup time t su(d) 10 ? ? ns serial data in hold time t h(d) 10 ? ? ns latch enable setup time t su(le) 20 ? ? ns latch enable hold time t h(le) 20 ? ? ns output enable set up time t su(oe) 40 ? ? ns output enable hold time t h(oe) 20 ? ? ns output enable pulse width t w(oe) 1200 ? ? ns clock to serial data out propagation delay time t p(do) 30 ? ? ns output enable to out0 propagation delay time t p(oe) ?75? ns staggering delay (between consecutive outputs) t d 10 20 40 ns total delay time (15 t d )t dtotal ? 300 ? ns clock pulse width t high, t low test mode, v dd = 4.5 to 5.5 v 20 ? ? ns serial data in setup time t su(d) 20 ? ? ns serial data in hold time t h(d) 20 ? ? ns latch enable setup time t su(le) 40 ? ? ns latch enable hold time t h(le) 20 ? ? ns output enable set up time t su(oe) 40 ? ? ns output enable hold time t h(oe) 20 ? ? ns output enable pulse width* t w(oe) 2.0 ? ? us clock to serial data out propagation delay time t p(do) 30 ? ? ns output enable to out0 propagation delay time t p(oe) ?75? ns staggering delay (between consecutive outputs) t d 10 20 40 ns total delay time (15 t d )t dtotal ? 300 ? ns output fall time t f 90% to 10% voltage ? 75 150 ns output rise time t r 10% to 90% voltage ? 75 150 ns *see led open circuit detection (test) mode timing diagram.
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com serial data input clock input shift register contents serial data out latch enable input latch contents output enable input output contents i 0 i 1 i 2 ? i n -1 i n i 0 i 1 i 2 ? i n -1 i n i 0 i 1 i 2 ? i n -1 i n h h r 0 r 1 ? r n -2 r n -1 r n -1 l l r 0 r 1 ? r n -2 r n -1 r n -1 x r 0 r 1 r 2 ? r n -1 r n r n x x x ? x x x l r 0 r 1 r 2 ? r n -1 r n p 0 p 1 p 2 ? p n -1 p n p n hp 0 p 1 p 2 ? p n -1 p n lp 0 p 1 p 2 ? p n -1 p n x x x ? x x h h h h ? h h l = low logic (voltage) level h = high logic (voltage) level x = don?t care p = present state r = previous state n = 7 for the a6278, n = 15 for the a6279 truth table inputs and outputs equivalent circuits v dd in v dd le v dd out v dd in v dd in output enable (active low) clock and serial data in latch enable serial data out
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a6278, n = 7 a6279, n = 15 clock output enable latch enable clock output enable latch enable clock output enable serial data out don't care t low t high t su(oe1) t su(le1) t h(le1) t w(oe1) 1 1 2 3 t h(oe1) t low t high 123 t su(oe1) t h(oe1) sdo n sdo n -1 sdo n- 2sdo 0 (a) to enter led ocd mode, a minimum of one clock pulse is required after latch enable is brought back low. (b) to output the latched error code, output enable must be held low a minimum of 3 clock cycles. (c) when returning to normal mode, a minimum of three clock pulses is required after output enable is brought back high. normal mode timing requirements led open circuit detection (test) mode timing requirements 01 n clock a6278, n = 7 a6279, n = 15 serial data in sdi n sdi n -1 sdi 0 don't care sdo n serial data out latch enable output enable out0 don't care out1 out n don't care don't care t low t high t su(d) t h(d) t p(do) t su(le) t h(le) t w(oe) t w(oe) t p( o e ) t d t d(total) t p( o e ) t d t d(total) t su(oe) logic levels: v dd and gnd logic levels: v dd and gnd
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com normal mode serial data present at the serial data in input is transferred to the shift register on the logic 0-to-logic 1 transition of the clock input pulse. on succeeding clock pulses, the register shifts data towards the serial data out pin. the serial data must appear at the input prior to the rising edge of the clock input waveform. data present in any register is transferred to the respective latch when the latch enable input is high (serial-to-parallel con- version). the latches continue to accept new data as long as the latch enable input is held high. applications where the latches are bypassed (latch enable tied high) will require that the output enable input be high during serial data entry. when the output enable input is high, the output sink drivers are disabled (off). the data stored in the latches is not affected by the output enable input. with the output enable input active (low), the outputs are controlled by the state of their respective latches. led open circuit detection (test) mode the led open circuit detection (ocd) mode, or test mode, is entered by clocking in the led ocd mode initialization sequence on the output enable (oe) and latch enable (le) pins. in normal mode, the oe and le pins do not change states while the clock signal is cycling. the initialization sequence is shown in panel a of the led ocd timing require- ments diagram on page 7. note: each step event during mode sequencing happens on the leading edge of the clock signal. five step events (clock pulses) are required to enter ocd mode and five step events are required to return to normal mode. a pattern, such as all highs, should first be loaded into the reg- isters and latched leaving le low. the device is then sequenced into led ocd mode. it should be noted that data is still being sent through the shift registers while entering the led ocd mode. however, this data is not latched when the le pin goes high and sees a clock pulse during the initialization sequence. open circuit detection does not take place until the sequence in panel b on page 7 is performed. during this sequence, the oe pin must be held low for a minimum of 2 s (t w(oe1) ) to ensure proper settling of the output currents and be given a minimum of three clock pulses. during the period that the oe pin is low (active), ocd testing begins. the v ce voltage on each of the output pins is compared to the open led detection theshold, v ce(ocd) . if the v ce of an enabled output is lower than v ce(ocd) , an error bit value of 0 is set in the corresponding shift register. a value of 1 will be set if no error is detected. if a particular output is not enabled, a 0 will be set. the error codes are summarized in the following table: after the testing process, setting the oe pin high causes the shift registers to latch the error code data where it can then be clocked out of the serial data out pin. the ocd latching sequence (oe low, 3 clock pulses, oe high as shown in panel b of the led ocd timing diagram) can then be repeated if necessary to look for intermittent contact problems. the state of the outputs can be programmed with new data at any time while in led ocd mode (the same as in normal mode). this allows specific patterns to be tested for open circuits. the pattern that is latched will then be tested during the ocd latching sequence and the resulting bit values can be clocked out of the serial data out pin. note: led open circuit detection will not work properly if the current is being externally limited by resistors to within the set current limit for the device. to return to normal mode, perform the clocking sequence shown in panel c of the timing diagram on the oe and le pins. functional description output state test condition error code meaning output state test condition error code meaning off n/a 0 n/a on v ce < v ce(ocd) 0 open/tsd v ce v ce(ocd) 1 normal
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com constant current (r ext ) the a6278 and a6279 allow the user to set the magnitude of the constant current to the leds. once set, the current remains constant regardless of the led voltage variation, the supply voltage variation, or other circuit parameters that could otherwise affect led current. the output current is determined by the value of an external current-control resistor (r ext ). the relationship of these parameters is shown in figure 1. typical characteristics for output current and v ce are shown in figure 2 for common values of r ext . 100 200 300 500 700 1k 2k 3k 5k figure 1. output current versus current control resistance t a = 25c, v ce = 0.7 v i o (ma/bit) r ext ( ) 90 80 70 60 50 40 30 20 10 0 100 200 300 500 700 1k 2k 3k 5k figure 2. output current versus device voltage drop t a = 25c i o (ma/bit) v ce (v) r ext = 225 r ext = 470 r ext = 3900 90 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com undervoltage lockout the a6278 and a6279 include an internal under-voltage lockout (uvlo) circuit that disables the outputs in the event that the logic supply voltage drops below a minimum acceptable level. this feature prevents the display of erroneous information, a necessary function for some critical applications. upon recovery of the logic supply voltage after a uvlo event, and on power-up, all internal shift registers and latches are set to 0. the a6278/a6279 is then in normal mode. output staggering delay the a6278/a6279 has a 20 ns delay between each output. the staggering of the outputs reduces the in-rush of currents onto the power and ground planes. this aids in power supply decoupling and emi/emc reduction. the output staggering delay occurs under the following condi- tions: ? output enable is pulled low ? output enable is held low and latch enable is pulled high ? output enable is held low, latch enable is held high, and clock is pulled high the 20 ns delays are cumulative across all the outputs. under any of the above conditions, the state of out0 gets set after a typical propagation delay, t p(oe) . out1 will get set 20 ns after out0, and so forth. in the a6279, out15 will get set after 300 ns (15 20 ns) plus t p(oe) . note: the maximum clock frequency is reduced in applica- tions where both the output enable pin is held low and the latch enable pin is held high continuously, and the outputs change state on the clock edges. the staggering delay could cause spurious output responses at clock speeds greater than 1 mhz. thermal shutdown when the junction temperature of the a6278/a6279 reaches the thermal shutdown temperature threshold, t jtsd (165c typical), the outputs are shut off until the junction temperature cools down below the recovery threshold, t jtsd ? t jtsdhys (15c typical). the shift register and output latches will remain active during a tsd event. therefore, there is no need to reset the data in the output latches. in led ocd mode, if the junction temperature reaches the ther- mal shut down threshold, the outputs will turn off, as in normal mode operation. however, all of the shift registers will be set with 0, the error bit value.
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com load supply voltage (v led ) these devices are designed to operate with driver voltage drops (v ce ) of 0.7 to 3v, with an led forward voltage, v f , of 1.2 to 4.0 v. if higher voltages are dropped across the driver, package power dissipation will increase significantly. to mini- mize package power dissipation, it is recommended to use the lowest possible load supply voltage, v led , or to set any series voltage dropping, v drop , according to the following formula: v drop = v led ? v f ? v ce , with v drop = i o r drop for a single driver or for a zener diode (v z ), or for a series string of diodes (approximately 0.7 v per diode) for a group of drivers (see figure 3). if the available volt- age source, v led , will cause unacceptable power dissipation and series resistors or diodes are undesirable, a voltage regulator can be used to provide supply voltages. for reference, typical led forward voltages are: led type v f (v) white 3.5 to 4.0 blue 3.0 to 4.0 green 1.8 to 2.2 yellow 2.0 to 2.1 amber 1.9 to 2.65 red 1.6 to 2.25 infrared 1.2 to 1.5 pattern layout this device has a common logic ground and power ground terminal, gnd. for the lp package, the gnd pin should be tied to the exposed metal pad, ep, allowing the ground plane copper to be used to dissipate heat. if the ground pattern layout contains large common mode resistance, and the voltage between the system ground and the latch enable, output enable, or clock terminals exceeds 2.5 v (because of switching noise), these devices may not work properly. package power dissipation (p d ) the maximum allowable package power dissipation based on package type is determined by: p d(max) = (150 ? t a ) / r ? ja , where r ? ja is the thermal resistance of the package, determined experimentally. power dissipation levels based on the package are shown in the package thermal characteristics section (see page 14). the actual package power dissipation is determined by: p d(act) = dc (v ce i o 16) + (v dd i dd ) , where dc is the duty cycle. the value 16 represents the maxi- mum number of available device outputs for the a6279, used for the worst-case scenario (displaying all 16 leds; this would be 8 for the a6278). when the load suppy voltage, v led , is greater than 3 to 5 v, and p d(act) > p d(max) , an external voltage reducer (v drop ) must be used (see figure 3). reducing the percent duty cycle, dc, will also reduce power dis- sipation. typical results are shown on the following pages. application information v led v drop v f v ce v led v drop v f v ce v led v drop v f v ce figure 3. typical appplications for voltage drops
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a package, t a = 25c a package, t a = 50c a package, t a = 85c lp package, t a = 25c lp package, t a = 50c lp package, t a = 85c lw package, t a = 25c lw package, t a = 50c lw package, t a = 85c i o (ma/bit) 90 0 90 0 90 0 i o (ma/bit) 90 0 90 0 90 0 i o (ma/bit) 90 0 90 0 90 0 allowable output current versus duty cycle, a6278 v dd = 5 v 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%)
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a package, t a = 25c a package, t a = 50c a package, t a = 85c lp package, t a = 25c lp package, t a = 50c lp package, t a = 85c lw package, t a = 25c lw package, t a = 50c lw package, t a = 85c i o (ma/bit) 90 0 90 0 90 0 i o (ma/bit) 90 0 90 0 90 0 i o (ma/bit) 90 0 90 0 90 0 0 100 dc (%) allowable output current versus duty cycle, a6279 v dd = 5 v 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%) 0 100 dc (%)
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic symbol test conditions* value unit package thermal resistance r ja a package, 16-pin, measured on 4-layer board based on jedec standard 38 c/w a package, 24-pin, measured on 4-layer board based on jedec standard 26 c/w lp package, 16-pin, measured on 4-layer board based on jedec standard 34 c/w lp package, 24-pin, measured on 4-layer board based on jedec standard 28 c/w lw package, 16-pin, measured on 4-layer board based on jedec standard 48 c/w lw package, 24-pin, measured on 4-layer board based on jedec standard 44 c/w et package, 24-pin, measured on 4-layer board based on jedec standard 32 c/w *additional thermal information is available on the allegro web site. a6278 a6279 5.0 4.0 3.0 2.0 1.0 0 25 ambient temperature, t a (c) allowable package power dissipation (w) 50 75 100 125 150 a, r q ja 26 c/w lp, r q ja 28c/w et, r q ja 32c/w lw, r q ja 44c/w 5.0 4.0 3.0 2.0 1.0 0 25 ambient temperature, t a (c) allowable package power dissipation (w) 50 75 100 125 150 a, r ja 38c/w lw, r ja 48c/ w lp, r ja 34c /w package thermal characteristics
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package a, 16-pin dip (a6278) 2 19.050.25 5.33 max 0.46 0.12 1.27 min 1 16 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area 6.35 +0.76 ?0.25 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 1.52 +0.25 ?0.38 0.25 +0.10 ?0.05 7.62 2.54 for reference only (reference jedec ms-001 bb) dimensions in inches, metric dimensions (mm) in brackets, for reference only package a, 24-pin dip (a6279) 2 0.018 1 24 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area for reference only (reference jedec ms-001 be) dimensions in millimeters 5.33 max 0.46 0.12 1.27 min 6.35 +0.76 ?0.25 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 30.10 +0.25 ?0.64 1.52 +0.25 ?0.38 0.25 +0.10 ?0.05 7.62 2.54
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 16-pin tssop with exposed thermal pad (a6278) c seating plane c 0.10 16x 6.10 0.65 0.45 1.70 3.00 5.00 0.10 3.00 3.00 3.00 1.20 max 0.15 max 0.65 0.25 (1.00) 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06 2 1 16 gauge plane seating plane b a 16 2 1 a terminal #1 mark area b for reference only (reference jedec mo-153 abt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 sop65p640x110-17m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 24-pin tssop with exposed thermal pad (a6279) 1.20 max c seating plane 0.15 max c 0.10 24x 0.65 6.10 3.00 4.32 1.65 0.45 0.65 0.25 2 1 24 3.00 4.32 (1.00) gauge plane seating plane b a a terminal #1 mark area b for reference only (reference jedec mo-153 adt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c 7.80 0.10 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lw, 24-pin soic (a6279) package lw, 16-pin soic (a6278) 9.50 0.65 2.25 1.27 c seating plane 1.27 0.25 0.20 0.10 0.41 0.10 2.65 max 10.300.33 7.500.10 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 10.300.20 c 0.10 16x 2 1 16 gauge plane seating plane for reference only dimensions in millimeters (reference jedec ms-013 aa) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area a b reference pad layout (reference ipc soic127p1030x265-16m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b pcb layout reference view 2 1 16 1.27 b reference pad layout (reference ipc soic127p1030x265-24m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b 0.20 0.10 0.41 0.10 2.20 0.65 9.60 1.27 2 1 24 a 15.400.20 2.65 max 10.300.33 7.500.10 c seating plane c 0.10 24x for reference only (reference jedec ms-013 ad) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area 0.25 gauge plane seating plane pcb layout reference view 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 2 1 24
serial-input, constant-current latched led drivers with open led detection a6278 and a6279 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0.25 +0.05 ?0.07 0.55 +0.20 ?0.10 0.50 0.90 0.10 c 0.08 29x seating plane c a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220vhhd-1) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 qfn50p500x500x100-29v1m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 28 2 1 a 28 1 2 pcb layout reference view b 3.15 3.15 3.15 3.15 0.30 1 28 0.50 1.15 4.80 4.80 c 5.00 0.15 5.00 0.15 d d coplanarity includes exposed thermal pad and terminals package et, 28-pin mlpq (a6279) copyright ?2005-2010, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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