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caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the hcpl-2602/12 are optically coupled line receivers that combine a gaasp light emitting diode, an input current regulator and an integrated high gain photo detector. the input regulator serves as a line termination for line receiver applications. it clamps the line voltage and regulates the led current so line reflections do not interfere with circuit performance. the regulator allows a typical led current of 8.5 ma before it starts to shunt excess current. the output of the detector ic is an open collector schottky clamped transistor. an enable input gates the detector. the internal detector shield provides a guaranteed common mode transient immunity specification of 1000 v/ms for the 2602, and 3500 v/ms for the 2612. dc specifications are defined similar to ttl logic. the optocoupler ac and dc operational parameters are guaranteed from 0 c to 70 c allowing trouble- free interfacing with digital logic circuits. an input current of 5 ma will sink an eight gate fan-out (ttl) at the output. hcpl-2602, hcpl-2612 high cmr line receiver optocouplers data sheet features 1000 v/ s minimum common mode rejection (cmr) at v cm = 50 v for hcpl-2602 and 3.5 kv/ s minimum cmr at v cm = 300 v for hcpl-2612 line termination included ?no extra circuitry required accepts a broad range of drive conditions led protection minimizes led efficiency degradation high speed: 10 mbd (limited by transmission line in many applications) guaranteed ac and dc performance over temperature: 0 c to 70 c external base lead allows ?ed peaking?and led current adjustment safety approval ul recognized ?3750 v rms for 1 minute csa approved mil-prf-38534 hermetic version available (hcpl-1930/1) applications isolated line receiver computer-peripheral interface microprocessor system interface digital isolation for a/d, d/a conversion current sensing instrument input/output isolation ground loop elimination pulse transformer replacement power transistor isolation in motor drives functional diagram a 0.1 f bypass capacitor must be connected between pins 5 and 8. 1 2 3 4 8 7 6 5 in in+ gnd v v cc o v e nc cathode led on off on off on off enable h h l l nc nc output l h h h l h truth table (positive logic) shield
2 selection guide widebody minimum cmr 8-pin dip (300 mil) small-outline so-8(400 mil) hermetic hermetic on- single dual single dual single single and dv/dt v cm current output channel channel channel channel channel dual channel (v/ s) (v) (ma) enable package package package package package packages na na 5 yes 6n137 hcpl-0600 hcnw137 no hcpl-2630 hcpl-0630 5,000 50 yes hcpl-2601 hcpl-0601 hcnw2601 no hcpl-2631 hcpl-0631 10,000 1,000 yes hcpl-2611 hcpl-0611 hcnw2611 no hcpl-4661 hcpl-0661 1,000 50 yes hcpl-2602 [1] 3,500 300 yes hcpl-2612 [1] 1,000 50 3 yes hcpl-261a hcpl-061a no hcpl-263a hcpl-063a 1,000 [2] 1,000 yes hcpl-261n hcpl-061n no hcpl-263n hcpl-063n 1,000 50 12.5 [3] hcpl-193x hcpl-56xx hcpl-66xx notes: 1. hcpl-2602/2612 devices include input current regulator. 2. 15 kv/ s with v cm = 1 kv can be achieved using avago application circuit. 3. enable is available for single channel products only, except for hcpl-193x devices. input the hcpl-2602/12 are useful as line receivers in high noise environments that conventional line receivers cannot tolerate. the higher led threshold voltage provides improved immunity to differential noise and the internally shielded detector provides orders of magnitude improvement in common mode rejection with little or no sacrifice in speed.
3 schematic shield 8 6 5 2 4 v i use of a 0.1 ? bypass capacitor connected between pins 5 and 8 is required (see note 1). i f i cc v cc v o gnd i o v e i e 7 3 i i + 90 ? ordering information hcpl-2602/hcpl-2612 is ul recognized with 3750 vrms for 1 minute per ul1577. option part rohs non rohs surface gull tape number compliant compliant package mount wing & reel quantity hcpl-2602 -000e no option 300 mil dip-8 50 per tube hcpl-2612 -300e #300 x x 50 per tube -500e #500 x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-2602-500e to order product of gull wing surface mount package in tape and reel packaging and rohs compliant. example 2: hcpl-2612 to order product of 300 mil dip package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation ?xxx?is used for existing products, while (new) products launched since july 15, 2001 and rohs compliant will use xxxe.
4 8-pin dip package with gull wing surface mount option 300 8-pin dip package package outline drawings 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 5?typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) 9.65 ?0.25 (0.380 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code 5 6 7 8 4 3 2 1 type number ul recognition ur 3.56 ?0.13 (0.140 ?0.005) 0.635 ?0.25 (0.025 ?0.010) 12?nom. 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.65 ?0.25 (0.380 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 ?0.320 (0.043 ?0.013) 3.56 ?0.13 (0.140 ?0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002)
5 regulatory information the hcpl-2602/2612 have been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca 88324. solder reflow thermal profile 0 time (seconds) temperature (?) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160? 140? 150? peak temp. 245? peak temp. 240? peak temp. 230? soldering time 200? preheating time 150?, 90 + 30 sec. 2.5? ?0.5?/sec. 3? + 1?/?.5? tight typical loose room temperature preheating rate 3? + 1?/?.5?/sec. reflow heating rate 2.5? ?0.5?/sec. recommended pb-free ir profile 217 ? ramp-down 6 ?/sec. max. ramp-up 3 ?/sec. max. 150 - 200 ? 260 +0/-5 ? t 25 ? to peak 60 to 150 sec. 20-40 sec. time within 5 ? of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 ? to peak temperature = 8 minutes max. t smax = 200 ?, t smin = 150 ? insulation and safety related specifications parameter symbol value units conditions min. external air gap l(i01) 7.1 mm measured from input terminals to output terminals, (external clearance) shortest distance through air. min. external tracking l(i02) 7.4 mm measured from input terminals to output terminals, path (external creepage) shortest distance path along body. min. internal plastic 0.08 mm through insulation distance, conductor to conductor, gap (internal clearance) usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. tracking resistance cti 200 v din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia material group (din vde 0110, 1/89, table 1) option 300 - surface mount classification is class a in accordance with cecc 00802. note: non-halide flux should be used. note: non-halide flux should be used.
6 recommended operating conditions parameter symbol min. max. units input current, low level i il 0 250 a input current, high level i ih 5* 60 ma supply voltage, output v cc 4.5 5.5 v high level enable voltage v eh 2.0 v cc v low level enable voltage v el 00.8 v fan out (@ r l = 1 k ? )n 5 ttl loads output pull-up resistor r l 330 4 k ? operating temperature t a 070 c *the initial switching threshold is 5 ma or less. it is recommended that an input current between 6.3 ma and 10 ma be used to obtain best performance and to provide at least 20% led degradation guardband. absolute maximum ratings (no derating required up to 85 c) parameter symbol min. max. units storage temperature t s -55 125 c operating temperature t a -40 85 c forward input current i i 60 ma reverse input current i ir 60 ma input current, pin 4 -10 10 ma supply voltage (1 minute maximum) v cc 7v enable input voltage (not to exceed v cc by v e v cc + 0.5 v more than 500 mv) output collector current i o 50 ma output collector voltage (selection for higher v o 7v output voltages up to 20 v is available.) output collector power dissipation p o 40 mw lead solder temperature t ls 260 c for 10 sec., 1.6 mm below seating plane solder reflow temperature profile see package outline drawings section
7 electrical characteristics over recommended temperature (t a = 0 c to +70 c) unless otherwise specified. see note 1. parameter sym. min. typ.* max. units test conditions fig. note high level output i oh 5.5 100 av cc = 5.5 v, v o = 5.5 v, 1 current i i = 250 a, v e = 2.0 v low level output v ol 0.35 0.6 v v cc = 5.5 v, i i = 5 ma, 2, 4, voltage v e = 2.0 v, 5, 14 i ol (sinking) = 13 ma high level supply i cch 7.5 10 ma v cc = 5.5 v, i i = 0 ma, current v e = 0.5 v low level supply i ccl 10 13 ma v cc = 5.5 v, i i = 60 ma, current v e = 0.5 v high level enable i eh - 0.7 -1.6 ma v cc = 5.5 v, v e = 2.0 v current low level enable i el - 0.9 -1.6 ma v cc = 5.5 v, v e = 0.5 v current high level enable v eh 2.0 v 10 voltage low level enable v el 0.8 v voltage 2.0 2.4 i i = 5 ma input voltage v i v3 2.3 2.7 i i = 60 ma input reverse v r 0.75 0.95 v i r = 5 ma voltage input capacitance c in 90 pf v i = 0 v, f = 1 mhz *all typicals at v cc = 5 v, t a = 25 c.
8 switching specifications over recommended temperature (t a = 0 c to +70 c), v cc = 5 v, i i = 7.5 ma, unless otherwise specified. parameter symbol device min. typ.* max. units test conditions fig. note propagation delay 75 ns t a = 25 c time to high output t plh 20 48 6, 7, 8 3 level 100 ns propagation delay 75 ns t a = 25 c time to low output t phl 25 50 6, 7, 8 4 level 100 ns r l = 350 ? pulse width |t phl -t plh | 3.5 35 ns c l = 15 pf 9 13 distortion propagation delay t psk 40 ns 12, skew 13 output rise time t r 24 ns 12 (10-90%) output fall time t f 10 ns 12 (90-10%) propagation delay t elh 30 ns r l = 350 ? , c l = 15 pf, time of enable from v el = 0 v, v eh = 3 v 10, 11 5 v eh to v el propagation delay t ehl 20 ns r l = 350 ? , c l = 15 pf, time of enable from v el = 0 v, v eh = 3 v 10, 11 6 v el to v eh common mode hcpl-2602 1000 10,000 v cm = 50 v v o(min) = 2 v, transient |cm h |v/ sr l = 350 ? ,137 , 9, immunity at high hcpl-2612 3500 15,000 v cm = 300 v i i = 0 ma, 10 output level t a = 25 c common mode hcpl-2602 1000 10,000 v cm = 50 v v o(max) = 0.8 v, transient |cm l |v/ sr l = 350 ? ,13 8, 9 immunity at low hcpl-2612 3500 15,000 v cm = 300 v i i = 7.5 ma, 10 output level t a = 25 c *all typicals at v cc = 5 v, t a = 25 c. package characteristics all typicals at t a = 25 c parameter sym. min. typ. max. units test conditions fig. note input-output momentary v iso 3750 v rms rh 50%, t = 1 min., 2, 11 withstand voltage * t a = 25 c input-output resistance r i-o 10 12 ? v i-o = 500 vdc 2 input-output capacitance c i-o 0.6 pf f = 1 mhz 2 *the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the iec/en/din en 60747-5-2 insulation characteristics table (if applicable) , your equipment level safety specification or avago application note 1074 entitled ?ptocoupler input-output endurance voltage.
9 notes: 1. bypassing of the power supply line is required, with a 0.1 f ceramic disc capacitor adjacent to each optocoupler as illustrated in figure 15. total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm. 2. device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 3. the t plh propagation delay is measured from the 3.75 ma point on the falling edge of the input pulse to the 1.5 v point on the rising e dge of the output pulse. 4. the t phl propagation delay is measured from the 3.75 ma point on the rising edge of the input pulse to the 1.5 v point on the falling e dge of the output pulse. 5. the t elh enable propagation delay is measured from the 1.5 v point on the falling edge of the enable input pulse to the 1.5 v point on the rising edge of the output pulse. 6. the t ehl enable propagation delay is measured from the 1.5 v point on the rising edge of the enable input pulse to the 1.5 v point on t he falling edge of the output pulse. 7. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state ( i.e., v out > 2.0 v). 8. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i .e., v out < 0.8 v). 9. for sinusoidal voltages, |dv cm | = f cm v cm (p-p) dt max 10. no external pull up is required for a high logic state on the enable input. if the v e pin is not used, tying v e to v cc will result in improved cmr performance. 11. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage of 4500 for one second (leakage detection current limit, i i-o 5 a). 12. t psk is equal to the worst case difference in t phl and/or t plh that will be seen between units at any given temperature within the operating condition range. 13. see application section titled ?ropagation delay, pulse-width distortion and propagation delay skew?for more information. figure 1. typical high level output current vs. temperature. figure 2. typical low level output voltage vs. temperature. figure 3. typical input characteristics. 1.0 0203 040 60 i i ?input current ?ma 10 50 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 v i ?input voltage ?v 25? 70? 0? figure 5. typical low level output current vs. temperature. figure 4. typical output voltage vs. forward input current. 1 6 2 3 4 5 1234 5 6 i f ?forward input current ?ma r l = 350 ? r l = 1 k ? r l = 4 k ? 0 0 v cc = 5 v t a = 25 ? v o ?output voltage ?v i oh ?high level output current ?? -60 0 t a ?temperature ?? 100 10 15 -20 5 20 v cc = 5.5 v v o = 5.5 v v e = 2 v i i = 250 ? 60 -40 0 40 80 v cc = 5.5 v v e = 2 v i i = 5 ma 0.5 0.4 -60 -20 20 60 100 t a ?temperature ?? 0.3 80 40 0 -40 0.1 v ol ?low level output voltage ?v 0.2 i o = 16 ma i o = 12.8 ma i o = 9.6 ma i o = 6.4 ma v cc = 5 v v e = 2 v v ol = 0.6 v 70 60 -60 -20 20 60 100 t a ?temperature ?? 50 80 40 0 -40 20 i ol ?low level output current ?ma 40 i i = 10-15 ma i i = 5.0 ma
10 figure 10. test circuit for t ehl and t elh . figure 11. typical enable propagation delay vs. temperature. figure 7. typical propagation delay vs. temperature. figure 8. typical propagation delay vs. pulse input current. figure 9. typical pulse width distortion vs. temperature. figure 6. test circuit for t phl and t plh . output v monitoring node o +5 v 7 5 6 8 2 3 4 1 pulse gen. z = 50 ? t = t = 5 ns o f i i l r r m cc v 0.1? bypass *c l *c l is approximately 15 pf which includes probe and stray wiring capacitance. gnd input monitoring node r 1.5 v t phl t plh i i input o v output i = 7.50 ma i i = 3.75 ma i v cc = 5 v i i = 7.5 ma 100 80 -60 -20 20 60 100 t a ?temperature ?? 60 80 40 0 -40 0 t p ?propagation delay ?ns 40 20 t plh , r l = 4 k ? t plh , r l = 1 k ? t plh , r l = 350 ? t phl , r l = 350 ? 1 k ? 4 k ? v cc = 5 v t a = 25? 105 90 5913 i i ?pulse input current ?ma 75 15 11 7 30 t p ?propagation delay ?ns 60 45 t plh , r l = 4 k ? t plh , r l = 1 k ? t plh , r l = 350 ? t phl , r l = 350 ? 1 k ? 4 k ? v cc = 5 v i i = 7.5 ma 40 30 -20 20 60 100 t a ?temperature ?? 20 80 40 0 -40 pwd ?pulse width distortion ?ns 10 r l = 350 k ? r l = 1 k ? r l = 4 k ? 0 -60 -10 output v monitoring node o 1.5 v t ehl t elh v e input o v output 3.0 v 1.5 v +5 v 7 5 6 8 2 3 4 1 pulse gen. z = 50 ? t = t = 5 ns o f i i l r cc v 0.1 ? bypass *c l *c l is approximately 15 pf which includes probe and stray wiring capacitance. gnd r 7.5 ma input v e monitoring node t e ?enable propagation delay ?ns -60 0 t a ?temperature ?? 100 90 120 -20 30 20 60 -40 0 40 80 60 v cc = 5 v v eh = 3 v v el = 0 v i i = 7.5 ma t elh , r l = 4 k ? t elh , r l = 1 k ? t ehl , r l = 350 ?, 1 k ?, 4 k ? t elh , r l = 350 ?
11 gnd bus (back) v cc bus (front) enable (if used) 0.1? output 1 nc nc enable (if used) 0.1? output 2 nc nc 10 mm max. (see note 1) figure 13. test circuit for common mode transient immunity and typical waveforms. figure 12. typical rise and fall time vs. temperature. t r , t f ?rise, fall time ?ns -60 0 t a ?temperature ?? 100 300 -20 40 20 60 -40 0 40 80 60 290 20 v cc = 5 v i i = 7.5 ma r l = 4 k ? r l = 1 k ? r l = 350 ?, 1 k ? , 4 k ? t rise t fall r l = 350 ? +5 v 7 5 6 8 2 3 4 1 cc v 0.1 ? bypass gnd output v monitoring node o pulse generator z = 50 ? o + i i b a cm v 350 ? v o 0.5 v o v (min.) 5 v 0 v switch at a: i = 0 ma i switch at b: i = 7.5 ma i cm v h cm cm l o v (max.) cm v (peak) v o figure 15. recommended printed circuit board layout. figure 14. typical input threshold current vs. temperature. i th ?input threshold current ?ma -60 0 t a ?temperature ?? 100 4 5 -20 2 20 60 -40 0 40 80 3 v cc = 5.0 v v o = 0.6 v 1 r l = 4 k ? r l = 1 k ? r l = 350 ?
12 using the hcpl-2602/12 line receiver optocouplers the primary objectives to fulfill when connecting an optocoupler to a transmission line are to provide a minimum, but not excessive, led current and to properly terminate the line. the internal regulator in the hcpl- 2602/12 simplifies this task. excess current from variable drive conditions such as line length variations, line driver differences, and power supply fluctuations are shunted by the regulator. in fact, with the led current regulated, the line current can be increased to improve the immunity of the system to differential-mode-noise and to enhance the data rate capability. the designer must keep in mind the 60 ma input current maximum rating of the hcpl- 2602/12 in such cases, and may need to use series limiting or shunting to prevent overstress. design of the termination circuit is also simplified; in most cases the transmission line can simply be connected directly to the input terminals of the hcpl-2602/12 without the need for additional series or shunt resistors. if reversing line drive is used it may be desirable to use two hcpl- 2602/12 or an external schottky diode to optimize data rate. polarity non-reversing drive high data rates can be obtained with the hcpl-2602/12 with polarity non-reversing drive. figure (a) illustrates how a 74s140 line driver can be used with the hcpl-2602/12 and shielded, twisted pair or coax cable without any additional components. there are some reflections due to the ?ctive termination,?but they do not interfere with circuit perform- ance because the regulator clamps the line voltage. at longer line lengths, t plh increases faster than t phl since the switching threshold is not exactly halfway between asymptotic line conditions. if optimum data rate is desired, a series resistor and peaking capacitor can be used to equalize t plh and t phl . in general, the peaking capacitance should be as large as possible; however, if it is too large it may keep the regulator from achieving turn-off during the negative (or zero) excursions of the input signal. a safe rule: make c 16t where: c = peaking capacitance in picofarads t = data bit interval in nanoseconds polarity reversing drive a single hcpl-2602/12 can also be used with polarity reversing drive (figure b). current reversal is obtained by way of the substrate isolation diode (substrate to collector). some reduction of data rate occurs, however, because the substrate diode stores charge, which must be removed when the current changes to the forward direction. the effect of this is a longer t phl . this effect can be eliminated and data rate improved considerably by use of a schottky diode on the input of the hcpl-2602/12. for optimum noise rejection as well as balanced delays, a split- phase termination should be used along with a flip-flop at the output (figure c). the result of current reversal in split-phase operation is seen in figure (c) with switches a and b both open. the coupler inputs are then connected in anti-series; however, because of the higher steady-state termina- tion voltage, in comparison to the single hcpl-2602/12 termination, the forward current in the substrate diode is lower and consequently there is less junction charge to deal with when switching. closing switch b with a open is done mainly to enhance common mode rejection, but also reduces propagation delay slightly because line-to-line capacitance offers a slight peaking effect. with switches a and b both closed, the shield acts as a current return path which prevents either input substrate diode from becoming reversed biased. thus the data rate is optimized as shown in figure (c). improved noise rejection use of additional logic at the output of two hcpl-2602/12s, operated in the split phase termination, will greatly improve system noise rejection in addition to balancing propagation delays as discussed earlier. a nand flip-flop offers infinite common mode rejection (cmr) for negatively sloped common mode transients but requires t phl > t plh for proper operation. a nor flip-flop has infinite cmr for positively sloped transients but requires t phl < t plh for proper operation. an exclusive-or flip- flop has infinite cmr for common mode transients of either polarity and operates with either t phl >t plh or t phl t plh , so nand gates are preferred in the r-s flip-flop. a higher drive amplitude or
13 figure b. polarity reversing, single ended. figure a. polarity non-reversing. figure c. polarity reversing, split phase. figure d. flip-flop configurations. < 1 < 1
14 different circuit configuration could make t phl t plh or t phl < t plh , or if the drive conditions may vary over the boundary for these conditions, the exclusive-or flip-flop of figure (d) should be used. rs-422 and rs-423 line drivers designed for rs-422 and rs-423 generally provide adequate voltage and current for operating the hcpl-2602/12. most drivers also have characteristics allowing the hcpl-2602/12 to be connected directly to the driver terminals. worst case drive conditions, however, would require current shunting to prevent overstress of the hcpl- 2602/12. propagation delay, pulse-width distortion and propagation delay skew propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. the propagation delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see figure 6). pulse-width distortion (pwd) results when t plh and t phl differ in value. pwd is defined as the difference between t plh and t phl and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. if this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t plh or t phl , for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). as illustrated in figure 16, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the difference between the shortest propagation delay, either t phl or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 17 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. the figure shows data and clock signals at the inputs and outputs of the optocouplers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. figure 17 shows that there will be uncertainty in both the data and the clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the t psk specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges.
15 figure 16. illustration of propagation delay skew - t psk . figure 17. parallel data transmission example. data t psk inputs clock data outputs clock t psk 50% 1.5 v i i v o 50% i i v o t psk 1.5 v
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries . data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. obsoletes 5989-2154en av01-0568en july 18, 2007

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