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hy[b/i]18t256400a[c/f](l) hy[b/i]18t256800a[c/f](l) hy[b/i]18t256160a[c/f](l) 256-mbit double-data-rate-two sdram ddr2 sdram rohs compliant products internet data sheet rev. 1.50 december 2007
internet data sheet hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram qag_techdoc_rev411 / 3.31 qag / 2007-01-22 2 03062006-7m17-pxbc we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com hy[b/i]18t256400a[c/f](l), hy[b/i]18t256800a[c/f](l), hy[b/i]18t256160a[c/f](l) revision history: 2007-12, rev. 1.50 page subjects (major changes since last revision) all adapted internet version all 25 new products added all editorial changes previous revision: 2007-01 rev. 1.41 all qimonda update previous revision: 2005-07 rev. 1.4 added low-power components hyb18t256[40/80/16]0afl-3.7 added ddr2-800 5-5-5 components 92 updated i dd currents ( i dd2p , i dd3p1 , i dd6 ) chapter 2 updated pin configuration - various editorial changes on notes previous revision: 2005-07 rev. 1.3
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 3 03062006-7m17-pxbc 1overview this chapter gives an overview of the 256-mbit double-d ata-rate-two sdram product family and describes its main characteristics. 1.1 features the 256-mbit double-data-rate-two s dram offers the following key features: ? 1.8 v 0.1 v power supply 1.8 v 0.1 v (sstl_18) compatible i/o ? dram organizations wit h 4,8,16 data in/outputs ? double data rate architecture: ? two data transfers per clock cycle ? four internal banks for concurrent operation ? programmable cas latency: 3, 4, 5 and 6 ? programmable burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differentia l data strobes (dqs and dqs ) are transmitted / received with da ta. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on-die-termination (odt) for better signal quality ? auto-precharge operation for read and write bursts ? auto-refresh, self-refresh and power saving power- down modes ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c ? programmable self refres h rate via emrs2 setting ? programmable partial array refresh via emrs2 settings ? dcc enabling via emrs2 setting ? full and reduced strengt h data-output drivers ? 1kb page size ? packages: pg-tfbga-84, pg-tfbga-60, p-tfbga-84, p-tfbga-60 ? rohs compliant products 1) ? all speed grades faster than ddr2?400 comply with ddr2?400 timing specifications when run at a clock rate of 200 mhz. 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers.
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 4 03062006-7m17-pxbc table 1 performance table 1.2 description the 256-mbit ddr2 dram is a high-speed double-data- rate-two cmos synchronous dram device containing 268,435,456 bits and internally configured as a quad-bank dram. the 256-mbit device is organized as 16 mbit 4 i/o 4 banks or 8 mbit 8 i/o 4 banks or 4 mbit 16 i/o 4 banks chip. these synchronous devices achieve high speed transfer rates starting at 400 mb/sec/pin for general applications. see table 1 for performance figures. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency. 2. write latency = read latency - 1. 3. normal and weak strength data-output driver. 4. off-chip driver (ocd) impedance adjustment. 5. on-die termination (odt) function. all of the control and address inputs are synchronized with a pair of externally supplied diff erential clocks. inputs are latched at the cross point of di fferential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 15 bit address bus for 4 and 8 organised components and a 15 bit address bus for 16 components is used to convey row, column and bank address information in a ras - cas multiplexing style. a 15 bit address bus is used to convey row, column and bank address information in a ras -cas multiplexing style. the ddr2 device operates with a 1.8 v 0.1 v power supply. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the ddr2 sdram is available in tfbga package. qag speed code ?25f ?2.5 ?3 ?3s ?3.7 ?5 unit note dram speed grade ddr2 ?800d ?800e ?667c ?667d ?533c ?400b cas-rcd-rp latencies 5?5?5 6?6?6 4?4?4 5?5?5 4?4?4 3?3?3 t ck max. clock frequency cl3 f ck3 200 200 200 200 200 200 mhz cl4 f ck4 266 266 333 266 266 200 mhz cl5 f ck5 400 333 333 333 266 ? mhz cl6 f ck6 ?400????mhz min. ras-cas-delay t rcd 12.5 15 12 15 15 15 ns min. row precharge time t rp 12.5 15 12 15 15 15 ns min. row active time t ras 45 45 45 45 45 40 ns min. row cycle time t rc 57.5 60 57 60 60 55 ns precharge-all (4 banks) command period t prea 12.5 15 12 15 15 15 ns
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 5 03062006-7m17-pxbc table 2 ordering information for rohs compliant products product type 1) org. speed cas-rcd-rp latencies 2)3)4) clock (mhz) package note 5) standard temperature range (0 c - +85 c) ddr2-800e( 6-6-6) hyb18t256400af-2.5 4 ddr2-800e 6-6-6 400 pg-tfbga-60 hyb18t256160af-2.5 16 ddr2-800e 6-6-6 400 pg-tfbga-84 ddr2-800d( 5-5-5) hyb18t256800af-25f 8 ddr2-800d 5-5-5 400 pg-tfbga-60 hyb18t256400af-25f 4 ddr2-800d 5-5-5 400 pg-tfbga-60 HYB18T256160AF-25f 16 ddr2-800d 5-5-5 400 pg-tfbga-84 ddr2-667d( 5-5-5) hyb18t256160af-3s 16 ddr2-667d 5-5-5 333 pg-tfbga-84 hyb18t256800af-3s 8 ddr2-667d 5-5-5 333 pg-tfbga-60 hyb18t256400af-3s 4 ddr2-667d 5-5-5 333 pg-tfbga-60 ddr2-667c( 4-4-4) hyb18t256160af-3 16 ddr2-667c 4-4-4 333 pg-tfbga-84 ddr2-533c( 4-4-4) hyb18t256160afl-3.7 16 ddr2-533c 4-4-4 266 pg-tfbga-84 hyb18t256400afl-3.7 4 ddr2-533c 4-4-4 266 pg-tfbga-60 hyb18t256800afl-3.7 8 ddr2-533c 4-4-4 266 pg-tfbga-60 hyb18t256800af-3.7 8 ddr2-533c 4-4-4 266 pg-tfbga-60 hyb18t256400af-3.7 4 ddr2-533c 4-4-4 266 pg-tfbga-60 hyb18t256160af-3.7 16 ddr2-533c 4-4-4 266 pg-tfbga-84 ddr2-533b( 3-3-3) hyb18t256800af-2.5 8 ddr2-533b 3-3-3 266 pg-tfbga-60 ddr2-400b( 3-3-3) hyb18t256800af-5 8 ddr2-400b 3-3-3 200 pg-tfbga-60 hyb18t256400af-5 4 ddr2-400b 3-3-3 200 pg-tfbga-60 hyb18t256160af-5 16 ddr2-400b 3-3-3 200 pg-tfbga-84 industrial temperature range (?40 c - +85 c) ddr2-667d( 5-5-5) hyi18t256800af-3s 8 ddr2-667d 5-5-5 333 pg-tfbga-60 hyi18t256160af-3s 16 ddr2-667d 5-5-5 333 pg-tfbga-84 hyi18t256400af-3s 4 ddr2-667d 5-5-5 333 pg-tfbga-60 ddr2-533c( 4-4-4) hyi18t256160af-3.7 16 ddr2-533c 4-4-4 266 pg-tfbga-84 hyi18t256800af-3.7 8 ddr2-533c 4-4-4 266 pg-tfbga-60
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 6 03062006-7m17-pxbc table 3 ordering information for non rohs compliant products hyi18t256400af-3.7 4 ddr2-533c 4-4-4 266 pg-tfbga-60 ddr2-400b( 3-3-3) hyi18t256160af-5 16 ddr2-400b 3-3-3 200 pg-tfbga-84 hyi18t256800af-5 8 ddr2-400b 3-3-3 200 pg-tfbga-60 hyi18t256400af-5 4 ddr2-400b 3-3-3 200 pg-tfbga-60 1) for detailed information regarding product type of qimonda please see chapter "product nom enclature" of this datasheet. 2) cas: column address strobe 3) rcd: row column delay 4) rp: row precharge 5) rohs compliant product: restriction of the use of certain hazardous substances (r ohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type 1) org. speed cas-rcd-rp latencies 2)3)4) clock (mhz) package note standard temperature range (0 c - +85 c) ddr2-667d( 5-5-5) hyb18t256160ac-3s 16 ddr2-667d 5-5-5 333 p-tfbga-84 hyb18t256800ac-3s 8 ddr2-667d 5-5-5 333 p-tfbga-60 hyb18t256400ac-3s 4 ddr2-667d 5-5-5 333 p-tfbga-60 ddr2-533c( 4-4-4) hyb18t256800ac-3.7 8 ddr2-533c 4-4-4 266 p-tfbga-60 hyb18t256400ac-3.7 4 ddr2-533c 4-4-4 266 p-tfbga-60 hyb18t256160ac-3.7 16 ddr2-533c 4-4-4 266 p-tfbga-84 ddr2-400b( 3-3-3) hyb18t256800ac-5 8 ddr2-400b 3-3-3 200 p-tfbga-60 hyb18t256400ac-5 4 ddr2-400b 3-3-3 200 p-tfbga-60 hyb18t256160ac-5 16 ddr2-400b 3-3-3 200 p-tfbga-84 industrial temperature range (?40 c - +85 c) ddr2-667d( 5-5-5) hyi18t256800ac-3s 8 ddr2-667d 5-5-5 333 p-tfbga-60 hyi18t256160ac-3s 16 ddr2-667d 5-5-5 333 p-tfbga-84 hyi18t256400ac-3s 4 ddr2-667d 5-5-5 333 p-tfbga-60 ddr2-533c( 4-4-4) hyi18t256800ac-3.7 8 ddr2-533c 4-4-4 266 p-tfbga-60 hyi18t256160ac-3.7 16 ddr2-533c 4-4-4 266 p-tfbga-84 hyi18t256400ac-3.7 4 ddr2-533c 4-4-4 266 p-tfbga-60 ddr2-400b( 3-3-3) hyi18t256160ac-5 16 ddr2-400b 3-3-3 200 p-tfbga-84 product type 1) org. speed cas-rcd-rp latencies 2)3)4) clock (mhz) package note 5)
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 7 03062006-7m17-pxbc hyi18t256800ac-5 8 ddr2-400b 3-3-3 200 p-tfbga-60 hyi18t256400ac-5 4 ddr2-400b 3-3-3 200 p-tfbga-60 1) for detailed information regarding product type of qimonda please see chapter "product nom enclature" of this datasheet. 2) cas: column address strobe 3) rcd: row column delay 4) rp: row precharge product type 1) org. speed cas-rcd-rp latencies 2)3)4) clock (mhz) package note
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 8 03062006-7m17-pxbc 2 configuration this chapter contains the chip configuration. 2.1 configuration for tfbga-60 the chip configuration of a ddr2 sdram is listed by function in table 4 . the abbreviations used in the ball#/buffer type columns are explained in table 5 and table 6 respectively. the ball numbering for the fbga package is depicted in figures. table 4 configuration ball# name ball type buffer type function clock signals e8 ck i sstl clock signal ck, ck f8 ck i sstl f2 cke i sstl clock enable control signals f7 ras i sstl row address strobe (ras), column address strobe (cas), write enable (we) g7 cas i sstl f3 we i sstl g8 cs i sstl chip select address signals g2 ba0 i sstl bank address bus 1:0 g3 ba1 i sstl h8 a0 i sstl address signal 12:0, address signal 10/autoprecharge h3 a1 i sstl h7 a2 i sstl j2 a3 i sstl j8 a4 i sstl j3 a5 i sstl j7 a6 i sstl k2 a7 i sstl k8 a8 i sstl k3 a9 i sstl h2 a10 i sstl ap i sstl k7 a11 i sstl l2 a12 i sstl
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 9 03062006-7m17-pxbc data signals 4 organization c8 dq0 i/o sstl data signal 3:0 c2 dq1 i/o sstl d7 dq2 i/o sstl d3 dq3 i/o sstl data signals 8 organization c8 dq0 i/o sstl data signal 7:0 c2 dq1 i/o sstl d7 dq2 i/o sstl d3 dq3 i/o sstl d1 dq4 i/o sstl d9 dq5 i/o sstl b1 dq6 i/o sstl b9 dq7 i/o sstl data strobe 4 organization b7 dqs i/o sstl data strobe a8 dqs i/o sstl data strobe 8 organisation b7 dqs i/o sstl data strobe a8 dqs i/o sstl b3 rdqs o sstl read data strobe a2 rdqs o sstl data mask 4 organization b3 dm i sstl data mask data mask 8 organization b3 dm i sstl data mask power supplies a9, c1, c3, c7, c9 v ddq pwr ? i/o driver power supply a1, l1, e9, h9 v dd pwr ? power supply a7, b2, b8, d2, d8 v ssq pwr ? i/o driver power supply a3, e3, j1, k9 v ss pwr ? power supply e2 v ref ai ? i/o reference voltage e1 v ddl pwr ? power supply e7 v ssdl pwr ? power supply not connected 4 organization a2, b1, b9, d1, d9, g1, l3, l7, l8 nc nc ? not connected ball# name ball type buffer type function
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 10 03062006-7m17-pxbc table 5 abbreviations for ball type table 6 abbreviations for buffer type not connected 8 organization g1, l3, l7, l8 nc nc ? not connected other balls 4 organization f9 odt i sstl on-die termination control other balls 8 organization f9 odt i sstl on-die termination control abbreviation description i standard input-only ball. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding ball has 2 oper ational states, active low and tristate, and allows multiple devices to share as a wire-or. ball# name ball type buffer type function
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 11 03062006-7m17-pxbc figure 1 chip configuration for 4 components, tfbga-60 (top view) notes 1. v ddl and v ssdl are power and ground for the dll. v ddl is connected to v dd on the device. v dd , v ddq , v ssdl , v ss , and v ssq are isolated on the device. 2. ball position l8 is not connected on 256-mbit 0 3 3 7 &6 %$ 1& 1& 9 5() $ $3 1& $ $ $ $ $ $ 1& '4 '0 6 6 9 $ $ $ '4 '46 9 66'/ 9 664 9 ''4 9 664 $ 1& $ 9 ''4 1& '4 1& $ % & ' ) * + - ( / . 9 '' 6 6 4 9 9 ''4 '4 9 ''4 6 6 4 9 9 ''/ 6 6 9 : ( &.( &. %$ 1& 6 6 9 9 '' ' 4 6 &$6 9 ''4 9 664 &. 9 '' 5$6 2'7 9 '' $ 9 1 & $ 66
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 12 03062006-7m17-pxbc figure 2 chip configuration for 8 components, tfbga-60 (top view) notes 1. rdqs / rdqs are enabled by emrs(1) command. 2. if rdqs / rdqs is enabled, the dm function is disabled 3. when enabled, rdqs & rdqs are used as strobe signals during reads. 4. v ddl and v ssdl are power and ground for the dll. v ddl is connected to v dd on the device. v dd , v ddq , v ssdl , v ss , and v ssq are isolated on the device. 5. ball position l8 is not connected on 256-mbit. 0337 &6 %$ '4 '4 9 5() 1&5'46 $$3 $ $ $ $ $ $ 1& '4 '05'46 9 66 $ $ $ '4 '46 9 66'/ 9 664 9 ''4 9 664 $ 1& $ 9 ''4 '4 '4 '4 $ % & ' ) * + - ( / . 9 '' 9 664 9 ''4 '4 9 ''4 9 664 9 ''/ 9 66 &.( :( &. %$ 1& 9 66 9 '' &$6 '46 9 ''4 9 664 &. 9 '' 5$6 2'7 9 '' $ 9 66 1&$
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 13 03062006-7m17-pxbc 2.2 configuration for tfbga-84 the chip configuration of a ddr2 sdram is listed by function in table 7 . the abbreviations used in the ball#/buffer type columns are explained in table 8 and table 9 respectively. table 7 configuration ball# name ball type buffer type function clock signals 16 organization j8 ck i sstl clock signal ck, ck k8 ck i sstl k2 cke i sstl clock enable control signals 16 organization k7 ras i sstl row address strobe (ras), co lumn address strobe (cas), write enable (we) l7 cas i sstl k3 we i sstl l8 cs i sstl chip select address signals 16 organization l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl m8 a0 i sstl address signal 12:0, address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 14 03062006-7m17-pxbc data signals 16 organization g8 dq0 i/o sstl data signal lower byte 7:0 g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl c8 dq8 i/o sstl data signal upper byte 15:8 c2 dq9 i/o sstl d7 dq10 i/o sstl d3 dq11 i/o sstl d1 dq12 i/o sstl d9 dq13 i/o sstl b1 dq14 i/o sstl b9 dq15 i/o sstl data strobe 16 organization b7 udqs i/o sstl data strobe upper byte a8 udqs i/o sstl f7 ldqs i/o sstl data strobe lower byte e8 ldqs i/o sstl data mask 16 organization b3 udm i sstl data mask upper byte f3 ldm i sstl data mask lower byte note: ldm is the input mask signal that controls the lower byte. power supplies 16 organization j2 v ref ai ? i/o reference voltage a9, c1, c3, c7, c9, e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply a1, e1, j9, m9, r1 v dd pwr ? power supply a7, b2, b8, d2, d8, e7, f2, f8, h2, h8 v ssq pwr ? power supply j7 v ssdl pwr ? power supply a3, e3, j3, n1, p9 v ss pwr ? power supply ball# name ball type buffer type function
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 15 03062006-7m17-pxbc table 8 abbreviations for ball type table 9 abbreviations for buffer type not connected 16 organization a2, e2, l1, r3, r7, r8 nc nc ? not connected other balls 16 organization k9 odt i sstl on-die termination control abbreviation description i standard input-only ball. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding ball has 2 oper ational states, active low and tristate, and allows multiple devices to share as a wire-or. ball# name ball type buffer type function
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 16 03062006-7m17-pxbc figure 3 configuration for 16 components, tfbga-84 (top view) notes 1. udqs/udqs is data strobe for dq[15:8], ldqs/ldqs is data strobe for dq[7:0] 2. ldm is the data mask sign al for dq[7:0], udm is the data mask signal for dq[15:8] 3. v ddl and v ssdl are power and ground for the dll. v ddl is connected to v dd on the device. v dd , v ddq , v ssdl , v ss , and v ssq are isolated on the device. 0 3 3 7 9 ' ' 1 & $ 9 6 6 4 1& 9 6 6 & . ( & . 9 6 6 8 ' 0 ' 4 9 ' ' 4 ' 4 ' 4 9 6 6 9 ' ' / $ 9 6 6 4 ' 4 /' 4 6 5 $6 9 ' ' $ % & ' ) * + - ( / 0 . 1 ' 4 9 ' ' % $ % $ $ $3 $ 9 6 6 9 ' ' 4 ' 4 ' 4 9 6 6 ' / $ $ $ '4 1 & 9 ' ' 1 & 3 5 $ $ $ $ 1 & 9 6 6 ' 4 9 ' ' 4 9 6 6 4 ' 4 / ' 0 9 ' ' 4 9 ' ' 4 '4 9 6 6 4 '4 9 5 ( ) : ( 1 & $ $ 8' 4 6 8 ' 4 6 ' 4 9 ' ' 4 9 ' ' 4 ' 4 9 6 6 4 ' 4 9 6 6 4 9 ' ' 4 / ' 4 6 9 6 6 4 9 ' ' 4 ' 4 9 ' ' 4 9 6 6 4 & . 9 ' ' 2 ' 7 & $6 & 6 9 6 6 4 9 6 6 4
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 17 03062006-7m17-pxbc 2.3 addressing this chapter describes the ddr2 addressing. table 10 256 mb ddr2 addressing configuration 64 mb x 4 1) 1) referred to as ?org? 32 mb x 8 2) 2) referred to as ?org? 16 mb x16 3) 3) referred to as ?org? note bank address ba[ 1:0] ba[1:0] ba[1:0] number of banks 4 4 4 auto precharge a10 / ap a10 / ap a10 / ap row address a[12:0] a[12:0] a[12:0] column address a11, a[9:0] a[9:0] a[8:0] number of column address bits 11 10 9 4) 4) referred to as ?colbits? number of i/os 4 8 16 page size [bytes] 1024 (1 k) 1024 (1 k) 1024 (1 k) 5) 5) pagesize = 2 colbits org/8 [bytes]
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 18 03062006-7m17-pxbc 3 functional description this chapter contains the functional description. 3.1 mode register set (mrs) the mode register stores the data for contro lling the various operating modes of ddr2 sdram. table 11 mode register definition, ba 2:0 = 000 b field bits type 1) description ba2 16 reg. addr. bank address 2 note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 bank address ba1 15 bank address 1 0 b ba1 bank address ba0 14 bank address 0 0 b ba0 bank address a13 13 address bus note: a13 is not available for 256 mb it and x16 512 mbit configuration 0 b a13 address bit 13 pd 12 w active power-down mode select 0 b pd fast exit 1 b pd slow exit wr [11:9] w write recovery 2) note: all other bit combinations are illegal. 001 b wr 2 010 b wr 3 011 b wr 4 100 b wr 5 101 b wr 6 dll 8 w dll reset 0 b dll no 1 b dll yes 03%7 %$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 3' :5 %/ uhjdggu z z zzzz '// 70 &/ %7 z
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 19 03062006-7m17-pxbc tm 7 w test mode 0 b tm normal mode 1 b tm vendor specific test mode cl [6:4] w cas latency note: all other bit combinations are illegal. 011 b cl 3 100 b cl 4 101 b cl 5 110 b cl 6 111 b cl 7 bt 3 w burst type 0 b bt sequential 1 b bt interleaved bl [2:0] w burst length note: all other bit combinations are illegal. 010 b bl 4 011 b bl 8 1) w = write only register bits 2) number of clock cycles for write re covery during auto-precharge. wr in cl ock cycles is calc ulated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr [cycles] t wr (ns) / t ck (ns). the mode register must be programmed to fulfill the minimum requirement for the analogue t wr timing wr min is determined by t ck.max and wr max is determined by t ck.min . field bits type 1) description
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 20 03062006-7m17-pxbc 3.2 extended mode register emr(1) the extended mode register emr(1) stores the data for enabling or disabling the dll, output driver stre ngth, additive latency, ocd program, odt, dqs and output buffers disable, rdqs and rdqs enable. table 12 extended mode register definition, ba 2:0 = 001 b field bits type 1) description ba2 16 reg. addr. bank address 2 note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 bank address ba1 15 bank address 1 0 b ba1 bank address ba0 14 bank address 0 1 b ba0 bank address a13 13 w address bus note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a13 address bit 13 qoff 12 w output disable 0 b qoff output buffers enabled 1 b qoff output buffers disabled rdqs 11 w read data strobe output (rdqs, rdqs ) 0 b rdqs disable 1 b rdqs enable dqs 10 w complement data strobe (dqs output) 0 b dqs enable 1 b dqs disable ocd program [9:7] w off-chip driver ca libration program 000 b ocd ocd calibration mode exit, maintain setting 001 b ocd drive (1) 010 b ocd drive (0) 100 b ocd adjust mode 111 b ocd ocd calibration default al [5:3] w additive latency note: all other bit combinations are illegal. 000 b al 0 001 b al 1 010 b al 2 011 b al 3 100 b al 4 0 3 % 7 % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 4 r i i 5 ' 4 6 ' 4 6 2 & ' 3 u r j u d p 5 w w $/ 5 w w ' , & ' // u h j d g g u z z z z z z z z
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 21 03062006-7m17-pxbc r tt 6,2 w nominal termination resistance of odt note: see table 22 ?odt dc electrical ch aracteristics? on page 28 00 b rtt (odt disabled) 01 b rtt 75 ohm 10 b rtt 150 ohm 11 b rtt 50 ohm dic 1 w off-chip driver im pedance control 0 b dic full (driver size = 100%) 1 b dic reduced dll 0 w dll enable 0 b dll enable 1 b dll disable 1) w = write only register bits field bits type 1) description
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 22 03062006-7m17-pxbc 3.3 extended mode register emr(2) the extended mode registers emr(2) and em r(3) are reserved for future use and must be programmed when setting the mode register during initialization. table 13 emr(2) programming extended mode register definition, ba 2:0 =010 b 1) w = write only 2) when dram is operated at 85 c t case 95 c the extended self refresh rate must be enabled by setting bit a7 to 1 before the self refresh mode can be entered. 3) if pasr (partial array self refresh) is enabled, data located in areas of the array beyond the specified location will be los t if self refresh is entered. data integrity will be maintained if t ref conditions are met and no self refresh command is issued. field bits type 1) description ba [15:14] w bank adress 00 b ba mrs 01 b ba emrs(1) 10 b ba emrs(2) 11 b ba emrs(3): reserved a [13:8] w address bus note: a13 is not available for 256 mbit and x16 512 mbit configuration 000000 b a address bits srf 7 w address bus, high temperature self refresh rate for t case > 85 c 0 b a7 disable 1 b a7 enable 2) a [6:4] w address bus 000 b a address bits dcc 3 w address bus, duty cycle correction (dcc) 0 b a3 dcc disabled 1 b a3 dcc enabled partial self refresh for 4 banks pasr [2:0] w address bus, partial array self refresh for 4 banks 2) note: only for 256 mbit and 512 mbit components 000 b pasr0 full array 001 b pasr1 half array (ba[1:0]=00, 01) 010 b pasr2 quarter array (ba[1:0]=00) 011 b pasr3 not defined 100 b pasr4 3/4 array (ba[1:0]=01, 10, 11) 101 b pasr5 half array (ba[1:0]=10, 11) 110 b pasr6 quarter array (ba[1:0]=11) 111 b pasr7 not defined 03%7 %$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ uhjdggu 65) '&& 3$65
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 23 03062006-7m17-pxbc 3.4 extended mode register emr(3) the extended mode register emr(3) is reserved for future us e and all bits except ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. table 14 emr(3) programming extended mode register definition, ba 2:0 =011 b field bits type 1) 1) w = write only description ba2 16 reg.addr bank address 2 note: ba2 is not available on 256mbit and 512mbit components 0 b ba2 bank address ba1 15 bank adress 1 1 b ba1 bank address ba0 14 bank adress 0 1 b ba0 bank address a [13:0] w address bus 13:0 note: a13 is not available for 256 mbit and x16 512 mbit configuration 00000000000000 b a[13:0] address bits 0 3 % 7 % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ u h j d g g u
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 24 03062006-7m17-pxbc 3.5 burst mode operation table 15 burst length and sequence burst length star ting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 25 03062006-7m17-pxbc 4 truth tables this chapter describes the truth tables. table 16 command truth table function cke cs ras cas we ba0 ba1 a[12:11] a10 a[9:0] note 1)2)3) 1) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 2) ?x? means h or l (but a defined logic level)?. 3) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initializa tion sequence before normal operation can continue. previous cycle current cycle (extended) mode register set h h l l l l ba op code 4)5)6) 4) all ddr2 sdram commands are defined by states of cs , we , ras , cas and cke at the rising edge of the clock. 5) bank addresses ba[1:0] determine which bank is to be operated upon. for (e)mrs ba[1:0] selects an (extended) mode register. 6) all banks must be in a precharged idle state, cke must be high at least for t xp and all read/write bursts must be finished before the (extended) mode register set command is issued. auto-refresh h h l l l h x x x x 4) self-refresh entry h l l l l h x x x x 4)7) 7) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 4)7)8) 8) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x 4)5) precharge all banks h h l l h l x x h x 4)5) bank activate h h l l h h ba row address 4)5) write h h l h l l ba column l column 4)5)9) 9) burst reads or writes at bl = 4 cannot be terminated. see chapter 3.5 for details. write with auto-precharge h h l h l l ba column h column 4)5)9) read h h l h l h ba column l column 4)5)9) read with auto-precharge h h l h l h ba column h column 4)5)9) no operation h x l h h h x x x x 4) device deselect h x h x x x x x x x 4) power down entry h l h x x x x x x x 4)10) 10) the power down mode does not perform any refresh operations. t he duration of power down is therefore limited by the refresh requirements. lh h h power down exit l h h x x x x x x x 4)10) lh h h
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 26 03062006-7m17-pxbc table 17 clock enable (cke) truth table for synchronous transitions table 18 data mask (dm) truth table current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2)3) ras, cas, we, cs 2) command (n) is the command registered at clock e dge n, and action (n) is a result of command (n) 3) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. action (n) 2) note 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initializa tion sequence before normal operation can continue. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; c ke (n-1) was the state of cke at the previous clock edge. current cycle 6) (n) power-down l l x maintain power-down 7)8)11) 7) the power-down mode does not perform any refresh operations. the duration of power-down mode is therefor limited by the refre sh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 7)9)10)11) 9) all states and sequences not shown ar e illegal or reserved unless explicitly described else where in this document. 10) valid commands for power-down entry and exit are nop and deselect only. 11) t cke.min of 3 clocks means cke must be registered on three consecutive positive cl ock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 clo cks of registration. thus, after any cke tr ansition, cke may not transition from its v alid level during the time period of t is + 2 t ck + t ih . self refresh l l x maintain self refresh 8)11)12) 12) v ref must be maintained during self refresh operation. l h deselect or nop self refresh exit 9)11)12)13)14) 13) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 14) valid commands for self refresh exit are nop and deselct only. bank(s) active h l deselect or nop active power-down entry 7)9)10)11)15) 15) power-down and self refresh can not be entered while read or wr ite operations, (extended) mode register operations, precharge o r refresh operations are in progress. all banks idle h l deselect or nop precharge power-down entry 9)10)11)15) h l autorefresh self refresh entry 7)11)14)16) 16) self refresh mode can only be entered from the all banks idle state. any state other than listed above h h refer to the command truth table 17) 17) must be a legal command as defined in the command truth table. name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit h x
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 27 03062006-7m17-pxbc 5 electrical characteristics this chapter describes the electrical characteristics. 5.1 absolute maximum ratings caution is needed not to exceed absolute maximum ratings of the dram device listed in table 19 at any time. table 19 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 20 dram component operating temperature range symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v 1) t stg storage temperature ?55 +100 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. symbol parameter rating unit notes min. max. t oper operating temperature 0 +95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dram specification will be suppor ted. during operation, the dr am case temperature must be maintained between 0 - 95 c for hyb... produc ts and -40 - +85 for hyi... pr oducts under all other specifica tion parameters. 3) above 85 c the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c tcase tem perature range, the high temperature self refresh has to be enable d by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50% -40 +85
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 28 03062006-7m17-pxbc 5.2 dc characteristics table 21 recommended dc operating conditions (sstl_18) table 22 odt dc electrical characteristics table 23 input and output leakage currents symbol parameter rating unit note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1) 1) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v 1) v ddq supply voltage for output 1.7 1.8 1.9 v 1) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2)3) 2) the value of v ref may be selected by the user to provide optimum noi se margin in the system. typically the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal terminati on resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . parameter / condition symbol min. nom. max. unit note termination resistor impedance value for emrs(1 )[a6,a2] = [0,1]; 75 ohm rtt1(eff) 60 75 90 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i(v ihac ) and i(v ilac ) respectively. rtt(eff) = (v ih(ac) ? v il(ac) ) /(i(v ihac ) ? i(v ilac )). termination resistor impedance value for emrs(1 )[a6,a2] =[1,0]; 150 ohm rtt2(eff) 120 150 180 1) termination resistor impedance value for emrs (1)(a6,a2)=[1,1]; 50 ohm rtt3(eff) 40 50 60 1)2) 2) optional for ddr2-400, ddr2-533 and ddr2-667, mandatory for ddr2-800. deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 3) 3) measurement definition for v m : turn odt on and measure voltage (v m ) at test pin (midpoint) with no load: delta v m =((2 xv m /v ddq )? 1) x 100% symbol parameter / condition min. max. unit note i il input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v i ol output leakage current; 0 v < vout < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs , rdqs, rdqs are disabled and odt is turned off
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 29 03062006-7m17-pxbc 5.3 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system des ign. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these ti ming relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and characterization but not subject to production test. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. table 24 dc & ac logic input levels table 25 single-ended ac input test conditions symbol parameter ddr2-667, ddr2-800 ddr2-533, ddr2-400 units min. max. min. max. v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.200 ? v ref + 0.250 ? v v il(ac) ac input low ? v ref ? 0.200 ? v ref - 0.250 v symbol condition value unit notes v ref input reference voltage 0.5 x v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing.max input signal maximum peak to peak swing 1.0 v 1) slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac).min to v ref for rising edges and the range from v ref to v il(ac).max for falling edges as shown in figure 4 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac) on the negative transitions.
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 30 03062006-7m17-pxbc figure 4 single-ended ac input test conditions diagram table 26 differential dc and ac in put and output logic levels figure 5 differential dc and ac input and output logic levels diagram symbol parameter min. max. unit notes v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 ? 1) 1) v in(dc) specifies the allowable dc execution of eac h input of differential pair such as ck, ck , dqs, dqs etc. v id(dc) dc differential input voltage 0.25 v ddq + 0.6 ? 2) 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . v id(ac) ac differential input voltage 0.5 v ddq + 0.6 v 3) 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) 4) the value of v ix(ac) is expected to equal 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which differential input signals must cross. v ox(ac) ac differential cross point output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 5) the value of v ox(ac) is expected to equal 0.5 v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which differential input signals must cross. 03(7 'howd75 'howd7) 9 6:,1*0$; 9 ''4 9 ,+df plq 9 ,+gf plq 9 5() 9 ,/gf pd[ 9 ,/df pd[ 9 66 5lvlqj6ohz 9 ,+df plq9 5() 'howd75 9 5() 9 ,/df pd[ )doolqj6ohz 'howd7) & u r v v l q j 3 r l q w 9 ' ' 4 9 6 6 4 9 , ' 9 , ; r u 9 2 ; 9 7 5 9 & 3
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 31 03062006-7m17-pxbc 5.4 output buffer characteristics this chapter describes the output buffer characteristics. table 27 sstl_18 output dc current drive table 28 sstl_18 output ac test conditions symbol parameter sstl_18 unit notes i oh output minimum source dc current ?13.4 ma 1)2) 1) v ddq = 1.7 v; v out = 1.42 v. ( v out ? v ddq ) / i oh must be less than 21 for values of v out between v ddq and v ddq ? 280 mv. 2) the values of i oh(dc) and i ol(dc) are based on the conditions given in 1) and 3) . they are used to test driv e current capability to ensure v ih.min . plus a noise margin and v il.max minus a noise margin are delivered to an sstl_18 rece iver. the actual current values are derived by shifting the desired driver operating points along 21 ohm lo ad line to define a convenient current for measurement. i ol output minimum sink dc current 13.4 ma 2)3) 3) v ddq = 1.7 v; v out = 280 mv. v out / i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. symbol parameter sstl_18 unit note v oh minimum required output pull-up v tt + 0.603 v 1) 1) sstl_18 test load for v oh and v ol is different from the referenced load . the sstl_18 te st load has a 20 ohm series resistor additionally to the 25 ohm termination resistor into v tt . the sstl_18 definition assumes that 335 mv must be developed across the effectively 25 ohm termination resistor (13.4 ma 25 ohm = 335 mv). with an additional series resistor of 20 ohm this translates into a minimum requirement of 603 mv swing relative to v tt , at the ouput device (13.4 ma 45 ohm = 603 mv). v ol maximum required output pull-down v tt ? 0.603 v 1) v otr output timing measurement reference level 0.5 v ddq v
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 32 03062006-7m17-pxbc table 29 ocd default characteristics symbol description min. nominal max. unit notes ? output impedance 1)2) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) impedance measurement condition for output source dc current: v ddq = 1.7 v, v out = 1420 mv; ( v out ? v ddq ) / i oh must be less than 23.4 ohms for values of v out between v ddq and v ddq ? 280 mv. impedance measurement conditi on for output sink dc current: v ddq = 1.7 v; v out = ?280 mv; v out / i ol must be less than 23.4 ohms for values of v out between 0 v and 280 mv. ? pull-up / pull down mismatch 0 ? 4 1)2)3) 3) mismatch is absolute value between pull-up and pull- down, both measured at same temperature and voltage. ? output impedance step size for ocd calibration 0 ? 1.5 4) 4) this represents the step size when the ocd is near 18 ohms at nominal conditions across all process parameters and represents only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd impedance is 18 0.75 ohms under nominal conditions. s out output slew rate 1.5 ? 5.0 v / ns 1)5)6)7)8) 5) slew rates v il(ac) to v ih(ac) . 6) the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac t o ac. this is verified by design and characterization but not subject to production test. 7) timing skew due to dram output slew rate mis-match between dqs / dqs and associated dq?s is included in t dqsq and t qhs specification. 8) dram output slew rate specification app lies to 400, 533 and 667 mt/s speed bins.
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 33 03062006-7m17-pxbc 5.5 input / output capacitance this chapter contains the input / output capacitance. table 30 input / output capacitance symbol parameter ddr2-800 ddr2-667 ddr2-533 ddr2-400 unit min. max. min. max. min. max. min. max. cck input capacitance, ck and ck 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 pf cdck input capacitance delta, ck and ck ? 0.25 ? 0.25 ? 0.25 ? 0.25 pf ci input capacitance, all other input-only pins 1.0 1.75 1.0 2.0 1.0 2.0 1.0 2.0 pf cdi input capacitance delta, all other input- only pins ? 0.25 ? 0.25 ? 0.25 ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs 2.5 3.5 2.5 3.5 2.5 4.0 2.5 4.0 pf cdio input/output capacitance delta, dq, dm, dqs, dqs ?0.5?0.5?0.5?0.5pf
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 34 03062006-7m17-pxbc 5.6 overshoot and undershoot specification this chapter contains overshoot and undershoot specification. table 31 ac overshoot / undershoot specification for address and control pins figure 6 ac overshoot / undershoot diagram for address and control pins parameter ddr2-400 ddr2-533 ddr2-667 ddr2-800 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 0.9 v maximum overshoot area above v dd 1.33 1.00 0.8 0.66 v-ns maximum undershoot area below v ss 1.33 1.00 0.8 0.66 v-ns 03(7 9rowv9 9 '' 9 66 0d[lpxp$psolwxgh 7lphqv 0d[lpxp$psolwxgh 2yhuvkrrw$uhd 8qghuvkrrw$uhd
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 35 03062006-7m17-pxbc table 32 ac overshoot / undershoot specification for clock, data, strobe and mask pins figure 7 ac overshoot / undershoot diagram for clock, data, strobe and mask pins parameter ddr2-400 ddr2-533 ddr2-667 ddr2-800 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 0.9 v maximum overshoot area above v ddq 0.38 0.28 0.23 0.23 v-ns maximum undershoot area below v ssq 0.38 0.28 0.23 0.23 v-ns 03(7 9rowv9 9 ''4 9 664 0d[lpxp$psolwxgh 7lphqv 0d[lpxp$psolwxgh 2yhuvkrrw$uhd 8qghuvkrrw$uhd
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 36 03062006-7m17-pxbc 6 currents measurement conditions this chapter describes the current measurement, specifications and conditions. table 33 i dd measurement conditions parameter symbol note operating current - one bank active - precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , cke is high, cs is high between valid commands. address and control inputs are switch ing; databus inputs are switching. i dd0 1)2)3)4)5)6) operating current - one bank active - read - precharge i out = 0 ma, bl = 4, t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , t rcd = t rcd(idd) , al = 0, cl = cl(idd); cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd1 1)2)3)4)5)6) precharge power-down current all banks idle; cke is low; t ck = t ck(idd) ;other control and address inputs are stable; data bus inputs are floating . i dd2p 1)2)3)4)5)6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are switching, data bus inputs are switching . i dd2n 1)2)3)4)5)6) precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are stable, data bus inputs are floating. i dd2q 1)2)3)4)5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to 0 (fast power-down exit). i dd3p(0) 1)2)3)4)5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to 1 (slow power-down exit); i dd3p(1) 1)2)3)4)5)6) active standby current all banks open; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd3n 1)2)3)4)5)6) operating current burst read: all banks open; continuous bu rst reads; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max.(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r 1)2)3)4)5)6) operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w 1)2)3)4)5)6) burst refresh current t ck = t ck(idd) , refresh command every t rfc = t rfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b 1)2)3)4)5)6) distributed refresh current t ck = t ck(idd) , refresh command every t refi = 7.8 s interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d 1)2)3)4)5)6)
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 37 03062006-7m17-pxbc detailed i dd7 the detailed timings are shown below for idd7. changes will be required if timing parameter changes are made to the specification. legend: a = active; ra = read with autoprecharge; d = deselect. i dd7 : operating current: all bank interleave read operation all banks are being interleaved at minimum t rc.idd without violating t rrd.idd using a burst length of 4. control and address bus inputs are stable during deselects. iout = 0 ma. table 34 definition for i dd self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 1)2)3)4)5)6) operating bank interleave read current 1. all banks interleaving reads, i out = 0 ma; bl = 4, cl = cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. 2. timing pattern: see detailed i dd7 timings shown below. i dd7 1)2)3)4)5)6) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. 2) i dd specifications are tested after the device is properly initialized. 3) i dd parameter are specified with odt disabled. 4) data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs and udqs . 5) definitions for i dd , see table 34 . 6) timing parameter minimum and maximum values for i dd current measurements are defined in chapter 7. ddr2-400 3-3-3: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d ddr2-533 4-4-4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d ddr2-667 5-5-5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d ddr2-667 4-4-4: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d ddr2-800 6-6-6: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d d ddr2-800 5-5-5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d parameter description low defined as v in v il.ac.max high defined as v in v ih.ac.min stable defined as inputs are stable at a high or low level floating defined as inputs are v ref = v ddq / 2 switching defined as: inputs are changing between high and lo w every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for dq signals not including mask or strobes parameter symbol note
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 38 03062006-7m17-pxbc table 35 i dd specification symbol ?25f ?2.5 ?3 ?3s ?3.7 ?5 unit note ddr2-800d ddr2-800e ddr2-667c ddr2-667d ddr2-533c ddr2-400b max. max. max. max. max. max. i dd0 80 75 65 62 55 50 ma 4/ 8/ 16 i dd1 90 85 75 71 60 55 ma 4/ 8/ 16 i dd2p 5.0 5.0 5.0 5.0 4.5 4.5 ma i dd2p low power 2.0 ma i dd2n 50 50 45 45 35 28 ma i dd2q 35 35 30 30 25 20 ma i dd3p_0 (fast) 22 22 19 19 16 13 ma 1) 1) mrs(12)=0 i dd3p_1 (slow) 5.0 5.0 5.0 5.0 4.5 4.5 ma 2) 2) mrs(12)=1 i dd3n 50 50 45 45 35 30 ma i dd4r 125 125 110 110 90 70 ma 4/ 8 i dd4r 175 175 145 145 115 90 ma 16 i dd4w 135 135 115 115 95 75 ma 4/ 8 i dd4w 190 190 160 160 130 105 ma 16 i dd5b 95 95 95 95 90 85 ma i dd5d 666666ma 3) 3) 0 t case 85 c. i dd6 4.5 4.5 4.5 4.5 4.5 4.5 ma 3) i dd6 low power 2.0 i dd7 165 155 145 138 135 125 ma 4/ 8 i dd7 180 170 165 157 150 140 ma 16
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 39 03062006-7m17-pxbc 7 timing characteristics this chapter contains speed grade definition, ac timing parameter and odt tables. 7.1 speed grade definitions table 36 speed grade definition speed grade ddr2?800d ddr2?800e unit note qag sort name ?25f ?2.5 cas-rcd-rp latencies 5?5?5 6?6?6 t ck parameter symbol min. max. min. max. ? clock period @ cl = 3 t ck 5858ns 1)2)3)4) @ cl = 4 t ck 3.75 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 2.5838ns 1)2)3)4) @ cl = 6 t ck 2.5 8 2.5 8 ns 1)2)3)4) row active time t ras 45 70k 45 70k ns 1)2)3)4)5) row cycle time t rc 57.5 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12.5 ? 15 ? ns 1)2)3)4) row precharge time t rp 12.5 ? 15 ? ns 1)2)3)4)
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 40 03062006-7m17-pxbc table 37 speed grade definition 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) . 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. . 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq 4) the output timing reference voltage level is v tt . 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . speed grade ddr2?667c ddr2?667d ddr2?533c ddr2?400b unit note qag sort name ?3 ?3s ?3.7 ?5 cas-rcd-rp latencies 4?4?4 5?5?5 4?4?4 3?3?3 t ck parameter symbol min. max. min. max. min. max. min. max. ? clock period @ cl = 3 t ck 58585858ns 1)2)3)4) @ cl = 4 t ck 383.7583.75858ns 1)2)3)4) @ cl = 5 t ck 38383.75858ns 1)2)3)4) row active time t ras 45 70k 45 70k 45 70k 40 70k ns 1)2)3)4)5) row cycle time t rc 57?60?60?55?ns 1)2)3)4) ras-cas-delay t rcd 12?15?15?15?ns 1)2)3)4) row precharge time t rp 12?15?15?15?ns 1)2)3)4)
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 41 03062006-7m17-pxbc 7.2 component ac timing parameters table 38 dram component timing parameter by speed grade - ddr2?800 and ddr2?667 parameter symbol ddr2?800 ddr2?667 unit note 1)2)3 )4)5)6)7) min. max. min. max. dq output access time from ck / ck t ac ?400 +400 ?450 +450 ps 8) cas to cas command delay t ccd 2?2?nck average clock high pulse width t ch.avg 0.48 0.52 0.48 0.52 t ck.avg 9)10) average clock period t ck.avg 2500 8000 3000 8000 ps cke minimum pulse width ( high and low pulse width) t cke 3?3?nck 11) average clock low pulse width t cl.avg 0.48 0.52 0.48 0.52 t ck.avg 9)10) auto-precharge write recovery + precharge time t dal wr + t nrp ?wr+ t nrp ?nck 12)13) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck .avg + t ih ?? t is + t ck .avg + t ih ?? ns dq and dm input hold time t dh.base 125 ?? 175 ?? ps 14)18)19) dq and dm input pulse width for each input t dipw 0.35 ? 0.35 ? t ck.avg dqs output access time from ck / ck t dqsck ?350 +350 ?400 +400 ps 8) dqs input high pulse width t dqsh 0.35 ? 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? 0.35 ? t ck.avg dqs-dq skew for dqs & associated dq signals t dqsq ? 200 ? 240 ps 15) dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 ? 0.25 + 0.25 t ck.avg 16) dq and dm input setup time t ds.base 50 ?? 100 ?? ps 17)18)19) dqs falling edge hold time from ck t dsh 0.2 ? 0.2 ? t ck.avg 16) dqs falling edge to ck setup time t dss 0.2 ? 0.2 ? t ck.avg 16) ck half pulse width t hp min( t ch.abs , t cl.abs ) __ min( t ch.abs , t cl.abs ) __ ps 20) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ps 8)21) address and control input hold time t ih.base 250 ? 275 ? ps 22)24) control & address input pulse width for each input t ipw 0.6 ? 0.6 ? t ck.avg address and control input setup time t is.base 175 ? 200 ? ps 23)24) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max 2x t ac.min t ac.max ps 8)21) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max t ac.min t ac.max ps 8)21) mrs command to odt update delay t mod 0 12 0 12 ns 34)
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 42 03062006-7m17-pxbc 1) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the reference load for timing measurements. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . mode register set command cycle time t mrd 2?2?nck ocd drive mode output delay t oit 0 12 0 12 ns 34) dq/dqs output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?ps 25) dq hold skew factor t qhs ? 300 ? 340 ps 26) average periodic refresh interval t refi ?7.8?7.8 s 27)28) ?3.9?3.9 s 27)29) auto-refresh to active/auto-refresh command period t rfc 75 ? 75 ? ns 30) read preamble t rpre 0.9 1.1 0.9 1.1 t ck.avg 31)32) read postamble t rpst 0.4 0.6 0.4 0.6 t ck.avg 31)33) active to active command period for 1kb page size products t rrd 7.5 ? 7.5 ? ns 34) internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns 34) write preamble t wpre 0.35 ? 0.35 ? t ck.avg write postamble t wpst 0.4 0.6 0.4 0.6 t ck.avg write recovery time t wr 15 ? 15 ? ns 34) internal write to read command delay t wtr 7.5 ? 7.5 ? ns 34)35) exit power down to read command t xard 2?2?nck exit active power-down mode to read command (slow exit, lower power) t xards 8 ? al ? 7 ? al ? nck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2?nck exit self-refresh to a non-read command t xsnr t rfc +10 ? t rfc +10 ? ns 34) exit self-refresh to read command t xsrd 200 ? 200 ? nck write command to dqs associated clock edges wl rl ? 1 rl?1 nck parameter symbol ddr2?800 ddr2?667 unit note 1)2)3 )4)5)6)7) min. max. min. max.
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 43 03062006-7m17-pxbc 8) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 9) input clock jitter spec parameter. these parameters and the ones in chapter 7.3 are referred to as 'input clock jitter spec parameters' and these parameters apply to ddr2?667 and ddr2?800 only. the jitter spec ified is a random jitter m eeting a gaussian distribution. 10) these parameters are specified per their average values, how ever it is understood that the relationship as defined in chapter 7.3 between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for ca lculations of chapter 7.3 ). 11) t cke.min of 3 clocks means cke must be registered on three consecutive po sitive clock edges. cke must rema in at the valid input level t he entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 12) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 13) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 14) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refe renced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 9 . 15) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 16) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 17) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is re ferenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the inpu t signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal appli ed to the device under test. dqs, dq s signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 9 . 18) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 19) these parameters are measured from a data signal ((l/u)dm, (l/u )dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 20) t hp is the minimum of the absolute hal f period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 21) t hz and t lz transitions occur in the same access time as valid data trans itions. these parameters are referenced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 22) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 10 . 23) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 10 . 24) these parameters are measured from a comm and/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 25) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 26) t qhs accounts for: 1) the pulse duration distortion of on-chip clock circuits, which represents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to da ta pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 27) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 28) 0 c t case 85 c. 29) 85 c < t case 95 c.
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 44 03062006-7m17-pxbc 30) a maximum of eight refresh commands can be posted to any giv en ddr2 sdram, meaning that the maximum absolute interval betwe en any refresh command and the next refresh command is 9 x t refi . 31) t rpst end point and t rpre begin point are not referenced to a specific voltage leve l but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 8 shows a method to calculate these point s when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. 32) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 33) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 34) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input cloc k jitter specifications are met, prechar ge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 35) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency.
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 45 03062006-7m17-pxbc table 39 dram component timing parameter by speed grade - ddr2?533 and ddr2?400 parameter symbol ddr2?533 ddr2?400 unit notes 1)2) 3)4)5)6) min. max. min. max. dq output access time from ck / ck t ac ?500 +500 ?600 +600 ps cas a to cas b command period t ccd 2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 t ck cke minimum high and low pulse width t cke 3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ?wr+ t rp ? t ck 7) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh.base 225 ?? 275 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1.base ?25 ? 25 ? ps 10) dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ?500 + 500 ps dqs input high pulse width (write cycle) t dqsh 0.35 ? 0.35 ? t ck dqs input low pulse width (write cycle) t dqsl 0.35 ? 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ? 350 ps 10) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds.base 100 ? 150 ? ps 10) dq and dm input setup time (single ended data strobe) t ds1.base ?25 ? 25 ? ps 10) dqs falling edge hold time from ck (write cycle) t dsh 0.2? 0.2? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2? 0.2? t ck clock half period t hp min. ( t cl, t ch ) min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ps 12) address and control input hold time t ih.base 375 ? 475 ? ps 10)
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 46 03062006-7m17-pxbc address and control input pulse width (each input) t ipw 0.6? 0.6? t ck address and control input setup time t is.base 250 ? 350 ? ps 10) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max 2 t ac.min t ac.max ps 13) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max t ac.min t ac.max ps 13) mrs command to odt update delay t mod 0 12 0 12 ns mode register set command cycle time t mrd 2?2? t ck ocd drive mode output delay t oit 0 12 0 12 ns data output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ? data hold skew factor t qhs ? 400 ? 450 ps average periodic refresh interval t refi ?7.8?7.8 s 13)14) average periodic refresh interval t refi ? 3.9 ? 3.9 s 15)17) auto-refresh to active/auto- refresh command period t rfc 75 ? 75 ? ns 16) read preamble t rpre 0.91.10.91.1 t ck 13) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 13) active bank a to active bank b command period for 1 kb page size t rrd 7.5? 7.5? ns 13)17) internal read to precharge command delay t rtp 7.5? 7.5? ns write preamble t wpre 0.25 ? 0.25 ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 t ck 18) write recovery time for write without auto-precharge t wr 15 ? 15 ? ns internal write to read command delay t wtr 7.5 ? 10 ? ns 19) exit power down to any valid command (other than nop or deselect) t xard 2?2? t ck 20) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? 6 ? al ? t ck 20) exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? t rfc +10 ? ns parameter symbol ddr2?533 ddr2?400 unit notes 1)2) 3)4)5)6) min. max. min. max.
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 47 03062006-7m17-pxbc 1) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. . timings are further guaranteed f or normal ocd drive strength (emrs(1) a1 = 0) under the reference load for timing measurements . 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. . 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) for timing definition, refer to the component data sheet. 10) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, wh ich specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access ti me windows as valid data transitions.these parameters are verified by design and characteri zation, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 c t case 85 c. 15) 85 c < t case 95 c. 16) a maximum of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval betwee n any refresh command and the next refresh command is 9 x t refi . 17) the t rrd timing parameter depends on the page size of the dram organization. 18) the maximum limit for the t wpst parameter is not a device limit. the device operates wi th a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 20) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. 21) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. exit self-refresh to read command t xsrd 200 ? 200 ? t ck write recovery time for write with auto-precharge wr t wr / t ck t wr / t ck t ck 21) parameter symbol ddr2?533 ddr2?400 unit notes 1)2) 3)4)5)6) min. max. min. max.
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 48 03062006-7m17-pxbc figure 8 method for calculating transitions and endpoint figure 9 differential input waveform timing - t ds and t dh

9 ''4 9 ,+$&0,1 9 ,+'&0,1 9 5() 9 ,/'&0$; 9 ,/$&0$; 9 66 03(7 w '6 w '+ w '6 w '+ '46 '46 '4
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 49 03062006-7m17-pxbc figure 10 differential input waveform timing - t ls and t lh 9 ''4 9 ,+$&0,1 9 ,+'&0,1 9 5() 9 ,/'&0$; 9 ,/$&0$; 9 66 03(7 w ,6 w ,+ w ,6 w ,+ &. &. &0' $gguhvv
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 50 03062006-7m17-pxbc 7.3 jitter definition and clock jitter specification generally, jitter is defined as ?the short-term variation of a si gnal with respect to its ideal position in time?. the followin g table provides an overview of the terminology. table 40 average clock and jitter symbols and definition symbol parameter description units t ck.avg average clock period t ck.avg is calculated as the average clo ck period within any consecutive 200-cycle window: n=200 ps t jit.per clock-period jitter t jit.per is defined as the largest deviation of any single t ck from t ck.avg : t jit.per =min/maxof{ t cki ? t ck.avg } where i = 1 to 200 t jit.per defines the single-period jitter when the dll is already locked. t jit.per is not guaranteed through final production testing. ps t jit (per, lck) clock-period jitter during dll-locking period t jit (per,lck) uses the same definition as t jit.per , during the dll-locking period only. t jit (per,lck) is not guaranteed through final production testing. ps t jit.cc cycle-to-cycle clock period jitter t jit.cc is defined as the absolute difference in clock period between two consecutive clock cycles: t jit.cc = max of abs{ t cki+1 ? t cki } t jit.cc defines the cycle - to - cycle jitte r when the dll is already locked. t jit.cc is not guaranteed through final production testing. ps t jit (cc, lck) cycle-to-cycle clock period jitter during dll-locking period t jit (cc,lck) uses the same definition as t jit.cc during the dll-locking period only. t jit (cc,lck) is not guaranteed through final production testing. ps t err.2per cumulative error across 2 cycles t err.2per is defined as the cumulative error across 2 consecutive cycles from t ck.avg : n=2 for t err (2per) where i = 1 to 200 ps

hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 51 03062006-7m17-pxbc the following parameters are specified per their average values however, it is understood t hat the following relationship between the average timing and the absolut e instantaneous timing holds all the time. t err.nper cumulative error across n cycles t err.2per is defined as the cumulative error across n consecutive cycles from t ck.avg : where, i = 1 to 200 and n=3 for t err.3per n = 4 for t err.4per n = 5 for t err.5per 6 n 10 for t err.6-10per 11 n 50 for t err.11-50per ps t ch.avg average high-pulse width t ch.avg is defined as the average high-pulse width, as calculated across any consecutive 200 high pulses: n=200 t ck.avg t cl.avg average low-pulse width t cl.avg is defined as the average low-puls e width, as calculated across any consecutive 200 low pulses: n=200 t ck.avg t jit.duty duty-cycle jitter t jit.duty = min/max of { t jit.ch , t jit.cl }, where: t jit.ch is the largest deviation of any single t ch from t ch.avg t jit.cl is the largest deviation of any single t cl from t cl.avg t jit.ch = { t chi - t ch.avg t ck.avg } where i=1 to 200 t jit.cl = { t cli - t cl.avg t ck.avg } where i=1 to 200 ps symbol parameter description units

hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 52 03062006-7m17-pxbc table 41 absolute jitter value definitions example: for ddr2-667, t ch.abs.min = (0.48 x 3000ps) ? 125 ps = 1315 ps = 0.438 x 3000 ps. table 42 shows clock-jitter specifications. table 42 clock-jitter specifications for ?667, ?800 symbol parameter min. max. unit t ck.abs clock period t ck.avg(min) + t jit.per(min) t ck.avg(max) + t jit.per(max) ps t ch.abs clock high-pulse width t ch.avg(min) x t ck.avg(min) + t jit.duty(min) t ch.avg(max) x t ck.avg(max) + t jit.duty(max) ps t cl.abs clock low-pulse width t cl.avg(min) x t ck.avg(min) + t jit.duty(min) t cl.avg(max) x t ck.avg(max) + t jit.duty(max) ps symbol parameter ddr2 -667 ddr2 -800 unit min. max. min. max. t ck.avg average clock period nominal w/o jitter 3000 8000 2500 8000 ps t jit.per clock-period jitter ?125 +125 ?100 +100 ps t jit(per,lck) clock-period jitter during dll locking period ?100 +100 ?80 +80 ps t jit.cc cycle-to-cycle clock-period jitter ?250 + 250 ?200 +200 ps t jit(cc,lck) cycle-to-cycle clock-period jitter during dll-locking period ?200 +200 ?160 +160 ps t err.2per cumulative error across 2 cycles ?175 +175 ?150 +150 ps t err.3per cumulative error across 3 cycles ?225 +225 ?175 +175 ps t err.4per cumulative error across 4 cycles ?250 +250 ?200 +200 ps t err.5per cumulative error across 5 cycles ?250 +250 ?200 +200 ps t err(6-10per) cumulative error across n cycles with n = 6 .. 10, inclusive ?350 +350 ?300 +300 ps t err(11-50per) cumulative error across n cycles with n = 11 .. 50, inclusive ?450 +450 ?450 +450 ps t ch.avg average high-pulse width 0.48 0.52 0.48 0.52 t ck.avg t cl.avg average low-pulse width 0.48 0.52 0.48 0.52 t ck.avg t jit.duty duty-cycle jitter ? 125 +125 ?100 +100 ps
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 53 03062006-7m17-pxbc 7.4 odt ac electrical characteristics this chapter describes the odt ac electrical characteristics. table 43 odt ac characteristics and operating conditions for ddr2-667 , ddr2-800 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 n ck 1) 1) new units, ? t ck.avg ? and ? n ck ?, are introduced in ddr2-667 and ddr2-800 unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ? n ck ? represents one clock cycle of the input clock, count ing the actual clock edges. note that in ddr2-400 and ddr2-533, ? t ck ? is used for both concepts. example: t xp = 2 [ n ck ] means; if power down exit is registered at t m , an active command may be registered at t m + 2, even if ( t m + 2 - t m ) is 2 x t ck.avg + t err.2per(min) . t aon odt turn-on t ac.min t ac.max +0.7ns ns 1)2) 2) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is w hen the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-667/800 t aond is 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges. t aonpd odt turn-on (power-down modes) t ac.min +2 ns 2 t ck + t ac.max +1 ns ns 1) t aofd odt turn-off delay 2.5 2.5 n ck 1) t aof odt turn-off t ac.min t ac.max +0.6ns ns 1)3) 3) odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-667/800, if t ck(avg) = 3 ns is assumed, t aofd is 1.5 ns (= 0.5 x 3 ns) after the se cond trailing clock edge counting from the cl ock edge that registered a first odt low and by counting the actual input clock edges. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max +1ns ns 1) t anpd odt to power down mode entry latency 3 ? n ck 1) t axpd odt power down exit latency 8 ? n ck 1)
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 54 03062006-7m17-pxbc table 44 odt ac characteristics and operating conditions for ddr2-533 & ddr2-400 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-400/533, t aond is 10 ns (= 2 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-400/533, t aofd is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 55 03062006-7m17-pxbc 8 package outline this chapter contains the package dimension figures. notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 figure 11 package outline p-tfbga-60 [ % [ $ 0 , 1 0 $ ; ? ? [ ? ? % 0 0 $ & 6 ( $ 7 , 1 * 3 / $ 1 ( & & ' x p p \ s d g v z l w k r x w e d o o 3 d f n d j h r u l h q w d w l r q p d u n $ 0 l g g o h r i s d f n d j h v h g j h v 0 $ ; 0 $ ; & % d g x q l w p d u n l q j % 8 0 0 ; $
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 56 03062006-7m17-pxbc figure 12 package outline p-tfbga-84 % 0$; 0lggoh ri sdfndjhv hgjhv 3dfndjh rulhqwdwlrq pdun $ 'xpp\ sdgv zlwkrxw edoo ? 0,1 ? ? ? $ [ 0 0 & & $ & [ 0$; )32b3b7)%*$bb 6($7,1* 3/$1( & & [ % 0$;
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 57 03062006-7m17-pxbc figure 13 package outline pg-tfbga-84 % 0 $; 0 l g g o h r i s d f n d j h v h g j h v 3 d f n d j h r u l h q w d w l r q p d u n $ ' x p p \ s d g v z l w k r x w e d o o ? 0 , 1 ? ? ? $ [ 0 0 & & $ & [ 0 $; ) 32 b 3 * 7 ) % * $b b 6 ( $ 7 , 1 * 3 /$1( & & [ % 0 $;
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 58 03062006-7m17-pxbc 9 product nomenclature for reference the qimonda sdram component nomenclature is enclosed in this chapter. table 45 examples for nomenclature fields table 46 ddr2 memory components example for field number 12345678910 ddr2 dram hyb 18 t 256 16 0 a c ?3.7 field description values coding 1 qimonda component prefix hyb memory components hyi memory components, industrial temperature range (-40c ? +85 c) 2 interface voltage [v] 18 sstl_18, + 1.8 v ( 0.1 v) 15 sstl_15, + 1.5 v ( 0.1 v) 3 dram technology t ddr2 4 component density [mbit] 32 32 mbit 64 64 mbit 128 128 mbit 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 4g 4 gbit 5 number of i/os 40 4 80 8 16 16 32 32 6 product variations 0 .. 9 look up table 7 die revision a ( 0...9 ) first b ( 0...9 ) second c ( 0...9 ) third 8 package, lead-free status c fbga, lead-containing f fbga, lead-free 9 power ? standard power product l low power product
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 59 03062006-7m17-pxbc 10 speed grade ?19f ddr2?1066 6?6?6 ?1.9 ddr2?1066 7?7?7 ?25f ddr2?800 5?5?5 ?2.5 ddr2?800 6?6?6 ?3 ddr2?667 4?4?4 ?3s ddr2?667 5?5?5 ?3.7 ddr2?533 4?4?4 ?5 ddr2?400 3?3?3 field description values coding
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 60 03062006-7m17-pxbc list of illustrations figure 1 chip configuration for 4 components, tfbga-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2 chip configuration for 8 components, tfbga-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3 configuration for 16 components, tfbga-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4 single-ended ac input test conditions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5 differential dc and ac input and output logic levels diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 6 ac overshoot / undershoot diagram for address and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7 ac overshoot / undershoot diagram for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8 method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 9 differential input waveform timing - t ds and t dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 10 differential input waveform timing - t ls and t lh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 11 package outline p-tfbga-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 12 package outline p-tfbga-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 13 package outline pg-tfbga-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 61 03062006-7m17-pxbc list of tables table 1 performance table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 ordering information for rohs compliant products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3 ordering information for non rohs compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5 abbreviations for ball type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8 abbreviations for ball type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10 256 mb ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11 mode register definition, ba 2:0 = 000 b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12 extended mode register definition, ba 2:0 = 001 b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13 emr(2) programming extended mode register definition, ba 2:0 =010 b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14 emr(3) programming extended mode register definition, ba 2:0 =011 b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17 clock enable (cke) truth table for synchronous transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18 data mask (dm) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 19 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20 dram component operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21 recommended dc operating conditions (sstl_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 22 odt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 23 input and output leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 24 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 25 single-ended ac input test condition s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 26 differential dc and ac input and output logic levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 27 sstl_18 output dc current drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 28 sstl_18 output ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 29 ocd default characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 30 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 31 ac overshoot / undershoot specification for address and co ntrol pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 32 ac overshoot / undershoot specification for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . . . . . . 35 table 33 i dd measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 34 definition for i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 35 i dd specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 36 speed grade definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 37 speed grade definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 38 dram component timing parameter by speed grade - ddr2?800 and ddr2?667 . . . . . . . . . . . . . . . . . . 41 table 39 dram component timing parameter by speed grade - ddr2?533 and ddr2?400 . . . . . . . . . . . . . . . . . . 45 table 40 average clock and jitter symbols and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 41 absolute jitter value definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 42 clock-jitter specifications for ?667, ?800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 43 odt ac characteristics and operating conditions for ddr2-667 , ddr2-800 . . . . . . . . . . . . . . . . . . . . . . . 53 table 44 odt ac characteristics and operating conditions for ddr2-533 & ddr2-400 . . . . . . . . . . . . . . . . . . . . . . . 54 table 45 examples for nomenclature fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 46 ddr2 memory components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
hy[b/i]18t256[40/80/16]0a[c/f](l) 256-mbit double-data-rate-two sdram internet data sheet rev. 1.50, 2007-12 62 03062006-7m17-pxbc contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 configuration for tfbga-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 configuration for tfbga-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 extended mode register emr(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 extended mode register emr(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 extended mode register emr(3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4truthtables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 input / output capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 currents measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 component ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 jitter definition and clock jitter specif ication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.4 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9 product nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
edition 2007-12 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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