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this is information on a product in full production. june 2013 docid15567 rev 5 1/53 l99h01 motor bridge driver for automotive applications datasheet - production data features ? operating supply voltage 6 v to 28 v ? central 2 stage charge pump ? 100% duty cycle ? full r dson down to 6 v (normal level mosfets) ? control of reverse battery protection mosfet ? charge pump current limited ? pwm operation up to 30 khz ? spi interface ? current sense amplifier / free configurable ? zero adjust for end of line trimming ? power management: programmable free wheeling ? sensing circuitry of external mosfets with embedded thermal sensors applications ? wiper ? power door ? seat belt tensioner ? seat positioning ? valve tronic ? park break ? 2h motors description the l99h01 is designed to control 4 external n-channel mos transistors in bridge configuration for dc-motor driving in automotive applications. a free configurable current sense amplifier is integrated. the integrated standard serial peripheral interface (spi) controls all outputs and provides diagnostic information. an interface pin for the thermal sensors of the external mosfets is implemented. POWERSSO-36 lqfp32 7x7mm table 1. device summary package order codes part number (tube) part number (tape and reel) part number (tray) POWERSSO-36 l99h01xp l99h01xptr ? lqfp32 ? l99h01qftr l99h01qf www.st.com
contents l99h01 2/53 docid15567 rev 5 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 pinout POWERSSO-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pinout lqfp32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 spi - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 dual power supply: v s and v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 standby mode (en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 h-bridge control (dir, pwm, bit fw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.7 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.8 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 28 3.9 short-circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . . 28 3.10 programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.11 current sense amplifier (csa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.12 thermal sensor interface / h-bridge switch-off input . . . . . . . . . . . . . . . . 29 3.12.1 ext_ts-bit = low (active off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.12.2 ext_ts-bit = high (thermal sensor interface) . . . . . . . . . . . . . . . . . . . . 29 3.13 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 functional description of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1 serial clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.2 serial data input (di) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid15567 rev 5 3/53 l99h01 contents 3 4.1.3 serial data output (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.4 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 general data description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.1 command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.2 opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.1 control and status (ram) address map . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.2 device (rom) address map (access with oc0 and oc1 set to ?1?) . . . 34 4.4 global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.1 spi clock monitor and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5 detailed byte description of status register (statreg0) . . . . . . . . . . . . . . 37 4.6 detailed byte description of application registers (applregx) . . . . . . . . . 38 4.6.1 description of the data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.7 read device information (rom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2 POWERSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3 packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.4 lqfp32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.5 POWERSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.6 lqfp32 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
list of tables l99h01 4/53 docid15567 rev 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. packages thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10. undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12. inputs: csn, clk, pwm, dir, en and di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 13. charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 14. gate drivers for external powermos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 15. cross current protection time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 16. drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 17. thermal sense interface (4.5 v < v cc < 5.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 18. current sense amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 19. di timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 20. do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 21. do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 22. en, csn timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 23. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 24. di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 25. do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 26. command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 27. operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 28. control and status (ram) address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 29. device (rom) address map (access with oc0 and oc1 set to ?1?) . . . . . . . . . . . . . . . . . . 34 table 30. stk_reset_q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 31. address 0<00(hex)>:statreg 0 - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 32. ds_mon - drivers relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 33. address 1 <01(hex)>:applreg1-read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 34. overvoltage threshold of the vs monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 35. diag monitoring of source voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 36. address 2 <02(hex)>: applreg2 ? read/write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 37. cross current protection time (t ccp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 38. multiplexer for current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 39. gain of current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 40. address 3 <03(hex)> : applreg3 ? read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 41. external threshold voltage, factor n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 42. external threshold voltage, factor m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 43. read device information (rom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 44. address 0 <00(hex)> : id-header - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 45. address 1 <01(hex)>: product id (lsb) - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 46. address 2 <02(hex)>: product id (msb) - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 47. address 3 <03(hex)>: spi frame id - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 48. POWERSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
docid15567 rev 5 5/53 l99h01 list of tables 5 table 49. lqfp32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 50. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
list of figures l99h01 6/53 docid15567 rev 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pinning of device in POWERSSO-36 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. pinning of device in lqfp-32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. output timing diagram (active free wheeling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. output timing diagram (passive free wheeling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. spi - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. spi - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. spi - do valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. spi - do enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. spi - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. global error flag diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12. POWERSSO-36 r thj-amb vs. pcb copper area in open free air condition . . . . . . . . . . . . . . . 43 figure 13. POWERSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 14. lqfp32 r thj-amb vs. pcb copper area in open box free air condition . . . . . . . . . . . . . . . . 47 figure 15. lqfp32 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 16. POWERSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17. POWERSSO-36 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 18. lqfp32 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 19. lqfp32 tray shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
docid15567 rev 5 7/53 l99h01 block diagram and pin description 52 1 block diagram and pin description figure 1. block diagram 1.1 pinout POWERSSO-36 &rqwuro/rjlf ', '2 &61 &/. ',5 3:0 63, ,qwhuidfh 026)(7 &rqwuro :dnhxs iurp 6ohhsprgh 'ate $river (3 'ate $river ,3 x &rqwuro 'ldjqrvlv &rqwuro 'ldjqrvlv *+ 6+ */ &6, &6, 'liihu hqw ldo&xu uhqw 6hqvh$psolilhu &6, &6, &62 &xuuhqw6hqvh08; 3urjudppdeoh *dlq *1' &3 &3 &3 &3 &3 &hqwudo6whs&kdujh3xps 9 &3 9 &3 3urjudppdeoh 9 '6 7 + w 'hd g *+ 6+ */ 6/ (1 8qghuyrowdjh 2yhuyrowdjh'hw 9ff 9v 7hpshudwxuh3u hzduqlqj 7hpshudw xuh6kxwgrzq 9v 6/ :dwfk'rj 9ff 76 $&7b2)) *1'' 9ffg ?& 9 5(* 66 - 4e mpdiodes n& n& n& 6 "!4 .2eset o p t i o n a l c o n t r o l 7 6 $ & 7 b 2 ) ) ? & o p t i o n a l c o n t r o l ("1($'5 table 2. pin definitions and functions pin symbol function 1 gnd ground. reference potential, connected to slug. 2 gndd digital ground. reference potential. 3v ccd logic voltage supply 3.3 v/5 v: for this input a ceramic capacitor as close as possible to gnd is recommended. 4v cc analog voltage supply 3.3 v/5 v: for this input a ceramic capacitor as close as possible to gnd is recommended. 5 en enable input. the enable input has a pull-down resistor. 6dir direction select input for h-bridge control. this input has a pull-down current. 7 pwm pwm input for h-bridge control. this input has a pull-down current. 8csn chip select not input: this input is low active and requires cmos logic levels. the serial data transfer between l99h01 and microcontroller is enabled by pulling the input csn to low-level. this input has a pull-up current.
block diagram and pin description l99h01 8/53 docid15567 rev 5 9clk serial clock input: this input controls the internal shift register of the spi and requires cmos logic levels.this input has a pull-down current. 10 di serial data in: the input requires cmos logic levels and receives serial data from the microcontroller. the data is an 8-bit control word and the most significant bit (msb, bit 7) is transferred first. this input has a pull-down current. 11 do serial data out: the diagnosis data is available via the spi and this tristate-output. the output remains in tristate, if the chip is not selected by the input csn (csn = high). 12, 14, 19, 20, 22 nc not connected. 13 cso current sense amplifier output: v cc compatible. 15 csi1+ current sense amplifier input: positive input 1, multiplexible. 16 csi1- current sense amplifier input: negative input 1, multiplexible. 17 csi2+ current sense amplifier input: positive input 2, multiplexible. 18 csi2- current sense amplifier input: negative input 2, multiplexible. 21 ts/ act_off thermal sensor interface or input to switch all driver active off. 23 gl2 gate driver for powermos low-side switch in halfbridge 2. 24 sl2 source of low-side switch in halfbridge 2. 25 gh2 gate driver for powermos high-side switch in halfbridge 2. 26 sh2 source/drain of halfbridge 2. 27 sl1 source of low-side switch in halfbridge 1. 28 gl1 gate driver for powermos low-side switch in halfbridge 1. 29 sh1 source/drain of halfbridge 1. 30 gh1 gate driver for powermos high-side switch in halfbridge 1. 31 cp charge pump output. 32 cp2+ charge pump pin for capacitor 2, positive side. 33 cp2- charge pump pin for capacitor 2, negative side. 34 cp1+ charge pump pin for capacitor 1, positive side. 35 cp1- charge pump pin for capacitor 1, negative side. 36 v s power supply voltage (external reverse protection required). for emi reason a ceramic capacitor as close as possible to gnd is recommended. table 2. pin definitions and functions (continued) pin symbol function
docid15567 rev 5 9/53 l99h01 block diagram and pin description 52 figure 2. pinning of device in POWERSSO-36 package 1. the slug is connected to pin 1. 1.2 pinout lqfp32 '.$ '.$$ 6 ##$ 6 ## %. $)2 07- #3. #,+ $) $/ .# #3/ .# #3) #3) #3) #3) .# .# 43!#4?/&& .# ', 3, '( 3( 3, ', 3( '( #0 #0 #0 #0 #0 6 3 0ower33/ ("1($'5 table 3. pin definitions and functions pin symbol function 1 cp2- charge pump pin for capacitor 2, negative side. 2 cp1+ charge pump pin for capacitor 1, positive side. 3 cp1- charge pump pin for capacitor 1, negative side. 4v s power supply voltage (external reverse protection required). for emi reason a ceramic capacitor as close as possible to gnd is recommended. 5 gnd ground. reference potential, connected to slug. 6 gndd digital ground. reference potential. 7v ccd logic voltage supply 3.3 v/5 v: for this input a ceramic capacitor as close as possible to gnd is recommended. 8v cc analog voltage supply 3.3 v/5 v: for this input a ceramic capacitor as close as possible to gnd is recommended. 9 en enable input. the enable input has a pull-down resistor.
block diagram and pin description l99h01 10/53 docid15567 rev 5 10 dir direction select input for h-bridge control. this input has a pull-down current. 11 pwm pwm input for h-bridge control. this input has a pull-down current. 12 csn chip select not input: this input is low active and requires cmos logic levels. the serial data transfer between l99h01 and microcontroller is enabled by pulling the input csn to low-level. this input has a pull-up current. 13 clk serial clock input: this input controls the internal shift register of the spi and requires cmos logic levels.this input has a pull-down current. 14 di serial data in: the input requires cmos logic levels and receives serial data from the microcontroller. the data is an 8-bit control word and the most significant bit (msb, bit 7) is transferred first. this input has a pull-down current. 15 do serial data out: the diagnosis data is available via the spi and this tristate-output. the output remains in tristate, if the chip is not selected by the input csn (csn = high). 16 cso current sense amplifier output: v cc compatible. 17 csi1+ current sense amplifier input: positive input 1, multiplexible. 18 csi1- current sense amplifier input: negative input 1, multiplexible. 19 csi2+ current sense amplifier input: positive input 2, multiplexible. 20 csi2- current sense amplifier input: negative input 2, multiplexible. 21 nc not connected. 22 ts/ act_off thermal sensor interface or external off for all gate drivers. 23 gl2 gate driver for powermos low-side switch in halfbridge 2. 24 sl2 source of low-side switch in halfbridge 2. 25 gh2 gate driver for powermos high-side switch in halfbridge 2. 26 sh2 source/drain of halfbridge 2. 27 sl1 source of low-side switch in halfbridge 1. 28 gl1 gate driver for powermos low-side switch in halfbridge 1. 29 sh1 source/drain of halfbridge 1. 30 gh1 gate driver for powermos high-side switch in halfbridge 1. 31 cp charge pump output. 32 cp2+ charge pump pin for capacitor 2, positive side. table 3. pin definitions and functions (continued) pin symbol function
docid15567 rev 5 11/53 l99h01 block diagram and pin description 52 figure 3. pinning of device in lqfp-32 package 'hylfh -2'1 #0 #0 #0 6 3 '.$ '.$$ 6##$ 6## %. $)2 07- #3. #,+ $) $/ #3/ #3) #3) #3) #3) .# 43!#4?/&& ', 3, '( 3( 3, ', 3( '( #0 #0 ("1($'5
electrical specifications l99h01 12/53 docid15567 rev 5 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in ta ble 4 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.2 esd protection table 4. absolute maximum ratings item symbol parameter value unit 4.1.1 v s power supply voltage -0,3 to 35 v 4.1.2 single pulse t max < 400 ms 40 v 4.2 v cc stabilished supply voltage -0.3 to 5.5 v 4.3 di, do, clk, csn, en, dir, pwm digital input / output voltage -0.3 to v cc + 0.3 v 4.4 cso, ts analog input / output voltage -0.3 to v cc + 0.3 v 4.5 csi1+, csi1-, csi2+, csi2- hv signal pins -4 to v s + 5v v 4.6 gl2, gh2, gl1, gh1 (gxy) hv signal pins sxy - 1 to sxy + 10; v cp +0.3 v 4.7 sl2, sh2, sl1, sh1 hv signal pins -6 to 40 v 4.8 cp2- cp1- hv signal pins -0.3 to v s + 0.3 v 4.9 cp1+ hv signal pins v s - 0.3 to v s +10 v 4.10 cp2+ hv signal pins v s - 0.6 to v s +10 v 4.11 cp power pin v s - 0.3 to v s +10 v table 5. esd protection item parameter value unit 5.1 all pins 2 (1) 1. - hbm according to mil 883c, method 3015.7 or eia/jesd22-a114-a. - hbm with all unzapped pins grounded. kv 5.2 v s versus gnd 4 (1) kv
docid15567 rev 5 13/53 l99h01 electrical specifications 52 2.3 thermal data 2.4 electrical characteristics v s = 6 v to 28 v, v cc = 3 v to 5.3 v, t j = -40c to 150c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 6. operating junction temperature item symbol parameter value unit 6.1 t j operating junction temperature -40 to 150 c table 7. temperature warning and thermal shutdown item symbol parameter min. typ. max. unit 7.1 t jtw on temperature warning threshold junction temperature t j 135 ? 165 c 7.2 t jsd on thermal shutdown threshold junction temperature t j increasing 155 ? 185 c 7.3 t jsd off thermal shutdown threshold junction temperature t j decreasing 150 ? 180 c table 8. packages thermal resistance item symbol parameter value unit POWERSSO-36 lqfp32 8.1 r thj-amb thermal resistance junction- ambient (max.) 58 (1) 1. minimum footprint. 80 (1) c/w table 9. supply item symbol parameter test condition min. typ. max. unit 9.1 v s operating supply voltage range 628v 9.2 v vs_ov1 overvoltage disable high threshold 1 spi: ovt = 1 28 30.5 32 v 9.3 v vs_ov1h overvoltage threshold 1 hysteresis 0.57 0.77 1.07 v 9.4 v vs_ov2 overvoltage disable high threshold 2 spi: ovt = 0 18 20 22 v 9.5 v vs_ov2h overvoltage threshold 2 hysteresis 0.42 0.62 0.82 v
electrical specifications l99h01 14/53 docid15567 rev 5 9.6 v vs_uv undervoltage disable low threshold 4.7 4.9 5.1 v 9.7 v vs_uvh undervoltage threshold hysteresis 0.2 0.3 0.4 v 9.8.1 i s v s dc supply current v s =13v; v cc =5v; active mode; outputs floating 4.5 5.5 6.5 ma 9.8.2 v s = 6 v to 28 v; v cc = 5.0 v; active mode; outputs floating 2.5 18 ma 9.9 i sl v s quiescent supply current v s =13v; v cc =0v; standby mode; t te s t = -40c, 25c; outputs floating 5a 9.10 i cc v cc dc supply current v s =13v; v cc =5v; active mode 1.5 1.8 2.5 ma 9.11 i cc v cc quiescent supply current v cc = 5 v; standby mode 30 70 150 a 9.12 i cc d v cc d supply current v s = 13 v; v cc =v cc d =5v; active mode 250 500 750 a table 10. undervoltage detection item symbol parameter test condition min. typ. max. unit 10.1 v por off power-on reset threshold v cc increasing 2.2 2.55 2.8 v 10.2 v por on power-on reset threshold v cc decreasing 2.0 2.25 2.6 v 10.3 v por hyst power-on reset hysteresis v por off - v por on 0.2 0.3 0.4 v table 11. watchdog item symbol parameter test condition min. typ. max. unit 11.1 t wdto watchdog time out ? 50 60 100 ms table 9. supply (continued) item symbol parameter test condition min. typ. max. unit
docid15567 rev 5 15/53 l99h01 electrical specifications 52 table 12. inputs: csn, clk, pwm, dir, en and di item symbol parameter test condition min. typ. max. unit 12.1 v in l low-level input voltage 0.3 * v cc 0.4 * v cc v 12.2 v in h high-level input voltage 0.6 * v cc 0.7 * v cc v 12.3 v in hyst input voltage hysteresis 0.1 * v cc v 12.4 i csn in pull-up current at input csn v csn =v cc -1.5v -50 -25 -10 a 12.5 i clk in pull-down current at input clk v clk =1.5v 103550a 12.6 i di in pull-down current at input di v di =1.5v 103550a 12.7 i dir in pull-down current at input dir v dir =1.5v 103550a 12.8 i pwm in pull-down current at input pwm v pwm =1.5v 103550a 12.9 r en in pull-down resistance at input en v en = v cc 100 210 480 k 12.10 c in (1) input capacitance at input csn, clk, di, dir and pwm 0v 12 v; i cp = 15 ma v s +11 v s +12 v s +13.5 v 13.2 i cp charge pump output current f cp = f sys_clk / 32; v s =14v; v cp =v s +10v 26 38 48 ma 13.3 v cp_low charge pump low threshold voltage v s +4.5 v s +5 v s +5.5 v 13.4.1 f sys_clk clock frequency (internal oscillator) v cc = 5 v 3 4 4.5 mhz 13.4.2 v cc = 3 v 2.4 3.3 3.5 mhz 13.5 t cp charge pump low filter time 64 s
electrical specifications l99h01 16/53 docid15567 rev 5 table 14. gate drivers for external powermos item symbol parameter test condition min. typ. max. unit drivers for external high-side powermos 14.1 i ghx(on) turn on current (source stage) t j = 25 c (1) 0.3 0.5 (2) 0.8 a 14.2.1 r ghx on-resistance of sink stage v shx = 0 v; i ghx = 50 ma; t j = 25c 34 5w 14.2.2 v shx = 0 v; i ghx = 50 ma; t j = 125c 4.5 5.3 7 w 14.3 v ghxh gate on voltage outputs floating v shx +8v v shx +10v v shx +12v v 14.4 r gshx passive gate clamp resistance 11 13 15 k drivers for external low-side powermos 14.5 i glx(on) turn on current (source stage) t j = 25c (1) 0.3 0.5 (2) 0.8 a 14.6.1 r glx on-resistance of sink stage v slx = 0 v; i ghx = 50 ma; t j = 25c 34 5w 14.6.2 v slx = 0 v; i ghx = 50 ma; t j = 125c 4.5 5.3 7 w 14.7 v glxh gate on voltage v slx +8v v slx +10v v slx + 12 v v 14.8 r gslx passive gate clamp resistance 11 13 15 k timing of the drivers 14.9 t ghxhl propagation delay time high to low v vs = 13.5 v; v shx = 0; r g =30 ; c g =4.7nf 0.8 1.4 1.9 s 14.10 t glxhl propagation delay time low to high v vs = 13.5 v; v slx = 0; r g =30 , ; c g =4.7nf 0.6 1.2 1.8 s 14.11 t ghxr2 rise time v vs = 13.5 v; v shx = 0; r g =0 ; c g =4.7nf 45 170 ns 14.12 t ghxf2 fall time v vs = 13.5 v; v shx = 0; r g =0 ; c g =4.7nf 60 210 ns 14.13 t glxr2 rise time v vs = 13.5 v; v slx = 0; r g =0 ; c g =4.7nf 45 170 ns 14.14 t glxf2 fall time v vs = 13.5 v; v slx = 0; r g =0 ; c g =4.7nf 60 210 ns 1. indirect measurement, parameter measured dynamically us ing 100 nf load capacitor and evaluating the slew rate. 2. average value.
docid15567 rev 5 17/53 l99h01 electrical specifications 52 table 15. cross current protection time (1) item symbol parameter test condition min. typ. max. unit 15.1 t ccp0 cross current protection time ? ? 250 (2) ? ns 15.2 t ccp1 cross current protection time ? 250 500 750 15.3 t ccp2 cross current protection time ? 500 750 1000 15.4 t ccp3 cross current protection time ? 700 1000 1300 15.5 t ccp4 cross current protection time ? 950 1250 1570 15.6 t ccp5 cross current protection time ? 1160 1500 1880 15.7 t ccp6 cross current protection time ? 1360 1750 2180 15.8 t ccp7 cross current protection time ? 1560 2000 2480 1. test conditions: v cc = 5 v, v s = 13.5 v 2. not tested table 16. drain source monitoring item symbol parameter test condition min. typ. max. unit 16.1 v scd1 drain - source threshold voltage ? 0.15 0.5 0.7 v 16.2 v scd2 drain - source threshold voltage ? 0.45 1 1.25 v 16.3 v scd3 drain - source threshold voltage ? 0.9 1.5 1.8 v 16.4 v scd4 drain - source threshold voltage ? 1.4 2 2.35 v 16.5 t scd drain - source filtertime ? 6 s table 17. thermal sense interface (4.5 v < v cc <5.3v) item symbol parameter min. typ. max. unit 17.1 i ts_bias output bias current 200 250 300 a 17.2 v th_ts ts threshold voltage v ts < v cc - 1 v n = number of diodes m = programmed level (0 to 7) n * (0.31 + m * 0.03) v table 18. current sense amplifier (1) item symbol parameter test condition min. typ. max. unit dc parameters 18.1 v icm input voltage range ? common mode -4 v cp - 8v v 18.2 v ioff50 input offset voltage gain = 50 -11 -4 3 mv 18.3 v ioff20 input offset voltage gain = 20 -23 -8 7 mv 18.4 v ioff10 input offset voltage gain = 10 -30 -10 10 mv 18.5 v ioff-t50 / t input offset voltage drift vs. temperature gain = 50 -10 (2) v/k
electrical specifications l99h01 18/53 docid15567 rev 5 18.6 v ioff-t20 / t input offset voltage drift vs. temperature gain = 20 -18 (2) v/k 18.7 v ioff-t10 / t input offset voltage drift vs. temperature gain = 10 -27 (2) v/k 18.8 v ioff-o_50 input offset voltage with offset compensation gain = 50 -3.5 -1 1.5 mv 18.9 v ioff-o_20 input offset voltage with offset compensation gain = 20 -6 -2 4 mv 18.10 v ioff-o_10 input offset voltage with offset compensation gain = 10 -10 -3 6 mv 18.11 p srr_50 power supply rejection ratio gain = 50 39 db 18.12 p srr_20 power supply rejection ratio gain = 20 31 db 18.13 p srr_10 power supply rejection ratio gain = 10 25 db 18.14 cmrr input common mode rejection t j = 25c, dc 60 db 18.15 gain 50 gain 46.75 50 53.25 18.16 gain 20 gain 19 20 21 18.17 gain 10 gain 9.5 10 10.5 18.18.1 v csoh high-level output voltage i out = 2 ma v cc - 250 mv v 18.18.2 i out = 200 a v cc - 50 mv v cc - 20 mv v 18.19.1 v csol low-level output voltage i out = -2 ma 100 250 mv 18.19.2 i out = -200 a 15 50 mv dynamic parameters 18.20 srcso_10 cso slew rate gain = 10; rl = 1 k ,; cl = 22 pf 2.8 4 v/s 18.21 srcso_20 cso slew rate gain = 20; rl = 1 k ,; cl = 22 pf 34.5v/s 18.22 srcso_50 cso slew rate gain = 50; rl = 1 k ,; cl = 22 pf 4.4 6 v/s 18.23 i csi_10 csi input current gain = 10 -114 -102 -90 a 18.24 i csi_20 csi input current gain = 20 -80 -72 -64 a 18.25 i csi_50 csi input current gain = 50 -39 -33 -27 a 1. test conditions: v s = 13 v, v cc = 5 v 2. not tested, guaranteed by design. table 18. current sense amplifier (1) (continued) item symbol parameter test condition min. typ. max. unit
docid15567 rev 5 19/53 l99h01 electrical specifications 52 figure 4. output timing diagram (active free wheeling) figure 5. output timing diagram (passive free wheeling) 07- t '(,x
t t '(xr t '(xf t '(x(, ',(x

t t ##0 t ',xr t ',xf t ',x(, t ##0
'(xfor&7 lowfreewheeling ',xfor&7 high

',xfor&7 low '(xfor&7 high ("1($'5 07- t '(,x
t t '(xr t '(xf t '(x(, t ',x(, 07- t '(,x
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electrical specifications l99h01 20/53 docid15567 rev 5 2.5 spi - electrical characteristics v s =6v to 28v, v cc = 3 v to 5.3 v, t j = -40c to 150c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 19. di timing (1) 1. di timing parameters tested in production by a passed / failed test: t j = -40c / +25c: spi communication @ 2 mhz. t j = +125c: spi communication @ 1.25 mhz. item symbol parameter test condition min. typ. max. unit 19.1 t clk clock period ? 1000 ? ns 19.2 t clkh clock high time ? 400 ? ns 19.3 t clkl clock low time ? 400 ? ns 19.4 t set csn csn setup time, csn low before rising edge of clk ? 400 ? ns 19.5 t set clk clk setup time, clk high before rising edge of csn ? 400 ? ns 19.6 t set di di setup time ? 200 ? ns 19.7 t hold di di hold time ? 200 ? ns 19.8 t r in rise time of input signal di, clk, csn ??100ns 19.9 t f in fall time of input signal di, clk, csn ??100ns table 20. do item symbol parameter test condition min. typ. max. unit 20.1 v dol low-level output voltage i d =-4ma 0.2 0.4 v 20.2 v doh high-level output voltage i d =4ma v cc -0.4 v cc -0.2 v 20.3 i dolk tristate leakage current v csn =v cc ; 0v docid15567 rev 5 21/53 l99h01 electrical specifications 52 table 21. do timing item symbol parameter test condition min. typ. max. unit 21.1 t r do do rise time c l = 100 pf; i load =-1ma ? 80 140 ns 21.2 t f do do fall time c l = 100 pf; i load = 1 ma ? 50 100 ns 21.3 t en do tri l do enable time from tristate to low-level c l = 100 pf; i load =1ma; pull-up load to v cc ? 100 250 ns 21.4 t dis do l tri do disable time from low-level to tristate c l = 100 pf; i load =4ma; pull-up load to v cc ? 380 450 ns 21.5 t en do tri h do enable time from tristate to high-level c l = 100 pf; i load = -1 ma; pull-down load to gnd ? 100 250 ns 21.6 t dis do h tri do disable time from high-level to tristate c l = 100 pf; i load = -4 ma; pull-down load to gnd ? 380 450 ns 21.7 t d do do delay time v do <0.3v cc ; v do >0.7v cc ; c l = 100 pf ? 50 250 ns table 22. en, csn timing item symbol parameter test condition min. typ. max. unit 22.1 t r do do rise time c l = 100 pf; i load =-1ma 80 140 ns 22.2 t f do do fall time c l = 100 pf; i load =1ma 50 100 ns 22.3 t csn_hi,min csn hi time, active mode:the min high time between two independent spi commands. transfer of spi- command to input register 2s
electrical specifications l99h01 22/53 docid15567 rev 5 figure 6. spi - transfer timing diagram figure 7. spi - input timing time time time time time #3.hightolow$/enabled actualdata $)datawillbeacceptedontherisingedgeof#,+signal newdata #3. #,+ $) $/ eg/54 $/datawillchangeonthefallingedgeof#,+signal statusinformation faultbit #3.lowtohighactualdatais transferredtooutputpowerswitches olddata actualdata ("1($'5 $ 2 ! 6## 6## 6## 6## 6## 6## 6alid 6a l id #3. #,+ $) t set#3. t #,+( t se t#,+ t #,+, t hold $) t set$) ("1($'5
docid15567 rev 5 23/53 l99h01 electrical specifications 52 figure 8. spi - do valid data delay time and valid time figure 9. spi - do enable and disable time 6# # 6# # 6# # 6## 6## 6 ## #,+ $/ lowtohi g h $/ h ightolow 6## t rin t r$/ t f$/ t d$/ t fin ("1($'5 #3. t fin rin t $/ $/ en$/tri, t t dis$/,tri 6## 6## en $/ tri ( t t dis $/ ( tri # p& , # p& , pull uploadto6## pull downloadto'.$ ("1($'5
electrical specifications l99h01 24/53 docid15567 rev 5 figure 10. spi - timing of status bit 0 (fault condition) #3. #,+ $) $/ #3.hightolowand#,+stayslowstatusinformationofdatab itfaultcondition istransferedto$/ $)dataisnotaccepted $/statusinformationofdatabitfaultcondition willsta yaslongas#3.islow time time time time $/statusinformationofthe'lobal%rror&lag',?%2 staysa slongas#3.islow ("1($'5
docid15567 rev 5 25/53 l99h01 device description 52 3 device description 3.1 dual power supply: v s and v cc the power supply voltage v s supplies the charge-pump. an internal charge-pump is used to drive the high-side switches and the low-side switches. the logic supply voltage v cc (3.3 v / 5 v) is used for the logic part and the spi of the device. due to the independent logic supply voltage the control and status information is not lost, even if the supply voltage v s is switched-off. in case of power-on (v cc increases from undervoltage to v por off = 2.5 v, typical) the circuit is initialized by an internally generated power-on reset (por). if the voltage v cc decreases under the minimum threshold (v por on =2.2v, typical), the outputs are switched-off and the status registers are cleared. 3.2 standby mode (en) the l99h01 is activated with enable input high signal. for enable input floating (not connected) or v en = 0 v the device is in standby mode. all latched data are cleared and the inputs and outputs are switched-off. in the standby mode the current at v s is less than 5 a (1 a) for csn = high (do in tristate). if v cc > v por off and en = high the device enters the active mode. in the active mode the charge-pump and the diagnostic functions are active. 3.3 h-bridge control (dir, pwm, bit fw) the dir and pwm inputs control the drivers of the external h-bridge transistors. the motor direction can be chosen with the dir input, the duty cycle and frequency with the pwm input. with the spi registers fw and fw-pas 4 different free wheeling modes (2 active and 2 passive) can be selected using the high-side transistors or the low-side transistors. unconnected inputs are defined by internal pull-down current.
device description l99h01 26/53 docid15567 rev 5 table 23. truth table n control pins control bits failure bits output pins spi do comment en dir pwm ts/act_off fw fw_pas cp_low ov uv sc tsd wdto gh1 gl1 gh2 gl2 gl_er 1 0 x x x x x x x x x x x rl rl rl rl t standby mode 2 1 x x x x x x x x x x x rl rl rl rl 1 power-on reset 31 x x 0 x 0 0 000 0 0 l l l l 0 ext_ts = 1 (external thermal shutdown) 4 1 x x 0 x 0 0 0 0 0 0 0 l l l l 0 ext_ts = 0 (active off) 5 1 x x 1 x x 1 0 0 0 0 0 rl rl rl rl 1 charge pump voltage too low 6 1 x x 1 x x 0 0 0 0 1 0 rl rl rl rl 1 internal thermal shutdown 7 1 x x 1 x x 0 1 0 0 0 0 l l l l 1 overvoltage 8 1 x x 1 x x 0 0 1 0 0 0 l l l l 1 undervoltage 91 x x 1 x x 0 001 0 0 l (1) l (1) l (1) l (1) 0 short-circuit (1) 10 1 x x 1 x x 0 0 0 0 0 1 l l l l 1 watchdog time out 111 0 1 1 x x 0 000 0 0 l h h l 0 - 12 1 x 0 1 0 0 0 0 0 0 0 0 l h l h 0 act. free wheeling mode ls 13 1 0 0 1 0 1 0 0 0 0 0 0 l h l l 0 pass. free wheeling mode ls 14 1 1 0 1 0 1 0 0 0 0 0 0 l l l h 0 pass. free wheeling mode ls 151 1 1 1 x x 0 000 0 0 h l l h 0 - 16 1 x 0 1 1 0 0 0 0 0 0 0 h l h l 0 act. free wheeling mode hs 17 1 0 0 1 1 1 0 0 0 0 0 0 l l h l 0 pass. free wheeling mode hs 18 1 1 0 1 1 1 0 0 0 0 0 0 h l l l 0 pass. free wheeling mode hs 1. only the halfbridge (low-side and high-side) where one mosfet is in short-circuit condition is s witched-off. both mosfet?s of the other halfbridge remain active and driven by dir and pwm.
docid15567 rev 5 27/53 l99h01 device description 52 symbols: ? x : don't care ? 1 : logic high or active ? 0 : logic low or not active ? h : output in source condition ? l : output in sink condition ? rl : resistive low (see section 3.4 ) ? t : tristate ? fw : free wheeling ? fw_pas : free wheeling passive ? cp_low : charge pump low ? ov : overvoltage ? uv : undervoltage ? sc : short-circuit ? tsd : thermal shutdown ? gl_er : global error flag 3.4 resistive low the resistive output mode protects the l99h01 and the h-bridge in the standby mode and in some failure modes (internal and external thermal shutdown (tsd), charge pump low (cp_low), stucked reset (stk_reset_q) and power-on reset (pores). when a gate driver changes into the resistive output mode due to a failure a sequence is started. in this sequence the concerning driver is switched in sink condition for 32 s to 64 s to ensure a fast switch-off of the h-bridge transistor. afterwards the driver is switched in the resistive output mode (resistive path to source). 3.5 diagnostic functions the diagnostic functions (over load, power supply over- and undervoltage, charge pump low, watchdog, temperature warning and internal/external thermal shutdown) are internally filtered and the condition has to be valid for at least 64 s (6 s for a short-circuit) before the corresponding status bit in the status registers is set. the filters are used to improve the noise immunity of the device. the internal temperature warning function is intended for information purpose and does not change the state of the output drivers. on the contrary, the over load condition switches the corresponding halfbridge in sink condition. the internal thermal shutdown condition and charge pump low disable all drivers (resistive low). the external thermal shutdown, watchdog, over- and undervoltage condition switch all driver in sink condition. the microcontroller needs to clear the status bits to reactivate the drivers. 3.6 overvoltage and undervoltage detection if the power supply voltage v s rises above the overvoltage threshold v vs_ovh (typical 20 v / 30 v), all gate driver stages are switched in sink condition to protect the h-bridge and the load, setting the ov bit. two values for the overvoltage threshold can be selected with the spi. when the voltage v s drops below the undervoltage threshold
device description l99h01 28/53 docid15567 rev 5 v vs_uv , all gate driver stages are switched in the sink condition to avoid driving the power devices without sufficient gate driving voltage (increased power dissipation), setting the uv bit. in both cases, overvoltage and undervoltage detection, the charge pump is disabled. if the supply voltage v s recovers from uv/ov to normal operating voltage range and if the ov_uv_rd is set to 0, then the charge pump is automatically enabled. in any case, regardless of the ov_uv_rd bit value, the microcontroller needs to clear the status register to reactivate the gate drivers. 3.7 charge pump the charge pump uses 2 external capacitors. the output of the charge pump has a current limitation. in standby mode and after overvoltage, undervoltage or a thermal shutdown has been triggered the charge pump is disabled. if the charge pump output voltage remains too low for longer than t cp , all gate drivers are switched-off (resistive output, see section 3.4 ). the cp_low bit has to be cleared through a software reset to reactivate the gate drivers. 3.8 temperature warning and thermal shutdown if junction temperature rises above t jtwon the temperature warning flag tw is set and is detectable via the spi. if junction temperature increases above the second threshold t jsdon , the thermal shutdown bit (tsd) is set. the gate drivers and the charge pump are switched-off to protect the device. the gates of the h-bridge are discharged by the resistive low mode (see section 3.4 ). in order to reactivate the output stages the junction temperature must decrease below t jsdoff and the thermal shutdown bit has to be cleared by the microcontroller. 3.9 short-circuit detection / drain source monitoring the drain - source voltage of each activated external mosfet of the h-bridge is monitored by comparators to detect shorts to ground or battery. if the voltage drop over the external mosfet exceeds the threshold voltage v scd for longer than the short current detection time t scd the corresponding gate driver switches the external mosfet off and the corresponding drain source monitoring flag (ds_mon [3:0]) is set. until this failure flag is reseted the corresponding half bridge is in sink condition. the ds_mon bits have to be cleared through a software reset to reactivate the gate drivers. the drain source monitoring has a filter time of 6 s. this monitoring is only active when the corresponding gate driver is in source condition. the threshold voltage v scd can be programmed in 4 steps between 0.5 v and 2 v with the spi. 3.10 programmable cross current protection the external power mosfet?s transistors in h-bridge (two halfbridges) configuration are switched-on with an additional delay time t ccp to prevent cross current in the halfbridge. the cross current protection time t ccp can be programmed with the spi.
docid15567 rev 5 29/53 l99h01 device description 52 3.11 current sense amplifier (csa) the current sense amplifier (csa) is specially designed for current shunt automotive applications. it is a bidirectional, single-supply difference amplifier for amplifying small differential voltages in a wide common mode voltage range (-4 v to (v cp - 8) v). it supports the current measurement at two shunts. the result of respective shunt can be multiplexed to the microcontroller compatible output voltage by a spi command. a gain of 50, 20 or 10 is spi programmable. the inputs (csi1+ / csi1- and csi2+ / csi2-) are build as a transconductance stage. therefore a series resistor (for filtering etc.) should not exceed 50 to keep the additional gain error below 1%. the output works at half scale: v cso0 = (0,5 * v cc ) v for v idiff = 0 v. an internal offset measurement is in normal mode available with the "off_cal" spi-bit. if this bit is set to logic "1" the input pins are disconnected from the amplifier and a virtual zero input differential voltage is selected. 3.12 thermal sensor interface / h-bridge switch-off input the ts/act_off pin is configurable by spi with the ext_ts bit. this pin could be used as temperature sensor interface for the h-bridge or external off for all gate drivers. the output bias current its_bias is on for en = high. 3.12.1 ext_ts-bit = low (active off) the ts/act_off input is used as a logic driver control input, without filter delay and without latching the information. pulling the ts/act_off pin below the programmed threshold all gate drivers are switched-off and the ot_ext bit is set. increasing the voltage at ts/act_off pin above the programmed threshold the device remains to the status set by dir and pwm-pins and the ot_ext bit is reseted. the threshold is programmable by spi with the registers extth_5:0. 3.12.2 ext_ts-bit = high (t hermal sensor interface) with the thermal sensor interface external diodes can be used to control the temperature of the external h-bridge. when the diode forward voltage decreases below the reference voltage for longer than the internal filter time (64 s) the ot_ext bit is set and the driver switches in resistive low (see section 3.4: resistive low ). in this mode the ot_ext-status-bit has to be cleared to reactivate the gate drivers. the threshold is programmable by spi with the registers extth_5:0. 3.13 watchdog the tasks of the watchdog is to monitor the microcontroller during normal operation within a nominal trigger cycle of 60 ms. the microcontroller has to restart the watchdog timer by sending the watchdog restart bit via spi repeatedly within the watchdog time t wdto . if no correct watchdog service is sent from the microcontroller, all gate drivers switch in sink
device description l99h01 30/53 docid15567 rev 5 condition and the watchdog time out bit (wdto) is set. once the watchdog times out, the gate drivers can only be reactivated by sending a software reset.
docid15567 rev 5 31/53 l99h01 functional description of the spi 52 4 functional description of the spi 4.1 signal description 4.1.1 serial clock (clk) this input signal provides the timing of the serial interface. data present at serial data input (di) is latched on the rising edge of serial clock (clk). data on serial data out (do) is shifted out at the falling edge of serial clock (clk). the serial clock clk must be active only during a frame (csn low phase). any other switching of clk close to any csn edge could generate setup/hold violations in the spi logic of the device. 4.1.2 serial data input (di) this input is used to transfer data serially into the device. values are latched on the rising edge of serial clock (clk). 4.1.3 serial data output (do) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (clk). do also reflects the status of the ( [7] ) while csn is low and no clock signal is present. 4.1.4 chip select not (csn) when this input signal is high, the communication interface of the device is deselected and serial data output (do) is high impedance. driving this input low enables the communication. the communication must start and stop on a low-level of serial clock (clk). the spi can be driven by a microcontroller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. for timing details and figures refer to section 2.5 . 4.2 general data description the spi communication is based on a spi interface structure using csn (chip select not), di (serial data in), do (serial data out/error) and clk (serial clock) signal lines. each di communication frame consists of a which is followed by 1 . the data returned on do within the same frame always starts with the , which provides general status information about the device. this byte is followed by 1 ( ?in-frame-response? ).
functional description of the spi l99h01 32/53 docid15567 rev 5 4.2.1 command byte each communication frame starts with a command byte. it consists of an operating code which specifies the type of operation ( , , , ) and a 6-bit address. comments: ? ocx : operating code ? ax : address 4.2.2 opcode definition the and operations allow access to the ram of the device. the operation is used to read a status register and subsequently clear its content. allows access to the rom area which contains device related information such as , , and . table 24. di command byte di - data byte 1514131211109876543210 oc1 oc0 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 table 25. do global status byte do - data byte 15 14 13 12 11109 8 76543210 gl_er fe stk_reset_q tsd tw uv ov wdto d7 d6 d5 d4 d3 d2 d1 d0 table 26. command byte command byte msb lsb op code address oc1 oc0 a5 a4 a3 a2 a1 a0 table 27. operating code definition oc1 oc0 meaning 0 0 0 1 1 0 1 1
docid15567 rev 5 33/53 l99h01 functional description of the spi 52 more detailed descriptions of the device information are available in section 4.7 .
functional description of the spi l99h01 34/53 docid15567 rev 5 4.3 device memory map 4.3.1 control and stat us (ram) address map 4.3.2 device (rom) address map (access with oc0 and oc1 set to ?1?) table 28. control and status (ram) address map name access address content a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stat reg0read/ clear000000ds_mon_3ds_mon_2ds_mon_1ds_mon_0 0 0 ot_extcp_low appl reg1read/ write000001 rwd fw_pas off_calclk_spctr ovt ov_uv_r d diag_1 diag_0 appl reg2read/ write000010 rwd copt_2 copt_1 copt_0 fw mcsa gcsa_1gcsa_0 appl reg3read/ write000011 rwd ext_ts extth_5 extth_4extth_3extth_2extth_1extth_0 table 29. device (rom) address map (access with oc0 and oc1 set to ?1?) name access address content a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 id-header read device 0 0 0 0 0 0 fam_1 fam_0 nr_pi_5 nr_pi_4 nr_pi_3 nr_pi_2 nr_pi_1 nr_pi_0 product code 1 read device 0 0 0 0 0 1 pr_id_7 pr_id_6 pr_id_5 pr_id_4 pr_id_3 pr_id_2 pr_id_1 pr_id_0 product code 2 read device 0 0 0 0 1 0 pr_id_15 pr_id_14 pr_id_13 pr_id_12 pr_id_11 pr_id_10 pr_id_9 pr_id_8 spi-frame-id read device 0 0 0 0 1 1 br ar5 ar4 ar3 32 bits 24 bits 16 bits 8 bits reserved read device 111111 reserved, accessing this address is recognized as a failure, the device enters a fail-safe state (see table 30: stk_reset_q ).
docid15567 rev 5 35/53 l99h01 functional description of the spi 52 4.4 global status byte this byte is shifted out first at do at every spi access. the gl_er bit is present at do with the falling edge of csn. this byte could be reseted with the command . comments: ? gl_er : global error flag. this signal is a logical or among all the errors of all the channels of the device. ? fe : frame error. if the number of clock pulses within the previous frame is not 16 the frame is ignored and this bit is set. ? stk_reset_q : if a stuck at ?1? on spi_di during any spi frame occurs, or if a power-on reset occurs. stk_reset_q is reset (?1?) with any spi command. when stk_reset_q is active (?0?), the gate drivers are switched-off (see section 3.4: resistive low ). after a startup of the circuit the stk_reset_q is active because of the por pulse and the gate drivers are switched-off. the gate drivers can only be activated after the stk_reset_q has been reset with a spi command. ? tsd : thermal shutdown due to an internal sensor. all the gate drivers and the charge pump must be switched-off (see section 3.4: resistive low ). the gate drivers can only be activated after the tsd has been reset with a spi command. ? tw : thermal warning ? uv : logical or among the filtered undervoltage signals. ? ov : logical or among the filtered overvoltage signals. ? wdto : watchdog time out. failures of < global status register> [8:14] are always linked to the . the is generated by an or combination of all failure events of the device (< global status register> [8:14]). the flag is reflected via the do pin while csn is held low and no clock signal is available. the flag remains as long as csn is low. this operation does not cause the bit in the to be set. table 30. stk_reset_q bit 15 14 13 12 11 10 9 8 name gl_er fe stk_reset_q tsd tw uv ov wdto 0 0 1 0 0 0 0 0
functional description of the spi l99h01 36/53 docid15567 rev 5 4.4.1 spi clock monitor and watchdog figure 11. global error flag diagram 1. writing a ?1? to rwd - bit in applregx restarts the internal watchdog counter. the clock monitor counts the number of clock pulses during a communication frame (while csn is low). if the number of sck pulses does not correspond with the frame width indicated in the (rom address 03hex) the frame is ignored and the bit in the is set. note: due to this safety functionality, daisy chaining the spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ics is recommended. 6&. 6', 6'2(uu &61 &rppxqlfdwlrq(uuru :'frxqwhu :dwfkgrj)dloxuh *oredo6wdwxv%\wh *oredo(uuru)odj &orfn 0rqlwru 5:' $sso5hj[ elw ("1($'5
docid15567 rev 5 37/53 l99h01 functional description of the spi 52 4.5 detailed byte description of status register (statreg0) the read operation starts always with the command byte followed by 1 data byte. the content of the send data byte has to be ?0?. the content of the addressed register is shifted out at do within the same frame (?in-frame response?). the device uses 1 status register to monitor the state of the device. tab le 31 shows the address and the content of the register. comments: ? ds_mon[3:0] : if max drain source voltage exceeds the defined thresholds, the ds_mon are set and the corresponding drivers go to sink mode. the ds_mon bits have to be cleared through a software reset to reactivate the drivers. ? ot_ext : depending on ext_ts bit following two meanings exist: ? ext_ts = low (active off): ts/act_off pin is used as input to switch the h-bridge in tristate and back. details are discribed in section 3.12.1 . ? ext_ts = high (thermal sensor interface): ts/act_off pin is used as thermal sensor interface for external temperature diodes. details are discribed in section 3.12.2 . ? cp_low : if a charge pump output voltage low occurs, all gate drivers must be switched-off (resistive low). the cp_low bit has to be cleared through a software reset to reactivate the gate driver. table 31. address 0<00(hex)>:statreg 0 - read only (1) 1. the errors of the status register are not linked to the . bit 7 6 5 4 3 2 1 0 name ds_mon_3 ds_mon_2 ds_mon_1 ds_mon_0 x x ot_ext cp_low 0 0 0 0 0 0 0 0 table 32. ds_mon - drivers relations register deactivated driver ds_mon_3 high-side 2 ds_mon_2 high-side 1 ds_mon_1 low-side 2 ds_mon_0 low-side 1
functional description of the spi l99h01 38/53 docid15567 rev 5 4.6 detailed byte description of application registers (applregx) the write/read operation starts always with a command byte followed by 1 data byte. 4.6.1 description of the data byte the device uses 3 application registers to configure the device. note that the last row shows the logic levels during a reset phase. comments: ? rwd : restarts the watchdog counter ? fw_pas : enables passive free wheeling according to table 23 ? off_cal : offset calibration mode for csa ? ovt: overvoltage threshold ? clk_spctr : switch the clock to the charge pump ? 0 : 125 khz (50% duty cycle) ? 1 : pulses train (max = 8 s, min = 2 s) to optimize power spectrum ? ov_uv_rd : over/undervoltage recovery disabled. ? 0: if v s recovers from ov/uv condition to normal operating voltage range, the charge pump is automatically enabled; ? 1: if v s recovers from ov/uv condition to normal operating voltage range, the charge pump remains disabled; in both cases the microcontroller has to clear the status register to enable the gate drivers ? diag[1:0] : drain source monitoring threshold voltage table 33. address 1 <01(hex)>:applreg1-read/write bit765 43210 name rwd fw_pas off_cal clk_spctr ovt ov_uv_ rd diag1 diag0 0 0 0 0 0 0 0 0 table 34. overvoltage threshold of the vs monitoring ovt threshold 020 v 129 v table 35. diag monitoring of source voltages diag[1] diag[0] monitoring threshold voltage 00 v scd1 = 0.5 v 01 v scd2 = 1 v 10 v scd3 = 1.5 v 11 v scd4 = 2 v
docid15567 rev 5 39/53 l99h01 functional description of the spi 52 comments: ? rwd : restarts the watchdog counter ? copt[2:0] : filter time to protect the two external halfbridges against cross current. ? fw : selects high-side or low-side free wheeling ? mcsa : multiplexer for current sense amplifier. ? gcsa[1:0] : gain of the current sense amplifier. table 36. address 2 <02(hex)>: applreg2 ? read/write bit76543210 name rwd copt_2 copt_1 copt_0 fw mcsa gcsa_1 gcsa_0 0 0 0 0 0 0 0 0 table 37. cross current protection time (t ccp ) copt_2 copt_1 copt _0 protection time 0 0 0 250 ns 0 0 1 500 ns 0 1 0 750 ns 0 1 1 1000 ns 1 0 0 1250 ns 1 0 1 1500 ns 1 1 0 1750 ns 1 1 1 2000 ns table 38. multiplexer for current sense amplifier mcsa selected amplifier 0 csa2 (csi2+ / csi2-) 1 csa1 (csi1+ / csi1-) table 39. gain of current sense amplifier gcsa_1 gcsa_0 gain 00 10 01 20 10 50 1 1 not applicable
functional description of the spi l99h01 40/53 docid15567 rev 5 comments: ? rwd : restarts the watchdog counter ? ext_ts : the bit select the mode of the input pin ts/act_off: ? ext_ts = low (active off): ts/act_off pin is used as input to switch the h-bridge in tristate and back. details are discribed in section 3.12.1 . ? ext_ts = high (thermal sensor interface): ts/act_off pin is used as thermal sensor interface for external temperature diodes. details are discribed in section 3.12.2 . ? extth[5:0] : determines the threshold of the external thermal shutdown/warning table 40. address 3 <03(hex)> : applreg3 ? read/write bit76543210 name rwd ext_ts extth_5 extth_4 extth_3 extth_2 extth_1 extth_0 00000000 table 41. external threshold voltage, factor n extth_5 extth_4 extth_3 n 000 7 001 6 010 5 011 4 100 3 101 2 110 1 111 0 table 42. external threshold voltage, factor m extth_2 extth_1 extth_0 m 000 7 001 6 010 5 011 4 100 3 101 2 110 1 111 0
docid15567 rev 5 41/53 l99h01 functional description of the spi 52 equation 1 v th = n * (0.31 + m * 0.03) v the purpose of factor n is to determine the number of external temperature sense diodes (in series). with factor m the level of the threshold voltage can be fine tuned. 4.7 read device information (rom) the device information is stored at the rom addresses defined below and is read using the respective operating code. the indicates the product family and specifies how many bytes of device information are available. ? fam[1:0] : family identifier, fam[1:0] = [0:1] stands for assps. ? nr_pi[5:0] : number of product information bytes. the represents a unique identifier of the device and version. table 43. read device information (rom) op code address device information oc1 oc0 ax 1 1 00h 1 1 01h 1 1 02h 1 1 03h 1 1 3fh reserved, accessing this address is recognized as a failure, the device enters a fail-safe state (see table 30: stk_reset_q ). table 44. address 0 <00(hex)> : id-header - read only (1) 1. addressable only through a r ead device information command. bit76543210 name fam_1 fam_0 nr_pi_5 nr_pi_4 nr_pi_3 nr_pi_2 nr_pi_1 nr_pi_0 01000010 table 45. address 1 <01(hex)>: product id (lsb) - read only (1) 1. addressable only through a r ead device information command. bit76543210 name pr_id_7 pr_id_6 pr_id_5 pr_id_4 pr_id_3 pr_id_2 pr_id_1 pr_id_0 00000001
functional description of the spi l99h01 42/53 docid15567 rev 5 the (rom address 03h) provides information about the register width (1, 2, 3 bytes) and the availability of ?burst mode read? option. comments: ? br : burst mode read. not supported ? ar5 : address width reduction. not supported ? ar4 : address width reduction. not supported ? ar3 : address width reduction. not supported ? 32 bits : 32 bits frame width. not supported ? 24 bits : 24 bits frame width. not supported ? 16 bits : 16 bits frame width, 8 bits command and 8 bits data ? 8 bits : 8 bits frame width. not supported table 46. address 2 <02(hex)>: product id (msb) - read only (1) 1. addressable only through a r ead device information command. bit76543210 name pr_id_15 pr_id_14 pr_id_13 pr_id_12 pr_id_11 pr_id_10 pr_id_9 pr_id_8 00101xxx table 47. address 3 <03(hex)>: spi frame id - read only (1) 1. addressable only through a read device information command. bit76543210 name br ar5 ar4 ar3 32 bits 24 bits 16 bits 8 bits 0 0 0 0 0 0 1 0
docid15567 rev 5 43/53 l99h01 packages thermal data 52 5 packages thermal data figure 12. POWERSSO-36 r thj-amb vs. pcb copper area in open free air condition 1. layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area = 129 mm x 60 mm, pcb thickness =1.6 mm, cu thickness =70 m (front and back side), copper areas: from minimum pad layout to 8 cm 2 ). 35 40 45 50 55 60 65 0246810 rthj_amb(c/w) pcb cu heatsink area (cm^2)
package and packing information l99h01 44/53 docid15567 rev 5 6 package and packing information 6.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
docid15567 rev 5 45/53 l99h01 package and packing information 52 6.2 POWERSSO-36 package information figure 13. POWERSSO-36 package dimensions ("1($'5
package and packing information l99h01 46/53 docid15567 rev 5 table 48. POWERSSO-36 mechanical data symbol millimeters min. typ. max. a 2.15 - 2.45 a2 2.15 - 2.35 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 d (1) 1. ?d? and ?e? do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side (0.006?). 10.10 - 10.50 e (1) 7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 h 10.1 - 10.5 h- -0.4 k0-8 l 0.55 - 0.85 m-4.3- n- -10 o-1.2- q-0.8- s-2.9- t-3.65- u-1- x 4.1 - 4.7 y 6.5 - 7.1
docid15567 rev 5 47/53 l99h01 package and packing information 52 6.3 packages thermal data figure 14. lqfp32 r thj-amb vs. pcb copper area in open box free air condition 1. layout condition of rth and zth measur ements (pcb: double layer, thermal vias, fr4 area = 78 mm x 86 mm, pcb thickness =1.6 mm, cu thickness =70 m (front and back side), copper areas: from minimum pad layout to 8 cm 2 ). 75 76 77 78 79 80 81 0 0.2 0.4 0.6 0.8 1 rthj_amb(c/w) pcb cu heatsink area (cm^2)
package and packing information l99h01 48/53 docid15567 rev 5 6.4 lqfp32 package information figure 15. lqfp32 package dimensions ("1($'5
docid15567 rev 5 49/53 l99h01 package and packing information 52 table 49. lqfp32 mechanical data dim. millimeter min. typ. max. a 1.60 a1 0.05 0.15 a2 (1) 1. lqfp stands for low profile quad flat pachage. low profile: body thickness (a2 = 1.40 mm) 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 d 8.80 9.00 9.20 d1 6.80 7.00 7.20 d3 5.60 e 8.80 9.00 9.20 e1 6.80 7.00 7.20 e3 5.60 e0.80 l 0.45 0.60 0.75 l1 1.00 0 3.5 7 ccc 0.10
package and packing information l99h01 50/53 docid15567 rev 5 6.5 POWERSSO-36 packing information figure 16. POWERSSO-36 tube shipment (no suffix) figure 17. POWERSSO-36 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base qty 49 bulk qty 1225 tube length (0.5) 532 a 3.5 b 13.8 c (0.1) 0.6 a c b reel dimensions base qty 1000 bulk qty 1000 a (max) 330 b (min) 1.5 c (0.2) 13 f 20.2 g (+2 / -0) 24.4 n (min) 100 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 (0.1) 4 component spacing p 12 hole diameter d (0.05) 1.55 hole diameter d1 (min) 1.5 hole position f (0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 (0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets sealed with cover tape. user direction of feed
docid15567 rev 5 51/53 l99h01 package and packing information 52 6.6 lqfp32 packing information figure 18. lqfp32 tape and reel shipment (suffix ?tr?) figure 19. lqfp32 tray shipment (no suffix)
revision history l99h01 52/53 docid15567 rev 5 7 revision history table 50. document revision history date revision changes 17-apr-2009 1 initial release. 19-aug-2009 2 updated corporate template from v3 to v3.1 updated figure 4 . removed items 17.16, 17.18 and 17.20 of the table 18: current sense amplifier . added table 15: cross current protection time table 18: current sense amplifier . ?v ioff 50 , v ioff 20 , v ioff 10 : added min/typ/max value, deleted ?t j = 25 c? for test condition ?v ioff-t50 / t: changed symbol (it was v ioff-t50 ), updated whole row. ?v ioff-t20 / t: changed symbol (it was v ioff-t20 ), updated whole row. ?v ioff-t10 / t: changed symbol (it was v ioff-t10 ), updated whole row. ?v ioff -50 , v ioff- 20 , v ioff- 10 : added min/typ/max value ?gain 50, gain 20, gain 10 : added min/typ/max value ? setting time: deleted row added figure 5: output timing diagram (passive free wheeling) updated table 23: truth table . updated section 3.9 , section 3.11 , section 3.12.1 and section 3.12.2 . table 30: stk_reset_q : changed title (it was ?global status byte?) updated section 4.4.1 and section 4.6.1 . updated table 43 . 20-apr-2010 3 updated the cp value in table 4: absolute maximum ratings 30-apr-2012 4 table 9: supply : ? v vs_ov1: : changed symbol (it was v vs_ovh1 ) ? v vs_ov1h: : changed symbol (it was v vs_ovh1 ) ? v vs_ov2: : changed symbol (it was v vs_ovh2 ) ? v vs_ov2h: : changed symbol (it was v vs_ovh2 ) ? v vs_uv: : changed symbol (it was v vs_uvh ) updated section 3.6: overvoltage and undervoltage detection and section 3.7: charge pump section 4.6.1: description of the data byte : ? updated ov_uv_rd bit description table 48: POWERSSO-36 mechanical data : ? l: updated values 21-jun-2013 5 updated table 17: thermal sense interface (4.5 v < vcc < 5.3 v)
docid15567 rev 5 53/53 l99h01 53 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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