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2 3 - s3 - c8248/c8245/p8245/c8247/c8249/p8249-032002 user's manual s3c8248/c8245/p8245 /c8247/c8249/p8249 8-bit cmos microcontroller s revision 3
s3c8248/c8245/p8245/c8247/c8249/p8249 product overview 1- 1 1 product overview s3c8-series microcontrollers samsung's s3c8 series of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. among the major cpu features are: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of four cpu clocks) can be assigned to specific interrupt levels. s3c8248/c8245/p8245/c8247/c8249/p8249 microcontroller the s3c8248/c8245/p8245/c8247/c8249/p8249 single-chip cmos microcontroller are fabricated using the highly advanced cmos process, based on samsung?s newest cpu architecture. the s3c8248, s3c8245, s3c8247, s3c8249 are a microcontroller with a 8k-byte, 16k-byte, 24k-byte. 32k-byte mask-programmable rom embedded respectively. the s3p8245 is a microcontroller with a 16k-byte one-time-programmable rom embedded. the s3p8249 is a microcontroller with a 32k-byte one-time-programmable rom embedded. using a proven modular design approach, samsung engineers have successfully developed the s3c8248/c8245/p8245/c8247/c8249/p8249 by integrating the following peripheral modules with the powerful sam8 core: ? six programmable i/o ports, including five 8-bit ports and one 5-bit port, for a total of 45 pins. ? eight bit-programmable pins for external interrupts. ? one 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). ? two 8-bit timer/counter and two 16-bit timer/counter with selectable operating modes. ? watch timer for real time. ? 8-input a/d converter ? serial i/o interface the s3c8248/c8245/p8245/c8247/c8249/p8249 is versatile microcontroller for camera, lcd and adc application, etc. they are currently available in 80-pin tqfp and 80-pin qfp package otp the s3p8245/p8249 are otp (one time programmable) version of the s3c8245/c8249 microcontroller. the s3p8245 microcontroller has an on-chip 16k-byte one-time-programmable eprom instead of a masked rom. the s3p8249 microcontroller has an on-chip 32k-byte one-time-programmable eprom instead of a masked rom. the s3p8245 is comparable to the s3p8245, both in function and in pin configuration. the s3p8249 is comparable to the s3p8249, both in function and in pin configuration.
product overview s3 c8248/c8245/p8245/c8247/c8249/p8249 1- 2 features memory ? rom: 32k-byte (s3c8249/p8249) ? rom: 16k-byte (s3c8245/p8245) ? ram: 1056-byte (s3c8249/p8249, s3c8247) ? ram: 544-byte (s3c8245/p8245, s3c8248) ? data memory mapped i/o oscillation sources ? crystal, ceramic, rc (main) ? crystal for subsystem clock ? main system clock frequency 1 -10 mhz (3 mhz at 1.8 v, 10 mhz at 2.7 v) ? subsystem clock frequency: 32.768 khz ? cpu clock divider (1/1, 1/2, 1/8, 1/16) two power-down modes ? idle (only cpu clock stops) ? stop (system clock stops) interrupts ? 6 level 8 vector 8 internal interrupt ? 2 level 8 vector 8 external interrupt 45 i/o pins ? 45 configurable i/o pins basic timer ? overflow signal makes a system reset. ? watchdog function 8-bit timer/counter a ? programmable 8-bit timer ? interval, capture, pwm mode ? match/capture, overflow i nterrupt 8-bit timer/counter b ? programmable 8-bit timer ? carrier frequency generator 16-bit timer/counter 0 ? programmable 16-bit timer ? match interrupt generates 16-bit timer/counter 1 ? programmable 16-bit timer ? interval, capture, pwm mode ? match/capture, overflow interrupt watch timer ? real-time and interval time measurement ? clock generation for lcd ? four frequency outputs for buzzer sound lcd controller/driver ? maximum 16-digit lcd direct drive capability ? display modes: static, 1/2 duty ( 1/2 bias) ? 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) a/d converter ? eight analog input channels ? 50 m s conversion speed at 1 mhz f adc clock ? 10-bit conversion resolution 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive mode ? lsb-first/msb-first transmission selectable ? internal/external clock source voltage booster ? lcd display voltage supply ? s/w control en/disable ? 3.0 v drive voltage detector ? programmable detection voltage (2.2 v, 2.4 v, 3.0 v, 4.0 v) ? en/disable s/w selectable instruction execution times ? 400 ns at 10 mhz (main) ? 122 us at 32.768 khz (subsystem) operating temperature range ? -40 c to 85 c operating voltage range ? 1.8 v to 5.5 v package type ? 80-pin qfp ? 80-pin tqfp s3c8249?s rom version device ? s3c8247 (rom 24k-byte) s3c8245?s rom version device ? s3c8248 (rom 8k-byte)
s3c8248/c8245/p8245/c8247/c8249/p8249 p roduct overview 1- 3 block diagram 544/1056 byte register file osc/ reset basic timer watch timer i/o port and interrupt control 16/32-kbyte rom sam88 rc cpu 8-bit timer/ counter b 16-bit timer/ counter 0 16-bit timer/ counter 1 i/o port 0 i/o port 1 a/d converter i/o port 2 8-bit timer/ counter a i/o port 3 taout/tapwm/p3.1 taclk/p3.2 tacap/p3.3 tbpwm/p3.0 t1cap/p1.0 t1clk/p1.1 t1out/t1pwm/p1.2 p0.0-p0.7/ int0-int7 p1.0-p1.7 av ref av ss p2.0-p2.7/ adc0-adc7 lcd driver serial i/o port p3.0-p3.4 voltage detector v vldref i/o port 5 i/o port 4 voltage booster cb ca vlc0-vlc2 com0-com3 seg0-seg15 seg16-seg31 si/p1.7 so/p1.5 sck/p1.6 p4.0-p4.7 p5.0-p5.7 reset buz/p1.4 x out xt out x in xt in figure 1-1. block diagram
product overview s3 c8248/c8245/p8245/c8247/c8249/p8249 1- 4 pin assignment seg25/p5.1 seg24/p5.0 seg23/p4.7 seg22/p4.6 seg21/p4.5 seg20/p4.4 seg19/p4.3 seg18/p4.2 seg17/p4.1 seg16/p4.0 seg15 seg14 seg13 seg12 seg11 seg10 seg26/p5.2 seg27/p5.3 seg28/p5.4 seg29/p5.5 seg30/p5.6 seg31/p5.7 p3.0/tbpwm p3.1/taout/tapwm p3.2/taclk p3.3/tacap/sdat p3.4/sclk v dd v ss x out x in test xt in xt out reset p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 p0.4/int4 s3c8248/c8245 /c8247/c8249 (80-qfp-1420c) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com3 com2 com1 com0 v lc2 v lc1 v lc0 ca cb av ss av ref p2.7/adc7/v vldref p2.6/adc6 p2.5/adc5 p0.5/int5 p0.6/int6 p0.7/int7 p1.0/t1cap p1.1/t1clk p1.2/t1out/t1pwm p1.3 p1.4/buz p1.5/so p1.6/sck p1.7/si p2.0/adc0 p2.1/adc1 p2.2/adc3 p2.3/adc4 p2.4/adc4 figure 1-2. s3c8248/c8245/c8247/c8249 pin assignments (80-qfp)
s3c8248/c8245/p8245/c8247/c8249/p8249 p roduct overview 1- 5 seg25/p5.1 seg24/p5.0 seg23/p4.7 seg22/p4.6 seg21/p4.5 seg20/p4.4 seg19/p4.3 seg18/p4.2 seg17/p4.1 seg16/p4.0 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg26/p5.2 seg27/p5.3 seg28/p5.4 seg29/p5.5 seg30/p5.6 seg31/p5.7 p3.0/tbpwm p3.1/taout/tapwm p3.2/taclk p3.3/tacap/sdat p3.4/sclk v dd v ss x out x in test xt in xt out reset p0.0/int0 s3c8248/c8245 /c8247/c8249 (80-tqfp-1212) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 seg5 seg4 seg3 seg2 seg1 seg0 com3 com2 com1 com0 v lc2 v lc1 v lc0 ca cb av ss av ref p2.7/adc7/v ldref p2.6/adc6 p2.5/adc5 p0.1/int1 p0.2/int2 p0.3/int3 p0.4/int4 p0.5/int5 p0.6/int6 p0.7/int7 p1.0/t1cap p1.1/t1clk p1.2/t1out/t1pwm p1.3 p1.4/buz p1.5/so p1.6/sck p1.7/si p2.0/adc0 p2.1/adc1 p2.2/adc3 p2.3/adc4 p2.4/adc4 figure 1-3. s3c8248/c8245/c8247/c8249 pin assignments (80-tqfp)
product overview s3 c8248/c8245/p8245/c8247/c8249/p8249 1- 6 pin descriptions table 1-1. s3c8248/c8245/c8247/c8249 pin descriptions pin names pin type pin description circuit type pin numbers (note) share pins p0.0?p0.7 i/o i/o port with bit programmable pins; schmitt trigger input or output mode selected by software; software assignable pull-up. p0.0?p0.7 can be used as inputs for external interrupts int0?int7 (with noise filter and interrupt control). d?4 20?27 int0?int7 p1.0?1.7 i/o i/o port with bit programmable pins; input or output mode selected by software; open-drain output mode can be selected by software; software assignable pull-up. alternately p1.0?p1.7 can be used as si, so, sck, buz, t1cap, t1clk, t1out, t1pwm e?2 28-35 si, so, sck, buz, t1cap t1clk t1out t1pwm p2.0?p2.7 i/o i/o port with bit programmable pins; normal input and ad input or output mode selected by software; software assignable pull-up. f?10 f?18 36?42, 43 adc0?adc6 v vldref (adc7) p3.0?p3.4 i/o i/o port with bit programmable pins. input or push-pull output with software assignable pull-up. alternately p3.0?p3.3 can be used as tacap, taclk, taout, tapwm, tbpwm d?2 7?11 tacap taclk taout tapwm tbpwm p4.0?p4.7 i/o i/o port with bit programmable pins. push-pull or open drain output and input with software assignable pull-up. p4.0?p4.7 can alternately be used as outputs for lcd seg h?14 71?78 seg16?seg23 p5.0?p5.7 i/o have the same characteristic as port 4 h?14 79?6 seg24?seg31
s3c8248/c8245/p8245/c8247/c8249/p8249 p roduct overview 1- 7 table 1-1. s3c8248/c8245/c8247/c8249 pin descriptions (continued) pin names pin type pin description circuit type pin numbers (note) share pins adc0?adc6 adc7 i a/d converter analog input channels f?10 f?18 36?42 43 p2.0?p2.6 p2.7 av ref ? a/d converter reference voltage ? 44 ? av ss ? a/d converter ground ? 45 ? int0?int7 i external interrupt input pins d?4 20?27 p0.0?p0.7 reset i system reset pin (pull-up resistor: 250 k w ) b 19 ? test i 0 v: normal mcu operating 5 v: test mode 12 v: for otp writing ? 16 ? sdat, sclk o serial otp interface pins; serial data and clock d?2 10, 11 p3.3, p3.4 v dd, v ss ? power input pins for cpu operation (internal) and power input for otp writing ? 12, 13 ? x out, x in ? main oscillator pins ? 14, 15 ? sck, so, si i/o serial i/o interface clock signal e?2 33?35 p1.5?p1.7 v vldref i voltage detector reference voltage input f?18 43 p2.7 tacap i timer a capture input d?2 10 p3.3 taclk i timer a external clock input d?2 9 p3.2 taout/tapwm o timer a output and pwm output d?2 8 p3.1 tbpwm o timer b pwm output d?2 7 p3.0 t1cap i timer 1 capture input e?2 28 p1.0 t1clk i timer 1 external clock input e?2 29 p1.1 t1out/t1pwm o timer 1 output and pwm output e?2 30 p1.2 com0?com3 o lcd common signal output h 51?54 ? seg0?seg15 o lcd segment output h 55?70 ? seg16?seg23 o lcd segment output h?14 71?78 p4.0?p4.7 seg24?seg31 o lcd segment output h?14 79?6 p5.0?p5.7 v lc0 ?v lc2 o lcd power supply ? 48?50 ? buz o 0.5, 1, 2 or 4 khz frequency output for buzzer sound with 4.19 mhz main system clock or 32768 hz subsystem clock e?2 32 p1.4 ca, cb ? capacitor terminal for voltage booster ? 46?47 ?
product overview s3 c8248/c8245/p8245/c8247/c8249/p8249 1- 8 pin circuits in v dd figure 1-4. pin circuit type b ( reset reset ) p-channel n-channel v dd out output disable data figure 1-5. pin circuit type c p-channel i/o output disable data circuit type c pull-up enable v dd figure 1-6. pin circuit type d-2 (p3) i/o output disable data pin circuit type c pull-up enable v dd noise filter ext.int input normal v dd figure 1-7. pin circuit type d-4 (p0)
s3c8248/c8245/p8245/c8247/c8249/p8249 p roduct overview 1- 9 v dd output disable data pull-up resistor v dd i/o p-ch n-ch schmitt trigger open drain enable figure 1-8. pin circuit type e-2 (p1) pull-up enable circuit type c data output disable adcen to adc data v dd i/o figure 1-9. pin circuit type f-10 (p2.0?p2.6) pull-up enable circuit type c data output disable adc & vld enable data to adc vld ref i/o v dd figure 1-10. pin circuit type f-18 (p2.7/vld ref ) out v lc1 seg/ com v lc0 v lc2 figure 1-11. pin circuit type h (seg/com)
product overview s3 c8248/c8245/p8245/c8247/c8249/p8249 1- 10 seg v lc2 v lc1 v lc0 output disable figure 1-12. pin circuit type h-4 v dd open drain en data lcd out en seg output disable pull-up enable v dd circuit type h-4 figure 1-13. pin circuit type h-14 (p4, p5)
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 1 2 address spaces overview the s3c8248/c8245/c8247/c8249 microcontroller has two types of address space: ? internal program memory (rom) ? internal register file a 16-bit address bus supports program memory operations. a separate 8-bit register bus carries addresses and data between the cpu and the register file. the s3c8248/c8245 has an internal 16-kbyte mask-programmable rom. the s3c8247/c8249 has an internal 32-kbyte mask-programmable rom. the 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes. a 16-byte lcd display register file is implemented. there are 1,109 mapped registers in the internal register file. of these, 1,040 are for general-purpose. (this number includes a 16-byte working register common area used as a ?scratch area? for data operations, four 192-byte prime register areas, and four 64-byte areas (set 2)). thirteen 8-bit registers are used for the cpu and the system control, and 53 registers are mapped for peripheral controls and data registers. twelve register locations are not mapped.
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 2 program memory (rom) program memory (rom) stores program codes or table data. the s3c8248 has 8k bytes internal mask- programmable program memory, the s3c8245 has 16k bytes, the s3c8247 has 24k bytes and the s3c8249 has 32k bytes. the first 256 bytes of the rom (0h?0ffh) are reserved for interrupt vector addresses. unused locations in this address range can be used as normal program memory. if you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. the rom address at which a program execution starts after a reset is 0100h. (decimal) 32,767 255 (hex) 7fffh (s3c8249) 0ffh 0h 0 interrupt vector area 32k-byte 3fffh (s3c8245) 4000h 16383 16384 16k-byte 5fffh (s3c8247) 6000h 24k-byte 1fffh (s3c8248) 2000h 8k-byte figure 2-1. program memory address space
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 3 register architecture in the s3c8248/c8245/c8247/c8249 implementation, the upper 64-byte area of register files is expanded two 64 -byte areas, called set 1 and set 2 . the upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. in case of s3c8247/c8249/p8249 the total number of addressable 8-bit registers is 1122. of these 1122 registers, 16 bytes are for cpu and system control registers, 16 bytes are for lcd data registers, 50 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 1024 registers are for general-purpose use, page 0-page 4 (in case of s3c8248/c8245/p8245, page 0-page 2). you can always address set 1 register locations, regardless of which of the four register pages is currently selected. set 1 locations, however, can only be addressed using register addressing modes. the extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, sb0 and sb1, and the register page pointer (pp). specific register types and the area (in bytes) that they occupy in the register file are summarized in table 2?1. table 2-1. s3c8247/c8249/p8249 register type summary register type number of bytes general-purpose registers (including the 16-byte common working register area, four 192-byte prime register area, and four 64-byte set 2 area) lcd data registers cpu and system control registers mapped clock, peripheral, i/o control, and data registers 1,040 16 16 50 total addressable bytes 1,122 table 2-2. s3c8248/c8245/p8245 register type summary register type number of bytes general-purpose registers (including the 16-byte common working register area, four 192-byte prime register area, and four 64-byte set 2 area) lcd data registers cpu and system control registers mapped clock, peripheral, i/o control, and data registers 528 16 16 50 total addressable bytes 610
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 4 system registers (register addressing mode) general purpose register (register addressing mode) bank 1 system and peripheral control registers bank 0 system and peripheral control registers (register addressing mode) set1 ffh e0h 32 bytes e0h dfh d0h cfh c0h prime data registers (all addressing modes) lcd display reigster ~ ~ page 4 0fh 00h 16 bytes ~ page 1 ~ page3 ~ page 2 ~ page 1 page 0 prime data registers (all addressing modes) page 0 set 2 general-purpose data registers (indirect register, indexed mode, and stack operations) ~ ~ ~ c0h bfh 00h ffh ffh ffh ffh 192 bytes 64 bytes 256 bytes note: in case of s3c8248/c8245/p8245, there are page 0, page 1, and page 2. page 2 is for lcd display register, 16 bytes. figure 2-2. internal register file organization
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 5 register page pointer (pp) the s3c8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. page addressing is controlled by the register page pointer (pp, dfh). in the s3c8248/c8245/c8247/c8249 microcontroller, a paged register file expansion is implemented for lcd data registers, and the register page pointer must be changed to address other pages. after a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing. register page pointer (pp) dfh ,set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 destination register page selection bits: 0000 destination: page 0 source register page selection bits: 0000 source: page 0 note: a hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. these values should be modified to address other pages. figure 2-3. register page pointer (pp) + + programming tip ? using the page pointer for ram clear (page 0, page 1) ld pp,#00h ; destination ? 0, source ? 0 srp #0c0h ld r0,#0ffh ; page 0 ram clear starts ramcl0 clr @r0 djnz r0,ramcl0 clr @r0 ; r0 = 00h ld pp,#10h ; destination ? 1, source ? 0 ld r0,#0ffh ; page 1 ram clear starts ramcl1 clr @r0 djnz r0,ramcl1 clr @r0 ; r0 = 00h note: you should refer to page 6-39 and use djnz instruction properly when djnz instruction is used in your program.
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 6 register set 1 the term set 1 refers to the upper 64 bytes of the register file, locations c0h?ffh. the upper 32-byte area of this 64-byte space (e0h?ffh) is expanded two 32-byte register banks, bank 0 and bank 1 . the set register bank instructions, sb0 or sb1, are used to address one bank or the other. a hardware reset operation always selects bank 0 addressing. the upper two 32-byte areas (bank 0 and bank 1) of set 1 (e0h?ffh) contains 50 mapped system and peripheral control registers. the lower 32-byte area contains 16 system registers (d0h?dfh) and a 16-byte common working register area (c0h?cfh). you can use the common working register area as a ?scratch? area for data operations being performed in other areas of the register file. registers in set 1 locations are directly accessible at all times using register addressing mode. the 16-byte working register area can only be accessed using working register addressing (for more information about working register addressing, please refer to chapter 3, ?addressing modes.?) register set 2 the same 64-byte physical space that is used for set 1 locations c0h?ffh is logically duplicated to add another 64 bytes of register space. this expanded area of the register file is called set 2 . for the s3c8247/c8249, the set 2 address range (c0h?ffh) is accessible on pages 0?3. s3c8248/c8245, the set 2 address range (c0h-ffh) is accessible on pages 0-1. the logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. you can use only register addressing mode to access set 1 locations. in order to access registers in set 2, you must use register indirect addressing mode or indexed addressing mode. the set 2 register area is commonly used for stack operations.
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 7 prime register space the lower 192 bytes (00h?bfh) of the s3c8248/c8245/c8247/c8249's four or two 256 -byte register pages is called prime register area. prime registers can be accessed using any of the seven addressing modes (see chapter 3, "addressing modes.") the prime register area on page 0 is immediately addressable following a reset. in order to address prime registers on pages 0, 1, 2, 3, or 4 you must set the register page pointer (pp) to the appropriate source and destination values. ffh fch e0h d0h c0h set 1 bank 0 peripheral and i/o general-purpose cpu and system control lcd data register ffh page 3 set 2 ffh page 2 set 2 ffh page 1 set 2 ffh c0h 00h bfh page 0 set 2 page 0 prime space lcd data register area page 4 00h 0fh bank 1 figure 2-4. set 1, set 2, prime area register, and lcd data register map
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 8 working registers instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. when 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." each slice comprises of eight 8-bit registers. using the two 8-bit register pointers, rp1 and rp0, two working register slices can be selected at any one time to form a 16-byte working register block. using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except the set 2 area. the terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: ? one working register slice is 8 bytes (eight 8-bit working registers, r0?r7 or r8?r15) ? one working register block is 16 bytes (sixteen 8-bit working registers, r0?r15) all the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. this makes it possible for each register pointer to point to one of the 24 slices in the register file. the base addresses for the two selected 8-byte register slices are contained in register pointers rp0 and rp1. after a reset, rp0 and rp1 always point to the 16-byte common area in set 1 (c0h?cfh). each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block. 1 1 1 1 1 x x x rp1 (registers r8-r15) rp0 (registers r0-r7) slice 32 slice 31 ~ ~ cfh c0h ffh f8h f7h f0h fh 8h 7h 0h slice 2 slice 1 10h set 1 only 0 0 0 0 0 x x x figure 2-5. 8-byte working register areas (slices)
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 9 using the register points register pointers rp0 and rp1, mapped to addresses d6h and d7h in set 1, are used to select two movable 8 -byte working register sli ces in the register file. after a reset, they point to the working register common area: rp0 points to addresses c0h?c7h, and rp1 points to addresses c8h?cfh. to change a register pointer value, you load a new value to rp0 and/or rp1 using an srp or ld instruction. (see figures 2-6 and 2-7). with working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by rp0 and rp1. you cannot, however, use the register pointers to select a working register space in set 2, c0h?ffh, because these locations can be accessed only using the indirect register or indexed addressing modes. the selected 16-byte working register block usually consists of two contiguous 8-byte slices. as a general programming guideline, it is recommended that rp0 point to the "lower" slice and rp1 point to the "upper" slice (see figure 2-6). in some cases, it may be necessary to define working register areas in different (non- contiguous) areas of the register file. in figure 2-7, rp0 points to the "upper" slice and rp1 to the "lower" slice. because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements. + + programming tip ? setting the register pointers srp #70h ; rp0 ? 70h, rp1 ? 78h srp1 #48h ; rp0 ? no change, rp1 ? 48h, srp0 #0a0h ; rp0 ? a0h, rp1 ? no change clr rp0 ; rp0 ? 00h, rp1 ? no change ld rp1,#0f8h ; rp0 ? no change, rp1 ? 0f8h fh (r15) 0h (r0) 16-byte contiguous working register block register file contains 32 8-byte slices rp0 rp1 8h 7h 0 0 0 0 1 x x x 0 0 0 0 0 x x x 8-byte slice 8-byte slice figure 2-6. contiguous 16-byte working register block
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 10 16-byte contiguous working register block register file contains 32 8-byte slices 0 0 0 0 0 x x x rp1 1 1 1 1 0 x x x rp0 0h (r0) 7h (r15) f0h (r0) f7h (r7) 8-byte slice 8-byte slice figure 2-7. non-contiguous 16-byte working register block + + programming tip ? using the rps to calculate the sum of a series of registers calculate the sum of registers 80h?85h using the register pointer. the register addresses from 80h through 85h contain the values 10h, 11h, 12h, 13h, 14h, and 15 h, respectively: srp0 #80h ; rp0 ? 80h add r0,r1 ; r0 ? r0 + r1 adc r0,r2 ; r0 ? r0 + r2 + c adc r0,r3 ; r0 ? r0 + r3 + c adc r0,r4 ; r0 ? r0 + r4 + c adc r0,r5 ; r0 ? r0 + r5 + c the sum of these six registers, 6fh, is located in the register r0 (80h). the instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. if the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: add 80h,81h ; 80h ? (80h) + (81h) adc 80h,82h ; 80h ? (80h) + (82h) + c adc 80h,83h ; 80h ? (80h) + (83h) + c adc 80h,84h ; 80h ? (80h) + (84h) + c adc 80h,85h ; 80h ? (80h) + (85h) + c now, the sum of the six registers is also located in register 80h. however, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 11 register addressing the s3c8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. with register (r) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. with working register addressing, you use a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space. registers are addressed either as a single 8-bit register or as a paired 16-bit register space. in a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register. working register addressing differs from register addressing as it uses a register pointer to identify a specific 8 -byte working register space in the internal register file and a specific 8-bit register within that space. msb rn lsb rn+1 n = even address figure 2-8. 16-bit register pair
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 12 rp1 rp0 register pointers 00h all addressing modes page 0 indirect register, indexed addressing modes page 0 register addressing only can be pointed by register pointer ffh e0h bfh control registers system registers special-purpose registers d0h c0h bank 1 bank 1 note: in the s3c8248/c8245/c8247/c8249 microcontroller, pages 0-4 are implemented. pages 0-4 contain all of the addressable registers in the internal register file. each register pointer (rp) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). after a reset, rp0 points to locations c0h-c7h and rp1 to locations c8h-cfh (that is, to the common working register area). ffh c0h set 2 prime registers cfh general-purpose register all addressing modes can be pointed to by register pointer lcd data registers figure 2-9. register file addressing
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 13 common working register area (c0h?cfh) after a reset, register pointers rp0 and rp1 automatically select two 8-byte register slices in set 1, locations c0h?cfh, as the active 16-byte working register block: rp0 ? c0h?c7h rp1 ? c8h?cfh this 16-byte address range is called common area . that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. ffh page 3 set 2 ffh page 2 set 2 ffh page 1 set 2 ffh c0h 00h bfh page 0 set 2 page 0 prime space lcd data registers page 4 00h 0fh ffh fch e0h d0h c0h set 1 following a hardware reset, register pointers rp0 and rp1 point to the common working register area, locations c0h-cfh. rp0 = rp1 = 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 ~ ~ ~ ~ ~ figure 2-10. common working register area
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 14 + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. examples 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: srp #0c0h ld r2,40h ; r2 (c2h) ? the value in location 40h 2. add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: srp #0c0h add r3,#45h ; r3 (c3h) ? r3 + 45h 4-bit working register addressing each register pointer defines a movable 8-byte slice of working register space. the address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. when an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: ? the high-order bit of the 4-bit address selects one of the register pointers ("0" selects rp0, "1" selects rp1). ? the five high-order bits in the register pointer select an 8-byte slice of the register space. ? the three low-order bits of the 4-bit address select one of the eight registers in the slice. as shown in figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. as long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. figure 2-12 shows a typical example of 4-bit working register addressing. the high-order bit of the instruction "inc r6" is "0", which selects rp0. the five high-order bits stored in rp0 (01110b) are concatenated with the three low-order bits of the instruction's 4-bit address (110b) to produce the register address 76h (01110110b).
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 15 together they create an 8-bit register address register pointer provides five high-order bits address opcode selects rp0 or rp1 rp1 rp0 4-bit address provides three low-order bits figure 2-11. 4-bit working register addressing register address (76h) rp0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 r6 0 1 1 0 1 1 1 0 selects rp0 instruction 'inc r6' opcode rp1 0 1 1 1 1 0 0 0 figure 2-12. 4-bit working register addressing example
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 16 8-bit working register addressing you can also use 8-bit working register addressing to access registers in a selected working register area. to initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100b." this 4-bit value (1100b) indicates that the remaining four bits have the same effect as 4-bit working register addressing. as shown in figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4 -bit addressing: bit 3 selects either rp0 or rp1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction. figure 2-14 shows an example of 8-bit working register addressing. the four high-order bits of the instruction address (1100b) specify 8-bit working register addressing. bit 4 ("1") selects rp1 and the five high-order bits in rp1 (10101b) become the five high-order bits of the register address. the three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. the five address bits from rp1 and the three address bits from the instruction are concatenated to form the complete register address, 0abh (10101011b). 8-bit logical address 8-bit physical address register pointer provides five high-order bits address selects rp0 or rp1 rp1 rp0 three low-order bits these address bits indicate 8-bit working register addressing 1 1 0 0 figure 2-13. 8-bit working register addressing
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 17 8-bit address form instruction 'ld r11, r2' rp0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 selects rp1 r11 register address (0abh) rp1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 specifies working register addressing figure 2-14. 8-bit working register addressing example
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 18 system and user stack the s3c8-series microcontrollers use the system stack for data storage, subroutine calls and returns. the push and pop instructions are used to control system stack operations. the s3c8248/c8245/c8247/c8249 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls, interrupts, and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction . when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address value is always decreased by one before a push operation and increased by one after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-15. stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2-15. stack operations user-defined stacks you can freely define stacks in the internal register file as data storage locations. the instructions pushui, pushud, popui, and popud support user-defined stack operations. stack pointers (spl, sph) register locations d8h and d9h contain the 16-bit stack pointer (sp) that is used for system stack operations. the most significant byte of the sp address, sp15?sp8, is stored in the sph register (d8h), and the least significant byte, sp7?sp0, is stored in the spl register (d9h). after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c8248/c8245/c8247/c8249, the spl must be initialized to an 8-bit value in the range 00h?ffh. the sph register is not needed and can be used as a general- purpose register, if necessary. when the spl register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the sph register as a general-purpose data register. however, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the spl register during normal stack operations, the value in the spl register will overflow (or underflow) to the sph register, overwriting any other data that is currently stored there. to avoid overwriting data in the sph register, you can initialize the spl value to "ffh" instead of "00h".
s3c8248/c8245/p8245/c8247/c8249/p8249 address spa ces 2- 19 + + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld spl,#0ffh ; spl ? ffh ; (normally, the spl is set to 0ffh by the initialization ; routine) ? ? ? push pp ; stack address 0feh ? pp push rp0 ; stack address 0fdh ? rp0 push rp1 ; stack address 0fch ? rp1 push r3 ; stack address 0fbh ? r3 ? ? ? pop r3 ; r3 ? stack address 0fbh pop rp1 ; rp1 ? stack address 0fch pop rp0 ; rp0 ? stack address 0fdh pop pp ; pp ? stack address 0feh
address spaces s3c8 248/c8245/p8245/c8247/c8249/p8249 2- 20 notes
s3c8248/c8245/p8245/c8247/c8249/p8249 a ddressing modes 3- 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam88rc instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the s3c8-series instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction. the seven addressing modes and their symbols are: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indirect address (ia) ? relative address (ra) ? immediate (im)
addressing modes s3 c8248/c8245/p8245/c8247/c8249/p8249 3- 2 register addressing mode (r) in register addressing mode (r), the operand value is the content of a specified register or register pair (see figure 3-1). working register addressing differs from register addressing in that it uses a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space (see figure 3-2). dst value used in instruction execution opcode operand 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3-1. register addressing dst opcode 4-bit working register point to the working register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the currently selected working register area. program memory register file src 3 lsbs rp0 or rp1 selected rp points to start of working register block operand msb point to rp0 ot rp1 figure 3-2. working register addressing
s3c8248/c8245/p8245/c8247/c8249/p8249 a ddressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3-3 through 3- 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. please note, however, that you cannot access locations c0h?ffh in set 1 using the indirect register addressing mode. dst address of operand used by instruction opcode address 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3-3. indirect register addressing to register file
addressing modes s3 c8248/c8245/p8245/c8247/c8249/p8249 3- 4 indirect register addressing mode (c ontinued ) dst opcode pair points to register pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3-4. indirect register addressing to program memory
s3c8248/c8245/p8245/c8247/c8249/p8249 a ddressing modes 3- 5 indirect register addressing mode (c ontinued ) dst opcode address 4-bit working register address point to the working register (1 of 8) sample instruction: or r3, @r6 program memory register file src 3 lsbs value used in instruction operand selected rp points to start fo working register block rp0 or rp1 msb points to rp0 or rp1 ~ ~ ~ ~ figure 3-5. indirect working register addressing to register file
addressing modes s3 c8248/c8245/p8245/c8247/c8249/p8249 3- 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 2-bit point to working register pair (1 of 4) lsb selects register pair 16-bit address points to program memory or data memory rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block figure 3-6. indirect working register addressing to program or data memory
s3c8248/c8245/p8245/c8247/c8249/p8249 a ddressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory. please note, however, that you cannot access locations c0h?ffh in set 1 using indexed addressing mode. in short offset indexed addressing mode, the 8 -bit displacement is treated as a signed integer in the range ?128 to +127. this applies to external memory accesses only (see figure 3-8.) for register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to that base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory and for external data memory, when implemented. dst/src opcode two-operand instruction example point to one of the woking register (1 of 8) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file x 3 lsbs value used in instruction operand index base address rp0 or rp1 selected rp points to start of working register block ~ ~ ~ ~ + figure 3-7. indexed addressing to register file
addressing modes s3 c8248/c8245/p8245/c8247/c8249/p8249 3- 8 indexed addressing mode (c ontinued ) register file operand program memory or data memory point to working register pair (1 of 4) lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block dst/src opcode program memory x offset 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits + ~ ~ figure 3-8. indexed addressing to program or data memory with short offset
s3c8248/c8245/p8245/c8247/c8249/p8249 a ddressing modes 3- 9 indexed addressing mode (c oncluded ) register file operand program memory or data memory point to working register pair lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits dst/src opcode program memory src offset 4-bit working register address offset + ~ ~ figure 3-9. indexed addressing to program or data memory
addressing modes s3 c8248/c8245/p8245/c8247/c8249/p8249 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3-10. direct addressing for load instructions
s3c8248/c8245/p8245/c8247/c8249/p8249 a ddressing modes 3- 11 direct address mode (c ontinued ) opcode program memory lower address byte memory address used upper address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3-11. direct addressing for call and jump instructions
addressing modes s3 c8248/c8245/p8245/c8247/c8249/p8249 3- 12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use the indirect address mode. because the indirect address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. current instruction program memory locations 0-255 program memory opcode dst lower address byte upper address byte next instruction lsb must be zero sample instruction: call #40h ; the 16-bit value in program memory addresses 40h and 41h is the subroutine start address. figure 3-12. indirect addressing
s3c8248/c8245/p8245/c8247/c8249/p8249 a ddressing modes 3- 13 relative address mode (ra) in relative address (ra) mode, a twos-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. several program control instructions use the relative address mode to perform conditional jumps. the instructions that support ra addressing are btjrf, btjrt, djnz, cpije, cpijne, and jr. opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3-13. relative addressing
addressing modes s3 c8248/c8245/p8245/c8247/c8249/p8249 3- 14 immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. the operand may be one byte or one word in length, depending on the instruction used. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3-14. immediate addressing
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 1 4 control registers overview in this chapter , deta iled descriptions of the s3c8248/c8245/c8247/c8249 control registers are presented in an easy-to-read format. you can use this chapter as a quick-reference source when writing application programs. figure 4-1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in part ii of this manual. data and counter registers are not described in detail in this reference chapter . more information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in part ii of this manual. the locations and read/write characteristics of all mapped registers in the s3c8248/c8245/c8247/c8249 register file are listed in table 4-1. the hardware reset value for each mapped register is described in chapter 8, ? reset and power-down ." table 4-1. set 1 registers register name mnemonic decimal hex r/w lcd control register lcon 208 d0h r/w lcd mode register lmod 209 d1h r/w interrupt pending register intpnd 210 d2h r/w basic timer control register btcon 211 d3h r/w clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w register pointer 0 rp0 214 d6h r/w register pointer 1 rp1 215 d7h r/w stack pointer (high byte) sph 216 d8h r/w stack pointer (low byte) spl 217 d9h r/w instruction pointer (high byte) iph 218 dah r/w instruction pointer (low byte) ipl 219 dbh r/w interrupt request register irq 220 dch r interrupt mask register imr 221 ddh r/w system mode register sym 222 deh r/w register page pointer pp 223 dfh r/w
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 2 t able 4- 2 . set 1, bank 0 registers register name mnemonic decimal hex r/w port 0 control high register p0 conh 224 e0h r/w port 0 control low register p0conl 225 e1h r/w port 0 interrupt control register p0int 226 e2h r/w port 0 interrupt pending register p0pnd 227 e3h r/w port 1 control high register p1conh 22 8 e 4 h r/w port 1 control low register p1conl 22 9 e 5 h r/w port 2 control high register p2conh 23 0 e 6 h r/w port 2 control low register p2conl 23 1 e 7 h r/w port 3 control high register p3conh 23 2 e 8 h r/w port 3 control low register p3conl 23 3 e 9 h r/w timer b data register (high byte) tbdatah 2 34 ea h r/w timer b data register (low byte) tbdatal 2 35 eb h r/w timer b control register tbcon 236 ech r/w timer a control register tacon 237 edh r/w timer a counter register tacnt 238 eeh r timer a data register tadata 239 efh r/w serial i/o control register siocon 240 f0h r/w serial i/o data register siodata 241 f1h r/w serial i/o pre-scale register siops 242 f2h r/w oscillator control register osccon 243 f3h r/w stop control register stpcon 244 f4h r/w port 1 pull-up control register p1pup 245 f5h r/w port 0 data register p0 246 f6h r/w port 1 data register p1 247 f7h r/w port 2 data register p2 248 f8h r/w port 3 data register p3 249 f9h r/w port 4 data register p4 250 fah r/w port 5 data register p5 251 f b h r/w location fch is factory use only. basic timer data register btcnt 253 fdh r external memory timing register emt 254 feh r/w interrupt priority register ipr 255 ffh r/w
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 3 table 4- 3 . set 1, bank 1 registers register name mnemonic decimal hex r/w locations e0h?ebh is not mapped. port 4 control high register p4conh 236 ech r/w port 4 control low register p4conl 237 edh r/w port 5 control high register p5conh 238 eeh r/w port 5 control low register p5conl 239 efh r/w locations f0h is factory use only. timer 0 control register t0con 241 f1h r/w timer 0 counter register (high byte) t0cnth 242 f2h r timer 0 counter register (low byte) t0cntl 243 f3h r timer 0 data register (high byte) t0datah 244 f4h r/w timer 0 data register (low byte) t0datal 245 f5h r/w voltage level detector control register vldcon 246 f6h r/w a/d converter control register adcon 247 f7h r/w a/d converter data register (high byte) addatah 248 f8h r/w a/d converter data register (low byte) addatal 249 f9h r/w watch timer control register wtcon 250 fah r/w timer 1 control register t1con 251 fbh r/w timer 1 counter register (high byte) t1cnth 252 fch r timer 1 counter register (low byte) t1cntl 253 fdh r timer 1 data register (high byte) t1datah 254 feh r/w timer 1 data register (low byte) t1datal 255 ffh r/w
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 4 flags - - system flags register .7 carry flag (c) .6 zero flag (z) .5 bit identifier reset reset value read/write bit addressing mode r = read-only w = write-only r/w = read/write '-' = not used type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) reset value notation: '-' = not used 'x' = undetermined value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing name of individual bit or related bits register name register id sign flag (s) 0 operation does not generate a carry or borrow condition 0 operation generates carry-out or borrow into high-order bit 7 0 operation result is a non-zero value 0 operation result is zero 0 operation generates positive number (msb = "0") 0 operation generates negative number (msb = "1") description of the effect of specific bit settings set 1 register location in the internal register file d5h register address (hexadecimal) .7 .6 .5 x x x r/w r/w r/w register addressing mode only .4 .3 .2 .1 .0 x r/w x r/w x r/w x r/w 0 r/w bit number: msb = bit 7 lsb = bit 0 figure 4-1. register description format
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 5 ad con ? a/d converter control register f7 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r r/w r/w r/w addressing mode register addressing mode only .7 not used for the s3c8248/c8245/c8247/c8249 . 6? . 4 a/d input pin selection bits 0 0 0 adc0 0 0 1 adc1 0 1 0 adc2 0 1 1 adc3 1 0 0 adc4 1 0 1 adc5 1 1 0 adc6 1 1 1 adc7 . 3 end-of-conversion bit (read-only) 0 conversion not complete 1 conversion complete .2? .1 clock source selection bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx .0 start or enable bit 0 disable operation 1 start operation
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 6 btcon ? basic timer control register d3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 watchdog timer function disable code (for system reset) 1 0 1 0 disable watchdog timer function others enable watchdog timer function .3? .2 basic timer input clock selection bits 0 0 fxx /4096 ( 3 ) 0 1 fxx /1024 1 0 fxx /128 1 1 fxx /16 .1 basic timer counter clear bit (1) 0 no effect 1 clear the basic timer counter value .0 clock frequency divider clear bit for basic timer and timer /counters (2) 0 no effect 1 clear both clock frequency dividers notes : 1. when you write a ?1? to btcon.1, the basic timer counter value is cleared to " 00h " . immediately following the write operation, the btcon.1 value is automatically cleared to ?0?. 2. when you write a "1" to btcon.0, the corresponding frequency divider is cleared to " 00h " . immediately following the write operation, the btcon.0 value is automatically cleared to "0". 3. the fxx is selected clock for system (main osc. or sub osc.).
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 7 clkcon ? system clock control register d4h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write ? ? ? r/w r/w ? ? ? addressing mode register addressing mode only .7? .5 not used for the s3c8248/c8245/c8247/c8249 .4? .3 cpu clock (system clock) selection bits (note) 0 0 fxx/16 0 1 fxx/8 1 0 fxx/2 1 1 fxx .2?.0 not used for the s3c8248/c8245/c8247/c8249 note : after a reset, the slowest clock (divided by 16) is selected as the system clock. to s elect faster clock speeds, load the appropriate v alues to clkcon.3 and clkcon.4.
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 8 emt ? external memory timing register fe h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? ? ? ? ? ? read/write ? ? ? ? ? ? ? ? addressing mode register addressing mode only .7?.0 not used for the s3c8248/c8245/c8247/c8249
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 9 flags ? system flags register d5h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r r/w addressing mode register addressing mode only .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is > +127 or < ?128 .3 decimal adjust flag (d) 0 add operation completed 1 subtraction operation completed .2 half-carry flag (h) 0 no carry-out of bit 3 or no borrow into bit 3 by addition or subtraction 1 addition generated carry-out of bit 3 or subtraction generated borrow into bit 3 .1 fast interrupt status flag (fis) 0 interrupt return (iret) in progress (when read) 1 fast interrupt service routine in progress (when read) .0 bank address selection flag (ba) 0 bank 0 is selected 1 bank 1 is selected
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 10 imr ? interrupt mask register ddh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only . 7 interrupt level 7 (irq 7 ) enable bit; external interrupts p0.4?0.7 0 disable (mask) 1 enable (unmask) .6 interrupt level 6 (irq6) enable bit; external interrupts p0.0?0.3 0 disable (mask) 1 enable (unmask) .5 interrupt level 5 (irq5) enable bit; watch timer overflow 0 disable (mask) 1 enable (unmask) .4 interrupt level 4 (irq4) enable bit; sio interrupt 0 disable (mask) 1 enable (unmask) . 3 interrupt level 3 (irq 3 ) enable bit; timer 1 match/capture or overflow 0 disable (mask) 1 enable (unmask) .2 interrupt level 2 (irq 2 ) enable bit; timer 0 match 0 disable (mask) 1 enable (unmask) .1 interrupt level 1 (irq1) enable bit; timer b match 0 disable (mask) 1 enable (unmask) .0 interrupt level 0 (irq0 ) enable bit; timer a match/capture or overflow 0 disable (mask) 1 enable (unmask) note: when an interrupt level is masked, any interrupt requests that may be issued are not recognized by the cpu.
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 11 i ntpnd ? interrupt pending register d 2 h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? 0 0 0 read/write ? ? ? ? ? r/w r/w r/w addressing mode register addressing mode only . 7?.3 not used for the s3c8248/c8245/c8247/c8249 .2 timer 1 overflow interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .1 timer 1 match/capture interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .0 timer a overflow interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 12 iph ? instruction pointer (high byte ) dah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (high byte) the high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (ip15?ip8). the lower byte of the ip address is located in the ipl register (dbh). ipl ? instruction pointer (low byte ) dbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (low byte) the low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (ip7 ? ip0). the upper byte of the ip address is located in the iph register (dah).
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 13 ipr ? interrupt priority register ffh set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7, .4, and .1 priority control bits for interrupt groups a, b, and c 0 0 0 group priority undefined 0 0 1 b > c > a 0 1 0 a > b > c 0 1 1 b > a > c 1 0 0 c > a > b 1 0 1 c > b > a 1 1 0 a > c > b 1 1 1 group priority undefined .6 interrupt subgroup c priority control bit 0 irq6 > irq7 1 irq7 > irq6 .5 interrupt group c priority control bit 0 irq5 > ( irq6 , irq7) 1 ( irq6 , irq7) > irq5 .3 interrupt subgroup b priority control bit 0 irq3 > irq4 1 irq4 > irq3 .2 interrupt group b priority control bit 0 irq2 > (irq3, irq4) 1 (irq3, irq4) > irq2 .0 interrupt group a priority control bit 0 irq0 > irq1 1 irq1 > irq0
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 14 irq ? interrupt request register dch set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r addressing mode register addressing mode only . 7 level 7 (irq 7 ) request pending bit; external interrupts p0.4?0.7 0 not pending 1 pending .6 level 6 (irq6) request pending bit; external interrupts p0.0?0.3 0 not pending 1 pending .5 level 5 (irq5) request pending bit; watch timer overflow 0 not pending 1 pending .4 level 4 (irq4) request pending bit; sio interrupt 0 not pending 1 pending . 3 level 3 (irq 3 ) request pending bit; timer 1 match/capture or overflow 0 not pending 1 pending . 2 level 2 (irq 2 ) request pending bit; timer 0 match 0 not pending 1 pending . 1 level 1 (irq1) request pending bit; timer b match 0 not pending 1 pending . 0 level 0 (irq0 ) request pending bit; timer a match/capture or overflow 0 not pending 1 pending
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 15 lcon ? lcd control register d0 h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w ? r/w r/w r/w addressing mode register addressing mode only . 7 lcd output segment and pin configuration bits 0 p5.4?p5.7 i/o is selected 1 seg28?seg31 is selected, p5.4?p5.7 i/o is disabled . 6 lcd output segment and pin configuration bits 0 p5.0?p5.3 i/o is selected 1 seg24?seg27 is selected, p5.0?p5.3 i/o is disabled . 5 lcd output segment and pin configuration bits 0 p4.4?p4.7 i/o is selected 1 seg20?eg23 is selected, p4.4?p4.7 i/o is disabled . 4 lcd output segment and pin configuration bits 0 p4.0?p4.3 i/o is selected 1 seg16?seg19 is selected, p4.0?p4.3 i/o is disabled . 3 not used for the s3c8248/c8245/c8247/c8249 . 2 lcd bias voltage selection bit 0 enable lcd initial circuit (internal bias voltage) 1 disable lcd initial circuit for external lcd driving resister (external bias voltage) . 1 voltage booster enable/disable bit 0 stop voltage booster (clock stop and cut off current charge path) 1 run voltage booster (clock run current and turn on charge path) . 0 lcd display control bit 0 lcd output low; turn display off, com and seg output low cut off voltage booster (booster clock disable) 1 com and seg output is in display mode; turn display on
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 16 lmod ? lcd mode control register d1h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? . 6 not used for the s3c8248/c8245/c8247/c8249 . 5? . 4 lcd clock (lcdck) frequency selection bits 0 0 32.768 khz watch timer clock ( fw)/2 9 = 64 hz 0 1 32.768 khz watch timer clock ( fw)/2 8 = 128 hz 1 0 32.768 khz watch timer clock ( fw)/2 7 = 256 hz 1 1 32.768 khz watch timer clock ( fw)/2 6 = 512 hz . 3? . 0 duty and bias selection for lcd display 0 x x x lcd display off (com and seg output low) 1 0 0 0 1/4 duty, 1/3 bias 1 0 0 1 1/3 duty, 1/3 bias 1 0 1 1 1/3 duty, 1/2 bias 1 0 1 0 1/2 duty, 1/2 bias 1 1 x x static
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 17 osccon ? oscillator control register f3h set 1 ,bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write ? ? ? r/w r/w r/w ? r/w addressing mode register addressing mode only . 7?.5 not used for the s3c8248/c8245/c8247/c8249 . 4 sub-system oscillator driving ability control bit 0 strong driving ability 1 normal driving ability . 3 main system oscillator control bit 0 main system oscillator run 1 main system oscillator stop . 2 sub system oscillator control bit 0 sub system oscillator run 1 sub system oscillator stop . 1 not used for the s3c8248/c8245/c8247/c8249 . 0 system clock selection bit 0 main oscillator select 1 subsystem oscillator select note: when osccon.4 is set to "0", sub operating current and sub idle current are large.
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 18 p0con h ? port 0 control register (high byte) e0h set 1,bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? . 6 p0.7/int7 0 0 schmitt trigger input mode; pull-up ; interrupt on falling edge 0 1 schmitt trigger input mode; interrupt on rising edge 1 0 schmitt trigger input mode; interrupt on rising or falling edge 1 1 output mode, push-pull . 5? . 4 p0.6/int6 0 0 schmitt trigger input mode; pull-up ; interrupt on falling edge 0 1 schmitt trigger input mode; interrupt on rising edge 1 0 schmitt trigger input mode; interrupt on rising or falling edge 1 1 output mode, push-pull . 3? . 2 p0.5/int5 0 0 schmitt trigger input mode; pull-up ; interrupt on falling edge 0 1 schmitt trigger input mode; interrupt on rising edge 1 0 schmitt trigger input mode; interrupt on rising or falling edge 1 1 output mode, push-pull . 1? . 0 p0.4/int4 0 0 schmitt trigger input mode; pull-up ; interrupt on falling edge 0 1 schmitt trigger input mode; interrupt on rising edge 1 0 schmitt trigger input mode; interrupt on rising or falling edge 1 1 output mode, push-pull
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 19 p0con l ? port 0 control register (low byte) e1h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? . 6 p0.3/int3 0 0 schmitt trigger input mode; pull-up ; interrupt on falling edge 0 1 schmitt trigger input mode; interrupt on rising edge 1 0 schmitt trigger input mode; interrupt on rising or falling edge 1 1 output mode, push-pull . 5? . 4 p0.2/int2 0 0 schmitt trigger input mode; pull-up ; interrupt on falling edge 0 1 schmitt trigger input mode; interrupt on rising edge 1 0 schmitt trigger input mode; interrupt on rising or falling edge 1 1 output mode, push-pull . 3? . 2 p0.1/int1 0 0 schmitt trigger input mode; pull-up ; interrupt on falling edge 0 1 schmitt trigger input mode; interrupt on rising edge 1 0 schmitt trigger input mode; interrupt on rising or falling edge 1 1 output mode, push-pull . 1? . 0 p0.0/int0 0 0 schmitt trigger input mode; pull-up ; interrupt on falling edge 0 1 schmitt trigger input mode; interrupt on rising edge 1 0 schmitt trigger input mode; interrupt on rising or falling edge 1 1 output mode, push-pull
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 20 p0 int ? port 0 interrupt control register e2h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p0.7 external interrupt (int7) enable bit 0 disable interrupt 1 enable interrupt .6 p0.6 external interrupt (int6) enable bit 0 disable interrupt 1 enable interrupt .5 p0.5 external interrupt (int5) enable bit 0 disable interrupt 1 enable interrupt .4 p0.4 external interrupt (int4) enable bit 0 disable interrupt 1 enable interrupt .3 p0.3 external interrupt (int3) enable bit 0 disable interrupt 1 enable interrupt .2 p0.2 external interrupt (int2) enable bit 0 disable interrupt 1 enable interrupt .1 p0.1 external interrupt (int1) enable bit 0 disable interrupt 1 enable interrupt .0 p0.0 external interrupt (int0) enable bit 0 disable interrupt 1 enable interrupt
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 21 p0 pnd ? port 0 interrupt pending register e3h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p0.7/int7 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .6 p0.6/int6 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .5 p0.5/int5 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .4 p0.4/int4 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .3 p0.3/int3 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .2 p0.2/int2 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .1 p0.1/int1 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .0 p0.0/int0 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 22 p 1 con h ? port 1 control register (high byte) e 4 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? . 6 p1.7/si 0 0 input mode (si) 0 1 output mode, open-drain 1 0 alternative function (push-pull output) 1 1 output mode, push-pull . 5? . 4 p1.6/sck 0 0 input mode (sck) 0 1 output mode, open-drain 1 0 alternative function (sck out) 1 1 output mode, push-pull . 3? . 2 p1.5/so 0 0 input mode 0 1 output mode, open-drain 1 0 alternative function (so) 1 1 output mode, push-pull . 1? . 0 p1.4/buz 0 0 input mode 0 1 output mode, open-drain 1 0 alternative function (buz) 1 1 output mode, push-pull
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 23 p 1 con l ? port 1 control register (low byte) e 5 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? . 6 p1.3 0 0 input mode 0 1 output mode, open-drain 1 0 alternative function (push-pull output mode) 1 1 output mode, push-pull . 5? . 4 p1.2/t1out/t1pwm 0 0 input mode 0 1 output mode, open-drain 1 0 alternative function (t1out, t1pwm) 1 1 output mode, push-pull . 3? . 2 p1.1/t1clk 0 0 input mode (t1clk) 0 1 output mode, open-drain 1 0 alternative function (push-pull output mode) 1 1 output mode, push-pull . 1? . 0 p1.0/t1cap 0 0 input mode (t1cap) 0 1 output mode, open-drain 1 0 alternative function (push-pull output mode) 1 1 output mode, push-pull
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 24 p 1pup ? port 1 pull-up control register f5h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p1.7 pull-up resistor enable bit 0 pull-up disable 1 pull-up enable .6 p1.6 pull-up resistor enable bit 0 pull-up disable 1 pull-up enable .5 p1.5 pull-up resistor enable bit 0 pull-up disable 1 pull-up enable .4 p1.4 pull-up resistor enable bit 0 pull-up disable 1 pull-up enable .3 p1.3 pull-up resistor enable bit 0 pull-up disable 1 pull-up enable .2 p1.2 pull-up resistor enable bit 0 pull-up disable 1 pull-up enable .1 p1.1 pull-up resistor enable bit 0 pull-up disable 1 pull-up enable .0 p1.0 pull-up resistor enable bit 0 pull-up disable 1 pull-up enable
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 25 p 2 conh ? port 2 control register (high byte ) e 6 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p2.7/vldref/adc7 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (adc & vld mode) 1 1 output mode, push-pull .5-.4 p2.6/adc6 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (adc mode) 1 1 output mode, push-pull .3?.2 p2.5/ adc5 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (adc mode) 1 1 output mode, push-pull .1? .0 p 2 .4 / adc4 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (adc mode) 1 1 output mode, push-pull
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 26 p 2 conl ? port 2 control register (low byte ) e7 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7? .6 p 2 .3 /adc3 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (adc mode) 1 1 output mode, push-pull .5? .4 p 2 .2 /adc2 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (adc mode) 1 1 output mode, push-pull .3? .2 p 2 .1 /adc1 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (adc mode) 1 1 output mode, push-pull .1? .0 p 2 .0 /adc0 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (adc mode) 1 1 output mode, push-pull
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 27 p 3 conh ? port 3 control register (high byte ) e 8 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write ? ? ? ? ? ? r/w r/w addressing mode register addressing mode only .7?.2 not used for the s3c8248/c8245/c8247/c8249 .1?.0 p3.4 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 x output mode, push-pull
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 28 p3 conl ? port 3 control register (low byte ) e9 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7? .6 p3. 3 /tacap mode selection bits 0 0 input mode (tacap) 0 1 input mode, pull-up (tacap) 1 0 output mode, push-pull 1 1 output mode, push-pull .5? .4 p3. 2 /taclk mode selection bits 0 0 input mode (taclk) 0 1 input mode, pull-up 1 0 output mode, push-pull 1 1 output mode, push-pull .3? .2 p3. 1 /taout/tapwm mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (taout or tapwm) 1 1 output mode, push-pull .1? .0 p3. 0 /tbpwm mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 alternative function (tbpwm) 1 1 output mode, push-pull
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 29 p4 conh ? port 4 control register (high byte ) e c h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p4.7/seg23 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .5?.4 p4.6/seg22 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .3?.2 p4.5/seg21 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .1? .0 p4. 4 /seg20 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 30 p4 conl ? port 4 control register (low byte ) ed h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7? .6 p4. 3 /seg19 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .5? .4 p4. 2 /seg18 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .3? .2 p4. 1 /seg17 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .1? .0 p4. 0 /seg16 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 31 p5conh ? port 5 control register (high byte ) ee h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p5.7/seg31 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .5?.4 p5.6/seg30 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .3?.2 p5.5/ seg29 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .1? .0 p5. 4 / seg28 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 32 p5 conl ? port 5 control register (low byte ) ef h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7? .6 p5. 3 /seg27 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .5? .4 p5. 2 /seg26 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .3? .2 p5. 1 /seg25 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode .1? .0 p5. 0 /seg24 mode selection bits 0 0 input mode 0 1 input mode, pull-up 1 0 open-drain output mode 1 1 push-pull output mode
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 33 pp ? register page pointer dfh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .4 destination register page selection bits 0 0 0 0 destination: page 0 0 0 0 1 destination: page 1 0 0 1 0 destination: page 2 0 0 1 1 destination: page 3 0 1 0 0 destination: page 4 .3 ? .0 source register page selection bits 0 0 0 0 source: page 0 0 0 0 1 source: page 1 0 0 1 0 source: page 2 0 0 1 1 source: page 3 0 1 0 0 source: page 4 note: in the s3c8247/c8249 microcontroller, the internal register file is configured as five pages (pages 0-4). the pages 0-3 are us ed for general purpose register file, and page 4 is used for lcd data register or general purpose registers. in case of s3c8248/c8245, pages 0-1 are used for general purpose and page 2 is used for lcd data register or general purpose registers.
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 34 rp0 ? register pointer 0 d6h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7 ? .3 register pointer 0 address value register pointer 0 can independently point to one of the 256 -byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp0 points to address c0h in register set 1, selecting the 8-byte working register slice c0h ? c7h. .2 ? .0 not used for the s3c8248/c8245/c8247/c8249 rp1 ? register pointer 1 d7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 1 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7 ? .3 register pointer 1 address value register pointer 1 can independently point to one of the 256 -byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp1 points to address c8h in register set 1, selecting the 8-byte working register slice c8h?cfh. .2 ? .0 not used for the s3c8248/c8245/c8247/c8249
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 35 siocon ? sio control register fo h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 sio shift clock selection bit 0 internal clock ( p.s clock) 1 external clock (sck) .6 data direction control bit 0 msb-first mode 1 lsb-first mode .5 sio mode selection bit 0 receive-only mode 1 transmit/receive mode . 4 shift clock edge selection bit 0 tx at falling edges, rx at rising edges 1 tx at rising edges, rx at falling edges .3 sio counter clear and shift start bit 0 no action 1 clear 3-bit counter and start shifting .2 sio shift operation enable bit 0 disable shifter and clock counter 1 enable shifter and clock counter .1 sio interrupt enable bit 0 disable sio interrupt 1 enable sio interrupt .0 sio interrupt pending bit 0 no interrupt pending 0 clear pending condition (when write) 1 interrupt is pending
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 36 sph ? stack pointer (high byte ) d8h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 stack pointer address (high byte) the high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (sp15?sp8). the lower byte of the stack pointer value is located in register spl (d9h). the sp value is undefined following a reset. spl ? stack pointer (low byte ) d9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 stack pointer address (low byte) the low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (sp7?sp0). the upper byte of the stack pointer value is located in register sph (d8h). the sp value is undefined following a reset.
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 37 stpcon ? stop control register f 4 h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ?.0 stop control bits 1 0 1 0 0 1 0 1 enable stop instruction other values disable stop instruction note: before execute the stop instruction, you must set this stpcon register as ?10100101b?. otherwise the stop instr uction will not execute.
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 38 sym ? system mode register de h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? x x x 0 0 read/write r/w ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 not used, but you must keep "0" .6? .5 not used for the s3c8248/c8245/c8247/c8249 .4 ? .2 fast interrupt level selection bits ( 1 ) 0 0 0 irq0 0 0 1 irq1 0 1 0 irq2 0 1 1 irq3 1 0 0 irq4 1 0 1 irq5 1 1 0 irq6 1 1 1 irq7 .1 fast interrupt enable bit ( 2 ) 0 disable fast interrupt processing 1 enable fast interrupt processing .0 global interrupt enable bit ( 3 ) 0 disable all interrupt processing 1 enable all interrupt processing notes : 1 . you can select only one interrupt level at a time for fast interrupt processing. 2 . setting sym.1 to "1" enables fast interrupt processing for the interrupt level currently selected by sym.2 ?sym.4. 3 . following a reset, you must enable global interrupt processing by executing an ei instruction (not by writing a "1" to sym.0).
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 39 t0con ? timer 0 control register f1 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.5 timer 0 input clock selection bits 0 0 0 tbof (t-ff) 0 1 0 fxx/256 1 0 0 fxx/64 1 1 0 fxx/8 x x 1 fxx .4 timer 0 operating mode selection bits not used for the s3c8248/c8245/c8247/c8249 .3 timer 0 counter clear bit 0 no effect 1 clear the timer 0 counter (when write) .2 timer 0 counter enable bit 0 disable counting operation 1 enable counting operation .1 timer 0 interrupt enable bit 0 disable timer 0 interrupt 1 enable timer 0 interrupt .0 timer 0 interrupt pending bit 0 no timer 0 interrupt pending (when read) 0 clear timer 0 interrupt pending condition (when write) 1 t0 interrupt is pending
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 40 t1con ? timer 1 control register fb h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.5 timer 1 input clock selection bits 0 0 0 fxx/1024 0 1 0 fxx/256 1 0 0 fxx/64 1 1 0 fxx/8 0 0 1 fxx/1 0 1 1 external clock (t1clk) falling edge 1 0 1 external clock (t1clk) rising edge 1 1 1 counter stop . 4?.3 timer 1 operating mode selection bits 0 0 interval mode 0 1 capture mode (capture on rising edge, counter running, ovf can occur) 1 0 capture mode (capture on falling edge, counter running, ovf can occur) 1 1 pwm mode (ovf & match interrupt can occur) .2 timer 1 counter enable bit 0 no effect 1 clear the timer 1 counter (when write) .1 timer 1 match/capture interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 1 overflow interrupt enable 0 disable overflow interrupt 1 enable overflow interrupt
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 41 t a con ? timer a control register ed h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 timer a input clock selection bits 0 0 fxx/1024 0 1 fxx/256 1 0 fxx/64 1 1 external clock (taclk) . 5? .4 timer a operating mode selection bits 0 0 internal mode (taout mode) 0 1 capture mode (capture on rising edge, counter running, ovf can occur) 1 0 capture mode (capture on falling edge, counter running, ovf can occur) 1 1 pwm mode (ovf interrupt can occur) .3 timer a counter clear bit 0 no effect 1 clear the timer a counter (when write) .2 timer a overflow interrupt enable bit 0 disable overflow interrupt 1 enable overflow interrupt .1 timer a match/capture interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer a match/capture interrupt pending bit 0 no interrupt pending 0 clear pending bit ( write) 1 i nterrupt is pending
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 42 t b con ? timer b control register ec h set 1 , bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 timer b input clock selection bits 0 0 fxx 0 1 fxx/2 1 0 fxx/4 1 1 fxx/8 .5?.4 timer b interrupt time selection bits 0 0 elapsed time for low data value 0 1 elapsed time for high data value 1 0 elapsed time for low and high data values 1 1 invalid setting .3 timer b interrupt enable bit 0 disable interrupt 1 enable interrupt . 2 timer b start/stop bit 0 stop timer b 1 start timer b .1 timer b mode selection bit 0 one-shot mode 1 repeating mode .0 timer b output flip-flop control bit 0 t-ff is low 1 t-ff is high note: fxx is selected clock for system.
s3c8248/c8245/p8245/c8247/c8249/p8249 c ontrol register 4- 43 vldcon ? voltage level detector control register f6 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write ? ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ?.5 not used for the s3c8248/c8245/c8247/c8249 . 4 v in source bit 0 internal source 1 external source . 3 v ld output bit 0 v in > v ref (when vld is enabled) 1 v in < v ref (when vld is enabled) . 2 v ld enable/disable bit 0 disable the vld 1 enable the vld . 1?.0 detection level bits 0 0 v vld = 2.2 v 0 1 v vld = 2.4 v 1 0 v vld = 3.0 v 1 1 v vld = 4.0 v
control registers s 3c8248/c8245/p8245/c8247/c8249/p8249 4- 44 wt con ? watch timer control register fa h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only . 7 watch timer clock selection bit 0 main system clock divided by 2 7 (fxx/128) 1 sub system clock ( fxt) . 6 watch timer interrupt enable bit 0 disable watch timer interrupt 1 enable watch timer interrupt .5? .4 buzzer signal selection bits 0 0 0.5 khz buzzer (buz) signal output 0 1 1 khz buzzer (buz) signal output 1 0 2 khz buzzer (buz) signal output 1 1 4 khz buzzer (buz) signal output .3 ?.2 watch timer speed selection bits 0 0 0.5 s interval 0 1 0.25 s interval 1 0 0.125 s interval 1 1 1.955 ms interval .1 watch timer enable bit 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer .0 watch timer interrupt pending bit 0 interrupt is not pending, clear pending bit when write 1 interrupt is pending note: watch timer clock frequency(fw) is assumed to be 32768hz.
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 1 5 interrupt structure overview the s3c8-series interrupt structure has three basic components: levels, vectors, and sources. the sam8 cpu recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. when a specific interrupt level has more than one vec t or address, the vector priorities are established in hardware . a vector address can be assigned to one or more sources. levels interrupt levels are the main unit for interrupt priority assignment and recognition. all peripherals and i/o blocks can issue interrupt requests. in other words, peripheral and i/o operations are interrupt-driven. there are eight possible interrupt levels: irq0?irq7, also called level 0?level 7. each interrupt level directly corresponds to an interrupt request number ( irqn). the total number of interrupt levels used in the interrupt structure varies fr om device to device. the s3c8248/c8245/c8247/c8249 interrupt structure recognizes eight interrupt levels. the interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. they are just identifiers for the interrupt levels that are recognized by the cpu. the relative priority of different interrupt levels is determined by settings in the interrupt priority register, ipr. interrupt group and subgroup logic controlled by ipr settings lets you define more complex priority relationships between different levels. vectors each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. the maximum number of vectors that can be supported for a given level is 128 (the actual number of vectors used for s3c8 -series devices is always much smaller) . if an interrupt level has more than one vector address, the vector priorities are set in hardware. s3c8248/c8245/c8247/c8249 uses sixteen vectors . sources a source is any peripheral that generates an interrupt. a source can be an external pin or a counter overflow . each vector can have several interrupt sources. in the s3c8248/c8245/c8247/c8249 interrupt structure, there are sixteen possible interrupt sources. when a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. the characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit.
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 2 interrupt types the three components of the s3c8 interrupt structure described before ? levels, vectors, and sources ? are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. there are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. the types differ in the number of vectors and interrupt sources assigned to each level (see figure 5-1): type 1: one level ( irqn) + one vector (v 1 ) + one source (s 1 ) type 2: one level ( irqn) + one vector (v 1 ) + multiple sources (s 1 ? s n ) type 3: one level ( irqn) + multiple vectors (v 1 ? v n ) + multiple sources (s 1 ? s n , s n+1 ? s n+m ) in the s3c8248/c8245/c8247/c8249 microcontroller, two interrupt types are implemented. vectors sources levels s 1 v 1 s 2 type 2: irqn s 3 s n v 1 s 1 v 2 s 2 type 3: irqn v 3 s 3 v 1 s 1 type 1: irqn v n s n + 1 s n s n + 2 s n + m notes: 1. the number of s n and v n value is expandable. 2. in the s3c8248/c8245/c8247/c8249 implementation, interrupt types 1 and 3 are used. figure 5-1. s 3c8 -series interrupt types
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 3 s3c8248/c8245/c8247/c8249 interrupt structure the s3c8248/c8245/c8247/c8249 microcontroller supports sixteen interrupt sources. all sixteen of the interrupt source s ha ve a corresponding interrupt vector address. eight interrupt levels are recognized by the cpu in this device-specific interrupt structure, as shown in figure 5-2. when multiple interrupt levels are active, the interrupt priority register (ipr) determines the order in which contending interrupts are to be serviced. if multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (the relative priorities of multiple interrupts within a single level are fixed in hardware) . when the cpu grants an interrupt request, interrupt processing starts . all other interrupts are disabled and the program counter value and status flags are pushed to stack. the starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. vectors sources levels reset/clear notes: 1. within a given interrupt level, the low vector address has high priority. for example, e0h has higher priority than e2h within the level irq.0 the priorities within each level are set at the factory. 2. external interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting. irq3 e8h timer 1 match/capture eah timer 1 overflow timer b match e4h timer 0 match e6h irq1 irq2 h/w sio interrupt ech watch timer overflow eeh irq4 irq5 p0.0 external interrupt p0.1 external interrupt p0.2 external interrupt p0.3 external interrupt irq6 f0h f2h f4h f6h p0.4 external interrupt p0.5 external interrupt p0.6 external interrupt p0.7 external interrupt irq7 f8h fah fch feh e0h timer a match/capture irq0 e2h timer a overflow h/w,s/w h/w,s/w h/w,s/w h/w,s/w h/w,s/w s/w s/w s/w s/w s/w s/w s/w s/w s/w s/w figure 5-2. s3c8248/c8245/c8247/c8249 interrupt structure
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 4 interrupt vector addresses all interrupt vector addresses for the s3c8248/c8245/c8247/c8249 interrupt structure are stored in the vector address area of the internal 32- kbyte rom, 0h? 7 f ff h , or 8, 16, 24-kbyte (see figure 5-3). you can allocate unused locations in the vector address area as normal program memory. if you do so, please be careful not to overwrite any of the stored vector addresses (table 5-1 lists all vector addresses) . the program reset address in the rom is 0100h. 32,767 0 (decimal) 255 00h 100h ffh 7fffh (hex) reset address interrupt vector address area 3fffh 16,383 internal program memory (rom) area 32-kbyte 16-kbyte figure 5-3. rom vector address area
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 5 table 5-1. i nterrupt vectors vector address interrupt source request reset/clear decimal value hex value interrupt level priority in level h/w s/w 256 100h basic timer overflow reset ? ? 226 e2 h timer a overflow irq0 1 ? ? 224 e0 h timer a match/capture 0 ? ? 228 e4 h timer b match irq1 ? ? 230 e6 h timer 0 match irq2 ? ? ? 234 eah timer 1 overflow irq 3 1 ? ? 232 e8h timer 1 match/capture 0 ? ? 236 ech sio interrupt irq4 ? ? 238 eeh watch timer overflow irq5 ? ? 246 f6h p0.3 external interrupt irq 6 3 ? 244 f4h p0.2 external interrupt 2 ? 242 f2h p0.1 external interrupt 1 ? 240 f0h p0.0 external interrupt 0 ? 254 feh p0.7 external interrupt irq7 3 ? 252 fch p0.6 external interrupt 2 ? 250 fah p0.5 external interrupt 1 ? 248 f8h p0.4 external interrupt 0 ? notes: 1. interrupt priorities are identified in inverse order: " 0 " is the highest priority, " 1 " is the next highest, and so on. 2. if two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. the priorities within a given level are fixed in hardware. 3. timer a or timer 1 can not service two interrupt sources simultaneously, then only one interrupt source have to be used.
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 6 enable/disable interrupt instructions (ei, di ) executing the enable interrupts (ei) instruction globally enables the interrupt structure. all interrupts are then serviced as they occur according to the established priorities. note the system initialization routine executed after a reset must always contain an ei instruction to globally enable the interrupt structure. during the normal operation, you can execute the di (disable interrupt) instruction at any time to globally disable interrupt processing. the ei and di instructions change the value of bit 0 in the sym register. system-level interrupt control registers in addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: ? the interrupt mask register, imr, enables ( un-masks) or disables (masks) interrupt levels. ? the interrupt priority register, ipr, controls the relative priorities of interrupt levels. ? the interrupt request register, irq, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). ? the system mode register, sym, enables or disables global interrupt processing (sym settings also enab le fast interrupts and control the activity of external interface, if implemented) . table 5-2. interrupt control register overview control register id r/w function description interrupt mask register imr r/w bit settings in the imr register enable or disable interrupt processing for each of the eight interrupt levels: irq0?irq7. interrupt priority register ipr r/w controls the relative processing priorities of the interrupt levels. the seven levels of s3c8248/c8245/c8247/c8249 are organized into three groups: a, b, and c. group a is irq0 and irq1, group b is irq2, irq3 and irq4, and group c is irq5 , irq6 , and irq7 . interrupt request register irq r this register contains a request pending bit for each interrupt level. system mode register sym r/w this register enable s/ disable s fast interrupt processing, d ynamic global interrupt processing, and external interface control (an external memory interface is implemented in the s3c8248/c8245/c8247/c8249 microcontroller). note: before imr register is changed t o any value, all interrupts must be disable. using di instruction is recommended.
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 7 interrupt processing control points interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. t he system-level control points in the interr upt structure are : ? global interrupt enable and disable (by ei and di instructions or by direct manipulation of sym.0 ) ? interrupt level enable/disable settings (imr register) ? interrupt level priority settings (ipr register) ? int errupt source enable/disable settings in the corresponding peripheral control registers note when writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. interrupt request register (read-only) irq0-irq7, interrupts interrupt mask register polling cycle interrupt priority register global interrupt control (ei, di or sym.0 manipulation) s r q reset ei vector interrupt cycle figure 5-4. interrupt function diagram
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 8 peripheral interrupt control registers for each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see table 5-3). table 5-3. interrupt source control and data registers interrupt source interrupt level register(s) location(s) in set 1 timer a overflow timer a match/capture irq0 tacon tacint tadata edh, bank 0 eeh, bank 0 efh, bank 0 timer b match irq1 tbcon tbdatah, tbdatal ech, bank 0 eah, ebh, bank 0 timer 0 match irq2 t0con, t0cnth t0cntl, t0datah t0datal f1h, f2h, bank 1 f3h, f4h, bank 1 f5h, bank 1 timer 1 overflow timer 1 match/capture irq3 t1con t1cnth t1cntl t1datah t1datal fbh, bank 1 fch, bank 1 fdh, bank 1 feh, bank 1 ffh, bank 1 sio interrupt irq4 siocon siodata siops f0h, bank 0 f1h, bank 0 f2h, bank 0 watch timer overflow irq5 wtcon fah, bank 1 p0.3 external interrupt p0.2 external interrupt p0.1 external interrupt p0.0 external interrupt irq6 p0conl p0int p0pnd e1h, bank 0 e2h, bank 0 e3h, bank 0 p0.7 external interrupt p0.6 external interrupt p0.5 external interrupt p0.4 external interrupt irq7 p0conh p0int p0pnd e0h, bank 0 e2h, bank 0 e3h, bank 0 note : because the timer 0 overflow interrupt is cleared by hardware, the t0con register controls only the enable/disable functions. the t0con register contains enable/disable and pending bits for the timer 0 match/capture interrupt.
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 9 system mode register (sym ) the system mode register, sym (set 1, deh), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see figure 5-5). a reset clears sym.1, and sym.0 to "0". the 3-bit value for fast interrupt level selection, sym.4?sym.2, is undetermined. the instructions ei and di enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the sym register. i n order to enable interrupt processing a n enable interrupt (ei) instruction must be included in the initialization routine, which follows a reset operation. although you can manipulate sym.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the ei and di instructions for this purpose. system mode register (sym) deh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb global interrupt enable bit: 0 = disable all interrupts processing 1 = enable all interrupts processing fast interrupt enable bit: 0 = disable fast interrupts processing 1 = enable fast interrupts processing fast interrupt level selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 not used for the s3c8248/c8245/c8247/c8249 figure 5-5. system mode register (sym )
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 10 interrupt mask register (imr ) the interrupt mask register, imr (set 1, ddh) is used to enable or disable interrupt processing for individual interrupt levels. after a reset, all imr bit values are undetermined and must therefore be written to their required settings by the initialization routine. each imr bit corresponds to a specific interrupt level: bit 1 to irq1, bit 2 to irq2, and so on. when the imr bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). when you set a level's imr bit to "1", interrupt processing for the level is enabled (not masked). the imr register is mapped to register location ddh in set 1. bit values can be read and written by instructions using the register addressing mode. interrupt mask register (imr) ddh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 irq2 irq4 irq5 irq6 irq7 irq0 interrupt level enable bits (7-4, 2-0) 0 = disable (mask) interrupt level 1 = enable (un-mask) interrupt level irq3 note: before imr register is changed to any value, all interrupts must be disable. using di instruction is recommended. figure 5-6. interrupt mask register (imr )
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 11 interrupt priority register (ipr ) the interrupt priority register, ipr (set 1, bank 0, ffh), is used to set the relative priorities of the interrupt levels in the microcontroller?s interrupt structure. after a reset, all ipr bit values are undetermined and must therefore be written to their required settings by the initialization routine. when more than one interrupt source s are active, the source with the highest priority level is serviced first. if two sources belong to the same interrupt level, the source with the lowe r vector address usually has the priority (this priority is fixed in hardware) . to support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. please note that these groups (and subgroups) are used only by ipr logic for the ipr register priority definitions (see figure 5-7): group a irq0, irq1 group b irq 2, irq3, irq3 group c irq5, irq6 , irq7 ipr group b ipr group c irq2 b1 irq4 b2 irq3 b22 b21 irq5 c1 irq7 c2 irq6 c22 c21 ipr group a irq1 a2 irq0 a1 figure 5-7. interrupt request priority groups as you can see in figure 5-8, ipr.7, ipr.4, and ipr.1 control the relative priority of interrupt groups a, b, and c. for example, the setting " 001b " for these bits would select the group relationship b > c > a . t he setting " 101b " would select the relationship c > b > a. the functions of the other ipr bit settings are as follows: ? ipr.5 controls the relative priorities of group c interrupts. ? interrupt group c includes a subgroup that has an additional priority relationship among the interrupt levels 5 , 6 , and 7 . ipr. 6 defines the subgroup c relationship . ipr. 5 controls the interrupt group c . ? ipr.0 controls the relative priority setting of irq0 and irq1 interrupts.
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 12 interrupt priority register (ipr) feh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb group a 0 = irq0 > irq1 1 = irq1 > irq0 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 group c 0 = irq5 > (irq6, irq7) 1 = (irq6, irq7) > irq5 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 group b 0 = irq2 > (irq3, irq4) 1 = (irq3, irq4) > irq2 group priority: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 = undefined = b > c > a = a > b > c = b > a > c = c > a > b = c > b > a = a > c > b = undefined d7 d4 d1 figure 5-8. interrupt priority register (ipr )
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 13 interrupt request register (irq ) you can poll bit values in the interrupt request register, irq (set 1, dch), to monitor interrupt request status for all levels in the microcontroller?s interrupt structure. each bit corresponds to the interrupt level of the same number: bit 0 to irq0, bit 1 to irq1, and so on. a "0" indicates that no interrupt request is currently being issued for that level . a "1" indicates that an interrupt request has been generated for that level. irq bit values are read-only addressable using register addressing mode. you can read (test) the contents of the irq register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. after a reset, all irq status bits are cleared to ?0?. you can poll irq register values even if a di instruction has been executed (that is, if global interrupt processing is disabled). if an interrupt occurs while the interrupt structure is disabled, the cpu will not service it. you can, however, still detect the interrupt request by polling the irq register. in this way, you can determine which events occurred while the interrupt structure was globally disabled. interrupt request register (irq) dch, set 1, read-only .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 irq2 irq3 irq4 irq5 irq6 irq7 irq0 interrupt level request pending bits: 0 = interrupt level is not pending 1 = interrupt level is pending figure 5-9. interrupt request register (irq )
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 14 interrupt pending function types overview there are two types of interrupt pending bits: o ne type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. pending bits cleared automatically by hardware for interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. it then issues an irq pulse to inform the cpu that an interrupt is waiting to be serviced. the cpu acknowledges the interrupt source by sending an iack, executes the service routine, and clears the pending bit to "0". this type of pending bit is not mapped and cannot, therefore, be read or written by application software. in the s3c8248/c8245/c8247/c8249 interrupt structure, the timer 0 overflow interrupt (irq0 ) belongs to this category of interrupts in which pending condition is cleared automatically by hardware. pending bits cleared by the service routine the second type of pending bit is the one that should be cleared by program software. the service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (iret) occurs. to do this, a "0" must be written to the corresponding pending bit location in the source?s mode or control register.
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 15 interrupt source polling sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request bit to "1". 2. the cpu polling procedure identifies a pending condition for that source. 3. the cpu checks the source's interrupt lev el. 4. the cpu generates an interrupt acknowledge signal. 5. interrupt logic determines the interrupt's vector address. 6. the service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. the cpu continues polling for interrupt requests. interrupt service routines before an interrupt request is serviced, the following conditions must be met: ? interrupt processing must be globally enabled (ei, sym.0 = "1") ? the interrupt level must be enabled (imr register) ? the i nterrupt level must have the highest priority if more than one level s are currently requesting service ? the interrupt must be enabled at the interrupt's source (peripheral control register) when all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the interrupt enable bit in the sym register (sym.0) to disable all subsequent inte rrupts. 2. save the program counter (pc) and status flags to the system stack. 3. branch to the interrupt vector to fetch the address of the service routine. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, the cpu issues an interrupt return (iret). the iret restores the pc and status flags , set ting sym.0 to "1" . it allows the cpu to process the next interrupt request.
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 16 generating interrupt vector addresses the interrupt vector area in the rom (00h?ffh) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to the stack. 2. push the program counter's high-byte value to the stack. 3. push the flag register values to the stack. 4. fetch the service routine's high-byte address from the vector location. 5. fetch the service routine's low-byte address from the vector location. 6. branch to the service routine spe cified by the concatenated 16-bit vector address. note a 16-bit vector address always begins at an even-numbered rom address within the range of 00h?ffh. nesting of vectored interrupts it is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. to do this, you must follow these steps: 1. push the current 8-bit interrupt mask register (imr) value to the stack (push imr). 2. load the imr register with a new mask value that enables only the higher priority inte rrupt. 3. execute an ei instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. when the lower-priority interrupt service routine ends, restore the imr to its original value by returning the previous mask value from the stack (pop imr). 5. execute an iret. depending on the application, you may be able to simplify the procedure above to some extent. instruction pointer (ip ) the instruction pointer (ip) is adopted by all the s3c8 -series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts . the ip consists of register pair dah and dbh. the names of ip register s are iph (high byte, ip15?ip8) and ipl (low byte, ip7?ip0). fast interrupt processing the feature called fast interrupt processing allows an interrupt within a given level to be completed in approxim ately 6 clock cycles rather than the usual 16 clock cycles. to select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to sym.4?sym.2. then, to enable fast interrupt processing for the selected level, you set sym.1 to ?1?.
s3c8248/c8245/p8245/c8247/c8249/p8249 interrupt structure 5 - 17 fast interrupt processing ( continued) two other system registers support fast interrupt processing: ? the instruction pointer (ip) contains the starting address of the service routine (and is later used to swap the program counter values), and ? when a fast interrupt occurs, the contents of the flags register is stored in an unmapped, dedicated register called flags' (?flags prime?). note for the s3c8248/c8245/c8247/c8249 microcontroller, the service routine for any one of the eight interrupt levels: irq0?irq7 , can be selected for fast interrupt processing. procedure for initiating fast interrupts to initiate fast interrupt processing, follow these steps: 1. load the start address of the service routine into the instruction pointer (ip). 2. load the interrupt level number ( irqn) into the fast interrupt selection field (sym.4?sym.2) 3. write a "1" to the fast interrupt enable bit in the sym regist er. fast interrupt service routine when an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. the contents of the instruction pointer and the pc are swapped. 2. the flag register values are written to the flags' ( ?flags prime?) register. 3. the fast interrupt status bit in the flags register is set. 4. the interrupt is serviced. 5. assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and pc values are swapped back. 6. the content of flags' ( ?flags prime?) is copied automatically back to the flags register. 7. the fast interrupt status bit in flags is cleared automatically. relationship to interrupt pending bit types as described previously, there are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed ; the other that must be cleared by the application program's interrupt service routine. you can select fast interrupt processing for interrupts with either type of pending condition clear function ? by hardware or by software. programming guidelines remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the sym register, sym.1. executing an ei or di instruction globally enables or disables all interrupt processing, including fast interrupts. if you use fast interrupts, remember to load the ip with a new start address when the fast interrupt service routine ends.
interrupt structure s3c8248/c8245/p8245 /c8247/c8249/p8249 5- 18 notes
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 1 6 instruction set overview the sam8 instruction set is specifically designed to support the large register files that are typical of most sam8 microcontrollers. there are 78 instructions. the powerful data manipulation capabilities and features of the instruction set include: ? a full complement of 8-bit arithmetic and logic operations, including multiply and divide ? no special i/o instructions (i/o control/data registers are mapped directly into the register file) ? decimal adjustment included in binary-coded decimal (bcd) operations ? 16-bit (word) data can be incremented and decremented ? flexible instructions for bit addressing, rotate, and shift operations data types the sam8 cpu performs operations on bits, bytes, bcd digits, and two-byte words. bits in the register file can be set, cleared, complemented, and tested. bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. register addressing to access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. for detailed information about register addressing, please refer to section 2, "address spaces." addressing modes there are seven explicit addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), immediate (im), and indirect (ia). for detailed descriptions of these addressing modes, please refer to section 3, "addressing modes."
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 2 table 6-1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldb dst,src load bit lde dst,src load external data memory ldc dst,src load program memory lded dst,src load external data memory and decrement ldcd dst,src load program memory and decrement ldei dst,src load external data memory and increment ldci dst,src load program memory and increment ldepd dst,src load external data memory with pre-decrement ldcpd dst,src load program memory with pre-decrement ldepi dst,src load external data memory with pre-increment ldcpi dst,src load program memory with pre-increment ldw dst,src load word pop dst pop from stack popud dst,src pop user stack (decrementing) popui dst,src pop user stack (incrementing) push src push to stack pushud dst,src push user stack (decrementing) pushui dst,src push user stack (incrementing)
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 3 table 6-1. instruction group summary (continued) mnemonic operands instruction arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare da dst decimal adjust dec dst decrement decw dst decrement word div dst,src divide inc dst increment incw dst increment word mult dst,src multiply sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 4 table 6-1. instruction group summary (continued) mnemonic operands instruction program control instructions btjrf dst,src bit test and jump relative on false btjrt dst,src bit test and jump relative on true call dst call procedure cpije dst,src compare, increment and jump on equal cpijne dst,src compare, increment and jump on non-equal djnz r,dst decrement register and jump on non-zero enter enter exit exit iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code next next ret return wfi wait for interrupt bit manipulation instructions band dst,src bit and bcp dst,src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst,src bit or bxor dst,src bit xor tcm dst,src test complement under mask tm dst,src test under mask
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 5 table 6-1. instruction group summary (concluded) mnemonic operands instruction rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag sb0 set bank 0 sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer 0 srp1 src set register pointer 1 stop enter stop mode
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 6 flags register (flags) the flags register flags contains eight bits that describe the current status of cpu operations. four of these bits, flags.7?flags.4, can be tested and used with conditional jump instructions; two others flags.3 and flags.2 are used for bcd arithmetic. the flags register also contains a bit to indicate the status of fast interrupt processing (flags.1) and a bank address status bit (flags.0) to indicate whether bank 0 or bank 1 is currently being addressed. flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. system flags register (flags) d5h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb bank address status flag (ba) first interrupt status flag (fis) half-carry flag (h) decimal adjust flag (d) overflow (v) sign flag (s) zero flag (z) carry flag (c) figure 6-1. system flags register (flags)
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 7 flag descriptions c carry flag (flags.7) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag. z zero flag (flags.6) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. s sign flag (flags.5) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. v overflow flag (flags.4) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. d decimal adjust flag (flags.3) the da bit is used to specify what type of instruction was executed last during bcd operations, so that a subsequent decimal adjust operation can execute correctly. the da bit is not usually accessed by programmers, and cannot be used as a test condition. h half-carry flag (flags.2) the h bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. it is used by the decimal adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (bcd) result. the h flag is seldom accessed directly by a program. fis fast interrupt status flag (flags.1) the fis bit is set during a fast interrupt cycle and reset during the iret following interrupt servicing. when set, it inhibits all interrupts and causes the fast interrupt return to be executed when the iret instruction is executed. ba bank address flag (flags.0) the ba flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. the ba flag is cleared to "0" (select bank 0) when you execute the sb0 instruction and is set to "1" (select bank 1) when you execute the sb1 instruction.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 8 instruction set notation table 6-2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6-3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter ip instruction pointer flags flags register (d5h) rp register pointer # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 9 table 6-4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6-6. r working register only rn (n = 0?15) rb bit (b) of working register rn.b (n = 0?15, b = 0?7) r0 bit 0 (lsb) of working register rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn (reg = 0?255, n = 0?15) rb bit 'b' of register or working register reg.b (reg = 0?255, b = 0?7) rr register pair or working register pair reg or rrp (reg = 0?254, even number only, where p = 0, 2, ..., 14) ia indirect addressing mode addr (addr = 0?254, even number only) ir indirect working register only @rn (n = 0?15) ir indirect register or indirect working register @rn or @reg (reg = 0?255, n = 0?15) irr indirect working register pair only @rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @rrp or @reg (reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode #reg [rn] (reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode #addr [rrp] (addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode #addr [rrp] (addr = range 0?65535, where p = 0, 2, ..., 14) da direct addressing mode addr (addr = range 0?65535) ra relative addressing mode addr (addr = number in the range +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255) iml immediate (long) addressing mode #data (data = range 0?65535)
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 10 table 6-5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im bor r0?rb p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im bcp r1.b, r2 p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im bxor r0?rb e 3 jp irr1 srp/0/1 im sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im btjr r2.b, ra r 4 da r1 da ir1 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im ldb r0?rb 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im bitc r1.b n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im band r0?rb i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im bit r1.b b 8 decw rr1 decw ir1 pushud ir1,r2 pushui ir1,r2 mult r2,rr1 mult ir2,rr1 mult im,rr1 ld r1, x, r2 b 9 rl r1 rl ir1 popud ir2,r1 popui ir2,r1 div r2,rr1 div ir2,rr1 div im,rr1 ld r2, x, r1 l a incw rr1 incw ir1 cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 cpije ir,r2,ra ldc r1,irr2 ldw rr2,rr1 ldw ir2,rr1 ldw rr1,iml ld r1, ir2 h d sra r1 sra ir1 cpijne irr,r2,ra ldc r2,irr1 call ia1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f swap r1 swap ir1 ldcpd r2,irr1 ldcpi r2,irr1 call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 11 table 6-5. opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 next p 1 enter p 2 exit e 3 wfi r 4 sb0 5 sb1 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 nop
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 12 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6-6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6-6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (note) c carry c = 1 1111 (note) nc no carry c = 0 0110 (note) z zero z = 1 1110 (note) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (note) eq equal z = 1 1110 (note) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (note) uge unsigned greater than or equal c = 0 0111 (note) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicates condition codes that are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 13 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam8 instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 14 adc ? add with carry adc dst,src operation: dst ? dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's- complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, desti nation register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 15 add ? add add dst,src operation: dst ? dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, register 02h = 03h add 01h,#25h ? register 01h = 46h in the first example, destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in register r1.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 16 and ? logical and and dst,src operation: dst ? dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, r egister 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 17 band ? bit and band dst,src.b band dst.b,src operation: dst(0) ? dst(0) and src(b) or dst(b) ? dst(b) and src(0) the specified bit of the source (or the destination) is logically anded with the zero bit (lsb) of the destination (or source). the resultant bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 67 r0 rb opc src | b | 1 dst 3 6 67 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h and register 01h = 05h: band r1,01h.1 ? r1 = 06h, register 01h = 05h band 01h.1,r 1 ? register 01h = 05h, r1 = 07h in the first example, source register 01h contains the value 05h (00000101b) and destination working register r1 contains 07h (00000111b). the statement "band r1,01h.1" ands the bit 1 value of the source register ("0") with the bit 0 value of register r1 (destination), leaving the value 06h (00000110b) in register r1.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 18 bcp ? bit compare bcp dst,src.b operation: dst(0) ? src(b) the specified bit of the source is compared to (subtracted from) bit zero (l sb) of the destination. the zero flag is set if the bits are the same; otherwise it is cleared. the contents of both operands are unaffected by the comparison. flags: c: unaffected. z: set if the two bits are the same; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 17 r0 rb note : in the second byte of the instruction format, the destination address is four bits, the bit addre ss 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h and register 01h = 01h: bcp r1,01h.1 ? r1 = 07h, register 01h = 01h if destination working register r1 contains the value 07h (00000111b) and the source register 01h contains the value 01h (00000001b), the statement "bcp r1,01h.1" compares bit one of the source register (01h) and bit zero of the destination register (r1). because the bit values are not identical, the zero flag bit (z) is cleared in the flags register (0d5h).
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 19 bitc ? bit complement bitc dst.b operation: dst(b) ? not dst(b) this instruction complements the specified bit within the destination without affecting any other bits in the destination. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 57 rb note : in the second byte of the instruction format, the dest ination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h bitc r1.1 ? r1 = 05h if working register r1 contains the value 07h (00000111b), the statement "bitc r1.1" complements bit one of the destination and leaves the value 05h (00000101b) in register r1. because the result of the complement is not "0", the zero flag (z) in the flags register (0d5h) is cleared.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 20 bitr ? bit reset bitr dst.b operation: dst( b) ? 0 the bitr instruction clears the specified bit within the destination without affecting any other bits in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bitr r1.1 ? r1 = 05h if the value of working register r1 is 07h (00000111b), the statement "bitr r1.1" clears bit one of the destination register r1, leaving the value 05h (00000101b).
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 21 bits ? bit set bits dst.b operation: dst(b) ? 1 the bits instruction sets the specified bit within the destination without affecting any other bits in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 1 2 4 77 rb note : in the second byte of the instruction format, the destination address is fo ur bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bits r1.3 ? r1 = 0fh if working register r1 contains the value 07h (00000111b), the statement "bits r1.3" sets bit three of the destination register r1 to "1", leaving the value 0fh (00001111b).
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 22 bor ? bit or bor dst,src.b bor dst.b,src operation: dst(0) ? dst(0) or src(b) or dst(b) ? dst(b) or src(0) the specified bit of the source (or the destination) is logically ored with bit zero (lsb) of the destination (or the source). the resulting bit value is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 07 r0 rb opc src | b | 1 dst 3 6 07 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit. examples: given: r1 = 07h and register 01h = 03h: bor r1, 01h.1 ? r1 = 07h, register 01h = 03h bor 01h.2, r1 ? register 01h = 07h, r1 = 07h in the first example, destination working register r1 contains the value 07h (00000111b) and source register 01h the value 03h (00000011b). the statement "bor r1,01h.1" logically ors bit one of register 01h (source) with bit zero of r1 (destination). this leaves the same value (07h) in working register r1. in the second example, destination register 01h contains the value 03h (00000011b) and the source working register r1 the value 07h (00000111b). the statement "bor 01h.2,r1" logically ors bit two of register 01h (destination) with bit zero of r1 (source). this leaves the value 07h in register 01h.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 23 btjrf ? bit test, jump relative on false btjrf dst,src.b operation: if src(b) is a "0", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrf instruction is executed. flags: no flags are affected. format: (note 1) bytes cycles opcode (hex) addr mode dst src opc src | b | 0 dst 3 10 37 ra rb note: in the second byte of the instruction format, the sourc e address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrf skip,r1.3 ? pc jumps to skip location if working register r1 contains the value 07h (00000111b), the statement "btjrf skip,r1.3" tests bit 3. because it is "0", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 24 btjrt ? bit test, jump relative on true btjrt dst,src.b operation: if src(b) is a "1", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrt instruction is executed. flags: no flags are affected. format: (note 1) bytes cycles opcode (hex) addr mode dst src opc src | b | 1 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrt skip,r1.1 if working register r1 contains the value 07h (00000111b), the statement "btjrt skip,r1.1" tests bit one in the source register (r1). because it is a "1", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 25 bxor ? bit xor bxor dst,src.b bxor dst.b,src operation: dst(0) ? dst(0) xor src(b) or dst(b) ? dst(b) xor src(0) the specified bit of the source (or the destination) is logically exclusive-ored with bit zero (lsb) of the destination (or source). the result bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 27 r0 rb opc src | b | 1 dst 3 6 27 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h (00000111b) and register 0 1h = 03h (00000011b): bxor r1,01h.1 ? r1 = 06h, register 01h = 03h bxor 01h.2,r1 ? register 01h = 07h, r1 = 07h in the first example, destination working register r1 has the value 07h (00000111b) and source register 01h has the value 03h (00000011b). the statement "bxor r1,01h.1" exclusive-ors bit one of register 01h (source) with bit zero of r1 (destination). the result bit value is stored in bit zero of r1, changing its value from 07h to 06h. the value of source register 01h is unaffected.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 26 call ? call procedure call dst operation: sp ? sp ? 1 @sp ? pcl sp ? sp ?1 @sp ? pch pc ? dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr opc dst 2 14 d4 ia examples: given: r0 = 35h, r1 = 21h, pc = 1a47h, and sp = 0002h: call 3521h ? sp = 0000h (memory locations 0000h = 1ah, 0001h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0000h (00 00h = 1ah, 0001h = 49h) call #40h ? sp = 0000h (0000h = 1ah, 0001h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0002h, the statement "call 3521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 0000h. the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 0001h (because the two-byte instruction format was used). the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040h contains 35h and program address 0041h contains 21h, the statement "call #40h" produces the same result as in the second example.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 27 ccf ? complement carry flag ccf operation: c ? not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction c omplements it in the flags register (0d5h), changing its value from logic zero to logic one.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 28 clr ? clear clr dst operation: dst ? "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r ) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 29 com ? complement com dst operation: dst ? not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the resu lt bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 30 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c and s flags destination working register r1 contains the value 02h and source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in working register r3.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 31 cpije ? compare, increment, and jump on equal cpije dst,src,ra operation: if dst ? src = "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise, the instruction immediately following the cpije instruction is executed. in either case, the source pointer is incremented by one before the next instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 c2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 02h: cpije r1,@r2,skip ? r2 = 04h, pc jumps to skip location in this example, working register r1 contains the value 02h, working register r2 the value 03h, and register 03 contains 02h. the statement "cpije r1,@r2,skip" compares the @r2 value 02h (00000010b) to 02h (00000010b). because the result of the comparison is equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source register (r2) is incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 32 cpijne ? compare, increment, and jump on non-equal cpijne dst,src,ra operation: if dst ? src "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the cpijne instruction is executed. in either case the source pointer is incremented by one before the next instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 d2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 04h: cpijne r1,@r2,skip ? r2 = 04h, pc jumps to skip location working register r 1 contains the value 02h, working register r2 (the source pointer) the value 03h, and general register 03 the value 04h. the statement "cpijne r1,@r2,skip" subtracts 04h (00000100b) from 02h (00000010b). because the result of the comparison is non-equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source pointer register (r2) is also incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 33 da ? decimal adjust da dst operation: dst ? da dst the destination operand is adjusted to form two 4-bit bcd digits following an addition or subtraction operation. for addition (add, adc) or subtraction (sub, sbc), the following table indicates the operation performed. (the operation is undefined if the destination operand was not the result of a valid addition or subtraction of bcd digits): instruction carry before da bits 4?7 value (hex) h flag before da bits 0?3 value (hex) number added to byte carry after da 0 0?9 0 0?9 00 0 0 0?8 0 a?f 06 0 0 0?9 1 0?3 06 0 add 0 a?f 0 0?9 60 1 adc 0 9?f 0 a?f 66 1 0 a?f 1 0?3 66 1 1 0?2 0 0?9 60 1 1 0?2 0 a?f 66 1 1 0?3 1 0?3 66 1 0 0?9 0 0?9 00 = ? 00 0 sub 0 0?8 1 6?f fa = ? 06 0 sbc 1 7?f 0 0?9 a0 = ? 60 1 1 6?f 1 6?f 9a = ? 66 1 flags: c: set if there was a carry from the most significant bit; cleared otherwise (see table). z: set if result is "0"; cleared otherwise. s: set if result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 40 r 4 41 ir
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 34 da ? decimal adjust da (continued) example: given: working register r0 contains the value 15 (bcd), working register r1 contains 27 (bcd), and address 27h contains 46 (bcd): add r1,r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = c, r1 ? 3ch da r1 ; r1 ? 3ch + 06 if addition is performed using the bcd values 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 = 3ch the da instruction adjusts this result so that the correct bcd representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 assuming the same values given above, the statements sub 27h,r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = 1 da @r1 ; @r1 ? 31?0 leave the value 31 (bcd) in address 27h (@r1).
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 35 dec ? decrement dec dst operation: dst ? dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 36 decw ? decrement word decw dst operation: dst ? dst ? 1 the contents of the destination location (whic h must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 80 rr 8 81 ir examples: given: r0 = 12h, r1 = 34h, r2 = 30h, register 30h = 0fh, and register 31h = 21h: decw rr0 ? r0 = 12h, r1 = 33h decw @r2 ? register 30h = 0fh, register 31h = 20h in the first example, destination register r0 contains the value 12h and register r1 the value 34h. the statement "decw rr0" addresses r0 and the following operand r1 as a 16-bit word and decrements the value of r1 by one, leaving the value 33h. note: a system malfunction may occur if you use a zero flag (flags.6) result together with a decw instruction. to avoid this problem, we recommend that you use decw as shown in the following example: loop: decw rr0 ld r2,r1 or r2,r0 jr nz,loop
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 37 di ? disable interrupts di operation: sym (0) ? 0 bit zero of the system mode control register, sym.0, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 01h: di if the value of the sym register is 01h, the statement "di" leaves the new value 00h in the register and clears sym.0 to "0", disabling interrupt processing. before changing imr, interrupt pending and interrupt source control register, be sure di state.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 38 div ? divide (unsigned) div dst,src operation: dst src dst (upper) ? remainder dst (lower) ? quotient the destination operand (16 bits) i s divided by the source operand (8 bits). the quotient (8 bits) is stored in the lower half of the destination. the remainder (8 bits) is stored in the upper half of the destination. when the quotient is 3 2 8 , the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. both operands are treated as unsigned integers. flags: c: set if the v flag is set and quotient is between 2 8 and 2 9 ?1; cleared otherwise. z: set if divisor or quotient = "0"; cleared othe rwise. s: set if msb of quotient = "1"; cleared otherwise. v: set if quotient is 3 2 8 or if divisor = "0"; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 26/10 94 rr r 26/10 95 rr ir 26/10 96 rr im note: execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles. examples: given: r0 = 10h, r1 = 03h, r2 = 40h, register 40h = 80h: div rr0,r2 ? r0 = 03h , r1 = 40h div rr0,@r2 ? r0 = 03h, r1 = 20h div rr0,#20h ? r0 = 03h, r1 = 80h in the first example, destination working register pair rr0 contains the values 10h (r0) and 03h (r1), and register r2 contains the value 40h. the statement "div rr0,r2" divides the 16-bit rr0 value by the 8-bit value of the r2 (source) register. after the div instruction, r0 contains the value 03h and r1 contains 40h. the 8-bit remainder is stored in the upper half of the destination register rr0 (r0) and the quotient in the lower half (r1).
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 39 djnz ? decrement and jump if non-zero djnz r,dst operation: r ? r ? 1 if r 1 0, pc ? pc + dst the working register being used as a counter is decremented. if the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the pc. the range of the relative address is +127 to ?128, and the original value of the pc is taken to be the address of the instruction byte following the djnz statement. note: in case of using djnz instruction, the working register being used as a counter should be set at the one of location 0c0h to 0cfh with srp, srp0, or srp1 instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst r | opc dst 2 8 (jump taken) ra ra 8 (no jump) r = 0 to f example: given: r1 = 02h and loop is the label of a relative address: srp #0c0h djnz r1,loop djnz is typically used to control a "loop" of instructions. in many cases, a label is used as the destination operand instead of a numeric relative address value. in the example, working register r1 contains the value 02h, and loop is the label for a relative address. the statement "djnz r1, loop" decrements register r1 by one, leaving the value 01h. because the contents of r1 after the decrement are non-zero, the jump is taken to the relative address specified by the loop label.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 40 ei ? enable interrupts ei operation: sym (0) ? 1 an ei instruction sets bit zero of the system mode register, sym.0 to "1". this allows interrupts to be serviced as they occur (assuming they have highest priority). if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 01h, enabling all interrupts. (sym.0 is the enable bit for global interrupt processing.)
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 41 enter ? enter enter operation: sp ? sp ? 2 @sp ? ip ip ? pc pc ? @ip ip ? ip + 2 this instruction is useful when implementing threaded-code languages. the contents of the instruction pointer are pushed to the stack. the program counter (pc) value is then written to the instruction pointer. the program memory word that is pointed to by the instruction pointer is loaded into the pc, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 1f example: the diagram below shows one example of how to use an enter statement. 0050 ip 0022 sp 22 data address data 0040 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 0043 ip 0020 sp 20 21 22 iph ipl data address data 0110 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 00 50 stack stack 110 routine before after
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 42 exit ? exit exit operation: ip ? @sp sp ? sp + 2 pc ? @ip ip ? ip + 2 this instruction is useful when imple menting threaded-code languages. the stack value is popped and loaded into the instruction pointer. the program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 (internal stack) 2f 16 (internal stack) example: the diagram below shows one example of how to use an exit statement. 0050 ip 0022 sp address data 0040 pc address data memory 0052 ip 0022 sp address data 0060 pc address data memory stack stack before after 22 data 20 21 22 iph ipl data 00 50 50 51 140 pcl old pch exit 60 00 2f 60 main
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 43 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle stops the cpu clock but not the system clock.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 44 inc ? increment inc dst operation: dst ? dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: in c r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of register 1bh from 0fh to 10h.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 45 incw ? increment word incw dst operation: dst ? dst + 1 the contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 a0 rr 8 a1 ir examples: given: r0 = 1ah, r1 = 02h, register 02h = 0fh, and register 03h = 0ffh: incw rr0 ? r0 = 1ah, r1 = 03h incw @r1 ? register 02h = 10h, register 03h = 00h in the first example, the working register pair rr0 contains the value 1ah in register r0 and 02h in register r1. the statement "incw rr0" increments the 16-bit destination by one, leaving the value 03h in register r1. in the second example, the statement "incw @r1" uses indirect register (ir) addressing mode to increment the contents of general register 03h from 0ffh to 00h and register 02h from 0fh to 10h. note: a system malfunction may occur if you use a zero (z) flag (flags.6) result together with an incw instruction. to avoid this problem, we recommend that you use incw as shown in the following example: loop: incw rr0 ld r2,r1 or r2,r0 jr nz,loop
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 46 iret ? interrupt return iret iret (normal) iret (fast) operation: flags ? @sp pc ? ip sp ? sp + 1 flags ? flags' pc ? @sp fis ? 0 sp ? sp + 2 sym(0) ? 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. a "normal iret" is executed only if the fast interrupt status bit (fis, bit one of the flags register, 0d5h) is cleared (= "0"). if a fast interrupt occurred, iret clears the fis bit that was set at the beginning of the service routine. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 10 (internal stack) bf 12 (internal stack) iret (fast) bytes cycles opcode (hex) opc 1 6 bf example: in the figure below, the instruction pointer is initially loaded with 100h in the main program before interrupts are enabled. when an interrupt occurs, the program counter and instruction pointer are swapped. this causes the pc to jump to address 100h and the ip to keep the return address. the last instruction in the service routine normally is a jump to iret at address ffh. this causes the instruction pointer to be loaded with 100h "again" and the program counter to jump back to the main program. now, the next interrupt can occur and the ip is still correct at 100h. iret interrupt service routine jp to ffh 0h ffh 100h ffffh note: in the fast interrupt example above, if the last instruction is not a jump to iret, you must pay attention to the order of the last two instructions. the iret cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the ipr register).
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 47 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc ? dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 ccd da cc = 0 to f opc dst 2 8 30 irr notes : 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 48 jr ? jump relative jr cc,dst operation: if cc is true, pc ? pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed. (see list of condition codes). the range of the relative address is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code is true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 49 ld ? load ld dst,src operation: dst ? src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 50 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? register 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 51 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: dst(0) ? src(b) or dst(b) ? src(0) the specified bit of the source is loaded into bit zero (lsb) of the destination, or bit zero of the source is loaded into the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 47 r0 rb opc src | b | 1 dst 3 6 47 rb r0 note : in the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r0 = 06h and general register 00h = 05h: ldb r0,00h.2 ? r0 = 07h, register 00h = 05h ldb 00h.0,r0 ? r0 = 06h, register 00h = 04h in the first example, destination working register r0 contains the value 06h and the source general register 00h the value 05h. the statement "ld r0,00h.2" loads the bit two value of the 00h register into bit zero of the r0 register, leaving the value 07h in register r0. in the second example, 00h is the destination register. the statement "ld 00h.0,r0" loads bit zero of register r0 to the specified bit (bit zero) of the destination register, leaving 04h in general register 00h.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 52 ldc/lde ? load memory ldc/lde dst,src operation: dst ? src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes 'irr' or 'rr' values an even number for program memory and odd an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [rr] 4. opc src | dst xs 3 12 f7 xs [rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [rr] 6. opc src | dst xl l xl h 4 14 b7 xl [rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes : 1. the source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0?1. 2. for formats 3 and 4, the destination address 'xs [rr]' and the source address 'xs [rr]' are each one byte. 3. for formats 5 and 6, the destination address 'xl [rr] and the source address 'xl [rr]' are each two bytes. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in for mats 9 and 10, are used to address data memory.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 53 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h; program memory locations 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 ? contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 ? contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc (note) @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0,#01h[rr2] ; r0 ? contents of program memory location 0105h ; (01h + rr2), ; r0 = 6dh, r2 = 01h, r3 = 04h lde r0,#01h[rr2] ; r0 ? contents of external data memory location 0105h ; (01h + rr2), r0 = 7dh, r2 = 01h, r3 = 04h ldc (note) #01h[rr2],r0 ; 11h (contents of r0) is loaded into program memory location ; 0105h (01h + 0104h) lde #01h[rr2],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0105h (01h + 0104h) ldc r0,#1000h[rr2] ; r0 ? contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 ? contents of external data memory location 1104h ; (1000h + 0 104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 ? contents of program memory location 1104h, r0 = 88h lde r0,1104h ; r0 ? contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h, (1105h) ? 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) ? 11h note: these instructions are not supported by masked rom type devices.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 54 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst ? src rr ? rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. the assembler makes 'irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by on e ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 ? rr6 ? 1) lded r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is decremented by one (rr6 ? rr6 ? 1) ; r8 = 0ddh, r6 = 10h, r7 = 32h
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 55 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst ? src rr ? rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes 'irr' even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0ddh, r6 = 10h, r7 = 34h
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 56 ldcpd/ldepd ? load memory with pre-decrement ldcpd/ ldepd dst,src operation: rr ? rr ? 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first decremented. the contents of the source location are then loaded into the destination location. the contents of the source are unaffected. ldcpd refers to program memory and lde pd refers to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for external data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f2 irr r examples: given: r0 = 77h, r6 = 30h, and r7 = 00h: ldcpd @rr6,r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into program memory location ; 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh ldepd @rr6,r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into external data memory ; location 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 57 ldcpi/ldepi ? load memory with pre-increment ldcpi/ ldepi dst,src operation: rr ? rr + 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first incremented. the contents of the source location are loaded into the destination location. the contents of the source are unaffected. ldcpi refers to program memory and ldepi refers to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f3 irr r examples: given: r0 = 7fh, r6 = 21h, and r7 = 0ffh: ldcpi @rr6,r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) i s loaded into program memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h ldepi @rr6,r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into external data memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 58 ldw ? load word ldw dst,src operation: dst ? src the contents of the source (a word) are loaded into the destination. the contents of the source are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 c4 rr rr 8 c5 rr ir opc dst src 4 8 c6 rr iml examples: given: r4 = 06h, r5 = 1ch, r6 = 05h, r7 = 02h, register 00h = 1ah, register 01h = 02h, register 02h = 03h, and register 03h = 0fh: ldw rr6,rr4 ? r6 = 06h, r7 = 1ch, r4 = 06h, r5 = 1ch ldw 00h,02h ? register 00h = 03h, register 01h = 0fh, register 02h = 03h, register 03h = 0fh ldw rr2,@r7 ? r2 = 03h, r3 = 0fh, ldw 04h,@01h ? register 04h = 03h, register 05h = 0fh ldw rr6,#1234h ? r6 = 12h, r7 = 34h ldw 02h,#0fedh ? register 02h = 0fh, register 03h = 0edh in the second example, please note that the statement "ldw 00h,02h" loads the contents of the source word 02h, 03h into the destination word 00h, 01h. this leaves the value 03h in general register 00h and the value 0fh in register 01h. the other examples show how to use the ldw instruction with various addressing modes and formats.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 59 mult ? multiply (unsigned) mult dst,src operation: dst ? dst src the 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. both operands are treated as unsigned integers. flags: c: set if result is > 255; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if msb of the result is a "1"; cleared otherwise. v: cleared. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 22 84 rr r 22 85 rr ir 22 86 rr im examples: given: register 00h = 20h, register 01h = 03h, register 02h = 09h, register 03h = 06h: mult 00h, 02h ? register 00h = 01h, register 01h = 20h, register 02h = 09h mult 00h, @01h ? register 00h = 00h, register 01h = 0c0h mult 00h, #30h ? register 00h = 06h, register 01h = 00h in the first example, the statement "mult 00h,02h" multiplies the 8-bit desti nation operand (in the register 00h of the register pair 00h, 01h) by the source register 02h operand (09h). the 16 -bit product, 0120h, is stored in the register pair 00h, 01h.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 60 next ? next next operation: pc ? @ ip ip ? ip + 2 the next instruction is useful when implementing threaded-code languages. the program memory word that is pointed to by the instruction pointer is loaded into the program counter. the instruction pointer is then incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 10 0f example: the following diagram shows one example of how to use the next instruction. data 01 10 before after 0045 ip address data 0130 pc 43 44 45 address h address l address h address data memory 130 routine 0043 ip address data 0120 pc 43 44 45 address h address l address h address data memory 120 next
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 61 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 62 or ? logical or or dst,src operation: dst ? dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r 1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and register r1 the value 2ah, the statement "or r0,r1" logical-ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or i nstruction with the various addressing modes and formats.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 63 pop ? pop from stack pop dst operation: dst ? @sp sp ? sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sph (0d8h) = 00h, spl (0d9h) = 0fbh, and stack register 0fbh = 55h: pop 00h ? register 00h = 55h, sp = 00fch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 00fch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 00fbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 00fch.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 64 popud ? pop user stack (decrementing) popud dst,src operation: dst ? src ir ? ir ? 1 this instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then decremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 92 r ir example: given: register 00h = 42h (user stack pointer register), register 42h = 6fh, and register 02h = 70h: popud 02h,@00h ? register 00h = 41h, register 02h = 6fh, register 42h = 6fh if general register 00h contains the value 42h and register 42h the value 6fh, the statement "popud 02h,@00h" loads the contents of register 42h into the destination register 02h. the user stack pointer is then decremented by one, leaving the value 41h.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 65 popui ? pop user stack (incrementing) popui dst,src operation: dst ? src ir ? ir + 1 the popui instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then incremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 93 r ir example: given: register 00h = 01h and register 01h = 70h: popui 02h,@00h ? register 00h = 02h, register 01h = 70h, register 02h = 70h if general register 00h contains the value 01h and register 01h the value 70h, the sta tement "popui 02h,@00h" loads the value 70h into the destination general register 02h. the user stack pointer (register 00h) is then incremented by one, changing its value from 01h to 02h.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 66 push ? push to stack push src operation: sp ? sp ? 1 @sp ? src a push instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 (internal clock) 70 r 8 (external clock) 8 (internal clock) 8 (external clock) 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sph = 00h, and spl = 00h: push 40h ? register 40h = 4fh, stack register 0ffh = 4fh, sph = 0ffh, spl = 0ffh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0ffh = 0aah, sph = 0ffh, spl = 0ffh in the first example, if the stack pointer contains the value 0000h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0000 to 0ffffh. it then loads the contents of register 40h into location 0ffffh and adds this new value to the top of the stack.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 67 pushud ? push user stack (decrementing) pushud dst,src operation: ir ? ir ? 1 dst ? src this instruction is used to address user-defined stacks in the register file. pushud decreme nts the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 82 ir r example: given: register 00h = 03h, register 01h = 05h, and register 02h = 1ah: pushud @00h,01h ? register 00h = 02h, register 01h = 05h, register 02h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushud @00h,01h" decrements the user stack pointer by one, leaving the value 02h. the 01h register value, 05h, is then loaded into the register addressed by the decremented user stack pointer.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 68 pushui ? push user stack (incrementing) pushui dst,src operation: ir ? ir + 1 dst ? src this instruction is used for user-defined stacks in the register file. pushui increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 83 ir r example: given: register 00h = 03h, register 01h = 05h, and register 04h = 2ah: pushui @00h,01h ? register 00h = 04h, register 01h = 05h, register 04h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushui @00h,01h" increments the user stack pointer by one, leaving the value 04h. the 01h register value, 05h, is then loaded into the location addressed by the incremented user stack pointer.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 69 rcf ? reset carry flag rcf rcf operation: c ? 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 70 ret ? return ret operation: pc ? @sp sp ? sp + 2 the ret instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 (internal stack) af 10 (internal stack) example: given: sp = 00f ch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 00feh the statement "ret" pops the contents of stack pointer location 00fch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 00feh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 00feh.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 71 rl ? rotate left rl dst operation: c ? dst (7) dst (0) ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the co ntents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 72 rlc ? rotate left through carry rlc dst operation: dst (0) ? c c ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 73 rr ? rotate right rr dst operation: c ? dst (0) dst (7) ? dst (0) dst (n ) ? dst (n + 1), n = 0?6 the contents of the destinat ion operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leavi ng the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 74 rrc ? rotate right through carry rrc dst operation: dst (7) ? c c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 0 0h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 75 sb0 ? select bank 0 sb0 operation: bank ? 0 the sb0 instruction clears the bank address flag in the flags register (flags.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 4f example: the statement sb0 clears flags.0 to "0", selecting bank 0 register addressing.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 76 sb1 ? select bank 1 sb1 operation: bank ? 1 the sb1 instruction sets the bank address flag in the flags register (flags.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (bank 1 is not implemented in some s3c8-series microcontrollers.) flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 5f example: the statement sb1 sets flags.0 to "1", selecting bank 1 register addressing, if implemented.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 77 sbc ? subtract with carry sbc dst,src operation: dst ? dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 78 scf ? set carry flag scf operation: c ? 1 the carry flag (c) is set to logic one, regardless o f its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 79 sra ? shift right arithmetic sra dst operation: dst (7) ? dst (7) c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 0 c 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? registe r 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 80 srp/srp0/srp1 ? set register pointer srp src srp0 src srp1 src operation: if src (1) = 1 and src (0) = 0 then: rp0 (3?7) ? src (3?7) if src (1) = 0 and src (0) = 1 then: rp1 (3?7) ? src (3?7) if src (1) = 0 and src (0) = 0 then: rp0 (4?7) ? src (4?7), rp0 (3) ? 0 rp1 (4?7) ? src (4?7), rp1 (3) ? 1 the source data bits one and zero (lsb) determine whether to write one or both of the register pointers, rp0 and rp1. bits 3?7 of the selected register pointer are written unless both register pointers are selected. rp0.3 is then cleared to logic zero and rp1.3 is set to logic one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode src opc src 2 4 31 im examples: the statement srp #40h sets register pointer 0 (rp0) at location 0d6h to 40h and register pointer 1 (rp1) at location 0d7h to 48h. the statement "srp0 #50h" sets rp0 to 50h, and the statement "srp1 #68h" sets rp1 to 68h.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 81 stop ? stop operation stop operation: the stop instruction stops the both the cpu clock and syste m clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or by external interrupts. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop halts all microcontroller operations.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 82 sub ? subtract sub dst,src operation: dst ? dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared other wise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = " 1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 83 swap ? swap nibbles swap dst operation: dst (0 ? 3) ? dst (4 ? 7) the contents of the lower four bits and upper four bits of the destination operand are swapped. 7 0 4 3 flags: c: undefined. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 f0 r 4 f1 ir examples: given: register 00h = 3eh, register 02h = 03h, and register 03h = 0a4h: swap 00h ? register 00h = 0e3h swap @02h ? register 02h = 03h, register 03h = 4ah in the first example, if general register 00h contains the value 3eh (00111110b), the state ment "swap 00h" swaps the lower and upper four bits (nibbles) in the 00h register, leaving the value 0e3h (11100011b).
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 84 tcm ? test complement under mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 85 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 0 0h,#54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 86 wfi ? wait for interrupt wfi operation: the cpu is effectively halted until an interrupt oc curs, except that dma transfers can still take place during this wait state. the wfi status can be released by an internal interrupt, including a fast interrupt . flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4n 3f ( n = 1, 2, 3, ? ) example: the following sample program structure shows the sequence of operations that follow a "wfi" statement: ei wfi (next instruction) main program . . . . . . interrupt occurs interrupt service routine . . . clear interrupt flag iret service routine completed (enable global interrupt) (wait for interrupt)
s3c8248/c8245/p8245/c8247/c8249/p8249 i nstruction set 6- 87 xor ? logical exclusive or xor dst,src operation: dst ? dst xor src the so urce operand is logically exclusive-ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 02h xor 00h,@01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive-ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
instruction set s3c8248/ c8245/p8245/c8247/c8249/p8249 6- 88 notes
s3c8248/c8245/p8245/c8247/c8249/p8249 clock circuit 7- 1 7 clock circuit overview the clock frequency generated for the s3c8248/c8245/c8247/c8249 by an external crystal can range from 1 mhz to 10 mhz. the maximum cpu clock frequency is 10 mhz. the x in and x out pins connect the external oscillator or clock source to the on-chip clock circuit. system clock circuit the system clock circuit has the following components: ? external crystal or ceramic resonator oscillation source (or an external clock source) ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock ( f xx divided by 1, 2, 8, or 16) ? system clock control register, clkcon ? oscillator control register, osccon and stop control register, stpcon x in x out c1 c2 s3c8248/c8245 /c8247/c8249 figure 7-1. main oscillator circuit (crystal or ceramic oscillator) x in x out s3c8248/c8245 /c8247/c8249 figure 7-2. main oscillator circuit (rc oscillator)
clock circuit s3c8248/c8245/p8245 /c8247/c8249/p8249 7- 2 c lock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with rc delay noise filter) , and can be release d by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock. ? in idle mode, the internal clock signal is gated to the cpu, but not to interrupt structure, timers and timer/ counters. idle mode is released by a reset or by an external or internal interrupt. 1/8-1/4096 frequency dividing circuit stop release main-system oscillator circuit selector 1 f x f x t stop driving ability sub-system oscillator circuit osccon.4 int osccon.0 osccon.3 osccon.2 selector 2 stpcon stop osc inst. f xx clkcon.4-.3 cpu clock stop watch timer basic timer timer/counter watch timer (fxx/128) lcd controller a/d converter sio system clock idle instruction 1/1 1/16 1/2 1/8 figure 7- 3 . system clock circuit diagram
s3c8248/c8245/p8245/c8247/c8249/p8249 clock circuit 7- 3 system clock control register (clkcon ) the system clock control register, clkcon , is located in the bank 0 of set 1, address d4h. it is read/write addressable and has the following functions: ? oscillator frequency divide-by value after the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed fxx/8, fxx/2, or fxx/1. system clock control register (clkcon) d4h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used (must keep always 0) not used (must keep always 0) divide-by selection bits for cpu clock frequency: 00 = f xx /16 01 = f xx /8 10 = f xx /2 11 = f xx /1 (non-divided) note: the fxx can be generated by both main-system and sub-system oscillator therefore while main-system stops peripherals can be operated by sub-system. figure 7- 4 . system clock control register (clkcon )
clock circuit s3c8248/c8245/p8245 /c8247/c8249/p8249 7- 4 oscillator control register (osccon) f3h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used system clock selection bit: 0 = main oscillator select 1 = subsystem oscillator select not used subsystem oscillator control bit: 0 = subsystem oscillator run 1 = subsystem oscillator stop mainsystem oscillator control bit: 0 = mainsystem oscillator run 1 = mainsystem oscillator stop subsystem oscillator driving ability control bit: 0 = strong driving ability 1 = normal driving ability note: in strong mode the warm-up time is less than 100 ms. when the cpu is operated with fxt (sub-oscillation clock), it is possible to use the stop instruction but in this case before using stop instruction, you must select fxx /128 for basic timer counter clock input. then the oscillation stabilization time is 62.5 ((1/32768) x 128 x 16) ms + 100 ms here the warm-up time is from the time that the stop release signal activates to the time that basic timer starts counting. figure 7-5. oscillator control register (osccon) stop control register (stpcon) f4h, set 1,bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb stop control bits: other values = disable stop instruction 10100101 = enable stop instruction figure 7-6. stop control register (stpcon)
s3c8248/c8245/p8245/c8247/c8249/p8249 reset and power-down 8- 1 8 reset reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a s chmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings the s3c8248/c8245/c8247/c8249 into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required time of a reset operation for oscillation stabilization is 1 millisecond. whenever a reset occurs during normal operation (that is, when both v dd and reset are high level), the reset pin is forced low level and the reset operation starts. all system and peripheral control registers are then reset to their default hardware values in summary, the following sequence of events occurs during a reset operation: ? all interrupt is disabled. ? the watchdog function (basic timer) is enabled. ? ports 0 -3 and set to input mode . ? perip heral control and data register settings are disabled and reset to the ir default hardware values . ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programme d oscillation stabilization time interval has elapsed, the instruction stored in rom location 0100h (and 0101h) is fetched and executed. normal mode reset operation in normal (masked rom) mode, the test pin is tied to v ss . a reset enables access to the 16-kbyte on-chip rom. (the external interface is not automatically configured). note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing " 1010b " to the upper nibble of btcon.
reset and power-down s3c8248/c8245/p8245 /c8247/c8249/p8249 8- 2 hardware reset values table 8-1 , 8-2, 8-3 list the reset values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic z ero, respectively. ? an " x " means that the bit value is undefined after a reset. ? a dash ( " ? " ) means that the bit is either not used or not mapped , but read 0 is the bit value. table 8-1. s3c8245/p8245 set 1 register and values after reset reset register name mnemonic address bit values a fter r r eset eset dec hex 7 6 5 4 3 2 1 0 lcd control register lcon 208 d0h 0 0 0 0 0 0 0 0 lcd mode register lmod 209 d1h 0 0 0 0 0 0 0 0 interrupt pending register intpnd 210 d2h 0 0 0 0 0 0 0 0 basic timer control register btcon 211 d3h 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x x x 0 0 register pointer (high byte) rp0 214 d6h 1 1 0 0 0 ? ? ? register pointer (low byte) rp1 215 d7h 1 1 0 0 1 ? ? ? stack pointer (high byte) sph 216 d8h x x x x x x x x stack pointer (low byte) spl 217 d9h x x x x x x x x instruction pointer (high byte) iph 218 dah x x x x x x x x instruction pointer (low byte) ipl 219 dbh x x x x x x x x interrupt request register irq 220 dch 0 0 0 0 0 0 0 0 interrupt mask register imr 221 ddh x x x x x x x x system mode register sym 222 deh 0 ? ? x x x 0 0 register page pointer pp 223 dfh 0 0 0 0 0 0 0 0
s3c8248/c8245/p8245/c8247/c8249/p8249 reset and power-down 8- 3 table 8 - 2 . ks88c2416/p2416 set 1, bank 0 register values after reset reset register name mnemonic address bit values a fter r r eset eset dec hex 7 6 5 4 3 2 1 0 port 0 control high register p0conh 224 e0h 0 0 0 0 0 0 0 0 port 0 control low register p0conl 225 e1h 0 0 0 0 0 0 0 0 port 0 interrupt control register p0int 226 e2h 0 0 0 0 0 0 0 0 port 0 interrupt pending register p0pnd 227 e3h 0 0 0 0 0 0 0 0 port 1 control high register p 1conh 22 8 e 4 h 0 0 0 0 0 0 0 0 port 1 control low register p 1conl 22 9 e 5 h 0 0 0 0 0 0 0 0 port 2 control high register p2conh 23 0 e 6 h 0 0 0 0 0 0 0 0 port 2 control low register p2conl 23 1 e 7 h 0 0 0 0 0 0 0 0 port 3 control high register p3conh 232 e8h 0 0 0 0 0 0 0 0 port 3 control low register p3conl 233 e9h 0 0 0 0 0 0 0 0 timer b data register (high byte) tbdatah 2 34 ea h 1 1 1 1 1 1 1 1 timer b data register (low byte) tbdatal 2 35 eb h 1 1 1 1 1 1 1 1 timer b control register tbcon 236 ec h 0 0 0 0 0 0 0 0 timer a control register tacon 237 ed h 0 0 0 0 0 0 0 0 timer a counter register tacnt 238 ee h 0 0 0 0 0 0 0 0 timer a data register tadata 239 ef h 1 1 1 1 1 1 1 1 serial i/o control register siocon 240 f0h 0 0 0 0 0 0 0 0 serial i/o data register siodata 241 f1h 0 0 0 0 0 0 0 0 serial i/o pre-scale register siops 242 f2h 0 0 0 0 0 0 0 0 oscillator control register osccon 243 f3h 0 0 0 0 0 0 0 0 stop control register stpcon 244 f4h 0 0 0 0 0 0 0 0 port 1 pull-up control register p1pup 245 f5h 0 0 0 0 0 0 0 0 port 0 data register p0 246 f6h 0 0 0 0 0 0 0 0 port 1 data register p1 247 f7h 0 0 0 0 0 0 0 0 port 2 data register p2 248 f8h 0 0 0 0 0 0 0 0 port 3 data register p3 249 f9h ? ? ? 0 0 0 0 0 port 4 data register p4 250 fah 0 0 0 0 0 0 0 0 port 5 data register p5 251 fbh 0 0 0 0 0 0 0 0 location fch is factory use only. basic timer data register btcnt 253 fdh 0 0 0 0 0 0 0 0 external memory timing register emt 254 f e h 0 ? ? ? ? ? ? ? interrupt priority register ipr 255 ffh x x x x x x x x
reset and power-down s3c8248/c8245/p8245 /c8247/c8249/p8249 8- 4 table 8 - 3 . s3c8245/p8245 set 1, bank 1 register values after reset reset register name mnemonic address bit values a fter r r eset eset dec hex 7 6 5 4 3 2 1 0 port 4 control high register p4conh 236 ech 0 0 0 0 0 0 0 0 port 4 control low register p4conl 237 edh 0 0 0 0 0 0 0 0 port 5 control high register p5conh 238 eeh 0 0 0 0 0 0 0 0 port 5 control low register p5conl 239 efh 0 0 0 0 0 0 0 0 locations f0h is factory use only. timer 0 control register t0con 241 f1h 0 0 0 0 0 0 0 0 timer 0 counter register (high byte) t0cnth 242 f2h 0 0 0 0 0 0 0 0 timer 0 counter register (low byte) t0cntl 243 f3h 0 0 0 0 0 0 0 0 timer 0 data register (high byte) t0datah 244 f4h 1 1 1 1 1 1 1 1 timer 0 data register (low byte) t0datal 245 f5h 1 1 1 1 1 1 1 1 voltage level detector control register vldcon 246 f6h 0 0 0 0 0 0 0 0 ad converter control register adcon 247 f7h 0 0 0 0 0 0 0 0 ad converter data register (high byte) addatah 248 f8h x x x x x x x x ad converter data register (low byte) addatal 249 f9h x x x x x x x x watch timer control register wtcon 250 fah 0 0 0 0 0 0 0 0 timer 1 control register t1con 251 fbh 0 0 0 0 0 0 0 0 timer 1 counter register (high byte) t1cnth 252 fch 0 0 0 0 0 0 0 0 timer 1 counter register (low byte) t1cntl 253 fdh 0 0 0 0 0 0 0 0 timer 1 data register (high byte) t1datah 254 feh 1 1 1 1 1 1 1 1 timer 1 data register (low byte) t1datal 255 ffh 1 1 1 1 1 1 1 1
s3c8248/c8245/p8245/c8247/c8249/p8249 reset and power-down 8- 5 power-down modes stop mode stop mode is invoked by the instruction stop ( opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 3 m a. all system functions stop when the clock ?freezes?, but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset or by interrupts, for more details see figure 7-3. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. using reset to release stop mode stop mode is released when the reset signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. a reset operation automatically selects a slow clock fxx/16 because clkcon.3 and clkcon.4 are cleared to ?00b?. after the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h (and 0101h) using an external interrupt to release stop mode e xternal interrupts with an rc-delay noise filter circuit can be used to release stop mode. which interrupt you can use to release stop mode in a given situation depends on the microcontroller?s current internal operating mode. the external interrupts in the s3c8248/c8245/c8247/c8249 interrupt structure that can be used to release stop mode are: ? external interrupts p0.0?p0.7 (int0?int7) please note the following conditions for stop mode release: ? if you release s top mode using an external interrupt, the current values in system and peripheral control registers are unchanged except stpcon register. ? if you use an internal or external interrupt for s top mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering s top mode. ? when the stop mode is released by external interrupt, the clkcon.4 and clkcon.3 bit-pair setting remains unchanged and the currently selected clock value is used. ? the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. using an internal interrupt to release stop mode activate any enabled interrupt, causing stop mode to be released. other things are same as using external interrupt. how to enter into stop mode there are two ways to enter into stop mode: 1. handling osccon register. 2. handling stpcon register then writing stop instruction (keep the order).
reset and power-down s3c8248/c8245/p8245 /c8247/c8249/p8249 8- 6 idle mode idle mode is i nvoked by the instruction idle ( opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu, but all peripherals timers remain active. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode : 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatica lly selects the slow clock fxx/16 because clkcon.4 and clkcon.3 are cleared to ?00b?. if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt , causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.4 and clkcon.3 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt (iret) occurs, the instruction immediately following the one that initiated idle mode is executed.
s3c8248/c8245/p8245/c8247/c8249/p8249 i/o ports 9- 1 9 i/o ports overview the s3c8248/c8245/c8247/c8249 microcontroller has two nibble-programmable and four bit-programmable i/o ports , p0?p5. the port 3 is a 5-bit port and the others are 8-bit ports. this gives a total of 45 i/o pins . each port can be flexibly configured to meet a pplication design requirements. the cpu accesses ports by directly wri ting or reading port registers. no special i/o instructions are required. table 9-1 gives y ou a general overview of the s3c8248/c8245/c8247/c8249 i/o port functions. table 9-1. s3c8248/c8245/c8247/c8249 port configuration overview port configuration options 0 1-bit programmable i/o port . schmitt trigger input or output mode selected by software; software assignable pull-up. p0.0?p0.7 can be used as inputs for external interrupts int0?int7 (with noise filter and interrupt control). 1 1-bit programmable i/o port . input or output mode selected by software; open-drain output mode can be selected by software; software assignable pull-up. alternately p1.0?p1.7 can be used as si, so, sck, buz, t1cap, t1clk, t1out, t1pwm. 2 1-bit programmable i/o port . normal input and ad input or output mode selected by software; software assignable pull-up. 3 1-bit programmable i/o port . input or push-pull output with software assignable pull-up. alternately p3.0?p3.3 can be used as tacap, taclk, taout, tapwm, tbpwm. 4 1-bit programmable i/o port . push-pull or open drain output and input with software assignable pull-up. p4.0?p4.7 can alternately be used as outputs for lcd seg. 5 have the same characteristic as port 4
i/o ports s3c8248/c 8245/p8245/c8247/c8249/p8249 9- 2 port data registers table 9-2 gives you an overview of t he register locations of all four s3c8248/c8245/c8247/c8249 i/o port data registers. data registers for ports 0 , 1, 2, 3, 4, and 5 have the general format shown in figure 9-1 . table 9-2. port data register summary register name mnemonic decimal hex location r/w port 0 data register p0 246 f6h set 1 , bank 0 r/w port 1 data register p1 247 f7h set 1 , bank 0 r/w port 2 data register p2 248 f8h set 1 , bank 0 r/w port 3 data register p3 249 f9h set 1 , bank 0 r/w port 4 data register p 4 250 fah set 1 , bank 0 r/w port 5 data register p 5 251 fbh set 1 , bank 0 r/w
s3c8248/c8245/p8245/c8247/c8249/p8249 i/o ports 9- 3 port 0 port 0 is an 8-bit i/o port that you can use two ways: ? general-purpose i/o ? external interr upt inputs for int0?int7 port 0 is accessed directly by writing or reading the port 0 data register, p0 at location f6h in set 1, bank 0. port 0 control register (p0conh, p0conl) port 0 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0: p0conl (low byte, e1h) and p0conh (high byte, e0h). when you select output mode, a push-pull circuit is automatically configured. in input mode, three different selections are available: ? schmitt trigger input with interrupt generation on falling signal edges. ? schmitt trigger input with interrupt generation on rising signal edges. ? schmitt trigger input with interrupt generation on falling/rising signal edges. port 0 interrupt enable and pending registers (p0int, p0pnd) to process external interrupts at the port 0 pins, two additional control registers are provided: the port 0 interrupt enable register p0int (e2h, set 1, bank 0) and the port 0 interrupt pending register p0pnd (e3h, set 1, bank 0). the port 0 interrupt pending register p0pnd lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the p0pnd register at regular intervals. when the interrupt enable bit of any port 0 pin is ?1?, a rising or falling signal edge at that pin will generate an interrupt request. the corresponding p0pnd bit is then automatically set to ?1? and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a ?0? to the corresponding p0pnd bit.
i/o ports s3c8248/c 8245/p8245/c8247/c8249/p8249 9- 4 port 0 control register, high byte (p0conh) e0h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.7 (int7) p0.6 (int6) p0.5 (int5) p0.4 (int4) p0conh bit-pair pin configuration 00 01 10 11 schmitt trigger input mode, pull-up, interrupt on falling edge schmitt trigger input mode, interrupt on rising edge schmitt trigger input mode, interrupt on rising or falling edge output mode, push-pull figure 9-1. port 0 high-byte control register (p0conh) port 0 control register, low byte (p0conl) e1h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.3 (int3) p0.2 (int2) p0.1 (int1) p0.0 (int0) p0conl bit-pair pin configuration 00 01 10 11 schmitt trigger input mode, pull-up, interrupt on falling edge schmitt trigger input mode, interrupt on rising edge schmitt trigger input mode, interrupt on rising or falling edge output mode, push-pull figure 9-2. port 0 low-byte control register (p0conl)
s3c8248/c8245/p8245/c8247/c8249/p8249 i/o ports 9- 5 port 0 interrupt control register (p0int) e2h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0int bit configuration settings: 0 1 interrupt disable int7 int6 int5 int4 int3 int2 int1 int0 interrupt enable figure 9-3. port 0 interrupt control register (p0int) port 0 interrupt pending register (p0pnd) e3h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0pnd bit configuration settings: 0 1 pnd7 pnd6 pnd5 pnd4 pnd3 pnd2 pnd1 pnd0 interrupt request is not pending, pending bit clear when write 0 interrupt request is pending figure 9-4. port 0 interrupt pending register (p0pnd)
i/o ports s3c8248/c 8245/p8245/c8247/c8249/p8249 9- 6 port 1 port 1 is an 8-bit i/o port with individually configurable pins. port 1 pins are accessed directly by writing or reading the port 1 data register, p1 at location f7h in set 1, bank 0. p1.0?p1.7 can serve inputs, as outputs (push pull or open-drain) or you can configure the following alternative functions: ? low-byte pins (p1.0-p1.3): t1cap, t1clk, t1out, t1pwm ? high-byte pins (p1.4-p1.7): sck, si, so and buz port 1 control register port 1 has two 8-bit control registers: p1conh for p1.4?p1.7 and p1conl for p1.0?p1.3. a reset clears the p1conh and p1conl registers to ?00h?, configuring all pins to input mode. you use control registers settings to select input or output mode (push-pull or open drain) and enable the alternative functions. when programming the port, please remember that any alternative peripheral i/o function you configure using the port 1 control registers must also be enabled in the associated peripheral module. port 1 pull-up resistor enable register (p1pup) using the port 1 pull-up resistor enable register, p1pup (f5h, set 1, bank 0), you can configure pull-up resistors to individual port 1 pins. port 1 control register, high byte e4h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.7/si p1conh bit-pair pin configuration settings 00 01 10 11 alternative function (sck out, buz, so, p1.7 is push-pull output) output mode, push-pull p1.6/sck p1.5/so p1.4/buz output mode, open-drain note: when use this port 1, user must be care of the pull-up resistance status. input mode (si, sck in) figure 9- 5. port 1 high-byte control register (p1conh)
s3c8248/c8245/p8245/c8247/c8249/p8249 i/o ports 9- 7 port 1 control register, low byte e5h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.3 p1conl bit-pair pin configuration settings 00 01 10 11 alternative function (t1out, t1pwm, other pins are push-pull are push-pull output mode) output mode, push-pull p1.2/t1out /t1pwm p1.1/t1clk p1.0/t1cap output mode, open-drain note: when use this port 1, user must be care of the pull-up resistance status. input mode (t1cap, t1clk) figure 9-6. port 1 low-byte control register (p1conl) port 1 pull-up control register f5h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1pup bit configuration settings: 0 1 pull-up disable p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 pull-up enable figure 9-7. port 1 pull-up control register (p1pup)
i/o ports s3c8248/c 8245/p8245/c8247/c8249/p8249 9- 8 port 2 port 2 is an 8-bit i/o port that can be used for general-purpose i/o as a/d converter inputs, adc0?adc7. the pins are accessed directly by writing or reading the port 2 data register, p2 at location f8h in set 1, bank 0. to individually configure the port 2 pins p2.0?p2.7, you make bit-pair settings in two control registers located in set 1, bank 0: p2conl (low byte, e7h) and p2conh (high byte, e6h). in input mode, adc or external reference voltage input are also available. port 2 control register s two 8-bit control registers are used to configure port 2 pins: p2conl ( e7 h, set 1 , bank 0) for pins p2.0?p2.3 and p2conh ( e6 h, set 1 , bank 0) for pins p2.4?p2.7 . each byte contains four bit-pairs and each bit-pair configures one port 2 pin. the p2conh and the p2conl registers also control the alternative functions . port 2 control register, high byte (p2conh) e6h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2.7 (vldref/adc7) p2.6 (adc6) p2.5 (adc5) p2.4 (adc4) p2conh bit-pair pin configuration 00 01 10 11 note: if a pin is enabled for adc mode by adcen or adc & vld enable signal, normal i/o and pull-up resistance are disabled. when pins are enabled for adc mode, the pins can be selected for adc input by adcon.6. 5. 4. and the p2.7 can be used for vld external input. input mode input mode, pull-up alternative function (adc & vld external input enable, adcen signal gen.) output mode, push-pull figure 9 -8 . port 2 high-byte c ontrol register (p2conh)
s3c8248/c8245/p8245/c8247/c8249/p8249 i/o ports 9- 9 port 2 control register,low byte (p2conl) e7h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2.2 (adc2) p2.1 (adc1) p2.0 (adc0) p2conl bit-pair pin configuration 00 01 10 11 alternative function (adc mode) output mode, push-pull input mode, pull-up note: if a pin is enabled for adc mode by adcen, normal i/o and pull-up resistance are disabled. when pins are enabled for adc mode by adcen, the pins can be selected for adc input by adcon.6.5.4. p2.3 (adc3) input mode figure 9-9 . port 2 low-byte control register (p2con l )
i/o ports s3c8248/c 8245/p8245/c8247/c8249/p8249 9- 10 port 3 port 3 is an 5-bit i/o port with individually configurable pins. port 3 pins are accessed directly by writing or reading the port 3 data register, p3 at location f9h in set 1, bank 0. p3.0?p3.3 can serve as inputs (with or without pull-ups), as push-pull outputs, or you can configure the following alternative functions: ? tacap, taclk, taout, tapwm and tbpwm port 3 control registers port 3 has two 8-bit control registers: p3conh for p3.4 and p3conl for p3.0?p3.3. a reset clears the p3conh and p3conl registers to ?00h?, configuring all pins to input mode. you use control registers settings to select input or output mode, enable pull-up resistors, and enable the alternative functions. when programming this port, please remember that any alternative peripheral i/o function you configure using the port 3 control registers must also be enabled in the associated peripheral module. port 3 control high register (p3conh) e8h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3.4 not used p3conh bit-pair pin configuration settings 00 01 1x input mode, pull-up output mode, push-pull input mode figure 9-10 . port 3 control high register (p3conh)
s3c8248/c8245/p8245/c8247/c8249/p8249 i/o ports 9- 11 port 3 control low register (p3conl) e9h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3.2/taclk p3.1/taout/ tapwm p3.0/tbpwm p3conl bit-pair pin configuration settings 00 01 10 11 alternative function (taout,tapwm, tbpwm p3.2, p3.3 is push-pull output mode) output mode, push-pull input mode, pull-up (tacap) p3.3/tacap input mode (tacap, taclk) figure 9- 11 . port 3 control low register (p3conl)
i/o ports s3c8248/c 8245/p8245/c8247/c8249/p8249 9- 12 port 4 port 4 is an 8-bit i/o port with individually configurable pins. port 4 pins are accessed directly by writing or reading the port 4 data register, p4 at location fah in set 1, bank 0. p4.0?p4.7 can serve as inputs (with or without pull-ups), as output (open drain or push-pull). and, they can serve as segment pins for lcd, also. port 4 control registers port 4 has two 8-bit control registers: p4conh for p4.4?p4.7 and p4conl for p4.0?p4.3. a reset clears the p4conh and p4conl registers to ?00h?, configuring all pins to input mode. output mode, push-pull port 4 control register, high byte ech, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p4.6/seg22 p4.5/seg21 p4.4/seg20 p4conh bit-pair pin configuration settings 00 01 10 11 input mode, pull-up p4.7/seg23 input mode opendrain output mode note: if lcd is enabled by lcon.5, seg signal go out otherwise port 4 i/0 can be selected. figure 9-12. port 4 high-byte control register (p4conh)
s3c8248/c8245/p8245/c8247/c8249/p8249 i/o ports 9- 13 port 4 control register, low byte edh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p4.2/seg18 p4.1/seg17 p4.0/seg16 p4conl bit-pair pin configuration settings 00 01 10 11 output mode, push-pull input mode, pull-up p4.3/seg19 input mode opendrain output mode note: if lcd is enabled by lcon.4, seg signal go out otherwise port 4 i/0 can be selected. figure 9-13. port 4 low-byte control register (p4conl)
i/o ports s3c8248/c 8245/p8245/c8247/c8249/p8249 9- 14 port 5 port 5 is an 8-bit i/o port with individually configurable pins. port 5 pins are accessed directly by writing or reading the port 5 data register, p5 at location fbh in set 1, bank 0. p5.0?p5.7 can serve as inputs (with without pull-ups), as output (open drain or push-pull). and, they can serve as segment pins for lcd also. port 5 control register s port 5 has two 8-bit control registers: p5conh for p5.4?p5.7 and p5conl for p5.0?p5.3. a reset clears the p5conh and p5conl registers to ?00h?, configuring all pins to input mode. output mode, push-pull port 5 control register, high byte eeh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p5.6/seg30 p5.5/seg29 p5.4/seg28 p5conh bit-pair pin configuration settings 00 01 10 11 input mode, pull-up p5.7/seg31 input mode opendrain output mode note: if lcd is enabled by lcon.7, seg signal go out otherwise port 5 i/0 can be selected. figure 9-14. port 5 high-byte control register (p5conh)
s3c8248/c8245/p8245/c8247/c8249/p8249 i/o ports 9- 15 output mode, push-pull port 5 control register, low byte efh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p5.2/seg26 p5.1/seg25 p5.0/seg24 p5conl bit-pair pin configuration settings 00 01 10 11 input mode, pull-up p5.3/seg27 input mode opendrain output mode note: if lcd is enabled by lcon.6, seg signal go out otherwise port 5 i/0 can be selected. figure 9-15. port 5 low-byte control register (p5conl)
i/o ports s3c8248/c 8245/p8245/c8247/c8249/p8249 9- 16 notes
s3c8248/c8245/p8245/c8247/c8249/p8249 basic timer 10- 1 10 basic timer overview s3c8248/c8245/c8247/c8249 has an 8-bit basic timer . basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider ( f xx divided by 4096, 1024, 128, or 16 ) with multiplexer ? 8-bit basic timer counter, btcnt (set 1, bank 0, fdh, read-only) ? basic timer control register, btcon (set 1, d3h, read/write) basic timer control register (btcon ) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using register addressing mode. a reset clears btcon to " 00h " . this enables the watchdog function and selects a basic timer clock frequency of f xx /4096. to disable the watchdog function, you must write the signature code " 1010b " to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt (set 1, bank 0, fdh), can be cleared at any time during the normal operation by writing a "1" to btcon.1. to clear the frequency dividers , write a "1" to btcon.0.
basic timer s3c8248/c8245/p824 5/c8247/c8249/p8249 10- 2 basic timer control register (btcon) d3h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb divider clear bit: 0 = no effect 1= clear dvider basic timer counter clear bit: 0 = no effect 1= clear btcnt basic timer input clock selection bits: 00 = f xx /4096 01 = f xx /1024 10 = f xx /128 11 = f xx /16 watchdog timer enable bits: 1010b = disable watchdog function other value = enable watchdog function figure 10-1. basic timer control register (btcon )
s3c8248/c8245/p8245/c8247/c8249/p8249 basic timer 10- 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7?btcon.4 to any value other than " 1010b " . (the " 1010b " value disables the watchdog function.) a reset clears btcon to " 00h " , automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting), divided by 4096, as the bt clock. the mcu is reseted whenever a basic timer counter overflow occurs, during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occuring, to do this, the btcnt value must be cleared (by writing a ?1? to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. . the btcnt value then starts increasing at the rate of f xx /4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt. 4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume the normal operation. in summary, the following events occur when stop mode is released: 1. during the stop mode, a power-on reset or an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. if an interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows. 4. when a btcnt.4 overflow occurs, the normal cpu operation resumes .
basic timer s3c8248/c8245/p824 5/c8247/c8249/p8249 10- 4 note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). mux f xx /4096 div f xx /1024 f xx /128 f xx /16 f xx bits 3, 2 bit 0 basic timer control register (write '1010xxxxb' to disable) clear bit 1 reset or stop data bus 8-bit up counter (btcnt, read-only) start the cpu (note) ovf reset r figure 10-2. basic timer block diagram
s3c8248/c8245/p8245/c8247/c8249/p8249 8 -bit timer a/b 11- 1 11 8-bit timer a/b 8-bit timer a overview the 8-bit timer a is an 8-bit general-purpose timer/counter. timer a has three operating modes, one of which you select using the appropriate tacon setting: ? interval timer mode (toggle output at taout pin) ? capture input mode with a rising or falling edge trigger at the tacap pin ? pwm mode (tapwm) timer a has the following functional components: ? clock frequency divider ( fxx divided by 1024, 256, or 64 ) with multiplexer ? external clock input pin ( taclk) ? 8-bit counter (tacnt), 8-bit comparator, and 8-bit reference data register (tadata) ? i/o pins for capture input (tacap) or pwm or match output (tapwm, taout) ? timer a overflow interrupt (irq0, vector e2h) and match/capture interrupt (irq0, vector e0h) generation ? timer a control register, tacon (set 1, edh, read/write)
8-bit timer a/b s3 c8248/c8245/p8245/c8247/c8249/p8249 11- 2 function description timer a interrupts (irq0, vectors e0h and e2h) the timer a module can generate two interrupts: the timer a overflow interrupt (taovf), and the timer a match/ capture interrupt (taint). taovf is interrupt level irq0, vector e2h. taint also belongs to interrupt level irq0, but is assigned the separate vector address, e0h. pending condition of timer a interrupts (overflow & match/capture) can be cleared automatically by hardware where the interrupts are enabled. otherwise pending condition must be cleared manually by software. interval timer function the timer a module can generate an interrupt: the timer a match interrupt (taint). taint belongs to interrupt level irq0, and is assigned the separate vector address, e0h. when timer a match interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. in interval timer mode, a match signal is generated and taout is toggled when the counter value is identical to the value written to the ta reference data register, tadata. the match signal generates a timer a match interrupt (taint, vector e0h) and clears the counter. if, for example, you write the value 10h to tadata and 0ah to tacon, the counter will increment until it reaches 10h. at this point, the ta interrupt request is generated, the counter value is reset, and counting resumes. pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the tapwm pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer a data register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at ffh, and then continues incrementing from 00h. although timer a overflow interrupt is occurred, this interrupt is not typically used in pwm-type applications. instead, the pulse at the tapwm pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. one pulse width is equal to t clk ? 256 . capture mode in capture mode, a signal edge that is detected at the tacap pin opens a gate and loads the current counter value into the ta data register. you can select rising or falling edges to trigger this operation. timer a also gives you capture input source: the signal edge at the tacap pin. you select the capture input by setting the value of the timer a capture input selection bit in the port 3 control register, p3conl, (set 1, bank 0, e9h). when p3conl.7.6 is 00, the tacap input or normal input is selected. when p3conl.7.6 is set to 11, normal output is selected. both kinds of timer a interrupts can be used in capture mode: the timer a overflow interrupt is generated whenever a counter overflow occurs; the timer a match/capture interrupt is generated whenever the counter value is loaded into the ta data register. by reading the captured data value in tadata, and assuming a specific value for the timer a clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the tacap pin.
s3c8248/c8245/p8245/c8247/c8249/p8249 8 -bit timer a/b 11- 3 timer a control register (tacon) you use the timer a control register, tacon, to ? select the timer a operating mode (interval timer, capture mode, or pwm mode) ? select the timer a input clock frequency ? clear the timer a counter, tacnt ? enable the timer a overflow interrupt or timer a match/capture interrupt ? clear timer a match/capture interrupt pending conditions tacon is located in set 1, bank 0 at address edh, and is read/write addressable using register addressing mode. a reset clears tacon to '00h'. this sets timer a to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer a interrupts. you can clear the timer a counter at any time during normal operation by writing a "1" to tacon.3. the timer a overflow interrupt (taovf) is interrupt level irq0 and has the vector address e2h. when a timer a overflow interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. timer a control register edh, set 1, bank 0, r/w, reset; 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer a match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer a match/capture interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (write) 1 = interrupt is pending timer a overflow interrupt enable 0 = disable overflow interrupt 1 = enable overflow interrupt timer a counter clear bit: 0 = no affect 1 = clear the timer a counter (when write) timer a input clock selection bits: 00 = f xx /1024 01 = f xx /256 10 = f xx /64 11 = external clock (taclk) timer a operating mode selection bits: 00 = interval mode (taout mode) 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf interrupt can occur) note: pending bit of overflow interrupt is located in intpnd (d2h, set1) register. figure 11-1. timer a control register (tacon)
8-bit timer a/b s3 c8248/c8245/p8245/c8247/c8249/p8249 11- 4 block diagram timer a data register (read/write) timer a buffer reg 8-bit comparator 8-bit up-counter (read only) clear match tacon.7-.6 f xx /1024 f xx /256 f xx /64 taclk tacon.2 pending tacon.3 m u x overflow taovf m u x m u x tacap taint tacon.1 taout tapwm tacon.0 pending tacon.5.4 tacon.5.4 data bus 8 data bus 8 note: timer a input clock must be slower than cpu clock. pending pending bit is located at intpnd register. figure 11-2. timer a functional block diagram
s3c8248/c8245/p8245/c8247/c8249/p8249 8 -bit timer a/b 11- 5 8-bit timer b overview the s3c8248/c8245/p8245 micro-controller has an 8-bit counter called timer b. timer b, which can be used to generate the carrier frequency of a remote controller signal. pending condition of timer b is cleared automatically by hardware. timer b has two functions: ? as a normal interval timer, generating a timer b interrupt at programmed time intervals. ? to supply a clock source to the 16-bit timer/cou nter module, timer 0, for generating the timer 0 overflow interrupt. 8-bit down counter timer b data high byte register mux tbcon.0 (tbof) to other block (p3.0/tbpwm) irq1 (tbint) int.gen tbcon.3 repeat control interrupt control m u x f xx /1 f xx /2 f xx /4 f xx /8 tbcon.6-.7 tbcon.2 timer b data low byte register clk tbcon.4-.5 data bus 8 notes: 1. the value of the tbdatal register is loaded into the 8-bit counter when the operation of the timer b starts. if a borrow occurs in the counter, the value of the tbdatah register is loaded into the 8-bit counter. however, if the next borrow occurs, the value of the tbdatal register is loaded into the 8-bit counter. 2. timer b input clock must be slower than cpu clock. figure 11-3. timer b functional block diagram
8-bit timer a/b s3c 8248/c8245/p8245/c8247/c8249/p8249 11- 6 timer b control register ech, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer b mode selection bit: 0 = one-shot mode 1 = repeating mode timer b output flip-flop control bit: 0 = tbof is low 1 = tbof is high timer b start/stop bit: 0 = stop timer b 1 = start timer b timer b interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer b input clock selection bits: 00 = fxx 01 = fxx /2 10 = fxx /4 11 = fxx/8 timer b interrupt time selection bits: 00 = elapsed time for low data value 01 = elapsed time for high data value 10 = elapsed time for low and high data values 11 = invalid setting figure 11-4. timer b control register (tbcon) timer b data high-byte register (tbdatah) fah, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value: ffh timer b data low-byte register (tbdatal) ebh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value: ffh figure 11-5. timer b registers
s3c8248/c8245/p8245/c8247/c8249/p8249 8-bit timer a/b 11- 7 timer b pulse width calculations t low t high t low to generate the above repeated waveform consisted of low period time, t low , and high period time, t high . when tbof = 0, t low = (tbdatal + 2) x 1/fx, 0h < tbdatal < 100h, where fx = the selected clock. t high = (tbdatah + 2) x 1/fx, 0h < tbdatah < 100h, where fx = the selected clock. when tbof = 1, t low = (tbdatah + 2) x 1/fx, 0h < tbdatah < 100h, where fx = the selected clock. t high = (tbdatal + 2) x 1/fx, 0h < tbdatal < 100h, where fx = the selected clock. to make t low = 24 us and t high = 15 us. f osc = 4 mhz, fx = 4 mhz/4 = 1 mhz when tbof = 0, t low = 24 us = (tbdatal + 2) / fx = (tbdatal + 2) x 1us, tbdatal = 22. t high = 15 us = (tbdatah + 2) / fx = (tbdatah + 2) x 1us, tbdatah = 13. when tbof = 1, t high = 15 us = (tbdatal + 2) / fx = (tbdatal + 2) x 1us, tbdatal = 13. t low = 24 us = (tbdatah + 2) / fx = (tbdatah + 2) x 1us, tbdatah = 22.
8-bit timer a/b s3c 8248/c8245/p8245/c8247/c8249/p8249 11- 8 timer b clock 0h tbof = '0' tbdatal = 01-ffh tbdatah = 00h tbof = '0' tbdatal = 00h tbdatah = 01-ffh tbof = '0' tbdatal = 00h tbdatah = 00h tbof = '1' tbdatal = 00h tbdatah = 00h low high low high timer b clock tbof = '1' tbdatal = deh tbdatah = 1eh tbof = '0' tbdatal = deh tbdatah = 1eh tbof = '1' tbdatal = 7eh tbdatah = 7eh tbof = '0' tbdatal = 7eh tbdatah = 7eh 0h 100h 200h e0h 20h 20h e0h 80h 80h 80h 80h figure 11-6. timer b output flip-flop waveforms in repeat mode
s3c8248/c8245/p8245/c8247/c8249/p8249 8-bit timer a/b 11- 9 + + programming tip ? to generate 38 khz, 1/3duty signal through p3.0 this example sets timer b to the repeat mode, sets the oscillation frequency as the timer b clock source, and tbdatah and tbdatal to make a 38 khz,1/3 duty carrier frequency. the program parameters are: 17.59 m s 37.9 khz 1/3 duty 8.795 m s ? timer b is used in repeat mode ? oscillation frequency is 4 mhz (0.25 m s) ? tbdatah = 8.795 m s/0.25 m s = 35.18, tbdatal = 17.59 m s/0.25 m s = 70.36 ? set p3.0 to tbpwm mode. org 0100h ; reset address start di ? ? ? ld tbdatal,#(70-2) ; set 17.5 m s ld tbdatah,#(35-2) ; set 8.75 m s ld tbcon,#00000110b ; clock source ? fxx ; disable timer b interrupt. ; select repeat mode for timer b. ; start timer b operation. ; set timer b output flip-flop (tbof) high. ; ld p3conl,#02h ; set p3.0 to tbpwm mode. ; this command generates 38 khz, 1/3 duty pulse signal through p3.0. ? ? ?
8-bit timer a/b s3c 8248/c8245/p8245/c8247/c8249/p8249 11- 10 + + programming tip ? to generate a one pulse signal through p3.0 this example sets timer b to the one shot mode, sets the oscillation frequency as the timer b clock source, and tbdatah and tbdatal to make a 40 m s width pulse. the program parameters are: 40 m s ? timer b is used in one shot mode ? oscillation frequency is 4 mhz (1 clock = 0.25 m s) ? tbdatah = 40 m s / 0.25 m s = 160, tbdatal = 1 ? set p3.0 to tbpwm mode org 0100h ; reset address start di ? ? ? ld tbdatah,# (160-2) ; set 40 m s ld tbdatal,# 1 ; set any value except 00h ld tbcon,#00000001b ; clock source ? f osc ; disable timer b interrupt. ; select one shot mode for timer b. ; stop timer b operation. ; set timer b output flip-flop (tbof) high ld p3conl, #02h ; set p3.0 to tbpwm mode. ? ? pulse_out: ld tbcon,#00000101b ; start timer b operation ; to make the pulse at this point. ? ; after the instruction is executed, 0.75 m s is required ? ; before the falling edge of the pulse starts. ?
s3c8248/c8245/p8245/c8247/c8249/p8249 1 6-bit timer 0/1 12- 1 12 16-bit timer 0/ 1 16-bit timer 0 overview the 16-bit timer 0 is an 16-bit general-purpose timer. timer 0 has the interval timer mode by using the appropriate t0con setting. timer 0 has the following functional components: ? clock frequency divider ( fxx divided by 256, 64, 8 or 1) with multiplexer ? tbof (from timer b) is one of the clock frequencies. ? 16-bit counter (t0cnth/l), 16-bit comparator, and 16-bit reference data register (t0datah/l) ? timer 0 interrupt (irq2, vector e6h) generation ? timer 0 control register, t0con (set 1, bank 1, f1h, read/write) function description interval timer function the timer 0 module can generate an interrupt, the timer 0 match interrupt (t0int). t0int belongs to interrupt level irq2, and is assigned the separate vector address, e6h. the t0int pending condition is automatically cleared by hardware when it has been serviced. even though t0int is disabled, the application?s service routine can detect a pending condition of t0int by the software and execute it?s sub-routine. when this case is used, the t0int pending bit must be cleared by the application subroutine by writing a ?0? to the t0con.0 pending bit. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the t0 reference data registers, t0datah/l. the match signal generates a timer 0 match interrupt (t0int, vector e4h) and clears the counter. if, for example, you write the value 0010h to t0datah/l and 0fh to t0con, the counter will increment until it reaches 10h. at this point, the t0 interrupt request is generated, the counter value is reset, and counting resumes.
16-bit timer 0/1 s 3c8248/c8245/p8245/c8247/c8249/p8249 12- 2 timer 0 control register (t0con) you use the timer 0 control register, t0con, to ? enable the timer 0 operating (interval timer) ? select the timer 0 input clock frequency ? clear the timer 0 counter, t0cnt ? enable the timer 0 interrupt and clear timer 0 interrupt pending condition t0con is located in set 1, at address f1h, and is read/write addressable using register addressing mode. a reset clears t0con to "00h". this sets timer 0 to disable interval timer mode, selects the tbof, and disables timer 0 interrupt. you can clear the timer 0 counter at any time during normal operation by writing a ?1? to t0con.3 to enable the timer 0 interrupt (irq2, vector e6h), you must write t0con.2, and t0con.1 to "1". to generate the exact time interval, you should write t0con.3 and 0, which cleared counter and interrupt pending bit. to detect an interrupt pending condition when t0int is disabled, the application program polls pending bit, t0con.0. when a "1" is detected, a timer 0 interrupt is pending. when the t0int sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0con.0. timer 0 control registers f1h, set 1, bank 1, r/w, reset; 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 0 interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer 0 interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending timer 0 count enable bit: 0 = disable counting operation 1 = enable counting operation timer 0 counter clear bit: 0 = no affect 1 = clear the timer 0 counter (when write) timer 0 input clock selection bits: 000 = tbof 010 = f xx /256 100 = f xx /64 110 = f xx /8 xx 1 = f xx not used note: for normal operation t0con.3 bit must be set 1. figure 12-1. timer 0 control register (t0con)
s3c8248/c8245/p8245/c8247/c8249/p8249 1 6-bit timer 0/1 12- 3 block diagram timer 0 data h/l reg (read/write) timer 0 buffer reg 16-bit comparator 16-bit up-counter h/l (read only) match bit 3 t0int counter clear signal (t0con.3) bits 7, 6, 5 m u x fxx/256 fxx/64 fxx/8 fxx/1 tbof bit 2 clear bit 0 bit 1 irq2 pending r data bus 8 data bus 8 notes: 1. to be loaded t0data value to buffer register for comparing, t0con.3 bit must be set 1. 2. timer 0 input clock must be slower than cpu clock. figure 12-2. timer 0 functional block diagram
16-bit timer 0/1 s 3c8248/c8245/p8245/c8247/c8249/p8249 12- 4 timer 0 counter high-byte (t0cnth) f2h, set 1, bank 1, r .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value: 00h timer 0 counter low-byte (t0cntl) f3h, set 1, bank 1, r .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value: 00h figure 12-3. timer 0 counter register (t0cnt) timer 0 data high-byte register (t0datah) f4h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value: ffh timer 0 data low-byte register (t0datal) f5h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value: ffh figure 12-4. timer 0 data register (t0datah, l)
s3c8248/c8245/p8245/c8247/c8249/p8249 1 6-bit timer 0/1 12- 5 16-bit timer 1 overview the 16-bit timer 1 is an 16-bit general-purpose timer/counter. timer 1 has three operating modes, one of which you select using the appropriate t1con setting: ? interval timer mod e (toggle output at t1out pin) ? capture input mode with a rising or falling edge trigger at the t1cap pin ? pwm mode (t1pwm) timer 1 has the following functional components: ? clock frequency divider ( fxx divided by 1024, 256, 64, 8 or 1) with multiplexer ? external clock input pin (t1clk) ? 16-bit counter (t1cnth/l), 16-bit comparator, and 16-bit reference data register (t1datah/l) ? i/o pins for capture input (t1cap), or pwm or match output (t1pwm, t1out) ? timer 1 overflow interrupt (irq3, vector eah) a nd match/capture interrupt (irq3, vector e8h) generation ? timer 1 control register, t1con (set 1, fbh, bank 1, read/write)
16-bit timer 0/1 s 3c8248/c8245/p8245/c8247/c8249/p8249 12- 6 function description timer 1 interrupts (irq3, vectors e8h and eah) the timer 1 module can generate two interrupts, the timer 1 overflow interrupt (t1ovf), and the timer 1 match/capture interrupt (t1int). t1ovf is interrupt level irq3, vector eah. t1int also belongs to interrupt level irq3, but is assigned the separate vector address, e8h. a timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. a timer 1 match/capture interrupt, t1int pending condition is also cleared by hardware when it has been serviced. interval timer function the timer 1 module can generate an interrupt: the timer 1 match interrupt (t1int). t1int belongs to interrupt level irq3, and is assigned the separate vector address, e8h. when a timer 1 measure interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. in interval timer mode, a match signal is generated and t1out is toggled when the counter value is identical to the value written to the t1 reference data register, t1datah/l. the match signal generates a timer 1 match interrupt (t1int, vector e8h) and clears the counter. if, for example, you write the value 0010h to t1datah/l and 06h to t1con, the counter will increment until it reaches 0010h. at this point, the t1 interrupt request is generated, the counter value is reset, and counting resumes. pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t1pwm pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1 data register. in pwm mode, however, the match signal does not clear the counter but can generate a match interrupt. the counter runs continuously, overflowing at ffffh, and then repeat the incrementing from 0000h. whenever an overflow is occurred, an overflow (ovf) interrupt can be generated. although you can use the match or the overflow interrupt in pwm mode, interrupts are not typically used in pwm-type applications. instead, the pulse at the t1pwm pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then pulse is held to high level for as long as the data value is greater than (>) the counter value. one pulse width is equal to t clk capture mode in capture mode, a signal edge that is detected at the t1cap pin opens a gate and loads the current counter value into the t1 data register. you can select rising or falling edges to trigger this operation. timer 1 also gives you capture input source, the signal edge at the t1cap pin. you select the capture input by setting the value of the timer 1 capture input selection bit in the port 1 control register low, p1conl, (set 1 bank 0, e5h). when p1conl.1.0 is 00, the t1cap input or normal input is selected .when p1conl.1.0 is set to 11, normal output is selected. both kinds of timer 1 interrupts can be used in capture mode, the timer 1 overflow interrupt is generated whenever a counter overflow occurs, the timer 1 match/capture interrupt is generated whenever the counter value is loaded into the t1 data register. by reading the captured data value in t1datah/l, and assuming a specific value for the timer 1 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the t1cap pin.
s3c8248/c8245/p8245/c8247/c8249/p8249 1 6-bit timer 0/1 12- 7 timer 1 control register (t1con) you use the timer 1 control register, t1con, to ? select the timer 1 operating mode (interval timer, capture mode, or pwm mode) ? select the timer 1 input clock frequency ? clear the timer 1 counter, t1cnth/l ? enable the timer 1 overflow interrupt or timer 1 match/capture interrupt ? clear timer 1 match/capture interrupt pending conditions t1con is located in set 1 and bank 1 at address fbh, and is read/write addressable using register addressing mode. a reset clears t1con to ?00h?. this sets timer 1 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 1 interrupts. to disable the counter operation, please set t1con.7-.5 to 111b. you can clear the timer 1 counter at any time during normal operation by writing a ?1? to t1con.3. the timer 1 overflow interrupt (t1ovf) is interrupt level irq3 and has the vector address eah. when a timer 1 overflow interrupt occurs and is serviced interrupt (irq3, vector e8h), you must write t1con.1 to ?1?. to generate the exact time interval, you should write t1con by the cpu, the pending condition is cleared automatically by hardware. to enable the timer 1 match/capture which clear counter and interrupt pending bit. to detect a match/capture or overflow interrupt pending condition when t1int or t1ovf is disabled, the application program should poll the pending bit. when a ?1? is detected, a timer 1 match/capture or overflow interrupt is pending. when her sub-routine has been serviced, the pending condition must be cleared by software by writing a ?0? to the interrupt pending bit. timer 1 control register (t1con) fbh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 1 match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer 1 overflow interrupt enable: 1 = enable overflow interrupt 0 = disable overflow interrupt timer 1 counter clear bit: 0 = no effect 1 = clear the timer 1 counter (when write) timer 1 input clock selection bits: 000 = f xx /1024 010 = f xx /256 100 = f xx /64 110 = f xx /8 00 1 = f xx /1 011 = external clock (t1clk) falling edge 101 = external clock (t1clk) rising edge 111 = counter stop timer 1 operating mode selection bits: 00 = interval mode 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf & match interrupt can occur) figure 12-5. timer 1 control register (t1con)
16-bit timer 0/1 s 3c8248/c8245/p8245/c8247/c8249/p8249 12- 8 block diagram timer 1 data h/l register timer 1 buffer reg 16-bit comparator 16-bit up-counter (read only) counter clear signal or match clear match t1con.7-5 f xx /1024 f xx /8 f xx /256 f xx /64 f xx /1 t1ovf irq3 t1con.0 ovf pending t1con.2 t1int irq3 pending t1con.1 t1out t1pwm t1con.4-.3 r m u x v ss t1clk m u x m u x t1cap t1con.4-.3 data bus 8 data bus 8 pending pending bit is located at intpnd register notes: 1. 16-bit pwm frequency. where 10 mhz clock is used and fxx/8 is selected, pwm frequency = 1 / { (8/10 mhz) x ffffh } = 19.07 hz 2. timer 1 input clock must be slower than cpu clock. figure 12-6. timer 1 functional block diagram
s3c8248/c8245/p8245/c8247/c8249/p8249 1 6-bit timer 0/1 12- 9 timer 1 counter high-byte register (t1cnth) fch, set 1, bank 1, r msb lsb reset value: 00h msb .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 lsb timer 1 counter low-byte register (t1cntl) fdh, set 1, bank 1, r reset value: 00h .7 .6 .5 .4 .3 .2 .1 .0 lsb timer 1 data high-byte register (t1datah) feh, set 1, bank 1, r/w reset value: ffh msb .7 .6 .5 .4 .3 .2 .1 .0 lsb timer 1 data low-byte register (t1datal) ffh, set 1, bank 1, r/w reset value: ffh msb note: pending bit is located in intpnd (d2h, set1) register. figure 12-7. timer 1 control register (t1cnth/l)
16-bit timer 0/1 s 3c8248/c8245/p8245/c8247/c8249/p8249 12- 10 notes
s3c8248/c8245/p8245/c8247/c8249/p8249 w atch timer 13- 1 13 watch timer overview watch timer functions include real-time and watch-time measurement and interval timing for the system clock. to start watch timer operation, set bit1 and bit 6 of the watch timer mode register, wtcon.1and 6, to ?1?. after the watch timer starts and elapses a time, the watch timer interrupt is automatically set to ?1?, and interrupt requests commence in 1.955 ms or 0.125, 0.25 and 0.5-second intervals. the watch timer can generate a steady 0.5 khz, 1 khz, 2 khz, or 4 khz signal to the buzzer output. by setting wtcon.3 and wtcon.2 to ?11b?, the watch timer will function in high-speed mode, generating an interrupt every 1.955 ms. high-speed mode is useful for timing events for program debugging sequences. the watch timer supplies the clock frequency for the lcd controller (f lcd ). therefore, if the watch timer is disabled, the lcd controller does not operate. ? real-time and watch-time measurement ? using a main system or subsystem clock source ? clock source generation for lcd controller ? buzzer output frequency generator ? timing tests in high-speed mode
watch timer s3c8248 /c8245/p8245/c8247/c8249/p8249 13- 2 watch timer control register (wtcon: r/w) fbh wtcon.7 wtcon.6 wtcon.5 wtcon.4 wtcon.3 wtcon.2 wtcon.1 wtcon.0 reset "0" "0" "0" "0" "0" "0" "0" "0" table 13-1. watch timer control register (wtcon): set 1, bank 1, fah, r/w bit name values function address wtcon.7 0 select (fxx/128) as the watch timer clock fah 1 select subsystem clock as watch timer clock wtcon.6 0 disable watch timer interrupt 1 enable watch timer interrupt wtcon.5?.4 0 0 0.5 khz buzzer (buz) signal output 0 1 1 khz buzzer (buz) signal output 1 0 2 khz buzzer (buz) signal output 1 1 4 khz buzzer (buz) signal output wtcon.3?.2 0 0 set watch timer interrupt to 0.5 s. 0 1 set watch timer interrupt to 0.25 s. 1 0 set watch timer interrupt to 0.125 s. 1 1 set watch timer interrupt to 1.955 ms. wtcon.1 0 disable watch timer, clear frequency dividing circuits 1 enable watch timer wtcon.0 0 interrupt is not pending, clear pending bit when write 1 interrupt is pending note: watch timer clock frequency ( fw) is assumed to be 32,768 hz.
s3c8248/c8245/p8245/c8247/c8249/p8249 w atch timer 13- 3 watch timer circuit diagram wtcon.1 wtcon.2 wtcon.3 wtcon.4 wtcon.5 enable/disable selector circuit mux wtcon.0 wtint wtcon.6 buzzer output f w /2 14 f w /2 13 f w /2 12 f w /2 6 f w /64 (0.5 khz) f w /32 (1 khz) f w /16 (2 khz) f w /8 (4 khz) 1 hz f xx = main system clock (4.19 mhz) f xt = subsystem clock (32768 hz) f w = watch timer clock selector wtcon.7 frequency dividing circuit f w 32.768 khz f xt fxx / 128 f lcd (512 hz) f vld (4096 hz) f booster (4096 hz) figure 13-1. watch timer circuit diagram
watch timer s3c8248 /c8245/p8245/c8247/c8249/p8249 13- 4 notes
s3c8248/c8245/p8245/c8247/c8249/p8249 l cd controller/driver 14- 1 14 lcd controller/driver overview the s3c8248/c8245/c8247/c8249 micro-controller can directly drive an up-to-16-digit (32-segment) lcd panel. the lcd module has the following components: ? lcd controller/driver ? display ram (00h?0fh) for storing display data in page 4 ? 32 segment output pins (seg0?seg31) ? four common output pins (com0?com3) ? three lcd operating power supply pins (v lc0? v lc2 ) ? lcd bias by voltage booster ? lcd bias by voltage dividing resistors bit settings in the lcd mode register, lmod, determine the lcd frame frequency, duty and bias, and the segment pins used for display output. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during stop and idle modes. the lcd control register lcon turns the lcd display on and off and switches current to the charge-pump circuits for the display. lcd data stored in the display ram locations are transferred to the segment signal pins automatically without program control. lcd controller/ driver 8 8-bit data bus 2 3 4 32 ca-cb v lc0 -v lc2 com0-com3 seg0-seg31 figure 14-1. lcd function diagram
lcd controller/driver s3c8248/c8245/p8245 /c8247/c8249/p8249 14- 2 lcd circuit diagram com2 com0 com3 lmod lcon timing controller 05h.1 05h.0 04h.7 04h.6 00h.3 00h.2 00h.1 00h.0 ofh.4 ofh.5 ofh.6 ofh.7 mux mux mux 8 8 8 8 8 f lcd com control com1 v lc0 v lc1 v lc2 ca cb seg31 seg30 seg29 seg28 seg27 seg26 seg0 seg16 seg15 seg14 seg13 seg12 seg11 segment driver note: f lcd = f w /2 6 , f w / 2 7 , f w /2 8 , f w /2 9 lcd voltage control figure 14-2. lcd circuit diagram
s3c8248/c8245/p8245/c8247/c8249/p8249 l cd controller/driver 14- 3 lcd ram address area ram addresses 00h - 0fh of page 4, or page 2, according to rom size, are used as lcd data memory. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0?seg31 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. seg0 bit.7 bit.3 bit.7 bit.3 bit.7 bit.3 bit.7 bit.3 bit.7 bit.3 bit.3 bit.7 bit.3 bit.7 bit.3 bit.7 bit.3 bit.7 bit.6 bit.2 bit.6 bit.2 bit.6 bit.2 bit.6 bit.2 bit.6 bit.2 bit.2 bit.6 bit.2 bit.6 bit.2 bit.6 bit.2 bit.6 bit.5 bit.1 bit.5 bit.1 bit.5 bit.1 bit.5 bit.1 bit.5 bit.1 bit.1 bit.5 bit.1 bit.5 bit.1 bit.5 bit.1 bit.5 bit.4 bit.0 bit.4 bit.0 bit.4 bit.0 bit.4 bit.0 bit.4 bit.0 bit.0 bit.4 bit.0 bit.4 bit.0 bit.4 bit.0 bit.4 seg1 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 00h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh com3 com2 com1 com0 figure 14-3. lcd display data ram organization
lcd controller/driver s3c8248/c8245/p8245 /c8247/c8249/p8249 14- 4 lcd control register (lcon), d0h table 14-1. lcd control register (lcon) organization lcon bit setting description lcon.7 0 p5.4?p5.7 i/o is selected 1 seg28?seg31 is selected, p5.4?p5.7 i/o is disabled lcon.6 0 p5.0?p5.3 i/o is selected 1 seg24?seg27 is selected, p5.0?p5.3 i/o is disabled lcon.5 0 p4.4?p4.7 i/o is selected 1 seg20?seg23 is selected, p4.4?p4.7 i/o is disabled lcon.4 0 p4.0?p4.3 i/o is selected 1 seg16?seg19 is selected, p4.0?p4.3 i/o is disabled lcon.3 0 this bit is used for internal testing only; always logic zero. lcon.2 0 enable lcd initial circuit (internal bias voltage). 1 disable lcd initial circuit for external lcd dividing resistors(external bias voltage). lcon.1 0 stop voltage booster(clock stop and cut off current charge path) 1 run voltage booster(clock run and turn on current charge path) lcon.0 0 lcd output low; turn display off, com and seg output low cut off voltage booster (booster clock disable). 1 com and seg output is in display mode; turn display on. table 14-2. relationship of lcon.0 and lmod.3 bit settings lcon.0 lmod.3 com0?com3 seg0?seg31 0 x output low; lcd display off output low; lcd display off 1 0 output low; lcd display off output low; lcd display off 1 com output corresponds to display mode seg output corresponds to display mode note: "x" means don?t care.
s3c8248/c8245/p8245/c8247/c8249/p8249 l cd controller/driver 14- 5 lcd mode register (lmod) the lcd mode control register lmod is mapped to ram addresses d1h. lmod controls these lcd functions: ? duty and bias selection (lmod.3?lmod.0) ? lcdck clock frequency selection (lmod.5?lmod.4) the lcd clock signal, lcdck, determines the frequency of com signal scanning of each segment output. this is also referred to as the 'frame frequency.' since lcdck is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the lcd display is turned on. reset clears the lmod register values to logic zero. this produces the following lcd control settings: ? display is turned off ? lcdck frequency is the watch timer clock (fw)/2 9 = 64 hz the lcd display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. the lcd output voltage level is always 3 v, supplied by the voltage booster. table 14-3. lcd clock signal (lcdck) frame frequency lcdck frequency static 1/2 duty 1/3 duty 1/4 duty fw/2 9 (64 hz) 64 32 21 16 fw/2 8 (128 hz) 128 64 43 32 fw/2 7 (256 hz) 256 128 85 64 fw/2 6 (512 hz) 512 256 171 128 note: ?fw? is the watch timer clock frequency of 32.768 khz.
lcd controller/driver s3c8248/c8245/p8245 /c8247/c8249/p8249 14- 6 table 14-4. lcd mode control register (lmod) organization, d1h lmod.7 always logic zero. lmod.6 always logic zero. lmod.5 lmod.4 lcd clock (lcdck) frequency 0 0 32.768 khz watch timer clock ( fw)/2 9 = 64 hz 0 1 32.768 khz watch timer clock (fw)/2 8 = 128 hz 1 0 32.768 khz watch timer clock (fw)/2 7 = 256 hz 1 1 32.768 khz watch timer clock (fw)/2 6 = 512 hz lmod.3 lmod.2 lmod.1 lmod.0 duty and bias selection for lcd display 0 x x x lcd display off (com and seg output low) 1 0 0 0 1/4 duty, 1/3 bias 1 0 0 1 1/3 duty, 1/3 bias 1 0 1 1 1/3 duty, 1/2 bias 1 0 1 0 1/2 duty, 1/2 bias 1 1 x x static note: ?x? means don?t care. table 14-5. maximum number of display digits per duty cycle lcd duty lcd bias com output pins maximum seg display static static com0 32 1/2 1/2 com0?com1 32 x 2 1/3 1/2 com0?com2 32 x 3 1/3 1/3 com0?com2 32 x 3 1/4 1/3 com0?com3 32 x 4
s3c8248/c8245/p8245/c8247/c8249/p8249 l cd controller/driver 14- 7 lcd drive voltage the lcd display is turned on only when the voltage difference between the common and segment signals is greater than v lcd . the lcd display is turned off when the difference between the common and segment signal voltages is less than v lcd. the turn-on voltage, + v lcd or - v lcd , is generated only when both signals are the selected signals of the bias. table 14-7 shows lcd drive voltages for static mode, 1/2 bias, and 1/3 bias. table 14-6. lcd drive voltage values lcd power supply static mode 1/2 bias 1/3 bias v lc2 v lcd v lcd v lcd v lc1 ? v lcd 2/3 v lcd v lc0 ? 1/2 v lcd 1/3 v lcd v ss 0 v 0 v 0 v note: the lcd panel display may deteriorate if a dc voltage is applied that lies between the common and segment signal voltage. therefore, always drive the lcd pan el with ac voltage. lcd seg/seg signals the 32 lcd segment signal pins are connected to corresponding display ram locations at 00h?0fh. bits 0-3 (and 4-7) of the display ram are synchronized with the common signal output pins com0, com1, com2, and com3. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin. each bias has select and no-select signals. com-seg fr select non-select 1 frame com seg v lc2 v ss v lc2 v ss v lc2 v ss -v lc2 figure 14-4. select/no-select bias signals in static display mode
lcd controller/driver s3c8248/c8245/p8245 /c8247/c8249/p8249 14- 8 fr select non-select 1 frame com v lc1, 2 v lc 0 v ss seg v ss com-seg v ss -v lc 0 -v lc1, 2 v lc1, 2 v lc 0 v lc1, 2 v lc 0 figure 14-5. select/no-select bias signals in 1/2 duty, 1/2 bias display mode fr select non-select 1 frame seg com com-seg v lc 2 v ss v lc 2 v ss v lc 2 v ss -v lc 2 figure 14-6. select/no-select bias signals in 1/3 duty, 1/3 bias display mode
s3c8248/c8245/p8245/c8247/c8249/p8249 l cd controller/driver 14- 9 fr 1 frame com0 com1 seg0 seg1 com0 -seg0 com0 -seg1 com1 -seg0 com1 -seg1 0 1 0 1 note: v lc1 = v lc0 seg1 seg2 seg3 seg0 seg3.1 x c1 .0 .1 .2 .3 1 0 x x 1 1 x x .4 .5 .6 .7 0 1 x x .0 .1 .2 .3 1 0 x x .4 .5 .6 .7 data register page 4, address 00h ld 00h, #31h data register page 4, address 01h ld 01h, #12h com0 com1 seg2.1 x c1 seg0.0 x c0 seg0.1 x c1 seg1.0 x c0 seg3.0 x c0 seg2.1 x c1 seg2.0 x c0 seg2.0 x c0 seg1.1 x c1 v lc1, 2 v ss v lc0 v lc1, 2 v ss v lc0 v lc1, 2 v ss v lc0 v lc1, 2 v ss v lc0 v lc1, 2 -v lc1, 2 v lc0 v ss -v lc0 v lc1, 2 -v lc1, 2 v lc0 v ss -v lc0 v lc1, 2 -v lc1, 2 v lc0 v ss -v lc0 v lc1, 2 -v lc1, 2 v lc0 v ss -v lc0 figure 14-7. lcd signal and wave forms example in 1/2 duty, 1/2 bias display mode
lcd controller/driver s3c8248/c8245/p8245 /c8247/c8249/p8249 14- 10 com0 com1 seg0 seg1 com0 -seg0 com0 -seg1 com1 -seg0 com1 -seg1 com2 v lc2 v ss v lc1 v lc0 v lc2 v ss v lc1 v lc0 v lc2 v ss v lc1 v lc0 v lc2 v ss v lc1 v lc0 v lc2 v ss v lc1 v lc0 fr 1 frame 0 1 2 0 1 2 seg1.6 x c2 seg2.1 x c1 seg2.0 x c0 seg0.0 x c0 seg2.1 x c1 seg1.4 x c0 seg0.2 x c2 seg2.0 x c0 seg1.5 x c1 seg0.1 x c1 com0 com1 seg0 data register page 4, address 00h ld 00h, #16h seg1 1 0 0 x .4 .5 .6 .7 seg2 1 1 0 x .0 .1 .2 .3 com2 v lc2 -v lc1 v lc1 v lc0 v ss -v lc0 -v lc2 v lc2 -v lc1 v lc1 v lc0 v ss -v lc0 -v lc2 v lc2 -v lc1 v lc1 v lc0 v ss -v lc0 -v lc2 v lc2 -v lc1 v lc1 v lc0 v ss -v lc0 -v lc2 .0 .1 .2 .3 0 1 1 x seg3 seg4 1 1 0 x .0 .1 .2 .3 data register page 4, address 02h ld 02h, #33h seg5 1 1 0 x .4 .5 .6 .7 data register page 4, address 01h ld 00h, #43h .4 .5 .6 .7 0 0 1 x figure 14-8. lcd signals and wave forms example in 1/3 duty, 1/3 bias display mode
s3c8248/c8245/p8245/c8247/c8249/p8249 l cd controller/driver 14- 11 1 frame 0 1 2 3 1 2 v lc2 v ss v lc1 v lc0 v lc2 v ss v lc1 v lc0 com0 com1 com3 seg0 com0 -seg0 com0 -seg1 com1 -seg1 com2 fr 0 3 v lc2 v ss v lc1 v lc0 v lc2 v ss v lc1 v lc0 v lc2 -v lc1 v lc1 v lc0 v ss -v lc0 -v lc2 v lc2 -v lc1 v lc1 v lc0 v ss -v lc0 -v lc2 v lc2 -v lc1 v lc1 v lc0 v ss -v lc0 -v lc2 v lc2 -v lc1 v lc1 v lc0 v ss -v lc0 -v lc2 v lc2 v ss v lc1 v lc0 v lc2 v ss v lc1 v lc0 seg1 com1 -seg0 seg1.7 x c3 seg2.1 x c1 seg1.4 x c0 seg0.0 x c0 seg0.1 x c1 seg1.5 x c1 seg0.3 x c3 seg2.0 x c0 seg1.6 x c2 seg0.2 x c2 com0 com1 com2 data register page 4, address 01h ld 01h, #7ah seg2 0 1 0 1 .0 .1 .2 .3 seg3 1 1 1 0 .4 .5 .6 .7 data register page 4, address 02h ld 02h, #63h seg4 1 1 0 0 .0 .1 .2 .3 seg5 0 1 1 0 .4 .5 .6 .7 com3 data register page 4, address 00h ld 00h, #3eh seg0 0 1 1 1 .0 .1 .2 .3 seg1 1 1 0 0 .4 .5 .6 .7 figure 14-9. lcd signals and wave forms example in 1/4 duty, 1/3 bias display mode
lcd controller/driver s3c8248/c8245/p8245 /c8247/c8249/p8249 14- 12 lcd voltage driving method by voltage booster for run the voltage booster ? make enable the watch timer for f booster ? set lcon.2 to "0" and lcon.1 to "1" for make enable voltage booster ? re commendable capacitance value is 0.1 uf (cab, c0, c1, c2) by voltage dividing resistors (externally) for make external voltage dividing resistors ? make enable the watch timer ? set lcon.2 to "1" and lcon.1 to "0" for make disable voltage booster ? make floating the ca and cb pin ? recommendable r = 100 k w v dd v lc2 v lc1 v lc0 v ss 2 x r r r r v dd v lc2 v lc1 v lc0 v ss r r r static and 1/3 bias (v lcd = 3 v at v dd = 5 v) 1/2 bias (v lcd = 3.3 v at v dd = 5 v) v dd v lc2 v lc1 v lc0 v ss r r r static and 1/3 bias (v lcd = 5 v at v dd = 5 v) note: 3.0 v v lcd 5.5 v figure 14-10. voltage dividing resistor circuit diagram
s3c8248/c8245/p8245/c8247/c8249/p8249 a /d converter 15- 1 15 10-bit analog-to-digital converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 -bit digital values. the a nalog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register (adcon) ? eight multiplexed analog data input pins (adc0?adc7) ? 10-bit a/d conversion data output register (addatah/l) ? 10 -bit digital input port (alternately, i/o port.) ? av ref and av ss pins, av ss is internally connected to v ss function description to initiate an analog-to-digital conversion procedure, at the first you must set adcen signal for adc input enable at port 2, the pin set with 1 can be used for adc analog input. and you write the channel selection data in the a/d converter control register adcon.4?.7 to select one of the eight analog input pins (adc0?7) and set the conversion start or enable bit, adcon.0. the read-write adcon register is located in set 1, bank 0, at address f3h. the pins witch are not used for adc can be used for normal i/o. during a normal conversion, adc logic initially sets the successive approximation register to 200h (the approximate half-way point of an 10 -bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.6? 4) in the adcon register. to start the a/d conversion, you should set the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion(eoc) bit is automatically set to 1 and the result is dumped into the addatah/l register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addatah/l before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the a/d converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the adc0?adc7 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block. you must use stop or idle mode after adc operation is finished.
a/d converter s3c8 248/c8245/p8245/c8247/c8249/p8249 15- 2 conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: when fxx/8 is selected for conversion clock with an 8 mhz fxx clock frequency, one clock cycle is 1 us. each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit 10 bits + set-up time = 50 clocks, 50 clock 1us = 50 us at 1 mhz a/d converter control register (adcon) the a/d converter control register, adcon, is located at address f7h in set 1, bank 0. it has three functions: ? a nalog input pin selection ( bits 4, 5, and 6 ) ? end-of-conversion status detection ( bit 3) ? a/d operation start or enable ( bit 0 ) after a reset, the start bit is turned off. you can select only one analog input channel at a time. other analog input pins (adc0?adc7) can be selected dynamically by manipulating the adcon.4?6 bits. and the pins not used for analog input can be used for normal i/o function. start or enable bit 0 = disable operation 1 = start operation a/d converter control register (adcon) f7h, set 1, bank 1, r/w (eoc bit is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb end-of-conversion bit 0 = conversion not complete 1 = conversion complete always logic zero a/d input pin selection bits: adc0 .6.5.4 adc1 adc2 adc3 adc4 adc5 adc6 adc7 000 001 010 011 100 101 110 111 clock selection bit: a/d input pin 00 01 10 11 f xx /16 f xx /8 f xx /4 f xx /1 .2.1 conversion clk figure 15-1. a/d converter control register (adcon)
s3c8248/c8245/p8245/c8247/c8249/p8249 a /d converter 15- 3 conversion data register (high byte) addatah f8h, set 1, bank 1, read only .7 .6 .5 .4 .3 .2 .1 .0 msb lsb conversion data register (low byte) addatal f9h, set 1, bank 1, read only .1 .0 msb lsb figure 15-2. a/d converter data register (addatah/l) internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to av ref (usually, av ref = v dd ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first conversion bit is always 1/2 av ref .
a/d converter s3c8 248/c8245/p8245/c8247/c8249/p8249 15- 4 block diagram input pins adc0-adc7 (p2.0-p2.7) clock selector conversion result (addatah/l f8, f9h, set 1, bank 1) - + upper 8-bit is loaded to a/d conversion data register to adcon.3 (eoc flag) successive approximation logic & register av ref av ss analog comparator 10-bit d/a converter m u x adcon.4-.6 (select one input pin of the assigned pins) adcen.0-.7 (assign pins to adc input) adcon.0 (ad/c enable) adcon.0 (ad/c enable) . . . adcon.2-.1 figure 15-3. a/d converter functional block diagram
s3c8248/c8245/p8245/c8247/c8249/p8249 a /d converter 15- 5 note: the symbol "r" signifies an offset resistor with a value of from 50 to 100 w . if this resistor is omitted, the absolute accuracy will be maximum of 3 lsbs. v ss s3c8248/c8245 /c8247/c8249 adc0-adc7 av ref reference voltage input analog input pin r v dd v dd 10 uf 103 c 101 c + - figure 15-4. recommended a/d converter circuit for highest absolute accuracy
a/d converter s3c8 248/c8245/p8245/c8247/c8249/p8249 15- 6 notes
s3c8248/c8245/p8245/c8247/c8249/p8249 serial i/o interface 1 6- 1 1 6 serial i/o interface overview serial i/o module, sio can interface with various types of external device that require serial data transfer. the components of each sio function block are: ? 8-bit control register (s iocon ) ? clock selector logic ? 8-bit data buffer (siodata) ? 8-bit prescaler (siops) ? 3-bit serial clock counter ? serial data i/o pins (si, so) ? external clock input/output pins (sck) the sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio modules, follow these basic steps: 1. configure the i/o pins at port (so, sck, si) by loading the appropriate value to the p1conh register if necessary. 2. load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3. for interrupt generation, set the serial i/o interrupt enable bit (siocon.1) to "1". 4. when you transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, the shift operation starts. 5. when the shift operation (transmit/receive) is completed, the sio pending bit (siocon.0) is set to "1" and an sio interrupt request is generated.
serial i/o interface s3c8248/c8245/p824 5/c8247/c8249/p8249 1 6- 2 sio control register (siocon) the control register for serial i/o interface module, siocon, is located at f0h in set 1, bank 0. it has the control settings for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counter and start shift operation ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset clears the siocon value to "00h". this configures the corresponding module with an internal clock source at the sck, selects receive-only operating mode, and clears the 3-bit counter. the data shift operation and the interrupt are disabled. the selected data direction is msb-first. serial i/o module control registers siocon: f0h, set 1, bank 0, r/w, reset; 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb sio interrupt enable bit: 0 = disable sio interrupt 1 = enable sio interrupt sio interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending sio shift operation enable bit: 0 = disable shifter and clock counter 1 = enable shifter and clock counter shift clock edge selection bit: 0 = t x at falling edeges, rx at rising edges. 1 = t x at rising edeges, rx at falling edges. data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio mode selection bit: 0 = receive only mode 1 = transmit/receive mode sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift clock selection bit: 0 = internal clock (p.s clock) 1 = external clock (sck) figure 1 6- 1. serial i/o module control registers (siocon)
s3c8248/c8245/p8245/c8247/c8249/p8249 serial i/o interface 1 6- 3 sio pre-scaler register (siops) the control register for serial i/o interface module, siops, is located at f2h in set 1, bank 0. the value stored in the sio pre-scale registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock (fxx/4)/(pre- scaler value + 1), or sck input clock, where the input clock is fxx/4 sio pre-scaler register (siops) f2h, set 1, bank 0 r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb baud rate = (f xx /4)/(siops + 1) figure 16-2. sio pre-scale registers (siops) block diagram sio int pending 3-bit counter clear siocon.0 fxx /2 siops (f2h, bank 0) sck siocon.7 prescaler value = 1/(siops +1) siocon.1 (interrupt enable) clk si siocon.3 data bus so m u x 1/2 8-bit p.s. irq4 8 8-bit sio shift buffer (siodata, f1h, bank 0) clk siocon.4 (edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) figure 16-3. sio functional block diagram
serial i/o interface s3c8248/c8245/p824 5/c8247/c8249/p8249 1 6- 4 serial i/o timing diagram so transmit complete irqs set siocon.3 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 si sck figure 16-4 . serial i/o timing in transmit/receive mode ( tx at falling, siocon.4 = 0) irqs do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck transmit complete si so set siocon.3 figure 16-5 . serial i/o timing in transmit/receive mode ( tx at rising, siocon.4 = 1)
s3c8248/c8245/p8245/c8247/c8249/p8249 v oltage booster 17- 1 17 voltage booster overview this voltage booster works for the power control of lcd : generates 3 v r (v lc2 ), 2 v r (v lc1 ), 1 v r (v lc0 ). this voltage booster allows low voltage operation of lcd display with high quality. this voltage booster circuit provides constant lcd contrast level even though battery power supply was lowered. this voltage booster include voltage regulator, and voltage charge/pump circuit. function description the voltage booster has built for driving the lcd. the voltage booster provides the capability of directly connecting an lcd panel to the mcu without having to separately generate and supply the higher voltages required by the lcd panel. the voltage booster operates on an internally generated and regulated lcd system voltage and generates a doubled and a tripled voltage levels to supply the lcd drive circuit. external capacitor are required to complete the power supply circuits. the v dd power line is regulated to get the v lc0 (v r ) level, which become a base level for voltage boosting. then a doubled and a tripled voltage will be made by capacitor charge and pump circuit.
voltage booster s3c 8248/c8245/p8245/c8247/c8249/p8249 17- 2 block diagram v dd clock lcon.0 lcon.2 voltage regulator v ss v lc0 (v r ) cab cab v lc1 (2 x v r ) v lc2 (3 x v r ) c0 c1 c2 lcon.1 figure 17-1. voltage booster block diagram lcd drive v lc1 v lc2 voltage booster v lc2 voltage regulator (1.05 v) v lc0 com0-3 seg0-seg31 ca cb cab c2 c1 v lc1 c0 v lc0 lcd drive v lc1 v lc2 voltage booster v lc2 voltage regulator (1.5 v) v lc0 com0-3 seg0-seg31 ca cb cab c1 c0 v lc0 v lc1 v lc0 v lc0 1/2 bias and static 1/3 bias figure 17-2. pin connection example
s3c8248/c8245/p8245/c8247/c8249/p8249 voltage level detec tor 18 - 1 18 voltage level detector overview the s3c8248/c8245/c8247/c8249 micro-controller has a built-in vld (voltage level detector) circuit which allows detection of power voltage drop or external input level through software. turning the vld operation on and off can be controlled by software. because the ic consumes a large amount of current during vld operation. it is recommended that the vl d operation should be kept off unless it is necessary. also the vld criteria voltage can be set by the software. the criteria voltage can be set by matching to one of the 4 kinds of voltage below that can be used. 2.2 v, 2.4 v, 3.0 v or 4.0 v (v dd reference voltage), or external input level (external reference voltage) the v ld block works only when v ldcon.2 is set. if v dd level is lower than the reference voltage selected with vldcon.1?.0, vldcon.3 will be set. if v dd level is higher, vldcon.3 will be cleared. when users need to minimize current consumption, do not operate the vld block. voltage level detector vldcon.3 vld out vldcon.4 mux vldcon.2 vld run voltage level setting p2conh.7-.6 extref/p2.7 extref input enable vldcon.1 vldcon.0 set the level v dd pin f vld figure 18-1. block diagram for voltage level detect
voltage level detector s3c8248/c8 245/p8245/c8247/c8249/p8249 18 - 2 voltage level detector control register (vldcon) the bit 2 of vldcon controls to run or disable the operation of voltage level detect. basically this v vld is set as 2.2 v by system reset and it can be changed in 4 kinds voltages by selecting voltage level detect control register (vldcon). when you write 2 bit data value to vldcon, an established resistor string is selected and the v vld is fixed in accordance with this resistor. table 18-1 shows specific v vld of 4 levels. voltage level detect control f6h, set 1, bank 1, r/w, reset : 00h .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not use + comparator m bandgap vld enable/disable vld out bias v ref v in r vld extref resistor string p2conh.7-.6 v bat notes: 1. the reset value of vldcon is #00h. 2. v ref is 1 volt. figure 18-2. voltage level detect circuit and control register table 18-1. vldcon value and detection level vldcon .1?.0 v vld 0 0 2.2 v 0 1 2.4 v 1 0 3.0 v 1 1 4.0 v
s3c8248/c8245/p8245/c8247/c8249/p8249 e lectrical data 19- 1 19 electrical data overview in this chapter, s3c8248/c8245/c8247/c8249 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? input/output capa citance ? d.c. electrical characteristics ? a.c. electrical characteristics ? oscillation characteristics ? oscillation stabilization time ? data retention supply voltage in stop mode ? serial i/o timing characteristics ? a/d converter electrical characteristics
electrical data s3c 8248/c8245/p8245/c8247/c8249/p8249 19- 2 table 19-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? 0.3 to +6.5 v input voltage v i ? 0.3 to v dd + 0.3 output voltage v o ? 0.3 to v dd + 0.3 output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 total pin current for port + 100 operating temperature t a ? 40 to + 85 c storage temperature t stg ? 65 to + 150 table 19-2. d.c. electrical characteristics (t a = -40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f cpu = 10 mhz 2.7 ? 5.5 v f cpu = 3 mhz 1.8 ? 5.5 input high voltage v ih1 all input pins except v ih2 0.8 v dd ? v dd v ih2 x in , xt in v dd -0.1 ? input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v il2 x in , xt in 0.1
s3c8248/c8245/p8245/c8247/c8249/p8249 e lectrical data 19- 3 table 19-2. d.c. electrical characteristics (continued) (t a = -40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit output high voltage v oh v dd = 5 v; i oh = -1 ma all output pins v dd ?1.0 ? ? v output low voltage v ol v dd = 5 v; i ol = 2 ma all output pins ? ? 0.4 input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 3 ua i lih2 v in = v dd, x in , xt in 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? -3 i lil2 v in = 0 v, x in , xt in , reset -20 output high leakage current i loh v out = v dd all i/o pins and output pins ? ? 3 output low leakage current i lol v out = 0 v all i/o pins and output pins ? ? -3 oscillator feed back resistors r osc1 v dd = 5.0 v t a = 25 c x in = v dd , x out = 0 v 800 1000 1200 k w pull-up resistor r l1 v in = 0 v; v dd = 5 v 10 % port 0,1,2,3,4,5 t a = 25 c 25 50 100 r l2 v in = 0 v; v dd = 5 v 10% t a =25 c, reset only 110 210 310 v lc0 out voltage (booster run mode) v lc0 t a = 25 c, (1/3 bias mode) 0.9 1.0 1.15 v t a = 25 c, (1/2 bias mode) 1.4 1.5 1.7 v lc1 out voltage (booster run mode) v lc1 t a = 25 c (1/2 and 1/3 bias mode) 2v lc0 - 0.1 ? 2v lc0 + 0.1 v lc2 out voltage (booster run mode) v lc2 t a = 25 c (1/3 bias mode) 3v lc0 - 0.1 ? 3v lc0 + 0.1 com output voltage deviation v dc v dd = v lc2 = 3 v (v lcd - comi) io = 15 m a ( i = 0-3) ? 60 120 mv seg output voltage deviation v ds v dd = v lc2 = 3 v (v lcd - segi) io = 15 m a ( i = 0-31) ? 60 120 note: low leakage current is absolute value.
electrical data s3c 8248/c8245/p8245/c8247/c8249/p8249 19- 4 table 19-2. d.c. electrical characteristics (concluded) (t a = -40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 (2) v dd = 5 v 10 % 10 mhz crystal oscillator ? 12 25 ma 3 mhz crystal oscillator 4 10 v dd = 3 v 10 % 10 mhz crystal oscillator 3 8 3 mhz crystal oscillator 1 5 i dd2 idle mode: v dd = 5 v 10 % 10 mhz crystal oscillator ? 3 10 3 mhz crystal oscillator 1.5 4 idle mode: v dd = 3 v 10 % 10 mhz crystal oscillator 1.2 3 3 mhz crystal oscillator 0.5 1.5 i dd3 sub operating: main- osc stop v dd = 3 v 10 % 32768 hz crystal oscillator osccon.4 = 1 ? 20 40 ua i dd4 sub idle mode: main- osc stop v dd = 3 v 10 % 32768 hz crystal oscillator osccon.4 = 1 ? 7 14 i dd5 main stop mode : sub- osc stop v dd = 5 v 10 % ? 1 3 v dd = 3 v 10 % 0.5 2 notes: 1. supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. i dd1 and i dd2 include a power consumption of subsystem oscillator. 3. i dd3 and i dd4 are the current when the main system clock oscillation stop and the subsystem clock is used. and does not include the lcd and voltage booster and voltage level detector 4. i dd5 is the current when the main and subsystem clock oscillation stop.
s3c8248/c8245/p8245/c8247/c8249/p8249 e lectrical data 19- 5 in case of s3c8248/c8245, the characteristic of v oh and v ol is differ with the characteristic of s3c8247/c8249 like as following. other characteristics are same each other. table 19-3. d.c electrical characteristics of s3c8248/c8245 (t a = -40 c to +85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit output high voltage v oh1 v dd = 5 v; i oh = -1 ma all output pins except v oh2 v dd -1.0 ? ? v v oh2 v dd = 5 v; i oh = -6 ma port 3.0 only in s3c8248/c8245 v dd -0.7 output low voltage v ol1 v dd = 5 v; i ol = 2 ma all output pins except v ol2 ? ? 0.4 v ol2 v dd = 5 v; i oh = 12 ma port 3.0 only in s3c8248/c8245 0.7
electrical data s3c 8248/c8245/p8245/c8247/c8249/p8249 19- 6 table 19-4. a.c. electrical characteristics (t a = -40 c to +85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width (p0.0?p0.7) tinth, tintl p0.0?p0.7, v dd = 5 v ? 200 ? ns reset input low width trsl v dd = 5 v 5 ? ? us note : user must keep more large value then min value. t tih t til 0.8 v dd 0.2 v dd 0.2 v dd figure 19-1. input timing for external interrupts (ports 0) t rsl 0.2 v dd reset figure 19-2. input timing for reset
s3c8248/c8245/p8245/c8247/c8249/p8249 e lectrical data 19- 7 table 19-5. input/output capacitance (t a = -40 c to +85 c, v dd = 0 v ) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 19-6. data retention supply voltage in stop mode (t a = -40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr 2 ? 5.5 v data retention supply current i dddr v dddr = 2 v ? ? 3 ua execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time normal operating mode data retention mode t wait reset v dd note: t wait is the same as 4096 x 16 x 1/fxx 0.2 v dd figure 19-3. stop mode release timing initiated by reset
electrical data s3c 8248/c8245/p8245/c8247/c8249/p8249 19- 8 execution of stop instruction ~ ~ v dddr ~ ~ stop mode idle mode data retention mode t wait v dd interrupt normal operating mode oscillation stabilization time 0.2 v dd note: t wait is the same as 16 x bt clock. figure 19-4. stop mode (main) release timing initiated by interrupts execution of stop instruction ~ ~ v dddr ~ ~ stop mode idle mode data retention mode t wait v dd interrupt normal operating mode oscillation stabilization time 0.2 v dd note: when the case of select the fxx/128 for basic timer input clock before enter the stop mode. twait = 128 x 16 x (1/32768) = 62.5 ms figure 19-5. stop mode (sub) release timing initiated by interrupts
s3c8248/c8245/p8245/c8247/c8249/p8249 e lectrical data 19- 9 table 19-7. a/d converter electrical characteristics (t a = - 40 c to +85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 10 ? bit total accuracy v dd = 5 v av ref = 5 v av ss = 0 v ? ? 3 lsb integral linearity error ile ? 2 differential linearity error dle ? 1 offset error of top eot 1 3 offset error of bottom eob 0.5 2 conversion time (1) t con ? ? 40 ? fxx analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss + 0.3 analog input current i adin av ref = v dd = 5 v ? ? 10 ua analog block current (2) i adc av ref = v dd = 5 v ? 1 3 ma av ref = v dd = 3 v 0.5 1.5 av ref = v dd = 5 v when power down mode 100 500 na notes : 1. 'conversion time' is the time required from the moment a conversion operation starts until it ends. 2. i adc is an operating current during a/d conversion.
electrical data s3c 8248/c8245/p8245/c8247/c8249/p8249 19- 10 table 19-8. voltage booster electrical characteristics (t a = 25 c, v dd = 2.0 v to 5.5 v, v ss = 0 v) parameter symbol test conditions min typ max unit operating voltage vdd 2.0 ? 5.5 v regulated voltage v lc0 i lc0 = 5 ua (1/3 bias) 0.9 1.0 1.15 booster voltage v lc1 connect 1 m w load between v ss and v lc1 2v lc0 - 0.1 ? 2v lc0 + 0.1 v lc2 connect 1 m w load between v ss and v lc2 3v lc0 - 0.1 ? 3v lc0 + 0.1 regulated voltage v lc0 i lc0 = 6 ua (1/2 bias) 1.4 1.5 1.7 booster voltage v lc1 connect 1 m w load between v ss and v lc1 2v lc0 - 0.1 ? 2v lc0 + 0.1 v lc2 connect 1 m w load between v ss and v lc2 table 19-9. characteristics of voltage level detect circuit (t a = 25 c) parameter symbol conditions min typ max unit operating voltage of vld v ddvld 1.8 ? 5.5 v voltage of vld v vld vldcon.1.0 = 00b 2.05 2.2 2.35 v vldcon.1.0 = 01b 2.25 2.4 2.55 vldcon.1.0 = 10b 2.8 3.0 3.2 vldcon.1.0 = 11b 3.7 4.0 4.3 hysteresys voltage of vld d v vlcdcon.1-.0=00 ? 10 100 mv sum of voltage booster, voltage detector and sub- idle current i vbvld i vb+ i vld+ i dd4, vdd=3.0v ? 15 40 ua
s3c8248/c8245/p8245/c8247/c8249/p8249 e lectrical data 19- 11 table 19-10. synchronous sio electrical characteristics (t a = -40 c to +85 c, v dd = 1.8 v to 5.5 v, v ss = 0 v, fxx = 10 mhz oscillator) parameter symbol conditions min typ max unit sck cycle time t cyc ? 200 ? ? ns serial clock high width t sckh ? 60 ? ? serial clock low width t sckl ? 60 ? ? serial output data delay time t od ? ? ? 50 serial input data setup time t id ? 40 ? ? serial input data hold time t ih ? 100 ? ? output data input data sck t sckh t cyc t sc kl 0.8 v dd 0.2 v dd t od t id t ih 0.8 v dd 0.2 v dd si so figure 19-6. serial data transfer timing
electrical data s3c 8248/c8245/p8245/c8247/c8249/p8249 19- 12 table 19-11. main oscillator frequency (f osc1 ) (t a = -40 c to +85 c, v dd = 1.8 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal x in c1 c2 x out crystal oscillation frequency 1 ? 10 mhz ceramic x in c1 c2 x out ceramic oscillation frequency 1 ? 10 mhz external clock x in x out x in input frequency 1 ? 10 mhz rc x in x out r v dd = 5 v 1 ? 2 mhz table 19-12. main oscillator clock stabilization time (t st1 ) (t a = -40 c to +85 c, v dd = 4.5 v to 5.5 v) oscillator test condition min typ max unit crystal v dd = 4.5 v to 5.5 v ? ? 10 ms ceramic stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms external clock x in input high and low level width (t xh , t xl ) 50 ? 500 ns note : oscillation stabilization time (t st1 ) is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is ended by a reset signal. the reset should therefore be held at low level until the t st1 time has elapsed
s3c8248/c8245/p8245/c8247/c8249/p8249 e lectrical data 19- 13 x in , xt in 1/fosc1, 1/fosc2 0.1v t xl , t xtl t xh , t xth v dd - 0.1v figure 19-7. clock timing measurement at x in table 19-13. sub oscillator frequency (f osc2 ) (t a = -40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal c1 c2 xt in xt out r crystal oscillation frequency c1 = 22 pf, c2 = 33 pf r = 39 k w 32 32.768 35 khz external clock xt in xt out xt in input frequency 32 ? 100 khz
electrical data s3c 8248/c8245/p8245/c8247/c8249/p8249 19- 14 table 19-14. sub oscillator(crystal) stabilization time (t st2 ) (t a = 25 c) oscillator test condition min typ max unit crystal normal mode v dd =4.5v to 5.5v ? 1 2 sec v dd =2.0v to 4.5v ? ? 10 sec crystal strong mode v dd =3.0v to 5.5v ? ? 6 sec v dd =2.0v to 3.0v ? ? 2 sec external clock v dd =2.0v to 5.5v xt in input high and low level width(t xth , t xtl ) 5 ? 15 usec note: oscillation stabilization time (t st2 ) is the time required for the oscillator to it?s normal oscillation when stop mode is released by interrupts. 10 mhz f cpu 3 mhz 1 mhz 1 2 3 4 5 6 7 supply voltage (v) minimum instruction clock = 1/4 x oscillator frequency 5.5 8 mhz 2.7 1.8 a b figure 19-8. operating voltage range
s3c8248/c8245/p8245/c8247/c8249/p8249 mechanical data 20 - 1 20 mechanical data overview the s3c8248/c8245/c8247/c8249 micr ocontroller is currently available in 80 -pin -qfp/tqfp package. 80-qfp-1420c #80 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 #1 0.80 0.35 + 0.10 note : dimensions are in millimeters. 0.15 max (0.80) 0.15 + 0.10 - 0.05 0-8 0.10 max 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.80 0.20 figure 20-1. package dimensions (80-qf p -1420c)
mechanical data s3c8248/c8245/p824 5/c8247/c8249/p8249 20 - 2 80-tqfp-1212 #80 12.00 bsc 14.00 bsc 12.00 bsc 14.00 bsc 0.09-0.20 0-7 note : dimensions are in millimeters. #1 (1.25) 0.50 0.60 0.15 0.05-0.15 1.00 0.05 1.20 max 0.17-0.27 0.08 max m figure 20-2. package dimensions (80-tqfp-1212)
s3c8248/c8245/p8245/c8247/c8249/p8249 s3 p8245/p8249 otp 21- 1 21 s3p8245/p8249 otp overview the s3p8245/p8249 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c8248/c8245/c8247/c8249 microcontroller. it has an on-chip otp rom instead of a masked rom. the eprom is accessed by serial data format. the s3p8245/p8249 is fully compatible with the s3c8248/c8245/c8247/c8249, both in function and in pin configuration. because of its simple programming requirements, the s3p8245/p8249 is ideal as an evaluation chip for the s3c8248/c8245/c8247/c8249.
s3p8245/p8249 otp s3 c8248/c8245/p8245/c8247/c8249/p8249 21- 2 seg25/p5.1 seg24/p5.0 seg23/p4.7 seg22/p4.6 seg21/p4.5 seg20/p4.4 seg19/p4.3 seg18/p4.2 seg17/p4.1 seg16/p4.0 seg15 seg14 seg13 seg12 seg11 seg10 p0.5/int5 p0.6/int6 p0.7/int7 p1.0/t1cap p1.1/t1clk p1.2//t1out/t1pwm p1.3 p1.4/buz p1.5/sio p1.6/sck p1.7/si p2.0/adc0 p2.1/adc1 p2.2/adc2 p2.3/adc3 p2.4/adc4 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com3 com2 com1 com0 vlc2 vlc1 vlc0 ca cb av ss av ref p2.7/adc7/v vldref p2.6/adc6 p2.5/adc5 sef26/p5.2 seg27/p5.3 seg28/p5.4 seg29/p5.5 seg30/p5.6 seg31/p5.7 p3.0/tbpwm p3.1/taout/tapwm p3.2/taclk p3.3/tacap/sdat p3.4/sclk v dd v ss x out x in v pp /test xt in xt out reset p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 p0.4/int4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 s3p8245/p8249 80-qfp (top view) note: the sequence of pins in tqfp package is identical with that in qfp package. figure 21-1. pin assignments (80-qfp)
s3c8248/c8245/p8245/c8247/c8249/p8249 s3 p8245/p8249 otp 21- 3 table 21-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.3 sdat 10 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p3.4 sclk 11 i serial clock pin. input only pin. v pp test 16 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 19 i chip initialization v dd /v ss v dd /v ss 12/13 ? logic power supply pin. v dd should be tied to +5 v during programming. table 21-2. comparison of s3p8245/p8249 and s3c8248/c8245/c8247/c8249 features characteristic s3p8245/p8249 s3c8248/c8245/c8247/c8249 program memory 16k/32k-byte eprom 16k/32k-byte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 80-qfp/80-tqfp 80-qfp/80-tqfp eprom programmability user program 1 time programmed at the factory
s3p8245/p8249 otp s3 c8248/c8245/p8245/c8247/c8249/p8249 21- 4 operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p8245/p8249, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 21-3 below. table 21-3. operating mode selection criteria v dd v pp (test) reg/ mem mem address(a15?a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level. table 21-4 . d.c electrical characteristics (t a = -40 c to +85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f cpu = 10 mhz 2.7 ? 5.5 v all input pins except v ih2, 3 1.8 ? 5.5 input high v ih1 port 4,5 v lcd2 3 v dd 0.8 v dd ? v dd voltage v ih2 x in , xt in 0.8 v dd ? v dd v ih3 all input pins except v il2 v dd - 0.1 ? v dd input low voltage v il1 x in , xt in ? ? 0.2 v dd v il2 v dd = 5 v; i oh = -1 ma all output pins 0.1 output high voltage v oh v dd = 5 v; i ol = 2 ma all output pins v dd -1.0 ? ? output low voltage v ol ? ? 0.4
s3c8248/c8245/p8245/c8247/c8249/p8249 s3 p8245/p8249 otp 21- 5 table 21-4. d.c. electrical characteristics (continued) (t a = -40 c to +85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 3 i lih2 v in = v dd x in , xt in 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? -3 i lil2 v in = 0 v x in , xt in , reset -20 ua output high leakage current i loh v out = v dd all i/o pins and output pins ? ? 3 output low leakage current i lol v out = 0 v all i/o pins and output pins ? ? -3 oscillator feed back resistors r osc1 v dd = 5.0 v t a = 25 c x in = v dd , x out = 0 v 800 1000 1200 k w pull-up resistor r l1 v in = 0 v; v dd = 5 v 10 % port 0,1,2,3,4,5 t a = 25 c 25 50 100 r l2 v in = 0 v; v dd = 5 v 10% t a =25 c, reset only 110 210 310 v lc0 out voltage (booster run mode) v lc0 t a = 25 c (1/3 bias mode) 0.9 1.0 1.15 v t a = 25 c (1/2 bias mode) 1.4 1.5 1.7 v lc1 out voltage (booster run mode) v lc1 t a = 25 c 2v lc0 - 0.1 ? 2v lc0 + 0.1 v lc2 out voltage (booster run mode) v lc2 t a = 25 c 3v lc0 - 0.1 ? 3v lc0 + 0.1 com output voltage deviation v dc v dd = v lc2 = 3 v (v lc - comi) io = 15 m a (1 = 0?3) ? 60 120 mv seg output voltage deviation v ds v dd = v lc2 = 3 v (v lc - comi) io = 15 m a (1 = 0?3) ? 60 120 note: low leakage current is absolute val ue.
s3p8245/p8249 otp s3 c8248/c8245/p8245/c8247/c8249/p8249 21- 6 table 21-4. d.c. electrical characteristics (concluded) (t a = -40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 (2) v dd = 5 v 10 % 10 mhz crystal oscillator ? 12 25 ma 3 mhz crystal oscillator 4 10 v dd = 3 v 10 % 10 mhz crystal oscillator 3 8 3 mhz crystal oscillator 1 5 i dd2 idle mode: v dd = 5 v 10 % 10 mhz crystal oscillator 3 10 3 mhz crystal oscillator 1.5 4 idle mode: v dd = 3 v 10 % 10 mhz crystal oscillator 1.2 3 3 mhz crystal oscillator 0.5 1.5 i dd3 sub operating: main- osc stop v dd = 3 v 10 % 32768 hz crystal oscillator osccon.4 = 1 ? 20 40 ua i dd4 sub idle mode: main- osc stop v dd = 3 v 10 % 32768 hz crystal oscillator osccon.4 = 1 ? 7 14 i dd5 main stop mode : sub- osc stop v dd = 5 v 10 % ? 1 3 v dd = 3 v 10 % 0.5 2 notes: 1. supply current does not include current drawn through internal p ull-up resistors or external output current loads. 2. i dd and i dd2 include a power consumption of subsystem oscillator. 3. i dd3 and i dd4 are the current when the main system clock oscillation stop and the subsystem clock is used. and does not include the lcd, voltage booster, and voltage level detector. 4. i dd5 is the current when the main and subsystem clock oscillation stop.
s3c8248/c8245/p8245/c8247/c8249/p8249 s3 p8245/p8249 otp 21- 7 case of s3p8245, the characteristic of v oh and v ol is differ with the characteristic of s3p8249 like as bellow. other characteristics are same each other. table 21-5. d.c electrical characteristics of s3c8248/c8245 (t a = -40 c to +85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit output high voltage v oh1 v dd = 5 v; i oh = -1 ma all output pins except v oh2 v dd -1.0 ? ? v v oh2 v dd = 5 v; i oh = -6 ma port 3.0 only in s3p8245 v dd -0.7 output low voltage v ol1 v dd = 5 v; i ol = 2 ma all output pins except v ol2 ? ? 0.4 v ol2 v dd = 5 v; i oh = 12 ma port 3.0 only in s3p8245 0.7 10 mhz f cpu 3 mhz 1 mhz 1 2 3 4 5 6 7 supply voltage (v) minimum instruction clock = 1/4 x oscillator frequency 5.5 8 mhz 2.7 1.8 a b figure 21-2. operating voltage range
s3p8245/p8249 otp s3 c8248/c8245/p8245/c8247/c8249/p8249 21- 8 notes
s3c8248/c8245/p8245/c8247/c8249/p8249 d evelopment tools 22- 1 22 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos , windows 95, and 98 as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, and openice for s3c7 , s3c9 , s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm88 the sasm88 is a relocatable assembler for samsung's s3c8 -series microcontrollers. the sasm88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm88 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value " ff " is filled into the unused rom area up to the maximum rom size of the target device automatically. target boards target boards are available for all s3c8 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board.
development tools s3c8248/c8245/p824 5/c8247/c8249/p8249 22- 2 bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb8249 target board eva chip target application system figure 22-1. smds product configuration (smds2+)
s3c8248/c8245/p8245/c8247/c8249/p8249 d evelopment tools 22- 3 tb8245/9 target board the tb8245/9 target board is used for the s3c8248/c8245/c8247/c8249 microcontroller. it is supported with the smds2+. tb8245/8249 sm1317a gnd v cc + idle + stop j101 50-pin connector 2 1 39 40 50-pin connector 42 41 79 80 100-pin connector 25 1 reset 7411 144 qfp s3e8240 eva chip j102 xi mds xtal to user_v cc off on device selection 8245 8249 figure 22-2 . tb8245/8249 target board configuration
development tools s3c8248/c8245/p824 5/c8247/c8249/p8249 22- 4 table 22-1. power selection settings for tb8245/9 " to user_vcc " s ettings operating mode comments to user_v cc off on target system smds2/smds2+ tb8245 tb8249 v cc v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2+ tb8245 tb8249 external v cc v ss v cc the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note: the following symbol in the " to user_vcc " setting column indicates the electrical short (off) configuration: table 22-2. main-clock selection settings for tb8245/9 sub clock settings operating mode comments x in xtal mds no connection smds2/smds2+ 100 pin connector eva chip s3e8240 x in x out set the xi switch to ?mds? when the target board is connected to the smds2/smds2+. x in xtal mds target board eva chip s3e8240 x in x out xtal set the xi switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+.
s3c8248/c8245/p8245/c8247/c8249/p8249 d evelopment tools 22- 5 table 22-3. device selection settings for tb8245/9 " to user_vcc " s ettings operating mode comments device selection 8245 8249 target system tb8249 operate with tb8249 device selection 8245 8249 target system tb8245 operate with tb8245 smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 22-4 . the smds2+ tool selection setting "sw1" setting operating mode smds2 smds2+ target system r/w r/w smds2+ idle led the yellow led is on when the evaluation chip ( s3e8240) is in idle mode. stop led the red led is on when the evaluation chip ( s3e8240 ) is in stop mode.
development tools s3c8248/c8245/p824 5/c8247/c8249/p8249 22- 6 j101 seg26/p5.2 seg28/p5.4 seg30/p5.6 p3.0/tbpwm p3.2/taclk p3.4/sclk v ss x in xt in reset p0.1/int1 p0.3/int3 p0.5/int5 p0.7/int7 p1.1/t1clk p1.3 p1.5/so p1.7/si p2.1/adc1 p2.3/adc3 seg27/p5.3 seg29/p5.5 seg31/p5.7 p3.1/taout/tapwm p3.3/tacap/sdat v dd x out test xt out p0.0/int0 p0.2/int2 p0.4/int4 p0.6/int6 p1.0/t1cap p1.2/t1out/t1pwm p1.4/buz p1.6/sck p2.0/adc0 p2.2/adc2 p2.4/adc4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 40-pin dip connector j102 p2.5/adc5 p2.7/adc7/v vldref av ss ca v lc1 com0 com2 seg0 seg2 seg4 seg6 seg8 seg10 seg12 seg14 seg16 seg18 seg20 seg22 seg24/p5.0 p2.6/adc6 av ref cb v lc0 v lc2 com1 com3 seg1 seg3 seg5 seg7 seg9 seg11 seg13 seg15 seg17 seg19 seg21 seg23 seg25/p5.1 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 40-pin dip connector figure 22-3 . 40 -pin connector s (j101, j102) for tb8245/8249 target board 40-pin dip connector target system j102 41 42 79 80 j101 1 2 39 40 target cable for 40-pin connector part name: as40d-a order code: sm6306 40-pin dip connectors 41 42 79 80 1 2 39 40 j102 j101 figure 22-4 . s3e8240 cables for 80 - qf p package
(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3c8 series mask rom order form product description: device number: s3c8__________- ___________(write down the rom code number) product order form: package pellet wafer package type: __________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantities: deliverable required delivery date quantity comments rom code ? not applicable see rom selection form customer sample risk order see risk order sheet please answer the following questions: + + for what kind of product will you be using this order? new product upgrade of an existing product replacement of an existing product other if you are replacing an existing product, please indicate the former product name ( ) + + what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation mask charge (us$ / won): ____________________________ customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3c8 series request for production at customer risk customer information: company name: ___________________________ _____________________________________ department: ________________________________________________________________ telephone number: __________________________ fax: _____________________________ date: __________________________ risk order information: device number: s3c8________- ________ (write down the rom code number) package: number of pins: ____________ package type: _____________________ intended application: ________________________________________________________________ product model number: ___ _____________________________________________________________ customer risk order agreement: we hereby request sec to produce the above named product in the quantity stated below. we believe our risk order product to be in full compliance with all sec production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. order quantity and delivery schedule: risk order quantity: _____________________ pcs delivery schedule: delivery date (s) quantity comments signatures: _______________________________ _________________________________ _____ _ (person placing the risk order) (sec sales representative)

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3c8248/c8245/c8247/c8249 mask option selection form device number: s3c8 _______-________(write down the rom code number) attachment (check one): diskette prom customer checksum: ________________________________________________________________ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ please answer the following questions: + + application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office a utomation remocon other please describe in detail its application

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3c8 series otp factory writing order form (1/2) product d escription: device number: s3p8________-________(write down the rom code number) product order form: package pellet w afer if the product order form is package: package type: _____________________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantity: rom code release date required delivery date of device quantity please answer the following questions: + + what is the purpose of this order ? new product development upgrade of an existing product replacement of an existing microcontroller other if you are replacing an existing microcontroller , please indicate the former microcontroller name ( ) + + what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation customer information: company name: ___________________ telephone number ___________ ______________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3p8245/p8249 otp factory writing order form (2/2) device number: s3p8 ________-__________ (write down the rom code number) customer checksums: _________ ____________________________ _________________________ _ company name: ________________________________________________________________ signature (engineer): _________________ _______________________________________________ read protection (1) : yes no please answer the following questions: + + are you going to continue ordering this device? yes no if so, how much will you be ordering? _________________ pcs + + application (product model id: _______________________) audio video telecom lcd databank caller i d lcd game industrials home appliance office a utomation remocon other please describe in detail its application ___________________________________________________________________________ notes 1. once you choose a read protection, you cannot read again the programming code from the eprom. 2. otp writing will be executed in our manufacturing site. 3. the writing program is completely verified by a customer. samsung does not take on any responsibility for errors occurred from the writing program.
book spine text samsung logo s3c8248/c8245/p8245/c8247/c8249/p8249 microcontroller s user's manual, rev. 3 march 2002

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