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universal clock chip for vi a?p4m/kt/km400 ddr systems cy28341-2 rev 1.0, november 21, 2006 page 1 of 18 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? supports via ? p4m/km/kt/266/333/400 chipsets ? supports pentium ? 4, athlon? processors ? supports two ddr dimms ? supports three sdram dimms at 100 mhz ? provides: ? two different programmable cpu clock pairs ? six differential sdram ddr pairs ? three low-skew/-jitter agp clocks ? seven low-skew/-jitter pci clocks ? one 48m output for usb ? one programmable 24m or 48m for sio ? dial-a-frequency ? and dial-a-db ? features ? spread spectrum for best electromagnetic interference (emi) reduction ? watchdog feature for system recovery ? smbus-compatible for programmability ? 56-pin ssop and tssop packages note: 1. pins marked with [*] have internal pull-up resistors. pins marked with [**] have internal pull-down resistors. table 1. frequency selection table fs(3:0) cpu agp pci 0000 66.80 66.80 33.40 0001 100.00 66.80 33.40 0010 120.00 60.00 30.00 0011 133.33 66.67 33.33 0100 72.00 72.00 36.00 0101 105.00 70.00 35.00 0110 160.00 64.00 32.00 0111 140.00 70.00 35.00 1000 77.00 77.00 38.50 1001 110.00 73.33 36.67 1010 180.00 60.00 30.00 1011 166.6 66.6 33.3 1100 90.00 60.00 30.00 1101 100.00 66.67 33.33 1110 200.00 66.67 33.33 1111 133.33 66.67 33.33 bl oc k di agram pin configuration [1] pll1 s2d convert smbus wd cpucs_t/c vddc vddi cpu(0:1)/cpu0d_t/c selp4_k7# pci(3:6) pci_f fs1 ref(0:1) vddr fs0 48m 24_48m fbout ddrt(0:5)/sdram(0,2,4,6,8,10) sclk sdata pd# agp(0:2) vddagp vdd48m vddd xtal xout xin fs2 pci2 pci1 vddpci pll2 sreset# / 2 buf_in ref0 fs3 multsel selsdr_ddr ddrc(0:5)/sdram(1,3,5,7,9,11) wden 56 pin ssop vssr *fs0/ref0 xin xout vddagp agp0 *selp4_k7/agp1 vssagp agp2 **selsdr_ddr/pci1 *multsel/pci2 vsspci pci3 pci4 vddpci pci5 pci6 vss48m **fs3/48m **fs2/24_48m vdd48m vdd vss iref *pd#/sreset# sclk sdata **fs1/pci_f vddr vttpwrgd#/ref1 vssc cput/cpuod_t cpuc/cpuod_c vddc vddi cpucs_t cpucs_c fbout buf_in ddrt0/sdram0 ddrc0/sdram1 ddrt1/sdram2 ddrc1/sdram3 vddd vssd ddrt2/sdram4 ddrc2/sdram5 ddrt3/sdram6 ddrc3/sdram7 vddd vssd ddrt4/sdram8 ddrc4/sdram9 ddrt5/sdram10 ddrc5/sdram11 vssi cy28341-2 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
cy28341-2 rev 1.0, november 21, 2006 page 2 of 18 pin description [2] pin number pin name pwr i/o pin description 3xin i oscillator buffer input . connect to a crystal or to an external clock. 4 xout vdd o oscillator buffer output . connect to a crystal. do not connect when an external clock is applied at xin. 1 fs0/ref0 vddr i/o pu power-on bidirectional input/output . at power-up, fs0 is the input. when the power supply voltage crosses the in put threshold voltage, fs0 state is latched and this pin becomes ref0, buffered copy of signal applied at xin. (1-2 x strength, selectable by smbus. default value is 1 x strength.) 56 vttpwrgd# vddr i if selp4_k7 = 1, with a p4 processor set up as cput/c . at power-up, vtt_pwrgd# is an input. when this input transitions to a logic low, the fs (3:0) and multsel are latched and all output clocks are enabled. after the first high to low transition on vtt_pwrgd#, this pin is ignored and will not effect the behavior of the device ther eafter. when the vtt_pwrgd# feature is not used, please connect this signal to ground through a 10k resistor. ref1 vddr o if selp4_k7 = 0, with an athlon (k7) processor as cpu_od(t:c) . vtt_pwrgd# function is disabled, and the feature is ignored. this pin becomes ref1 and is a buffered copy of the signal applied at xin. 44,42,38, 36,32,30 ddrt (0:5)/sdram (0,2,4,6,8,10) vddd o these pins are programmable th rough strapping pin11, selsdr_ddr# . if selsdr_ddr#.= 0, these pins are c onfigured for ddr clock outputs. they are ?true? copies of signal applied at pin45, buf_in. in this mode, vddd must be 2.5vif selsdr_ddr#.= 1, these pins are configured for sdram(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase with) signal applied at pin45, buf_in. in this mode, vddd must be 3.3v 43,41,37 35,31,29 ddrc (0:5)/sdram (1,3,5,7,9,11) vddd o these pins are programmable th rough strapping pin11, selsdr_ddr# . if selsdr_ddr#.= 0, these pins are co nfigured for ddr clock outputs. they are ?complementary? copies of signal ap plied at pin45, buf_in. in this mode, vddd must be 2.5vif selsdr_ddr#.= 1, these pins are configured for sdram(1,3,5,7,9,11) single ended clock outputs, copies of (and in phase with) signal applied at pin45, buf_in. in this mode, vddd must be 3.3v. 7 selp4_k7 / agp1 vddagp i/o pu power-on bidirectional input/output. at power-up, selp4_k7 is the input. when the power supply voltage crosse s the input threshold voltage, selp4_k7 state is latched and this pin becomes agp1 clock output. selp4_k7 = 1, p4 mode. selp4_k7 = 0, k7 mode. 12 multsel/pci2 vddpci i/o pu power-on bidirectional input/output . at power-up, multsel is the input. when the power supply voltage crosses the input threshold voltage, multsel state is latched and this pin becomes pc i2 clock output. multsel = 0, ioh is 4 x irefmultsel = 1, ioh is 6 x iref 53 cput/cpuod_t vddc o 3.3v cpu clock outputs . this pin is programmable through strapping pin7, selp4_k7. if selp4_k7 = 1, this pin is configured as the cput clock output. if selp4_k7 = 0, this pin is configur ed as the cpuod_t open drain clock output. see table 1 52 cpuc/cpuod_c vddc o 3.3v cpu clock outputs . this pin is programmable through strapping pin7, selp4_k7. if selp4_k7 = 1, this pin is configured as the cpuc clock output. if selp4_k7 = 0, this pin is confi gured as the cpuod_c open drain clock output. see table 1 48,49 cpucs_t/c vddi o 2.5v cpu clock outputs for chipset . see ta ble 1 . 14,15,17,18 pci (3:6) vddpci o pci clock outputs . are synchronous to cpu clocks. see table 1 10 fs1/pci_f vddpci i/o pd power-on bidirectional input/output . at power-up, fs0 is the input. when the power supply voltage crosses the in put threshold voltage, fs1 state is latched and this pin becomes pci_f clock output. 20 fs3/48m vdd48m i/o pd power-on bidirectional input/output . at power-up, fs3 is the input. when the power supply voltage crosses the in put threshold voltage, fs3 state is latched and this pin becomes 48m, a usb clock output. note: 2. pu = internal pull-up. pd = internal pull-down. typically = 250 k (range 200 k to 500 k ).
cy28341-2 rev 1.0, november 21, 2006 page 3 of 18 11 selsdr_ddr#/ pci1 vddpci i/o pd power-on bidirectional input/output . at power-up, selsdr_ddr is the input. when the power supply voltage cr osses the input threshold voltage, selsdr_ddr state is latched and this pin becomes pci clock output. selsdr_ddr#.= 0, ddr mode. selsdr_ddr#.= 1, sdr mode. 21 fs2/24_48m vdd48m i/o pd power-on bidirectional input/output . at power-up, fs2 is the input. when the power supply voltage crosses the in put threshold voltage, fs2 state is latched and this pin becomes 24_48m, a sio programmable clock output. 6 agp0 vddagp o agp clock output . is synchronous to cpu clocks. see table 1 8 agp2 vddagp o agp clock output . is synchronous to cpu clocks. see table 1 25 iref i current reference programm ing input for cpu buffers . a precise resistor is attached to this pin, which is conn ected to the internal current reference. 28 sdata i/o serial data input . conforms to the phillips i2c specification of a slave receive/transmit device. it is an input when receiving data. it is an open drain output when acknowledging or transmitting data. 27 sclk i serial clock input . conforms to the philips i2c specification. 26 pd#/sreset# i/o pu power-down input/system reset control output . if byte6 bit7 = 0(default), this pin becomes a sreset# open drain output. see system reset description. if byte6bit7 = 1, this pin becomes pd# input with an internal pull-up. when pd# is asserted low, the device enters power down mode. see power management function. 45 buf_in if selsdr_ddr#.= 0, 2.5v cmos type input to the ddr differential buffers . if selsdr_ddr#.= 1, 3.3v cmos type input to the sdr buffer. 46 fbout if selsdr_ddr#.= 0, 2.5v single en ded sdram buffered output of the signal applied at buf_in . it is in phase with the ddrt(0:5) signals.if selsdr_ddr#.= 1, 3.3v single ended sdram buffered output of the signal applied at buf_in. it is in phase with the sdram(0:11) signals 5 vddagp 3.3v power supply for agp clocks 51 vddc 3.3v power supply for cput/c clocks 16 vddpci 3.3v power supply for pci clocks 55 vddr 3.3v power supply for ref clock 50 vddi 2.5v power supply for cpucs_t/c clocks 22 vdd_48m 3.3v power supply for 48m 23 vdd 3.3v common power supply 34,40 vddd if selsdr_ddr#.= 0, 2.5v power supply for ddr clocksif selsdr_ddr#.= 1, 3.3v power supply for sdr clocks. 9 vssagp ground for agp clocks 13 vsspci ground for pci clocks 54 vssc ground for cput/c clocks 33,39 vssd ground for ddr clocks 19 vss_48m ground for 48m clock 47 vssi ground for icpucs_t/c clocks 2 vssr ground for ref 24 vss common ground pin description [2] (continued) pin number pin name pwr i/o pin description
cy28341-2 rev 1.0, november 21, 2006 page 4 of 18 power management functions all clocks can be individually enabled or stopped via the two-wire control interf ace. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stop and on transitions from stopped to running when the chip was not powered down. on power up, the vcos will stabilize to the correct pulse widths within about 0.5 ms. serial data interface to enhance the flexibility and functi on of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. the registers associated with the serial data interface initializes to their default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read oper ation from the controller. for block write/read operation, t he bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access i ndividual indexe d bytes. the offset of the indexed byte is encoded in the command code, as described in table 2 . the block write and block read protocol is outlined in table 3 while table 4 outlines the corresponding byte write and byte read protocol.the slave receiver address is 11010010 (d2h). table 2. command code definition bit description 7 0 = block read or block write operation. 1 = byte read or byte write operation (6:0) byte offset for byte r ead or byte write operation. for block read or block write operations, these bits should be ?0000000? table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8-bit ?00000000? stands for block operation 11:18 command code ? 8-bit ?00000000? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 0 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte n/slave acknowledge... 39:46 data byte from slave ? 8 bits .... data byte n ? 8 bits 47 acknowledge .... acknowledge from slave 48:55 data byte from slave ? 8 bits .... stop 56 acknowledge .... data bytes from slave/acknowledge .... data byte n from slave ? 8 bits .... not acknowledge .... stop
cy28341-2 rev 1.0, november 21, 2006 page 5 of 18 serial control registers table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8-bit ?1xxxxxxx? stands for byte operationbit[6:0] of the command code repre- sents the offset of th e byte to be accessed 11:18 command code ? 8-bit ?1xxxxxxx? stands for byte operationbit[6:0] of the command code repre- sents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 not acknowledge 39 stop byte 0: frequency select register bit @pup pin# name description 7 0 reserved reserved 6 h/w setting 21 fs2 for selecting frequencies in frequency selection table on page 1 5 h/w setting 10 fs1 for selecting frequencies in frequency selection table on page 1 4 h/w setting 1 fs0 for selecting frequencies in frequency selection table on page 1 3 0 if this bit is programmed to ?1?, it enables write to bits (6:4,1) for selecting the frequency via software (smbus) if this bit is programmed to a ?0? it enable only read of bits (6:4,1), which reflect the hardware setting of fs(0:3). 2 h/w setting 11 selsdr_ddr only for reading the ha rdware setting of the sdram interface mode, status of selsdr_ddr# strapping. 1 h/w setting 20 fs3 for selecting frequencies in frequency selection table on page 1 0 h/w setting 7 selp4_k7 only for reading the har dware setting of the cpu interface mode, status of selp4_k7# strapping. byte 1: cpu clocks register bit @pup pin# name description 7 0 mode 0 = down spread. 1 = center spread. see table 9 on page 9 6 1 sscg 1 = enable (default). 0 = disable 5 1 sst1 select spread bandwidth. see table 9 on page 9 4 1 sst0 select spread bandwidth. see table 9 on page 9 3 1 48,49 cpucs_t, cpucs_c 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 53,52 cput/cpuod_t cpuc/cpuod_c 1 = output enabled (running). 0 = output disable. 1 1 53,52 cput/c in k7 mode, this bit is ignored.in p4 mode, 0 = when pd# asserted low, cput stops in a high state, cpuc stops in a low state. in p4 mode, 1 = when pd# asserted low, cput and cpuc stop in high-z. 0 1 11 mult0 only for reading the hardware setting of the pin11 mult0 value.
cy28341-2 rev 1.0, november 21, 2006 page 6 of 18 byte 2: pci clock register bit @pup pin# name description 7 0 pci_drv pci clock output drive streng th 0 = low strength, 1 = high strength 6 1 10 pci_f 1 = output enabled (running). 0 = out put disabled asynchronously in a low state. 5 1 18 pci6 1 = output enabled (running). 0 = out put disabled asynchronously in a low state. 4 1 17 pci5 1 = output enabled (running). 0 = out put disabled asynchronously in a low state. 3 1 15 pci4 1 = output enabled (running). 0 = out put disabled asynchronously in a low state. 2 1 14 pci3 1 = output enabled (running). 0 = out put disabled asynchronously in a low state. 1 1 12 pci2 1 = output enabled (running). 0 = out put disabled asynchronously in a low state. 0 1 11 pci1 1 = output enabled (running). 0 = out put disabled asynchronously in a low state. byte 3 : agp/peripheral clocks register bit @pup pin# name description 70 21 24_48m 0 = pin21 output is 24 mhz. writing a '1' into this register asynchronously changes the frequency at pin21 to 48 mhz. 6 1 20 48mhz 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 5 1 21 24_48m 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 4 0 6,7,8 dasag1 programming these bits allow shifti ng skew of the agp(0:2) signals relative to their default value. see table 5 . 3 0 6,7,8 dasag0 2 1 8 agp2 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 1 7 agp1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 0 1 6 agp0 1 = output enabled (running). 0 = output disabled asynchronously in a low state. table 5. dial-a-skew ? agp(0:2) dasag (1:0) agp(0:2) skew shift 00 default 01 ?280 ps 10 +280 ps 11 +480 ps byte 4 : peripheral clocks register bit @pup pin# name description 7 1 20 48m 1 = low strength, 0 = high strength 1 = strength x 1. 0= strength x 2 6 1 21 24_48m 1 = low strength, 0 = high strength 1 = strength x 1. 0= strength x 2 5 0 6,7,8 darag1 programming these bits allow mo difying the frequency ratio of the agp(2:0), pci(6:1, f) clocks relative to the cpu clocks. see ta ble 6 . 4 0 6,7,8 darag0 3 1 1 ref0 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 56 ref1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 1 1 ref0 1 = low strength, 0 = high strength 0 1 56 ref1 1 = low strength, 0 = high strength (k7 mode only) table 6. dial-a-ratio ? agp(0:2) darag (1:0) cu/agp ratio 00 frequency selection default 01 2/1 10 2.5/1 11 3/1
cy28341-2 rev 1.0, november 21, 2006 page 7 of 18 byte 5 : sdr/ddr clock register bit @pup pin# name description 7 0 45 buf_in threshold voltage ddr mode, buf_in thres hold setting. 0 = 1.15v, 1 = 1.05vsdr mode, buf_in threshold setting. 0 = 1.35v, 1 = 1.25v 6 1 46 fbout 1 = output enabled (running). 0 = out put disabled asynchronously in a low state. 5 1 29,30 ddrt/c5/sdram(10,11) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 4 1 31,32 ddrt/c4/sdram(8,9) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 3 1 35,36 ddrt/c3/sdram(6,7) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 37,38 ddrt/c2/sdram(4,5) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 1 41,42 ddrt/c1/sdram(2,3) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 0 1 43,44 ddrt/c0/sdram(0,1) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. byte 6: watchdog register bit @pup pin# name description 7 0 26 sreset# 1 = pin 26 is the input pin as pd# signal. 0 = pin 26 is the output pin as sreset# signal. 6 0 frequency revert this bit allows setting the re vert frequency once the system is rebooted due to watchdog time out only.0 = selects frequency of existing h/w setting1 = selects frequency of the second to last s/w setting. (the software setting prior to the one that caused a system reboot). 5 0 wdtest for imi test - wd-test, always program to '0' 4 0 wd alarm this bit is set to ?1? when the watchdog times out. it is reset to ?0? when the system clears the wd time stamps (wd3:0). 3 0 wd3 this bit allows the selection of the time stamp for the watchdog timer. see table 7 2 0 wd2 this bit allows the selection of the time stamp for the watchdog timer. see table 7 1 0 wd1 this bit allows the selection of the time stamp for the watchdog timer. see table 7 0 0 wd0 this bit allows the selection of the time stamp for the watchdog timer. see table 7 table 7. watchdog time stamp wd3 wd2 wd1 wd0 function 00 0 0off 0 0 0 1 1 second 0 0 1 0 2 seconds 0 0 1 1 3 seconds 0 1 0 0 4 seconds 0 1 0 1 5 seconds 0 1 1 0 6 seconds 0 1 1 1 7 seconds 1 0 0 0 8 seconds 1 0 0 1 9 seconds 1 0 1 0 10 seconds 1 0 1 1 11 seconds 1 1 0 0 12 seconds 1 1 0 1 13 seconds 1 1 1 0 14 seconds 1 1 1 1 15 seconds byte 7: dial-a-frequency control register n bit @pup pin# name description
cy28341-2 rev 1.0, november 21, 2006 page 8 of 18 dial-a-frequency feature smbus dial-a-frequency feature is available in this device via byte7 and byte9. p is a pll constant that depe nds on the frequency selection prior to accessing the dial-a-frequency feature. 7 0 reserved reserved for device function test. 6 0 n6, msb these bits are for programming the pll?s internal n register. this access allows the user to modify the cpu frequency at very high resolution (accuracy). all other synchronous clocks (clocks that are generated from the same pll, such as pci) remain at their existing ratios relative to the cpu clock. 50 n5 40 n4 30 n3 20 n2 10 n3 00 n0, lsb byte 7: dial-a-frequency control register n byte 8: silicon signature register (all bits are read-only) bit @pup pin# name description 7 0 revision_id3 revision id bit [3] 6 0 revision_id2 revision id bit [2] 5 0 revision_id1 revision id bit [1] 4 1 revision_id0 revision id bit [0] 3 1 vendor_id3 cypress's vendor id bit [3]. 2 0 vendor_id2 cypress's vendor id bit [2]. 1 0 vendor_id1 cypress's vendor id bit [1]. 0 0 vendor_id0 cypress's vendor id bit [0]. byte9: dial-a-frequency control register r bit @pup pin# name description 70 reserved 6 0 r5, msb these bits are for programming the pll?s internal r register. this access allows the user to modify the cpu frequency at very high resolution (accuracy). all other synchronous cl ocks (clocks that are generated from the same pll, such as pci) remain at their existing ratios relative to the cpu clock. 50 r4 40 r3 30 r2 20 r1 10 r0 00 daf_enb r and n register mux selection. 0 = r and n values come from the rom. 1 = data is load from daf (smbus) registers. table 8. fs(4:0) p xxxxx 96016000
cy28341-2 rev 1.0, november 21, 2006 page 9 of 18 spread spectrum clock generation (sscg) spread spectrum is enabled/disabled via smbus register byte 1, bit 7. system self recovery clock management this feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in ca se of a hang up due to the frequency change. when the system sends an smbus command requesting a frequency change through byte 4 or through bytes 13 and 14, it must have previously sent a command to byte 12, for selecting which time out stamp the watchdog must perform, otherwise the system self reco very feature will not be appli- cable. consequently, this device will change frequency and then the watchdog timer starts timing. meanwhile, the system bios is running its operation with the new frequency. if this device receives a new smbus command to clear the bits origi- nally programmed in byte 12, bits (3:0) (reprogram to 0000), before the watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. if the watchdog times out the first time before the new smbus reprograms byte 12, bits (3:0) to (0000), then this device will send a low system reset pulse, on sreset# (see byte12, bit7), and changes wd alarm (byte12, bit4) status to ?1? then restarts the watchdog timer again. if the watchdog times out a second time, then this device will send another low pulse on sreset#, will relatch original hardware strapping frequency (or second to last so ftware selected frequency, see byte12, bit6) selection, set wd alarm bit (byte12, bit4) to ?1,? then start wd timer again. the above-described sequence will keep repeating until the bios clears the smbus byte12 bits (3:0). once the bios sets byte 12 bits (3:0) = 0000, then the watchdog timer is turned off and the wd alarm bit (byte 12, bit4) is reset to ?0.? table 9. spread spectrum table mode sst1 sst0 % spread 0 0 0 +0.14, ?1.23 0 0 1 +0, ?1.00 0 1 0 +0, ?0.60 0 1 1 +0, ?0.52 1 0 0 +0.72, ?0.71 1 0 1 +0.47, ?0.49 1 1 0 +0.34, ?0.33 1 1 1 +0.30, ?0.28 swing select functions through hardware multsel board target trace/term z reference r, iref = vdd/(3*rr) output current voh@z 0 50 ohm rr = 221 1%, iref = 5.00 ma ioh = 4* iref 1.0v@50 1 50 ohm rr = 475 1%, iref = 2.32 ma ioh = 6* iref 0.7v@50
cy28341-2 rev 1.0, november 21, 2006 page 10 of 18 p4 processor selp4_k7# = 1 power-down assertion (p4 mode) when pd# is sampled low by two consecutive rising edges of cpu# clock then all clock out puts except cpu clocks must be held low on their next high to low transition. cpu clocks must be held with the cpu clock pin driven high with a value of 2 x iref, and cpu# undriven. note that figure 1 shows cpu = 133 mhz. this diagram and description are applicable for all valid cpu frequencies 66, 100, 133, 200 mhz. due to the state of internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. power-down deassertion (p4 mode) the power-up latency needs to less than 3 ms. s ystem running with originally selected frequency via hardw are strapping. r eceive frequency c hange r equest via smbus byte 4 or via dial- a-frequency? s tart internal w atch dog tim er. w atch d og tim e out? turn off w atch dog tim er. k eep new frequency setting. s et w d alarm bit (byte 12, bit4) to ''0' 1) s end another 3m s low pulse on s r e s et 2) r elatch original hardware strapping selection for return to original frequency settings. 3) s et w d a larm bit (byte 12, b it4) to "1" 4 ) s ta rt w d tim e r frequency w ill change but s ystem s elf r ecovery not applicable (no tim e stam p selected and byte 12, bit(3:0) is still = "0000" no no yes no no yes s m b us byte 12 tim e out stam p disabled? is smbus byte 9, tim e out stam p enabled - (byte 12, bit (3:0) 0000)? c hange to a new frequency yes 1) send sr e se t pulse 2) set w d bit (byte12, bit4) to '1' 3 ) s ta rt w d tim e r yes w atch d og tim e out? no yes sm bus byte 9 tim e out stam p disabled, b yte 12, bit(3:0) = (0000)? yes no figure 1. watchdog recovery clock pci 33mhz pw rdw n# cput 133mhz cput# 133mhz ref 14.318mhz usb 48mhz sdram 133mhz ddrt 133mhz ddrc 133mhz agp 66mhz figure 2. power-down assertion timing waveform (in p4 mode)
cy28341-2 rev 1.0, november 21, 2006 page 11 of 18 amd k7 processor selp4_k7# = 0 power-down assertion (k7 mode) when the pd# signal is asserted low, all clocks are disabled to a low level in an orderly fashion prior to removing power from the part. when pd# is asserted (forced) low, the device transitions to a shutdown (power-down) mode and all power supplies may then be removed. when pd# is sampled low by two consecutive rising edges of cpu clock, then all affected clocks are stopped in a low state as soon as possible. when in power-down (and before power is removed), all outputs are synchronously stopped in a low state (see figure 3 below), all pll?s are shut off, and the crystal oscillator is disabled. when the device is shut down, the i 2 c function is also disabled. pci 33mhz pw rdw n# cpu 133mhz cpu# 133mhz agp 66mhz ref 14.318mhz usb 48mhz <1.5 m sec sdram 133mhz ddrt 133mhz ddrc 133mhz figure 3. power-down deassertion timing waveform (in p4 mode) pci 33mhz pwrdwn# ref 14.318mhz usb 48mhz sdram 133mhz ddrt 133mhz ddrc 133mhz agp 66mhz cpuod_c 133mhz cpucs_c 133mhz cpuod_t 133mhz cpucs_t 133mhz figure 4. power-down assertion timing waveform (in k7 mode)
cy28341-2 rev 1.0, november 21, 2006 page 12 of 18 power-down deassertion (k7 mode) when deasserted pd# to high level, all clocks are enabled and start running on the rising edge of the next full period in order to guarantee a glitch-fre e operation, no partial clock pulses. note: 3. this time diagram shows that vtt_pwrgd# transits to a logic lo w in the first time at power-up. after the first high-to-low tr ansition of vtt_pwrgd#, device is not affected, vtt_pwrgd# is ignored. pci 33mhz pw rdw n# cpu 133mhz cpu# 133mhz agp 66mhz ref 14.318mhz usb 48mhz <1.5 m sec sdram 133mhz ddrt 133mhz ddrc 133mhz fi g ure 5. power-down deassertion timin g waveform ( in k7 mode ) vid (0:3), sel (0,1) vtt_pwrgd# pwrgd vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_gd# sample sels off off on on state 1 (note a) figure 6. vtt_pwgd# timing diagram (w ith advanced piii processor selp4_k7 = 1 ) [3]
cy28341-2 rev 1.0, november 21, 2006 page 13 of 18 connection circuit ddrt/c signals for open-drain cpu output signals (with k7 processor selp4_k7#=0) for differential cpu output signals (with p4 processor selp4_k7= 1) the following diagram shows lumped test load configurations for the differential host clock outputs. vt t pw r g d # = l o w delay 0.25ms s1 power off s0 vdda = 2.0v sample inputs fs(3:0) s2 vdd3.3 = off normal operation s3 wait for 1.146m s enable outputes figure 7. clock generator power-up/run st ate diagram (with p4 processor selp4_k7#=1 ) figure 8. k7 load termination measurement point measurement point 20 pf 20 pf 680 pf 680 pf 47 ohm 47 ohm 150 ohm 52 ohm 5" cpuod_t cpuod_c vddcpu(1.5v) 500 ohm vddcpu(1.5v) 500 ohm 60.4 ohm 60.4 ohm 301 ohm 500 ohm 500 ohm 52 ohm 1 " 52 ohm 1" 3.3v 3.3v 52 ohm 5" 150 ohm vddcpu(1.5v) vddcpu(1.5v) 6? 6? figure 9. cs load termination table 10.signal loading table clock name max load (in pf) ref (0:1), 48mhz (usb), 24_48mhz 20 agp(0:2), sdram (0:11) 30 pci_f(0:5) 30 ddrt/c (0:5), fbout cput/c see figure 10 cpuod_t/c see figure 8 cpucs_t/c see figure 9
cy28341-2 rev 1.0, november 21, 2006 page 14 of 18 note: 4. ideally the probes should be placed on th e pins. if there is a transmission line between the test point and the pin for one s ignal of the pair (e.g., cpu), the same length transmission line should be added to the other signal of the pair (e.g., agp). table 11.lumped test load configuration component 0.7v amplitude value 1.0v amplitude value r ta1 , r ta2 33 0 r la1 , r la2 49.9 ? t pcb 3? 50 z 3? 50 z r lb1 , r lb2 63 r d 470 r tb1 , r tb2 0 33 c la , c lb 2 pf 2 pf r ref 475 w/mult0 = 1 221 w/mult0 = 0 group timing relationships and tolerances [4] offset (ps) tolerance (ps) conditions t csagp cpucs to agp 750 500 cpucs leads t ap agp to pci 1,250 500 agp leads clk measurement point r ref r ta1 cput multsel clk measurement point r la1 r d r lb1 r la2 r lb2 r ta2 r tb1 r tb2 c la c lb t pcb t pcb cput# figure 10. p4 load termination 0ns 10ns 20ns 30ns agp clock 66.6mhz pci clock 33.3mhz cpu clock 66.6mhz cpu clock 100mhz cpu clock 133.3mhz t ap t csagp
cy28341-2 rev 1.0, november 21, 2006 page 15 of 18 maximum ratings [5] input voltage relative to v ss :...............................v ss ? 0.3v input voltage relative to v ddq or av dd : ............. v dd + 0.3v storage temperature: ................................ ?65 c to + 150 c operating temperature:.................................... 0 c to +70 c maximum esd............................................................. 2000v maximum power supply: ................................................ 5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field. however, precautions should be take to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc parameters ( v dd = v ddpci = v ddagp = v ddr = v dd48m = v ddc = 3.3v5%, v ddi = v dd = 2.55%, ta = 0c to +70c) parameter description conditions min. typ. max. unit v il1 input low voltage applicable to pd#, f s(0:4) 0.8 vdc v ih1 input high voltage 2.0 vdc v il2 input low voltage applicable to sdata and sclk 1.0 vdc v ih2 input high voltage 2.2 vdc v ol output low voltage for sreset# i ol 0.4 v i ol pull-down current for sreset# v ol = 0.4v 24 35 ma i oz three-state leakage current 10 a i dd3.3v dynamic supply current cpu frequency set at 133.3 mhz, note 6 150 190 ma i dd2.5v dynamic supply current cpu frequency set at 133.3 mhz, note 6 175 195 ma i pd power-down supply current pd# = 0 95 600 a i pup internal pull-up device current input @ v ss ?25 a i pdwn internal pull-down device current input @ v dd 10 a c in input pin capacitance 5pf c out output pin capacitance 6pf l pin pin inductance 7pf c xtal crystal pin capacitance measured from the xin or xout to v ss 27 36 45 pf ac parameters parameter description 100 mhz 133 mhz 200 mhz unit notes min. max. min. max min. max. xtal t dc xin duty cycle 45 55 45554555%7,14 t period xin period 69.84 71.00 69.84 71.0 69.84 71.0 ns 7,14 v high xin high voltage 0.7v dd v dd 0.7v dd v dd 0.7v dd v dd v12 v low xin low voltage 0 .3v dd 0.3v dd 0.3v dd v15 t r /t f xin rise and fall times 10.0 10 10 ns 13 t ccj xin cycle to cycle jitter 500 500 500 ps 8,11 t xs crystal start-up time 30 30 30 ms 10,12 p4 mode cpu at 0.7v t dc cput/c duty cycle 45 55 45 55 45 55 % 7,8,9,15,16 t period cput/c period 9.85 10.2 7.35 7.65 4.85 5.1 ns 7,8,9,15,16 notes: 5. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 6. all outputs loaded as per maximum capacitive load table. 7. this parameter is measured as an average over a 1-us duration, with a crystal center frequency of 14.31818 mhz. 8. all outputs loaded as per loading specified in the table 11 . 9. probes are placed on the pins, and measurem ents are acquired at 1.5v for 3.3v signals and at 1.25v for 2.5v, and 50% point fo r differential signals. 10. probes are placed on the pins, and measurements are acquired at 0.4v. 11. when xin is driven from and external clock source (3.3v parameters apply). 12. when crystal meets minimum 40-ohm dev ice series resistance specification. 13. measured between 0.2v dd and.7v dd . 14. this is required for the duty cycle on the ref clock out to be as specified. the device will operate reliably with input dut y cycles up to 30/70 but the ref clock duty cycle will not be within data sheet specifications. 15. measured at vx, or where subt raction of clk-clk# crosses 0v. 16. see figure 10 for 0.7v loading specification.
cy28341-2 rev 1.0, november 21, 2006 page 16 of 18 t r /t f cput/c rise and fall times 175 700 175 700 175 700 ps 24 rise/fall matching 20% 20% 20% 24,26 t r /t f rise/fall time variation 125 125 125 ps 8,24,16 t skew cpucs_t/c to cput/c clock skew 0 200 0 150 0 200 ps 8,18,15,16 t ccj cput/c cycle to cycle jitter ?150 +150 ?150 +150 ?200 +200 ps 8,18,15,16 v cross crossing point voltage at 0.7v swing 280 430 280 430 280 430 mv 16 p4 mode cpu at 1.0v t dc cput/c duty cycle 45 55 45 55 45 55 % 8,9,15 t period cput/c period 9.85 10.2 7.35 7.65 4.85 5.1 ns 8,9,15 differential t r /t f cput/c rise and fall times 175 467 175 467 175 467 ps 7,14,27 t skew cpucs_t/c to cput/c clock skew 0 200 0 150 0 200 0 8,14,11 t ccj cput/c cycle to cycle jitter ?150 +150 ?150 +150 ?200 +200 ps 8,14,11 v cross crossing point voltage at 1v swing 510 760 510 760 510 760 mv 27 se-deltaslew absolute single-ended rise/fall waveform symmetry 325 325 325 ps 26 k7 mode t dc cpuod_t/c duty cycle 45 55 45 55 45 55 % 8,9 t period cpuod_t/c period 9.98 10.5 7.5 8.0 5 5.5 ns 8,9 t low cpuod_t/c low time 2.8 1.67 2.8 ns 8,9 t f cpuod_t/c fall time 0.4 1 .6 0.4 1.6 0.4 1.6 ns 8,13 t skew cpucs_t/c to cput/c clock skew 0 200 0 150 0 200 0 8,14,11 t ccj cpuod_t/c cycle-to-cycle jitter ?150 +150 ?150 +150 ?200 +200 ps 8,9 v d differential voltage ac 0.4 vp+0.6v 0.4 vp+0.6v 0.4 vp+.06v v 23 v x differential crossover voltage 500 1100 500 1100 500 1100 mv 23 chipset clock t dc cpucs_t/c duty cycle 45 55 45 55 45 55 % 7,8,9 t period cpucs_t/c period 10.0 10.5 15 15.5 10.0 10.5 ns 7,8,9 t r / t f cpucs_t/c rise and fall times 0.4 1.6 0.4 1.6 0.4 1.6 ns 7,8,13 v d differential voltage ac 0.4 vp+.06v 0.4 vp+.06v .4 vp+.06v v 24 v x differential crossover voltage 0.5*v dd i ?0.2 0.5*v dd i +0.2 0.5*v d d i?0.2 0.5*v dd i +0.2 0.5*v d d i?0.2 0.5*v dd i +0.2 v11 agp t dc agp(0:2) duty cycle 45 55 45 55 45 55 % 7,8,9 t period agp(0:2) period 15 16 15 16 15 16 ns 7,8,9 t high agp(0:2) high time 5.25 5.25 5.25 ns 8,21 t low agp(0:2) low time 5.05 5.05 5.05 ns 8,10 t r / t f agp(0:2) rise and fall times 0.4 1.6 0.4 1.6 0.4 1.6 ns 8,13 notes: 17. probes are placed on the pins, and measur ements are acquired between 0.4v and 2.4v for 3.3v signals and between 0.4v and 2.0 v for 2.5v signals, and between 20% and 80% for differential signals. 18. this measurement is applicable with spread on or spread off. 19. probes are placed on the pins, and meas urements are acquired at 2.4v for 3.3v signals and at 2.0v for 2.5v signals). 20. time specified is measured from when all vdds reach their respective supply rail (3.3v and 2.5v) till frequency output is st able and operating within specs. 21. the typical value of vx is expected to be 0.5*v ddd (or 0.5*v ddc for cpucs signals) and will track the vari ations in the dc level of the same. 22. vd is the magnitude of the difference between the measured voltage level on a ddrt (and cpucs_t) clock and the measured volt age level on its complementary ddrc (and cpucs_c) one. 23. measured at vx between the rising edge and the following falling edge of the signal. 24. measured from v ol = 0.175v to v oh = 0.525v. 25. measurement taken from differential waveform, from ?0.35v to +0.35v. 26. measurements taken from common mode waveforms, measure rise/fall time from 0.41v to 0.86v. rise/fall time matching is define d as ?the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (r ise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time?. this parameter is designed for waveform symmetry. 27. measured in absolute voltage, i.e., single-ended measurement. ac parameters (continued) parameter description 100 mhz 133 mhz 200 mhz unit notes min. max. min. max min. max.
cy28341-2 rev 1.0, november 21, 2006 page 17 of 18 t skew any agp to any agp clock skew 250 250 250 ps 8,14 t ccj agp(0:2) cycle-to-cycle jitter 500 500 500 ps 8,9,14 pci t dc pci(_f,1:6) duty cycle 45 55 45 55 45 55 % 7,8,9 t period pci(_f,1:6) period 30.0 30.0 30.0 ns 7,8,9 t high pci(_f,1:6) high time 12.0 12.0 12.0 ns 8,21 t low pci(_f,1:6) low time 12.0 12.0 12.0 ns 8,10 t r / t f pci(_f,1:6) rise and fall times 0.5 2.5 0.5 2.5 0.5 2.5 ns 8,13 t skew any pci to any pci clock skew 500 500 500 ps 8,14 t ccj pci(_f,1:6) cycle-to-cycle jitter 500 500 500 ps 8,9,14 48 mhz t dc 48-mhz duty cycle 45 55 45 55 45 55 % 7,8,9 t period 48-mhz period 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 7,8,9 t r / t f 48-mhz rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 ns 8,13 t ccj 48-mhz cycle-to-cycle jitter 500 500 500 ps 8,9,14 24 mhz t dc 24-mhz duty cycle 45 55 45 55 45 55 % 7,8,9 t period 24-mhz period 41.660 41.667 41.660 41.667 41.660 41.667 ns 7,8,9 t r / t f 24-mhz rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 ns 8,13 t ccj 24-mhz cycle-to-cycle jitter 500 500 500 ps 8,9,14 ref t dc ref duty cycle 45 55 45554555%7,8,9 t period ref period 69.8413 71.0 69.8413 71.0 69.8413 71.0 ns 7,8,9 t r / t f ref rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 ns 8,13 t ccj ref cycle-to-cycle jitter 1000 1000 1000 ps 8,9,14 ddr v x crossing point voltage of ddrt/c 0.5*v ddd ?0.2 0.5*v ddd +0.2 0.5*v dd d ?0.2 0.5*v dd d +0.2 0.5*v dd d ?0.2 0.5*v dd d +0.2 v15 v d differential voltage swing 0.7 vddd + 0.6 0.7 vddd + 0.6 0.7 vddd + 0.6 v23 t dc ddrt/c(0:5) duty cycle 45 55 45 55 45 55 % 11 t period ddrt/c(0:5) period 9.85 10.2 14.85 15.3 9.85 10.2 ns 11 t r / t f ddrt/c(0:5) rise/fall slew rate 1 3 1 3 1 3 v/ns 13 t skew ddrt/c to any ddrt/c clock skew 100 100 100 ps 8,14,11 t ccj ddrt/c(0:5) cycle-to-cycle jitter 75 75 75 ps 8,14,11 t hpj ddrt/c(0:5) half-period jitter 100 100 100 ps 8,14,11 t delay buf_in to any ddrt/c delay 1 4 1 4 1 4 ns 8,9 t skew fbout to any ddrt/c skew 100 100 100 ps 8,9 t stable all-clock stabilization from power-up 3 3 3 ms 22 ac parameters (continued) parameter description 100 mhz 133 mhz 200 mhz unit notes min. max. min. max min. max. ordering information part number package type product flow cy28341oc?2 56-pin shrunk small outline package (ssop) commercial, 0 to 70 c cy28341oc?2t 56-pin shrunk small outline pa ckage (ssop)?tape and reel commercial, 0 to 70 c cy28341zc?2 56-pin thin shrunk small outline package (tssop) commercial, 0 to 70 c cy28341zc?2t 56-pin thin shrunk small outline package (tssop)?tape and reel commercial, 0 to 70 c lead-free cy28341oxc?2 56-pin shrunk small outline package (ssop) commercial, 0 to 70 c cy28341oxc?2t 56-pin shrunk small outline package (ssop)?tape and reel commercial, 0 to 70 c
rev 1.0, november 21, 2006 page 18 of 18 cy28341-2 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions seating plane 1 bsc 0-8 max. gauge plane 28 29 56 1.100[0.043] 0.051[0.002] 0.851[0.033] 0.508[0.020] 0.249[0.009] 7.950[0.313] 0.25[0.010] 6.198[0.244] 13.894[0.547] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] 14.097[0.555] 0.152[0.006] 0.762[0.030] dimensions in mm[inches] min. max. 0.170[0.006] 0.279[0.011] 0.20[0.008] 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.42gms part # z5624 standard pkg. zz5624 lead free pkg. 56-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z56 56-leadshrunksmalloutlinepackageo56

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