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1 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms pin symbol pin symbol pin symbol pin symbol 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 dnu 86 dq32 128 cke0 3 dq1 45 s2# 87 dq33 12? nc (s3#) 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v dd 48 d n u 90 v dd 132 nc ( a13 ) 7 dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n c 92 dq37 134 n c 9 dq6 51 n c 93 dq38 135 n c 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n c 103 dq46 145 n c 20 dq15 62 n c 104 dq47 146 n c 21 cb0 63 nc (cke1) 105 cb4 147 nc 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n c 66 dq22 108 n c 150 dq54 25 n c 67 dq23 109 n c 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we# 69 dq24 111 cas# 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0# 72 dq27 114 nc (s1#) 156 dq59 31 d n u 73 v dd 115 ras# 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 nc (ck3) 38 a10 80 n c 122 ba0 164 n c 39 ba1 81 nc/wp** 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 nc (ck1) 167 sa2 42 ck0 84 v dd 126 a12 168 v dd **-13e/-133/-10e version only pin assignment (front view) synchronous dram module mt5lsdt472a, mt5lsdt872a, mt5lsdt1672a for the latest data sheet, please refer to the micron web site: www.micronsemi.com/datasheets/datasheet.html features ? pc66-*, pc100- and pc133-compliant jedec-standard 168-pin, dual in-line memory module (dimm) utilizes 100 mhz*, 125 mhz, and 133 mhz sdram components unbuffered 32mb (4 meg x 72), 64mb (8 meg x 72), 128mb (16 meg x 72) single +3.3v 0.3v power supply fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal sdram banks for hiding row access/ precharge programmable burst lengths: 1, 2, 4, 8 or full page auto precharge, includes concurrent auto precharge, and auto refresh modes self refresh mode 64ms, 4,096-cycle refresh lvttl-compatible inputs and outputs serial presence-detect (spd) options marking package 168-pin dimm (gold) g frequency/cas latency 133 mhz/cl = 2 (7.5ns, 133 mhz sdram) -13e 133 mhz/cl = 3 (7.5ns, 133 mhz sdrams) -133 100 mhz/cl = 2 (8ns, 125 mhz sdrams) -10e 66 mhz/cl = 2 (10ns, 100 mhz sdrams) -662* *32mb only 168-pin dimm micron is a registered trademark of micron technology, inc. note: pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only. key sdram component timing parameters module speed cas access setup hold marking grade latency time times times -13e -7e 2 5.4ns 1.5ns 0.8ns -133 -75 3 5.4ns 1.5ns 0.8ns -10e -8e 2 6ns 2ns 1ns -662 -10 2 9ns 3ns 1ns
2 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms general description the mt5lsdt472a, mt5lsdt872a and mt5lsdt1672a are high-speed cmos, dynamic random-access, 32mb, 64mb and 128mb memories organized in a x72 configuration. these modules use internally configured quad-bank sdrams with a syn- chronous interface (all signals are registered on the positive edge of the clock signals ck0, ck2). read and write accesses to the sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registra- tion of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank, a0-a11 select the row). the address bits registered coincident with the read or write com- mand are used to select the starting column location for the burst access. these modules provide for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. these modules use an internal pipelined architec- ture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access opera- tion. these modules are designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram opera- tion, refer to the 64mb, 128mb, or 256mb: x4, x8, x16 sdram data sheets. serial presence-detect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048- bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organization and timing parameters. the remaining 128 bytes of storage are available for use by the cus- tomer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/eeprom addresses. part numbers part number configuration system bus speed mt5lsdt472ag-13e _ 4 meg x 72 133mhz mt5lsdt472ag-133 _ 4 meg x 72 133 mhz mt5lsdt472ag-10e _ 4 meg x 72 100 mhz mt5lsdt472ag-662 _ 4 meg x 72 66 mhz mt5lsdt872ag-13e _ 8 meg x 72 133 mhz mt5lsdt872ag-133 _ 8 meg x 72 133 mhz mt5lsdt872ag-10e _ 8 meg x 72 100 mhz mt5lsdt1672ag-13e _ 16 meg x 72 133 mhz mt5lsdt1672ag-133 _ 16 meg x 72 100 mhz mt5lsdt1672ag-10e 16 meg x 72 133 mhz note : all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt5lsdt472ag-10e b6.
3 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms functional block diagram mt5lsdt472a (32mb)/mt5lsdt872a (64mb)/mt5lsdt1672a (128mb) note: 1. all resistor values are 10 ohms. u1-u5 = mt48lc4m16a2tg sdrams for 32mb u1-u5 = mt48lc8m16a2tg sdrams for 64mb u1-u5 = mt48lc16m16a2tg sdrams for 128mb dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmh u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s2# ras# cas# cke0 we# ras#: sdrams u0-u4 cas#: sdrams u0-u4 cke: sdrams u0-u4 we#: sdrams u0-u4 a0-a11: sdrams u0-u4 ba0-1: sdrams u0-u4 a0-a11 ba0-1 v dd v ss sdrams u0-u4 sdrams u0-u4 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb1 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmh u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dqmb1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb5 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb3 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmh u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb7 s0# 10pf ck1, ck3 ck0 10pf a0 sa0 spd u6 sda a1 sa1 a2 sa2 wp scl 47k u0 u1 u3 ck2 15pf u2 u4 dqmh u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs#
4 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms pin descriptions pin numbers symbol type description 27, 111, 115 we#, cas#, input command inputs: we#, cas# and ras# (along with ras# s0#, s2#) define the command being entered. 42, 79 ck0, ck2 input clock: ck0, ck2 are driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and controls the output registers. 128 cke0 input clock enable: cke0 activates (high) and deactivates (low) the ck0, ck2 signals. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power- down (row active in any bank), or clock suspend operation (burst access in progress). cke0 is synchro- nous except after the device enters power-down and self refresh modes, where cke0 becomes asynchro- nous until after exiting the same mode. the input buffers, including ck0, ck2, are disabled during power-down and self refresh modes, providing low standby power. 30, 45 s0#, s2# input chip select: s0# and s2# en able (registered low) and disable (registered high) the command decoder. all commands are masked when s0# and s2# are registered high. s0# and s2# are considered part of the command code. 28-29, 46-47, dqmb0-dqmb7 input input/output mask: dqmb is an input mask signal 112-113, 130-131 for write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dqmb is sampled high during a read cycle. 39, 122 ba1, ba0 input bank address: ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. 33, 117, 34, 118, 35, 119, a0-a12 input address inputs: a0-a12 are sampled during the 36, 120, 37, 121, 38, 123, active command (row-address a0-a11/a12) and 126 read/write command (column-address a0-a7/a8 with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. 81 wp input write protect: serial presence-detect hardware write protect. applies to -13e/-133/-10e versions only. 83 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module.
5 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms pin descriptions (continued) pin numbers symbol type description 165-167 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 2-5, 7-11, 13-17, 19-20, dq0-dq63 input/ data i/os: data bus. 55-58, 60, 65-67, 69-72, output 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 21, 22, 52, 53, 105, 106, cb0-cb7 input/ check bits. 136, 137 output 82 sda input/ serial presence-detect data: sda is a bidirectional output pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 6, 18, 26, 40, 41, 49, 59, v dd supply power supply: +3.3v 0.3v. 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, v ss supply ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 31, 44, 48 dnu ? do not use: these pins are not connected on this module but are assigned pins on the compatible dram version.
6 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms figure 1 data validity scl sda data stable data stable data change scl sda start bit stop bit figure 2 definition of start and stop scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 3 acknowledge response from receiver spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (fig- ures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop con- dition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an ac- knowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the spd device will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
7 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? serial presence-detect matrix byte description entry (version) mt5lsdt472a mt5lsdt872a mt5lsdt1672a 0 number of bytes used by micron 128 80 80 80 1 total number of spd memory bytes 256 08 08 08 2 memory type sdram 04 04 04 3 number of row addresses 12 or 13 0c 0c 0d 4 number of column addresses 8 or 9 08 09 09 5 number of banks 1 01 01 01 6 module data width 72 48 48 48 7 module data width (continued) 0 00 00 00 8 module voltage interface levels lvttl 01 01 01 9 sdram cycle time, t ck 7 (-13e) 70 70 70 (cas latency = 3) 7.5 (-133) 75 75 75 8 (-10e) 80 80 80 10 (-662) a0 a0 a0 10 sdram access from clock, t ac 5.4 (-13e/-133) 54 54 54 (cas latency = 3) 6 (-10e) 60 60 60 7.5 (-662) 75 75 75 11 module configuration type ecc 02 02 02 12 refresh rate/type 15.6s/self 80 80 80 13 sdram width (primary sdram) 16 10 10 10 14 error-checking sdram data width 16 10 10 10 15 minimum clock delay, t ccd 1 01 01 01 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 8f 17 number of banks on sdram device 4 04 04 04 18 cas latencies supported 2, 3 06 06 06 19 cs latency 0 01 01 01 20 we latency 0 01 01 01 21 sdram module attributes unbuffered 00 00 00 22 sdram device attributes: general 0e 0e 0e 0e 23 sdram cycle time, t ck 7.5 (-13e) 75 75 75 (cas latency = 2) 10 (-133/-10e) a0 a0 a0 15 (-662) f0 f0 f0 24 sdram access from ck, t ac 5.4 (-13e) 54 54 54 (cas latency = 2) 6 (-133/-10e) 60 60 60 9 (-662) 90 90 90 25 sdram cycle time, t ck ? 00 00 00 (cas latency = 1) 26 sdram access from ck, t ac ? 00 00 00 (cas latency = 1) 27 minimum row precharge time, t rp 15 (-13e) 0f 0f 0f 20 (-133/-10e) 14 14 14 30 (-662) 1e 1e 1e 28 minimum row active to row active, 14 (-13e) 0e 0e 0e t rrd 15 (-133) 0f 0f 0f 20 (-10e/-662) 14 14 14 29 minimum ras# to cas# delay, t rcd 15 (-13e) 0f 0f 0f 20 (-133/-10e) 14 14 14 30 (-662) 1e 1e 1e
8 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. x = variable data. serial presence-detect matrix (continued) byte description entry (version) mt5lsdt472a mt5lsdt872a mt5lsdt1672a 30 minimum ras# pulse width, t ras 37 (-13e) 25 25 25 44 (-133) 2c 2c 2c 50 (-10e) 32 32 32 60 (-662) 3c 3c 3c 31 module bank density 32mb, 64mb, or 128mb 08 09 10 32 command and address setup time 1.5 (-13e/-133) 15 15 15 2 (-10e/-662) 20 20 20 33 command and address hold time 0.8 (-13e/-133) 08 08 08 1 (-10e/-662) 10 10 10 34 data signal input setup time 1.5 (-13e/-133) 15 15 15 2 (-10e/-662) 20 20 20 35 data signal input hold time 0.8 (-13e/-133) 08 08 08 1 (-10e/-662) 10 10 10 36-61 reserved 00 00 00 62 spd revision 1.2 12 12 12 63 checksum for bytes 0-62 -13e 68 6a 72 -133 b6 b8 c0 -10e fe 00 08 -662 d1 d3 db 64 manufacturer ? s jedec id code mi cron 2c 2c 2c 65-71 manufacturer ? s jedec id code ff ff ff (continued) 72 manufacturing location 01 01 01 02 02 02 03 03 03 04 04 04 05 05 05 06 06 06 07 07 07 08 08 08 09 09 09 73-90 module part number (ascii) xxx 91 pcb identification code 1 01 01 01 2 020202 3 030303 4 040404 5 050505 6 060606 7 070707 8 080808 9 090909 92 identification code (continued) 0 00 00 00 93 year of manufacture in bcd xxx 94 week of manufacture in bcd xxx 95-98 module serial number xxx 99-125 manufacturer-specific (rsvd) ??? 126 system frequency 100 mhz (-13e/-133/-10e) 64 64 64 66 mhz (-662) 66 66 66 127 sdram component and clock af af af detail
9 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms commands truth table 1 provides a general reference of avail- able commands. for a more detailed description of truth table 1 ? commands and dqmb operation (note: 1) name (function) cs# ras# cas# we# dqmb addr dqs notes command inhibit (nop) h xxxx x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) l h l h l/h 8 bank/col x 4 write (select bank and column, and start write burst) l h l l l/h 8 bank/col valid 4 burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or l l l h x x x 6, 7 self refresh (enter self refresh mode) load mode register l l l l x op-code x 2 write enable/output enable ???? l ? active 8 write inhibit/output high-z ???? h ? high-z 8 note: 1. cke is high for all commands shown except self refresh. 2. a0-a11/a12 define the op-code written to the mode register. 3. a0-a11/a12 provide row address, and ba0, ba1 determine which bank is made active. 4. a0-a7/a8 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine which bank is being precharged. a10 high: all banks are precharged and ba0, ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). commands and operations, refer to the 64mb, 128mb, or 256mb: x4, x8, x16 sdram data sheet.
10 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a7/a8 cn, cn + 1, cn + 2 page cn + 3, cn + 4... not supported (y) (location 0-y) ? cn - 1, cn ? figure 4 mode register definition note: 1. for full-page accesses: y = 256 (32mb); y = 512 (64mb/128mb). 2. for a burst length of two, a1-a7/a8 select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-a7/a8 select the block-of-four burst; a0-a1 select the starting column within the block. 4. for a burst length of eight, a3-a7/a8 select the block-of-eight burst; a0-a2 select the starting column within the block. 5. for a full-page burst, the full row is selected, and a0-a7/a8 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a7/a8 select the unique column to be accessed, and mode register bit m3 is ignored. m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 a11 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m12, m11, m10 = ? 0, 0, 0 ? to ensure compatibility with future devices. a12 12 unused
11 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms absolute maximum ratings* voltage on v dd supply relative to v ss .. -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss ................................. -1v to +4.6v operating temperature, t a (ambient) .. 0c to +70c storage temperature (plastic) ........... -55c to +125c power dissipation ................................................... 5w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1, 2) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 3 input low voltage: logic 0; all inputs v il -0.5 0.8 v 3 input leakage current: dqmb0, dqmb2-dqmb7 i i 1 -5 5 a any input 0v v in v dd ck2, s2#, dqmb1 i i 2 -10 10 a (all other pins not under test = 0v) ck0, s0# i i 3 -15 15 a cke0, ras#, cas#, a0-a11, i i 4 -25 25 a ba0-ba1, we# output leakage current: dq0-dq63, cb0-cb7 i oz -5 5 a dqs are disabled; 0v v out v dd output levels: v oh 2.4 ? v output high voltage (i out = -4ma) output low voltage (i out = 4ma) v ol ? 0.4 v note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. v ih overshoot: v ih (max) = v dd + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate.
12 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms i dd specifications and conditions (notes: 1-4) (v dd = +3.3v 0.3v) parameter/condition symbol size -13e -133 -10e -662 units notes operating current: active mode; burst = 2; i dd 1 32mb 625 575 475 450 ma 5, 6, read or write; t rc = t rc (min); cas latency = 3 64mb 800 750 700 n/a 7, 8 128mb tbd tbd tbd n/a standby current: power-down mode; i dd 2 32mb 10 10 10 15 ma 8 cke = low; all banks idle 64mb 10 10 10 n/a 128mb 10 10 10 n/a standby current: active mode; s0#, s2# = high; i dd 3 32mb 225 225 175 150 ma 5, 7, cke = high; all banks active after t rcd met; 64mb 250 250 200 n/a 8, 9 no accesses in progress 128mb 275 250 200 n/a operating current: burst mode; i dd 4 32mb 750 700 600 525 ma 5, 6, continuous burst; read or write; all banks active; 64mb 825 750 700 n/a 7, 8 cas latency = 3 128mb tbd tbd tbd n/a auto refresh current: t rc = t rc (min); i dd 5 32mb 1,150 1,050 950 850 ma cke = high; s0#, s2# = high cl = 3 64mb 1,650 1,550 1,350 n/a 5, 6, 128mb tbd tbd tbd n/a 7, 8, t rc = 15.625s; i dd 6 32mb 15 15 15 15 ma 9, 10 cl = 3 64mb 15 15 15 n/a 128mb 20 20 20 n/a self refresh current: cke 0.2v i dd 7 32mb 5 5 5 10 ma 11 64mb 10 10 10 n/a 128mb tbd 20 20 n/a max note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1 ns, then the timing is referenced at v il (max) and v il (min) and no longer at the isv crossover point. 4. i dd specifications are tested after the device is properly initialized. 5. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 6. the i dd current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 7. address transitions average one transition every two clocks. 8. t ck = 7ns for -13e; t ck = 7.5ns for -133; t ck = 10ns for -10e; t ck = 15ns for -662. 9. other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid v ih or v il levels. 10. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 11. enables on-chip refresh and address counters.
13 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms capacitance parameter symbol min max units input capacitance: a0-a11, ba0, ba1, ras#, cas#, we#, cke0 c i 1 15 26 p f input capacitance: ck2, s2#, dqmb1 c i 2 610pf input capacitance: ck0, s0# c i 3 915pf input capacitance: dqmb0#, dqmb2#-dqmb7# c i 4 47pf input capacitance: scl, sa0-sa2 c i 5 ? 6pf input/output capacitance: dq0-dq63, cb0-cb7, sda c io 69pf note: this parameter is sampled. v dd = +3.3v; f = 1 mhz, t a = 25 c; pin under test biased at 1.4v.
14 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms sdram component* ac electrical characteristics (notes: 1-5) ac characteristics -13e (pc133) -133 (pc133) -10e (pc100) -662 (pc66) parameter symbol min max min max min max min max units notes access time from ck (pos. edge) cl = 3 t ac 5.4 5.4 6 7.5 ns cl = 2 t ac 5.4 6 6 9 ns address hold time t ah 0.8 0.8 1 1 ns address setup time t as 1.5 1.5 2 2 ns ck high-level width t ch 2.5 2.5 3 3 ns ck low-level width t cl 2.5 2.5 3 3 ns clock cycle time cl = 3 t ck 7 7.5 8 10 ns 24 cl = 2 t ck 7.5 10 10 15 ns 24 cke hold time t ckh 0.8 0.8 1 1 ns cke setup time t cks 1.5 1.5 2 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 2 2 ns data-in hold time t dh 0.8 0.8 1 1 ns data-in setup time t ds 1.5 1.5 2 2 ns data-out high-impedance time cl = 3 t hz 5.4 5.4 6 8 ns 10 cl = 2 t hz 5.4 6 7 10 ns 10 data-out low-impedance time t lz 1 1 1 2 ns data-out hold time (load) t oh 2.7 2.7 3 3 ns data-out hold time (no load) t oh n 1.8 1.8 1.8 n/a ns 29 active to precharge command t ras 37 120,000 44 120,000 50 120,000 60 120,000 ns active to active command period t rc 60 66 70 90 ns active to read or write delay t rcd 15 20 20 30 ns refresh period (4,096 cycles) t ref 64 64 64 64 ms auto refresh period t rfc 66 66 70 90 ns precharge command period t rp 15 20 20 30 ns active bank a to active bank b command t rrd 14 15 20 20 ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 1 1.2 ns 7 write recovery time t wr 1 ck + 1 ck + 1 ck + 1 ck + ? 25 7ns 7.5ns 7ns 7ns 14 15 15 15 ns 26 exit self refresh to active command t xsr 67 75 80 90 ns 20 *specifications for the sdram components used on the module. note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a +70 c) is ensured. 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. outputs measured at 1.5v with equivalent load: 5. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1 ns, then the timing is referenced at v il (max) and v il (min) and no longer at the isv crossover point. q 50pf
15 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms notes: (continued) 6. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 7. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 8. parameter guaranteed by design. 9. ac characteristics assume t t = 1ns. 10. auto precharge mode only. the precharge timing budget ( t rp) begins 7ns/7.5ns/7ns after the first clock delay, after the last write is executed. 11. precharge mode only. 12. clk must be toggled a minimum of two times during this period.
16 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms ac functional characteristics (notes:1-6) parameter symbol -133 -13e/-10e -662 units notes read/write command to read/write command t ccd 1 1 1 t ck 7 cke to clock disable or power-down entry mode t cked 1 1 1 t ck 8 cke to clock enable or power-down exit setup mode t ped 1 1 1 t ck 8 dqm to input data delay t dqd000 t ck 7 dqm to data mask during writes t dqm 0 0 0 t ck 7 dqm to data high-impedance during reads t dqz 2 2 2 t ck 7 write command to input data delay t dwd 0 0 0 t ck 7 data-in to active command t dal 5 4 4 t ck 9, 11 data-in to precharge command t dpl 2 2 2 t ck 10, 11 last data-in to burst stop command t bdl111 t ck 7 last data-in to new read/write command t cdl111 t ck 7 last data-in to precharge command t rdl222 t ck 10, 11 load mode register command to active or refresh command t mrd 2 2 2 t ck 12 data-out to high-impedance from precharge command cl = 3 t roh 3 3 3 t ck 7 cl = 2 t roh 2 2 2 t ck 7 note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a 70 c) is ensured. 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. ac characteristics assume t t = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 5. outputs measured at 1.5v with equivalent load: 6. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1 ns, then the timing is referenced at v il (max) and v il (min) and no longer at the isv crossover point. 7. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 8. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 9. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 10. timing actually specified by t wr. 11. based on t ck = 133 mhz for -13e/-133, 100 mhz for -10e and 66 mhz for -662. 12. jedec and pc100 specify three clocks. q 50pf
17 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms serial presence-detect eeprom ac operating conditions (note: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 s start condition hold time t hd:sta 4 s clock high period t high 4 s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 2 serial presence-detect eeprom dc operating conditions (note : 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ? 0.4 v input leakage current: v in = gnd to v dd i li ? 10 a output leakage current: v out = gnd to v dd i lo ? 10 a standby current: i sb ? 30 a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i dd ? 2ma scl clock frequency = 100 khz note: 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd = +3.3v; f = 1 mhz, t a = 25 c; pin under test biased at 1.4v.
18 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined serial presence-detect eeprom timing parameters symbol min max units t aa 0.3 3.5 s t buf 4.7 s t dh 300 ns t f 300 ns t hd:dat 0 s t hd:sta 4 s spd eeprom symbol min max units t high 4 s t low 4.7 s t r1s t su:dat 250 ns t su:sta 4.7 s t su:sto 4.7 s
19 4, 8, 16 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm25_1.p65 ? rev. 5/00 ?2000, micron technology, inc. 4, 8, 16 meg x 72 sdram dimms 168-pin dimm pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) .250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 1.005 (25.53) 0.995 (25.27) 5.256 (133.50) 5.244 (133.20) .125 (3.18) max .054 (1.37) .046 (1.17) note: all dimensions in inches (millimeters) max or typical where noted. min 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micronsemi.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.
micron memory dram module reference guide densit y description pins components on module part number speed hei g ht samples prod. 4mb ss 1 me g x 32 gold simm/tin sim m 72 (2) 1 me g x 16 mt2d132g/m (x) 50,60 .800" now now 4mb ss 1 me g x 32 3.3v gold sodimm 72 (2) 1 me g x 16 3.3v tsop mt2ldt132hg (x) 60 1.000" now now 4mb ss 1 me g x 32 3.3v gold dimm 100 (2) 1 me g x 16 3.3v tsop mt2ld132ug (x) 60 1.000" now now 8mb ds 2 me g x 32 gold simm/tin sim m 72 (4) 1 me g x 16 mt4d232dg/m (x) 50,60 .800" now now 8mb ss 2 me g x 32 3.3v gold sodimm 72 (4) 1 me g x 16 3.3v tsop mt4ldt232hg (x) 60 1.000" now now 8mb ss 2 me g x 32 3.3v gold dimm 100 (4) 1 me g x 16 3.3v mt4ld232ug (x) 60 1.000" now now 8mb ss 1 me g x 64 3.3v gold sodimm 144 (4) 1 me g x 16 3.3v tsop mt4ldt164hg (x) 60 1.000" now now 8mb ds 1 me g x 64 3.3v gold dimm 168 (4) 1 me g x 16 3.3v tsop mt4ldt164ag (x) 60 1.000" now now 16mb ss 4 me g x 32 gold simm/tin sim m 72 (8) 4 me g x 4 mt8d432g/m (x) 50, 60 1.000" now now 16mb ss 4 me g x 36 ecc gold simm/tin sim m 72 (9) 4 me g x 4 mt9d436g/m (x) 50, 60 1.000" now now 16mb ds 4 me g x 32 3.3v gold sodimm 72 (8) 4 me g x 4 3.3v tsop mt8ldt432hg (x) 60 1.000" now now 16mb ss 4 me g x 32 3.3v gold sodimm 72 (2) 4 me g x 16 3.3v tsop mt2ldt432hg (x) 60 1.000" now now 16mb ss 4 me g x 32 3.3v gold dimm 100 (2) 4 me g x 16 3.3v tsop mt2ldt432ug (x) 60 1.000" now now 32mb ds 8 me g x 32 gold simm/tin sim m 72 (16) 4 me g x 4 mt16d832g/m (x) 50, 60 1.000" now now 32mb ds 8 me g x 36 ecc gold simm/tin sim m 72 (18) 4 me g x 4 mt18d836g/m (x) 50, 60 1.000" now now 32mb ds 8 me g x 32 3.3v gold sodimm 72 (4) 4 me g x 16 3.3v tsop mt4ldt832hg (x) 60 1.000" now now 32mb ds 8 me g x 32 3.3v gold dimm 100 (4) 4 me g x 16 3.3v tsop mt4ldt832ug (x) 60 1.000" now now 32mb ds 4 me g x 64 3.3v gold sodimm 144 (4) 4 me g x 16 3.3v tsop mt4ldt464hg (x)(s) 50,60 1.000" now now 32mb ss 4 me g x 64 3.3v gold dimm 168 (4) 4 me g x 16 3.3v tsop mt4ldt464ag (x) 50,60 1.000" now now 32mb ds 4 me g x 64 3.3v gold dimm 168 (16) 4 me g x 4 3.3v mt16ld464ag (x) 60 1.000" now now 32mb ds 4 me g x 72 3.3v ecc gold dimm 168 (18) 4 me g x 4 3.3v mt18ld472(a)g (x) 60 unbuff = 1.000", buff = 1.000" now now 32mb ss 4 me g x 72 3.3v ecc gold dimm 168 (5) 4 me g x 16 3.3v tsop mt5ldt472(a)g (x) 60 unbuff = 1.000", buff = 1.050" now now 64mb ds 8 me g x 64 3.3v gold sodimm 144 (8) 8 me g x 8 3.3v tsop mt8ldt864hg (x)(s) 60 1.050" now now 64mb ds 8 me g x 64 3.3v gold dimm 168 (32) 4 me g x 4 3.3v mt32ld864ag (x) 60 1.500" now now 64mb ss 8 me g x 64 3.3v gold dimm 168 (8) 8 me g x 8 3.3v mt8ld864ag (x) 50, 60 1.100" now now 64mb ds 8 me g x 72 3.3v ecc gold dimm 168 (36) 4 me g x 4 3.3v mt36ld872(a)g (x) 60 unbuff = 1.500", buff = 1.500" now now 64mb ss 8 me g x 72 3.3v ecc gold dimm 168 (9) 8 me g x 8 3.3v mt9ld872(a)g (x) 50, 60 unbuff = 1.100", buff = 1.250" now now 64mb ss 8 me g x 72 3.3v ecc gold dimm 168 (9) 8 me g x 8 3.3v tsop mt9ldt872g (x) 50, 60 1.350" now now 128mb ds 16 me g x 64 3.3v gold dimm 168 (16) 16 me g x 4 3.3v mt16ld1664ag (x) 50,60 1.250" now now 128mb ds 16 me g x 72 3.3v ecc gold dimm 168 (18) 16 me g x 4 3.3v mt18ld1672(a)g (x) 50,60 unbuff = 1.250", buff = 1.100" now now 128mb ds 16 me g x 72 3.3v ecc gold dimm 168 (18) 16 me g x 4 3.3v tsop mt18ldt1672g (x) 50,60 2.000" now now 256mb ds 32 me g x 72 3.3v ecc gold dimm 168 (36) 16 me g x 4 3.3v mt36ld3272g (x) 50, 60 2.000" now now 256mb ds 32 me g x 72 3.3v ecc gold dimm 168 (36) 16 me g x 4 3.3v tsop mt36ldt3272g (x) 50, 60 2.000" now now rev. 3/26/01 ss - single sided ds - double sided g - gold plated m - tin plated u - 100-pin dimm (h) - small-outline dimm (sodimm) (x) - edo; no "x" denotes fpm version (a) - 8-cas; spd version; unbuffered (no "a" denotes buffered version for x72 dimms) (s) - self refresh micron technology, inc. reserves the right to change products or specifications without notice. availability
micron memory sdram module reference guide availability density description pins components on module base part number speed die rev. pcb (height) mhz* samples production notes 4mb ss 1 meg x 32 3.3v gold dimm 100 (2) 1 meg x 1 6 3.3v tsop mt2lsdt132ug -10e1 e = y72g 1 = 6649 (1.000") 100 now now -8e1 125 now now ss 1 meg x 32 aimm (2) 1 meg x 1 6 3.3v tsop mt2lsdt132ag p -6e2 e = y72g 2 = 0164b (1.4") 133 now now aimm ss 1 meg x 32 aimm (1) 2 meg x 32 3.3v tsop mt1lsdt132ag p -6e1 e = y84w 1 = 0178 (1.4") 133 now now aimm 8mb ds 2 meg x 32 3.3v gold dimm 100 (4) 1 meg x 1 6 3.3v tsop mt4lsdt232udg -10e1 e = y72g 1 = 6649 (1.000") 100 now now -8e1 125 now now 16mb ss 4 meg x 32 3.3v gold dimm 100 (2) 4 meg x 1 6 3.3v tsop mt2lsdt432ug -10c1 c = y84 1 = 6660 (1.000") 100 now now -8c1 125 now now 32mb ds 8 meg x 32 3.3v gold dimm 100 (4) 4 meg x 1 6 3.3v tsop mt4lsdt832udg -10c1 c = y84 1 = 6660 (1.000") 100 now now -8c1 125 now now 32mb ds 4 meg x 64 3.3v gold sodimm 144* (4) 4 meg x 1 6 3.3v tsop mt4lsdt464hg -662c1 c = y84 1 = 6645 (1.150") 66 now now -662c2 2 = 6669 (1.000") 66 now now -10ec3 3 = 0118b (1.000") 100 now now pc100 -10ec4 4 = 0180 (1.000") 100 now now pc100 -133c4 133 now now pc133 rev 1.0 -13ec4 133 now now pc133 rev 1.0 32mb ss 4 meg x 64 3.3v gold dimm 168 (4) 4 meg x 1 6 3.3v tsop mt4lsdt464ag -662c6 c = y84 6 = 0134b (1.000") 66 now now -10cc6 100 now now -10ec6 100 now now -133c6 133 now now cl3 -13ec6 133 now now cl2 32mb ss 4 meg x 72 3.3v ecc gold dimm 168* (5) 4 meg x 1 6 3.3v tsop mt5lsdt472ag -662c6 c = y84 6 = 0134b (1.000") 66 now now -10cc6 100 now now -10ec6 100 now now -133c6 133 now now cl3 -13ec6 133 now now cl2 64mb ds 16 meg x 32 3.3v gold dimm 100 (4) 16 meg x 8 3.3v tsop mt4lsdt1632ug -10b1 b = y85b 1 = 6692(1.15") 100 now now -8b1 e = y95c 125 now now -10e1 100 now now -8e1 125 now now (4) 8 meg x 1 6 3.3v tsop mt4lsdt1632udg -10b1 b = y85b 1 = 6660(1.00") 100 now now -8b1 f = y95w 125 now now -10f1 100 2q01 3q01 -8f1 125 2q01 3q01 64mb ds 8 meg x 64 3.3v gold sodimm 144* (8) 8 meg x 8 3.3v tsop mt8lsdt864hg -662c3 c = y84 3 = 6678 (1.050") 66 now now (8) 4 meg x 1 6 3.3v tsop -10ec5 5 = 0115c (1.250") 100 now now pc100 64mb ds 8 meg x 64 3.3v gold sodimm 144* (4) 8 meg x 1 6 3.3v tsop mt4lsdt864hg -662b1 b = y85b 1 = 0118b (1.000") 66 now now -10eb1 f = y95w 2 = 0180 (1.000") 100 now now pc100 -10eb2 100 now now pc100 -133b2 133 now now pc133 rev 1.0 -13eb2 133 now now pc133 rev 1.0 -10ef2 100 2q01 3q01 -133f2 133 2q01 3q01 -13ef2 133 2q01 3q01 64mb ss 8 meg x 64 3.3v gold dimm 168 (8) 8 meg x 8 3.3v tsop mt8lsdt864ag -662c7 c = y84 7 = 0104b (1.375") 66 now now -10cc7 100 now now -10ec7 100 now now -133c7 133 now now cl3 -13ec7 133 now now cl2 64mb ss 8 meg x 64 3.3v gold dimm 168 (4) 8 meg x 1 6 3.3v tsop mt4lsdt864ag -662b1 b = y85b 1 = 0134b (1.00") 66 now now -10cb1 f = y95w 100 now now -10eb1 100 now now -133b1 133 now now cl3 -13eb1 133 now now cl2 -10ef1 100 2q01 3q01 -133f1 133 2q01 3q01 -13ef1 133 2q01 3q01 ds 8 meg x 64 3.3v gold dimm 144 (4) 8 meg x 1 6 3.3v tsop mt4lsdt864wg -133f1 f = y95w 1 = 0182 (1.18") 133 2q01 3q01 micro dimm 64mb ss 8 meg x 72 3.3v gold dimm 168 (5) 8 meg x 1 6 3.3v tsop mt5lsdt872ag -10eb1 b = y85b 1 = 0134b (1.00") 100 now now -133b1 f = y95w 133 now now cl3 -13eb1 133 now now cl2 -10ef1 100 2q01 3q01 -133f1 133 2q01 3q01 -13ef1 133 2q01 3q01 64mb ss 8 meg x 72 3.3v ecc gold dimm 168 (9) 8 meg x 8 3.3v tsop mt9lsdt872ag -662c7 c = y84 7 = 0104b (1.375") 66 now now -10cc7 100 now now -10ec7 100 now now -133c7 133 now now cl3 -13ec7 133 now now cl2 64mb ss 8 meg x 72 3.3v ecc gold dimm 168 (9) 8 meg x 8 3.3v tsop mt9lsdt872g -10cc3 c = y84 3 = 0144 (1.500") 100 now now -10ec3 100 now now -133c3 133 now now cl3 -13ec3 133 now now cl2 128mb ds 32 me g x 32 3.3v gold dimm 100 (8) 16 meg x 8 3.3v tsop mt8lsdt3232ug -10b1 b = y85b 1 = 6692 (1.15") 100 now now -8b1 e = y95c 125 now now -10e1 100 now now -8e1 125 now now (8) 8 meg x 16 3.3v tsop mt8lsdt3232udg -10b1 b = y85b 1 = tbd (1.15") 100 tbd tbd -8b1 f = y95w 125 tbd tbd -10f1 100 tbd tbd -8f1 125 tbd tbd 128mb ds 16 meg x 64 3.3v gold sodimm 144 (8) 8 meg x 16 3.3v tsop mt8lsdt1664hg -10cb1 b = y85b 1 = 0115c (1.25") 100 now now pc100 -10eb1 f = y95w 2 = 6678 (1.050") 100 now now pc100 16 meg x 8 3.3v tsop -662b2 3 = 0179 (1.25") 66 now now 8 meg x 16 3.3v tsop -10eb3 100 now now pc100 -133b3 133 now now pc133 rev 1.0 -13eb3 133 now now pc133 rev 1.0 -10ef3 100 2q01 3q01 -133f3 133 2q01 3q01 -13ef3 133 2q01 3q01 128mb ds 16 meg x 64 3.3v gold dimm 168 (16) 8 meg x 8 3.3v tsop mt16lsdt1664ag -662c7 c = y84 7 = 0104b(1.375") 66 now now -10cc7 100 now now -10ec7 100 now now -133c7 133 now now cl3 -13ec7 133 now now cl2 128mb ds 16 meg x 64 3.3v gold dimm 168 (8) 16 meg x 8 3.3v tsop mt8lsdt1664ag -10cb1 b = y85b 1 = 0104b(1.375") 100 now now -10eb1 e = y95c 100 now now -133b1 133 now now cl3 -13eb1 133 now now cl2 -10ee1 100 now now -133e1 133 now now cl3 -13ee1 133 now now cl2 ss 16 meg x 64 3.3v gold dimm 168 (4) 16 meg x 16 3.3v tsop mt4lsdt1664ag -10eb1 b = y96 1 = tbd (1.00") 100 2q01 3q01 -133b1 133 2q01 3q01 -13eb1 133 tbd tbd ds 16 meg x 64 3.3v gold dimm 144 (4) 16 meg x 16 3.3v tsop mt4lsdt1664wg -133b1 b = y96 1 = 0182 (1.18") 133 2q01 3q01 micro dimm ds 16 meg x 64 3.3v gold dimm 144 (4) 16 meg x 16 3.3v tsop mt4lsdt1664hg -10eb1 b = y96 1 = 0180 (1.00") 100 2q01 3q01 -133b1 133 2q01 3q01 -13eb1 133 tbd tbd 128mb ds 16 meg x 72 3.3v ecc gold dimm 168 (18) 8 meg x 8 3.3v tsop mt18lsdt1672ag -662c7 c = y84 7 = 0104b(1.375") 66 now now -10cc7 100 now now -10ec7 100 now now -133c7 133 now now cl3 -13ec7 133 now now cl2 128mb ss 16 meg x 72 3.3v ecc gold dimm 168 (9) 16 meg x 8 3.3v tsop mt9lsdt1672ag -10cb1 b = y85b 1 = 0104b(1.375") 100 now now -10eb1 e = y95c 100 now now -133b1 133 now now cl3 -13eb1 133 now now cl2 -10ee1 100 now now -133e1 133 now now cl3 -13ee1 133 now now cl2 ss 16 meg x 72 3.3v ecc gold dimm 168 (5) 32 meg x 8 3.3v tsop mt5lsdt1672ag -10eb1 b = y96 1 = tbd (1.00") 100 2q01 3q01 -133b1 133 2q01 3q01 -13eb1 133 tbd tbd 168 (9) 16 meg x 8 3.3v tsop mt9lsdt1672g -10cb1 b = y85b 1 = 0144(1.500") 100 now now -10eb1 e = y95c 100 now now -133b1 2 = 0198(1.125") 133 now now cl3
-13eb1 133 now now cl2 -10ee1 100 now now -133e1 133 now now cl3 -13ee1 133 now now cl2 ds -10ee2 100 2q01 3q01 1u -133e2 133 2q01 3q01 1u -13ee2 133 2q01 3q01 1u 128mb ds 16 meg x 72 3.3v ecc gold dimm 168 (18) 16 meg x 4 3.3v tsop mt18lsdt1672g -10cc2 c = y84 2 = 0129 (1.700") 100 now now -10ec2 100 now now -133c2 133 now now cl3 -13ec2 133 now now cl2 256mb ds 32 meg x 64 3.3v gold dimm 168 (16) 16 meg x 8 3.3v tsop mt16lsdt3264ag -10cb1 b = y85b 1 = 0104b (1.375") 100 now now -10eb1 e = y95c 100 now now -133b1 133 now now cl3 -13eb1 133 now now cl2 -10ee1 100 now now -133e1 133 now now cl3 -13ee1 133 now now cl2 ds 32 meg x 64 3.3v gold sodimm 144 (8) 16 meg x 16 3.3v tsop mt8lsdt3264hg -10eb1 b = y96 1 = 0179 (1.25") 100 now now pc100 -133b1 133 now now pc133 rev 1.0 ss 32 meg x 64 3.3v gold dimm 168 (8) 32 meg x 8 3.3v tsop mt8lsdt3264ag -10eb1 b = y96 1 = tbd (1.375") 100 2q01 3q01 -133b1 133 2q01 3q01 -13eb1 133 tbd tbd ds 32 meg x 64 3.3v gold sodimm 144 (8) 32 meg x 8 3.3v fbga mt8lsdf3264wg -133b1 b = y96 1 = 0189 (1.25") 133 3q01 4q01 micro dimm ds 32 meg x 64 3.3v gold sodimm 144 (16) 16 meg x 8 3.3v fbga mt16lsdf3264hg -10eb2 b = y85b 2 = 0155 (1.25") 100 now now -133b2 e = y95c 3 = 0185 (1.25") 133 now now -10ee3 100 2q01 3q01 -133e3 133 2q01 3q01 256mb ds 32 meg x 72 3.3v ecc gold dimm 168 (18) 16 meg x 8 3.3v tsop mt18lsdt3272ag -10cb1 b = y85b 1 = 0104b (1.375") 100 now now -10eb1 e = y95c 100 now now -133b1 133 now now cl3 -13eb1 133 now now cl2 -10ee1 100 now now -133e1 133 now now cl3 -13ee1 133 now now cl2 256mb ds 32 meg x 72 3.3v ecc gold dimm 168 (18) 32 meg x 4 3.3v tsop mt18lsdt3272g -10eb1 b = y85b 1 = 0129 (1.700") 100 now now -133b1 e = y95c 133 now now cl3 -13eb1 133 now now cl2 -10ee1 100 now now -133e1 133 now now cl3 -13ee1 133 now now cl2 ds 32 meg x 72 3.3v ecc gold dimm 168 (18) 16 meg x 8 3.3v tsop mt18lsdt3272dg -10eb1 b = y85b 1 = 0156 (1.7") 100 now now -133b1 e = y95c 133 now now cl3 -13eb1 133 now now cl2 -10ee1 100 now now -133e1 133 now now cl3 -13ee1 133 now now cl2 ss 32 meg x 72 3.3v ecc gold dimm 168 (9) 32 meg x 8 3.3v tsop mt9lsdt3272ag -10eb1 b = y96 1 = tbd (1.375") 100 2q01 3q01 -133b1 133 2q01 3q01 -13eb1 133 tbd tbd ss 32 meg x 72 3.3v ecc gold dimm 168 (9) 32 meg x 8 3.3v tsop mt9lsdt3272g -10eb1 b = y96 1 = tbd (1.70") 100 2q01 3q01 -133b1 2 = 0198(1.125") 133 2q01 3q01 -13eb1 133 tbd tbd ds -10eb2 100 2q01 3q01 1u -133b2 133 2q01 3q01 1u -13eb2 133 tbd tbd 1u 512mb ds 64 meg x 72 3.3v ecc gold dimm 168 (36) 32 meg x 4 3.3v fbga mt36lsdf6472g -10eb1 b = y85b 1 = 0123(1.70") 100 now now 11x13pkg -133b2 2 = 0142(1.70") 133 now now cl3 ds 64 meg x 64 3.3v gold dimm 168 (16) 32 meg x 8 3.3v tsop mt16lsdt6464ag -10eb1 b = y96 1 = tbd (1.375") 100 2q01 3q01 -133b1 133 2q01 3q01 cl3 -13eb1 133 tbd tbd cl2 ds 64 meg x 64 3.3v gold dimm 144 (16) 32 meg x 8 3.3v fbga mt16lsdf6464hg -10eb1 b = y96 1 = 0185 (1.25") 100 2q01 3q01 -133b1 133 2q01 3q01 ds 64 meg x 72 3.3v ecc gold dimm 168 (18) 32 meg x 8 3.3v tsop mt18lsdt6472ag -10eb1 b = y96 1 =tbd (1.375") 100 2q01 3q01 -133b1 133 2q01 3q01 cl3 -13eb1 133 tbd tbd cl2 ds 64 meg x 72 3.3v ecc gold dimm 168 (18) 64 meg x 4 3.3v tsop mt18lsdt6472g -10eb1 b = y96 1 = 0129 (1.700") 100 2q01 3q01 -133b1 133 2q01 3q01 cl3 -13eb1 133 tbd tbd cl2 ds 64 meg x 72 3.3v ecc gold dimm 168 (18) 32 meg x 8 3.3v tsop mt18lsdt6472dg -10eb1 b = y96 1 =0156 (1.70") 100 2q01 3q01 -133b1 2 =0198 (1.125") 133 2q01 3q01 -13eb1 133 tbd tbd -10eb2 100 2q01 3q01 1u -133b2 133 2q01 3q01 1u -13eb2 133 tbd tbd 1u ds 64 meg x 72 3.3v ecc gold dimm 168 (18) 64 meg x 4 3.3v fbga mt18lsdf6472g -10eb1 b = y96 1 = 0187 (1.05") 100 2q01 3q01 1u -133b1 133 2q01 3q01 1u -13eb1 133 tbd tbd 1u 1gb ds 128 meg x 72 3.3v ecc gold dimm 168 (36) 64 meg x 4 3.3v fbga mt36lsdf12872g -10eb1 b = y96 1 = tbd (1.700") 100 2q01 3q01 -133b1 133 2q01 3q01 cl3 -13eb1 133 tbd tbd cl2 ab rev. 3/26/01 *for 168-pin dimms (66 mhz/100 mhz), adheres to intel's 4-clock sdram module specs (66 mhz will use -10 components; 100 mhz wil l use -8 components). for 100-pin dimms, 100 mhz uses -10 components; adheres to jedec standard. ss - single sided ds - double sided g - gold plated u - 100-pin dimm udg - double-sided, dual-bank 100-pin dimm (h) - small-outline dimm (sodimm) lp - low power (a) - 8-cas; spd version; unbuffered (no "a" denotes registered version for x72 dimms) (w) - micro dimm intel is a registered trademark of intel corporation. micron technology, inc. reserves the right to change products or specific ations without notice. part number = a + b example: mt36lsdf12872g-13eb1
micron memory ddr sdram module reference guide availability density description pins components on module base part number speed die rev. pcb (height) mhz samples production 64mb ss 8 meg x 64 2.5v gold sodimm 200 (4) 8 meg x 16 tsop mt4vddt864hg -202b1 b = t95 1 = 0175 (1.25") 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ss 8 meg x 64 2.5v gold dimm 184 (4) 8 meg x 16 tsop mt4vddt864ag -202b1 b = t95 1 = 0151 (1.0") 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ds 8 meg x 64 2.5v gold dimm 172 (4) 8 meg x 16 tsop mt4vddt864wg -202b1 b = t95 1 = 0207 (1.25") 200 2q01 3q01 -265b1 266 2q01 3q01 128mb ss 16 meg x64 2.5v gold dimm 184 (8) 16 meg x 8 tsop mt8vddt1664ag -202a1 a = t85 1 = 0161 (1.25") 200 now now -265a1 b = t95 266 now now -202b1 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ds 16 meg x64 2.5v gold sodimm 200 (8) 16 meg x 8 tsop mt8vddt1664hg -202a1 a = t85 1 = 0168(1.25") 200 contact mktg contact mktg -265a1 266 contact mktg contact mktg ds 16 meg x64 2.5v gold sodimm 200 (8) 8 meg x 16 tsop mt8vddt1664hg -202b2 b = t95 2 = 0174 (1.25") 200 2q01 3q01 -265b2 266 2q01 3q01 -262b2 266 tbd tbd ss 16 meg x 64 2.5v gold sodimm 200 (4) 16 meg x 16 tsop mt4vddt1664hg -202a1 a = t96 1 = 0175 (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd ss 16 meg x 64 2.5v gold sodimm 184 (4) 16 meg x 16 tsop mt4vddt1664ag -202a1 a = t96 1 = 0151 (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd ds 16 meg x 64 2.5v gold sodimm 172 (4) 16 meg x 16 tsop mt4vddt1664wg -202a1 a = t96 1 = 0207 (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 ss 16 meg x72 ecc 2.5v gold dimm 184 (9) 16 meg x 8 tsop mt9vddt1672ag -202a1 a = t85 1 = 0161 (1.25") 200 now now -265a1 b = t95 266 now now -202b1 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ss 16 meg x72 ecc 2.5v gold dimm 184 (5) 16 meg x 16 tsop mt5vddt1672ag -202a1 a = t96 1 = 0151 (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd ss 16 meg x72 ecc 2.5v gold dimm 184 (9) 16 meg x 8 tsop mt9vddt1672g -202a1 a = t85 1 = 0162 (1.70") 200 now now -265a1 b = t95 2 = tbd (1.2") 266 now now -202b1 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ds -202a2 200 2q01 3q01 -265a2 266 2q01 3q01 -202b2 200 2q01 3q01 -265b2 266 2q01 3q01 256mb ds 32 meg x64 2.5v gold dimm 184 (16) 16 meg x 8 tsop mt16vddt3264ag -202a1 a = t85 1 = 0116b (1.25") 200 now now -265a1 b = t95 266 now now -202b1 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ds 32 meg x64 2.5v gold sodimm 200 (8) 16 meg x 16 tsop mt8vddt3264hg -202a1 a = t96 1 = 0174 (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd ss 32 meg x64 2.5v gold sodimm 184 (8) 32 meg x 8 tsop mt8vddt3264ag -202a1 a = t96 1 = 0161 (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd 256mb ds 32 meg 72 ecc 2.5v gold dimm 184 (18) 16 meg x 8 tsop mt18vddt3272ag -202a1 a = t85 1 = 0116b (1.25") 200 now now -265a1 b = t95 266 now now -202b1 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ds 32 meg 72 ecc 2.5v gold dimm 184 (18) 32 meg x 4 tsop mt18vddt3272g -202a1 a = t85 1 = 0163 (1.70") 200 now now -265a1 b = t95 266 now now -202b1 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ds 32 meg 72 ecc 2.5v gold dimm 184 (18) 16 meg x 8 tsop mt18vddt3272dg -202a1 a = t85 1 = 0162 (1.70") 200 now now -265a1 b = t95 266 now now -202b1 200 2q01 3q01 -265b1 266 2q01 3q01 -262b1 266 tbd tbd ss 184 (9) 32 meg x 8 tsop mt9vddt3272ag -202a1 a = t96 1 = 0161 (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 200 tbd tbd ds 184 (9) 32 meg x 8 tsop mt9vddt3272g -202a1 a = t96 1 = tbd (1.2") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 200 tbd tbd 512mb ds 64 meg 64 2.5v gold dimm 184 (16) 32 meg x 8 tsop mt16vddt6464ag -202a1 a = t96 1 = 0116b (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd ds 64 meg 72 ecc 2.5v gold dimm 184 (18) 32 meg x 8 tsop mt18vddt6472ag -202a1 a = t96 1 = 0116b (1.25") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd ds 64 meg 72 ecc 2.5v gold dimm 184 (18) 32 meg x 8 tsop mt18vddt6472dg -202a1 a = t96 1 = 0162 (1.70") 200 2q01 3q01 -265a1 2 = tbd (1.2") 266 2q01 3q01 -262a1 266 tbd tbd -202a2 200 2q01 3q01 -265a2 266 2q01 3q01 ds 64 meg 72 ecc 2.5v gold dimm 184 (18) 64 meg x 4 tsop mt18vddt6472g -202a1 a = t96 1 = 0163 (1.70") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd ds 184 (18) 64 meg x 4 fbga mt18vddf6472g -202a1 a = t96 1 = tbd (1.125") 200 2q01 3q01 -265a1 266 2q01 3q01 1gb ds 128 meg 72 ecc 2.5v gold dimm 184 (36) 64 meg x 4 fbga mt36vddf12872g -202a1 a = t96 1 = 0173 (1.70") 200 2q01 3q01 -265a1 266 2q01 3q01 -262a1 266 tbd tbd ab ss - single sided ds - double sided g - gold plated (h) - small-outline dimm (sodimm) (a) - 8-cas; spd version; unbuffered (no "a" denotes registered version for x72 dimms) part number = a + b example mt36vddt6472g-262b1
micron memory rambus ? rimm ? module reference guide availability density description pins components on module base part number speed die rev. pcb (height) mhz samples production 128mb ss 64 meg x 16 non-ecc 184 (4) 16 meg x 16 mt4vr6416ag -653a1 a = r96a 1 = tbd (1.25") 600 tbd tbd -750a1 700 tbd tbd -745a1 700 tbd tbd -845a1 800 tbd tbd -840a1 800 tbd tbd 128mb ss 32 meg x 18 ecc 184 (4) 16 meg x 18 mt4vr6418ag -653a1 a = r96a 1 = tbd (1.25") 600 tbd tbd -750a1 700 tbd tbd -745a1 700 tbd tbd -845a1 800 tbd tbd -840a1 800 tbd tbd 256mb ss 64 meg x 16 non-ecc 184 (8) 16 meg x 16 mt8vr12816ag -653a1 a = r96a 1 = tbd (1.25") 600 tbd tbd -750a1 700 tbd tbd -745a1 700 tbd tbd -845a1 800 tbd tbd -840a1 800 tbd tbd 256mb ss 64 meg x 18 ecc 184 (8) 16 meg x 18 mt8vr12818ag -653a1 a = r96a 1 =tbd (1.25") 600 tbd tbd -750a1 700 tbd tbd -745a1 700 tbd tbd -845a1 800 tbd tbd -840a1 800 tbd tbd 512mb ds 128 meg x 16 non-ecc 184 (16) 16 meg x 16 mt16vr25616ag -653a1 a = r96a 1 = tbd (1.25") 600 tbd tbd -750a1 700 tbd tbd -745a1 700 tbd tbd -845a1 800 tbd tbd -840a1 800 tbd tbd 512mb ds 128 meg x 18 ecc 184 (16) 16 meg x 18 mt16vr25618ag -653a1 a = r96a 1 = tbd (1.25") 600 tbd tbd -750a1 700 tbd tbd -745a1 700 tbd tbd -845a1 800 tbd tbd -840a1 800 tbd tbd ab rev. 3/26/01 part number = a + b example mt16vr25618ag-840a1

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