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vishay siliconix si9139 document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 1 multi-output, individual on/off control power-supply controller description the si9139 is current-mode pwm and psm converter controller, with two high current, high efficiency synchronous buck controllers and an adjustable buck-boost controller whose output can be set between 1.24 v and 20 v with an external resistor divider. designed for fixed and portable devices, it offers a total of five power outputs (three tightly regulated dc/dc converter outputs, a precision 3.3 v reference and a 5 v ldo output. individually controlled power-up sequencing, power-good signal with delay, internal frequency compensation networks and automatic boot- strapping simplify the system by minimizing the number of external components while achieving conversion efficiencies approaching 95 %. the si9139 is available in a 28 pin ssop package and specified to operate over the extended commercial (- 40 c to 85 c) temperature range. features ? five output 50 w, triple output dc/dc-controller ? up to 95 % efficiency ? 3 % total regulation (line, load and temperature) ? 4.5 v to 30 v input voltage range ? two fixed 1.5 v, 1.8 v, 2.0 v, 2.2 v, 2.5 v, 2.8 v, 3.3 v outputs ? one adjustable 1.24 v to 20 v output ? 3.3 v reference output ? 5 v/30 ma linear regulator output ? individual on/off control for a and b outputs ? 300 khz low-noise fixed frequency operation ? high efficiency pulse skipping mode operation at light load ? only three inductors required - no transformer ? little foot ? optimized output drivers ? internal under voltage lockout and soft-start ? minimum number of external control components ? 28 pin ssop package ? output overvoltage protection ? output undervoltage shutdown ? power-good output (reset ) applications ? notebook and subnotebook computers ? pdas and mobile communicators ? portable display ? multimedia set-top box ? telecommunications infrastructure ? network equipment ? distributed power conversion functional block diagram 5 v linear regulator 3.3 v voltage reference 1.5 v - 3.3 v smps a 1.8 v - 3.3 v smps b auxiliary smps programmable v in (4.5 v to 30 v) 0 - 6 a v l (5.0 v) v ref (+ 3.3 v) 1.24 v to 20 v/500 ma adjustable power_good reset (power_good) on a on b logic control 0 - 6 a v out c v out b v out a
www.vishay.com 2 document number: 71841 s09-1455-rev. b, 03-aug-09 vishay siliconix si9139 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 9.52 mw/c above 70 c. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter limit unit v in to gnd - 0.3 to + 36 v p gnd to gnd 2 v l to gnd - 0.3 to + 6.5 bst a , bst b , bst c to gnd - 0.3 to + 36 v l short to gnd continuous lx a to bst a ; lx b to bst b ; lx c to bst c - 6.5 to 0.3 v inputs/outputs to gnd (cs a , cs b , csp, csn) - 0.3 to (v l + 0.3) reset , on a , on b - 0.3 + 5.5 dl a , dl b , dl c to pgnd - 0.3 to (v l + 0.3) dh a to lx a , dh b to lx b , dh c to lx c - 0.3 to (bst x + 0.3 ) continuous power dissipation (t a = 70 c) a 28-pin ssop b 762 mw operating temperature range - 40 to 85 c storage temperature range - 40 to 125 lead temperature (soldering, 10 s) 300 specifications parameter test conditions v in = 15 v, i vl = i ref = 0 ma t a = - 45 c to 85 c, all controllers on limits unit min. a typ. b max. a buck controller a total regulation (line, load, and temperature) v in = 4.5 to 30 v, 0 < v cs3 - v fb3 < 90 mv - 3 0 3 % line regulation v in = 6.0 to 30 v 0.5 v in = 4.5 to 30 v 1.0 load regulation 0 < v cs3 - v fb3 < 90 mv 0.5 current limit v csa - v fba v out > 2.5 v 90 125 160 mv v out < 2.5 v 100 180 bandwidth l = 10 h, c = 330 f 50 khz phase margin r sense = 20 m 65 minimum duty cycle 7% buck controller b total regulation (line, load, and temperature) v in = 4.5 to 30 v, 0 < v cs5 - v fb5 < 90 mv - 3 0 3 % line regulation v in = 6.0 to 30 v 0.5 v in = 4.5 to 30 v 1.0 load regulation 0 < v csb - v fbb < 90 mv 0.5 current limit v csb - v fbb v out > 2.5 v 90 125 160 mv v out < 2.5 v 100 180 bandwidth l = 10 h, c = 330 f 50 khz phase margin r sense = 20 m 65 minimum duty cycle 7% auxiliary controller c total regulation (line, load, and temperature) output voltage set to 12 v v in = 4.5 v to 30 v, 0 < v csp - v csn < 300 mv r 5 = 26.4 k , r 6 = 10 k (see figure 1) - 5 0 5 % line regulation v in = 6.0 to 30 v 0.5 v in = 4.5 to 30 v 1.0 load regulation 0 < v csp - v fbn < 300 mv 0.5 current limit v csp - v csn 280 360 450 mv bandwidth l = 10 h, c = 100 f 10 khz
document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 3 vishay siliconix si9139 notes: a. the algebraic convention is used whereby the most negativ e value is a minimum and the most positive a maximum. b. typical values are for design aid only, not guaranteed no r subject to production test ing, and are measured at t a = 25 c. specifications parameter specific test conditions v in = 15 v, i vl = i ref = 0 ma t a = - 45 c to 85 c, all controllers on limits unit min. a typ. b max. a auxiliary controller c phase margin r sense = 100 m , c comp = 120 pf 65 current-sense common mode voltage range 0.0 2.1 v feedback input voltage range 0.0 2.1 minimum duty cycle 7 % maximum duty cycle v in = 5 v 85 internal 5 v regulator v l output current (internal and external) 30 60 ma v l output all controllers off, v in > 5.5 v, 0 < i l < 30 ma 4.7 5.5 v v l fault lockout voltage v l falling edge 3.6 4.2 v l fault lockout hysteresis 75 mv reference ref output 3.24 3.3 3.36 v ref load regulation 0 to 1 ma 25 60 mv auxiliary feedback voltage fb c pin 1.20 1.24 1.28 v supply current supply current - shutdown all converters off, no load 25 60 a supply current - operation all controllers on, no load, f ocs = 300 khz 1100 1800 oscillator oscillator frequency 270 300 330 khz maximum duty cycle 92 95 % fault detection smps a and smps b outputs overvoltage trip threshold with respect to unloaded output voltage 6 10 14 % overvoltage-fault propagation delay cs a or cs b driven 2 % above overvoltage trip threshold 1.5 s output undervoltage threshold with respect to unloaded output voltage - 40 - 30 - 20 % output undervoltage lockout time from each smps enabled 16 20 24 ms reset reset start threshold with respect to unloaded output voltage rising edge - 5.5 % reset propagation delay (falling) falling edge, fb a or fb b driven 2 % above overvoltage or 2 % below undervoltage lockout thresholds 1.5 s reset delay time (rising) with respect to 2nd smps lockout time done 92 107 122 ms inputs and outputs feedback input leakage current fb c = 1.24 v 1 a input leakage current on a , on b , v in = 0 v or v l 1 gate driver sink/source current (buck) dl a , dh a , dl b , dh b forced to 2 v 1 a gate driver on-resistance (buck) high or low 2 7 gate driver sink/source current (auxiliary) dh c , dl c forced to 2 v 0.2 a gate driver on-resistance (auxiliary) high or low 15 reset output low voltage reset , i sink = 4 ma 0.4 v reset output high leakage reset = 5 v 1 a on a , on b logic low v il 0.8 v logic high v ih 2.4
www.vishay.com 4 document number: 71841 s09-1455-rev. b, 03-aug-09 vishay siliconix si9139 pin configuration reset fb a fb c ssop-28 dh a bst c lx a dh c bst a lx c dl c csp dl a v in v l top view 25 26 27 28 2 3 4 1 22 23 24 5 6 7 csn fb b comp pgnd gnd dl b ref bst b on a on b cs b lx b dh b cs a 18 19 20 21 9 10 11 8 15 16 17 12 13 14 pin description pin symbol description 1 reset open drain nmos output active-low timed reset output. reset swings gnd to v l . goes high after a fixed 32,000 clock cycle delay following proper power- up of all supply outputs indicating power_good. 2 fb c feedback for auxiliary controller c. normally connected to an external resistor divider used to set the auxiliary output voltage. 3 bst c boost capacitor connection for auxiliary smps controller c 4 dh c gate-drive output for auxiliary smps controller c high-side mosfet 5 lx c inductor connection for auxiliary smps controller c 6 dl c gate-drive output for auxiliary smps controller c low-side mosfet 7 csp current sense positive input for auxiliary smps controller c 8 csn current sense negative input for auxiliary smps controller c 9 comp auxiliary smps controller c compensation connection, if required 10 gnd analog ground 11 ref 3.3 v internal reference 12 on a logic high enables the smps controller a 13 on b logic high enables the smps controller b and the auxilia ry smps controller c adjustable smps controllers 14 cs b current sense input for smps controller b 15 dh b gate-drive output for smps controller b high-side mosfet 16 lx b inductor connection for smps controller b 17 bst b boost capacitor connection for smps controller b 18 dl b gate-drive output for smps controller b low-side mosfet 19 pgnd power ground 20 fb b feedback for smps controller b 21 v l 5 v logic supply voltage for internal circuitry 22 v in input voltage 23 dl a gate-drive output for smps controller a low-side mosfet 24 bst a boost capacitor connection for smps controller a 25 lx a gate-drive output for smps controller a high-side mosfet 26 dh a inductor connection for smps c ontroller a low-side mosfet 27 fb a feedback for smps controller a 28 cs a current sense input for smps controller a
document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 5 vishay siliconix si9139 typical characteristics 25 c, unless otherwise noted ordering information part number temperature range smps b , smps a output voltages si9139dg - 3328 - 40 c to 85 c 3.3 v, 2.8 v si9139dg - 3325 3.3 v, 2.5 v si9139dg - 3322 3.3 v, 2.2 v si9139dg - 3320 3.3 v, 2.0 v si9139dg - 3318 3.3 v, 1.8 v si9139dg - 3315 3.3 v, 1.5 v si9139dg - 2825 2.8 v, 2.5 v si9139dg - 2822 2.8 v, 2.2 v si9139dg - 2820 2.8 v, 2.0 v si9139dg - 2818 2.8 v, 1.5 v si9139dg - 2815 2.8 v, 1.8 v si9139dg - 2522 2.5 v, 2.2 v si9139dg - 2520 2.5 v, 2.0 v si9139dg - 2518 2.5 v, 1.8 v si9139dg - 2515 2.5 v, 1.5 v si9139dg - 2220 2.2 v, 2.0 v si9139dg - 2218 2.2 v, 1.8 v si9139dg - 2215 2.2 v, 1.5 v si9139dg - 2018 2.0 v, 1.8 v si9139dg - 2015 2.0 v, 1.5 v si9139dg - 1815 1.8 v, 1.5 v si9139dg contact factory for other voltages evaluation board temperature range board type si9139db - 40 c to 85 c surface mount efficiency vs. smps b output current 0.1 50 80 100 60 70 0 1 1 efficiency (%) load current (a) 90 v in = 5 v v in = 24 v smps a no load v out = 2.5 v v in = 12 v efficiency vs. auxiliary smps c output current (buck-boost configuration) 0.001 55 0.1 65 85 60 70 1 0.01 efficiency (%) current (a) 75 80 frequency = 300 khz 6 v 30 v v in = 15 v smps a, b no load v out = 12 v
www.vishay.com 6 document number: 71841 s09-1455-rev. b, 03-aug-09 vishay siliconix si9139 typical characteristics 25 c, unless otherwise noted typical waveforms efficiency vs. auxiliary smps c output current (buck configuration) 0.01 0 1 30 90 15 45 10 0.1 efficiency (%) output current (a) 60 75 smps a, b no load v out = 2.1 v v in = 24 v v in = 12 v v in = 5 v efficiency vs. smps b output current 0.01 0 60 100 20 40 1 1 . 0 efficiency (%) load current (a) 80 v in = 5 v smps a no load v out = 12.5 v v in = 12 v pwm loading b converter psm to pwm b converter 20.0 s/div (v in = 5.0 v, v out = 2.5 v) v out (100 mv/div) load (1 a/div) (v in = 5.0 v, v out = 2.5 v) v out (50 mv/div) load (1 a/div) 50 s/div (0.1 a to 1.8 a) pwm unloading b converter pwm to psm b converter (v in = 5.0 v, v out = 2.5 v) 20.0 s/div v out (100 mv/div) load (1 a/div) v out (50 mv/div) load (1 a/div) 50 s/div (0.1 a to 1.8 a) (v in = 5.0 v, v out = 2.5 v)
document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 7 vishay siliconix si9139 typical waveforms psm operation b converter pwm loading b converter psm to pwm a converter v out (20 mv/div) inductor node (lxb) (5 v/div) inductor current (0.5 a/div) 10.0 s/div v (v in = 5.0 v, v out = 2.5 v) (i out = 100 ma) v out (20 mv/div) load (1 a/div) 50 s/div (v in = 12.0 v, v out = 2.5 v) (1.5 a to 4.0 a ) v out (50 mv/div) 50 s/div v v in = 5.0 v, v out = 2.0 v (0.1 a to 3.0 a ) load (1 a/div) psm operation b converter pwm unloading a converter pwm to psm a converter v out (20 mv/div) inductor node (lxb) (5 v/div) inductor current (0.5 a/div) 10.0 s/div (v in = 5.0 v, v out = 2.5 v) (i out = 1.2 a) v out (20 mv/div) 50 s/div load (1 a/div) (v in = 12.0 v, v out = 2.0 v) (1.8 a to 4.3 a ) v out (50 mv/div) 50 s/div (3 a to 0.1 a ) load (1 a/div) (v in = 10.0 v, v out = 3.3 v)
www.vishay.com 8 document number: 71841 s09-1455-rev. b, 03-aug-09 vishay siliconix si9139 typical waveforms 250 ma transient auxiliary converter c (buck-boost mode - output set to 12 v) v out (100 mv/div) 200 s/div v v in = 10.0 v load current (100 ma/div)
document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 9 vishay siliconix si9139 standard application circuit (buck-boost auxiliary) figure 1. a bst c dh c lx c dl c csp csn fb c dl b lx b dh b bst b v l comp pgnd fb b cs b v in bst a dh a lx a dl a cs a fb a reset ref gnd on a on b v in 4.5 ~ 30 v c7 33 f c1 0.1 f q1 si7888 c6 330 f l2 10 h q3 si7886 r 1 0.02 c11 1f 3.3 v 1 ma cmpd2836 d1a d1b c2 0.1f d3 cmpd2836 c8 0.1 f q2 si7888 q4 si7886 c4 33 f d2, bys10-35 q5 si3456 l3, 10 h q6 si3456 r 3 c10 100 f c9 4.7 f d4, bys10-35 1.24 to 20 v 500 ma l1, 10 h r 2 0.02 c5 10 f + 5 v c3 330 f v out c12 120 pf r 5 r 6 0.2 gnd* pgnd* *pgnd and gnd planes should be connected to a single point (star) ground. v l 20 k 22 24 26 25 23 28 27 1 12 13 11 10 19 9 2 8 7 6 5 4 3 20 14 18 16 15 17 21 b v out c v out a ss34 ss34
www.vishay.com 10 document number: 71841 s09-1455-rev. b, 03-aug-09 vishay siliconix si9139 standard application circuit (5 v input - auxiliary in boost mode) figure 1. b dl c csp csn fb c dl b lx b dh b bst b v l comp pgnd fb b cs b v in bst a dh a lx a dl a cs a fb a reset ref gnd on a on b v in 4.5 ~ 5.5 v c7 33 f c1 0.1 f q1 si7888 c6 330 f l2 10 h q3 si7886 r 1 0.02 c11 1f 3.3 v 1 ma cmpd2836 d1a d1b c2 0.1 f q2 si7888 q4 si7886 c4 33 f l3, 10 h q6 si3456 r 3 c10 100 f d4, bys10-35 (v in + 0.5 v) to 20 v 500 ma l1, 10 h r 2 0.02 c3 330 f c12 120 pf r 5 r 6 0.2 gnd* pgnd* *pgnd and gnd planes should be connected to a single point (star) ground. v l 20 k 22 24 26 25 23 28 27 1 12 13 11 10 19 9 2 8 7 6 20 14 18 16 15 17 21 v out c v out a v out b ss34 ss34
document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 11 vishay siliconix si9139 standard application circuit (5 v input - auxiliary in buck mode) figure 1. c bst c dh c lx c csp csn fb c dl b lx b dh b bst b v l comp pgnd fb b cs b v in bst a dh a lx a dl a cs a fb a reset ref gnd on a on b v in 4.5 ~ 5.5 v c7 33 f c1 0.1f q1 si7888 c6 330 f l2 10 h q3 si7886 r 1 0.02 c11 1f 3.3 v 1 ma cmpd2836 d1a d1b c2 0.1f d3 cmpd2836 c8 0.1 f q2 si7888 q4 si7886 c4 33 f d2, bys10-35 q5 si3456 l3, 10 h c10 100 f 1.24 to 2.1 v 500 ma l1, 10 h r 2 0.02 c3 330 f c12 120 pf r 5 r 6 gnd* pgnd* *pgnd and gnd planes should be connected to a single point (star) ground. v l 20 k 22 24 26 25 23 28 27 1 12 13 11 10 19 9 2 8 7 5 4 3 20 14 18 16 15 17 21 r 3 v out a v out b v out c ss34 ss34 c17 r 4
www.vishay.com 12 document number: 71841 s09-1455-rev. b, 03-aug-09 vishay siliconix si9139 timing diagrams figure 2. converter is enabled before v in is applied, a or b controllers on a or on b v in v l v ref osc en (sysmon en) osc f max (ss) dh d l the converter is enabled v in is applied ldo is activated after v in is applied ref circuit is activated after v l becomes available after v ref goes above 0.8 v, the converter is turned on oscillator is activated slow soft-start gradually increases the maximum inductor current high-side gate drive duty ratio gradually increases to maximum low-side gate drive 4 ms 0.8 v t bbm figure 3. converter is enabled after v in is applied, a or b controllers on a or on b v in v l v ref osc en (sysmon en) osc f max (ss) dh dl the converter is enabled v in is applied ldo is activated after v in is applied ref circuit is activated after v l becomes available after v ref goes above 0.8 v, the converter is turned on oscillator is activated slow soft-start gradually increases the maximum inductor current 0.8 v 4 ms
document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 13 vishay siliconix si9139 timing diagrams figure 4. power off sequence v in v l v ref osc f max (ss) d h d l v (v l ) reset 4 v 3.4 v osc en (sysmon en) v in is removed ldo deactivated afte r v in is removed oscillator disabled
www.vishay.com 14 document number: 71841 s09-1455-rev. b, 03-aug-09 vishay siliconix si9139 detailed functional block diagrams figure 5. buck block diagram (smps a and b controllers) + - + - logic control - + bbm on a or on b 1x dh dl lx_ v l dh dl internal reference pwmcmp pulse skipping control current limit sync rectifier control 20 mv t cs_ fb_ fb_ slc r x r y bst_ error amplifier v soft-start figure 6. buck-boost block diagram (auxiliary smps controller c) + - + - + - + - t dh dl fb c r 2 r 3 dh c dl c bst c lx c pulse skipping control pwm comparator 100 mv 1.24 v comp csn csp c/s amplifier current limit error amplifier logic control soft-start v on b v l slc
document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 15 vishay siliconix si9139 detailed functional block diagrams description of operation shutdown mode the logic threshold for the on a and on b pins is 1.6 v. input voltage must be 0.8 v or less for logic low and 2.4 v or higher for logic high. start-up sequence start-up is controlled by individual on/off control. the a output is controlled by on a whilst the b and the c adjustable outputs are both controlled by on b . when both the a and b smps out puts are within tolerance and 32 000 clock cycles (typic ally equal to 107 ms) have elapsed since the second smps output went into regulation, the reset pin will go high, signifying that all converters are operating correctly (see reset power good voltage monitor). the si9139 converts a 4.5 v to 30 v input voltage to five different output voltages; two buck (step-down) high current, pwm, switch-mode supplies of 1.5 v to 3.3 v, one "buck- boost" pwm switch-mode supp ly adjustable from 1.24 v to 20 v, one precision 3.3 v reference and one 5 v low drop out (ldo) linear regulator output. switch-mode supply output current capabilities depend on external components (can be selected to exceed 10 a). in the standard application circuit illustrated in figure 1, each buck converter is capable of delivering 5 a, with the buck- boost converter delivering 500 ma. figure 7. complete si9139 block diagram a smps controller fb a cs a bst a dh a lx a dl a 5 v linear regulator 3.3 v reference 4 v 2.4 v b smps controller fb b cs b bst b dh b lx b dl b auxiliary 1.2 to 20 v adjustable buck-boost controller c fb c csp csn bst c dh c lx c dl c v in v l reset on b reset handler on a enable good a enable good b enable
www.vishay.com 16 document number: 71841 s09-1455-rev. b, 03-aug-09 vishay siliconix si9139 description of operation (cont?d) buck converter operation: converters a and b the a and b buck converters are both current-mode pwm and psm (during light load operation) regulators using high- side bootstrap n-channel and low-side n-channel mosfets. at light load conditi ons, the converters switch at a lower frequency than the clock frequency. this operating condition is defined as pulse-skipping. the operation of the converter(s) switching at clock frequency is defined as normal operation. normal operation pwm: buck converters a and b in normal operation, the buck converter high-side mosfet is turned on with a delay (known as break-before-make time - t bbm ), after the rising edge of the clock. after a certain on time, the high-side mosfet is turned off and then after a delay (t bbm ), the low-side mosfet is turned on until the next rising edge of the clock, or the inductor current reaches zero. the t bbm (approximately 25 ns to 60 ns), has been optimized to guarantee the efficiency is not adversely affected at the high switching frequency and a specified minimum to account for variations of possible mosfet gate capacitances. during the normal operation, the high-side mosfet switch on-time is controlled internally to provide excellent line and load regulation over temperatur e. both buck converters have load, line, regulation to within 1.0 % tolerance. pulse skipping operation: buck converters a and b when the buck converter switching frequency is less than the internal clock frequency, its operation mode is defined as pulse skipping mode. during this mode, the high-side mosfet is turned on until v cs - v fb reaches 20 mv, or the on time reaches its maximum duty ratio. after the high-side mosfet is turned off, the lo w-side mosfet is turned on after the t bbm delay, which will remain on until the inductor current reaches zero. the output voltage will rise slightly above the regulation voltage after this sequence, causing the controller to stay idle for the ne xt clock cycle, or several clock cycles. when the output voltage falls slightly below the regulation level, the high-side mosfet will be turned on again at the next clock cycle. with the converter remaining idle during some clock cycl es, the switching losses are reduced preserving conversion efficiency during the light output current condition. current limit: bu ck converters when the buck converter induct or current is too high, the voltage across pin cs3 and pin fb will exceed the 125 mv current limit threshold, causin g the high-side mosfet to be turned off instantaneously rega rdless of the input, or output condition. the si9139 features clock cycle by clock cycle current limiting capability. auxiliary converter c operat ion: buck-boost operation the si9139 has an auxiliary adjustable 1.24 v to 20 v output non-isolated buck-boost converter, called for brevity a buck- boost. the input voltage range can span above or below the regulated output voltage. it consists of two n-channel mosfet switches that are tu rned on and off in phase, and two diodes. similar to the buck converter, during the light load conditions, the buck-boos t converter will switch at a frequency lower than the internal clock frequency, which can be defined as pulse skipping mode (psm); otherwise, it operates in normal pwm mode. the output voltage of the buck-boost converter is set by two resistors (r 5 and r 6 , see figure 1.a) where, auxiliary converter c normal operation: buck-boost mode in buck-boost operation mode, the two mosfets are turned on at the rising edge of the clock, and then turned off. the on time is controlled internally to provide excellent load, line, and temperature regulation. the buck-boost converter has load, line and temperature regulation well within 5 %. auxiliary converter c pulse skipping operation: buck-boost converter under the light load conditions, similar to the buck converter, the buck-boost converter will enter pulse skipping mode. the mosfets will be turned on until the inductor current increases to such a level that the voltage across the pin csp and pin csn reaches 360 mv, or the on time reaches the maximum duty cycle. after the mosfets are tu rned off, the inductor current will conduct through two diodes until it reaches zero. at this point, the buck-boost converter output will rise slightly above the regulation level, and the converter will stay idle for one or several clock cycle(s) until the output falls back slightly below the regulation level. the switching losses are reduced by skipping pulses preserving the efficiency during light load. auxiliary converter c normal operation: boost mode the auxiliary converter may be operated in boost mode as shown in figure 1.b when operating from a 5 v 10 % input supply voltage. this ability reduces the component count of the converter and provides a high efficiency output voltage of in the range of 6 v to 20 v at up to 10 w of power. operation is similar to the buck-boost mode described above. v out c (r 5 r 6 ) r 6 v fb + x
document number: 71841 s09-1455-rev. b, 03-aug-09 www.vishay.com 17 vishay siliconix si9139 description of operation (cont?d) auxiliary converter c no rmal operation: buck mode the auxiliary converter may also be operated in buck mode as shown in figure 1.c when operating from a 5 v 10 % input supply voltage. this ability reduces the component count of the converter and provides a high efficiency output voltage of in the range of 1. 24 v to 2.1 v with 1 w of power. operation is similar to the buck-boost mode described above. auxiliary converte r c current limit similar to the buck converter; when the voltage across pin csp and pin csn exceeds 360 mv typical, the two mosfets will be turned off regardless of the input and output conditions. grounding: there are two separate ground s on the si9139, analog signal ground (gnd) and power ground (pgnd). the purpose of two separate groun ds is to prevent the high currents on the power devices (both external and internal) from interfering with the analog signals. the internal components of si9139 have their grounds tied (internally) together. these two grounds are then tied together (externally) at a single point, to ensure si9139 noise immunity. this separation of grounds should be maintained in the external circuitry, with the pow er ground of all power devices being returned directly to the input capacitors, and the small signal ground being returned to the gnd pin of si9139. reset handler the power-good monitor generates a system reset signal. at first power-up (on a/b going high), reset is held low until the a and b outputs are in regulation and beyond the uvlo timer. at this point, an internal timer begins counting oscillator pulses and reset continues to be held low until 32 000 cycles have elapsed. after this timeout period, 107 ms at 300 khz, reset is actively pulled up to v l , when the recommended 20 k resistor to v l is on the reset pin. output overvoltage protection the a and b smps outputs are mo nitored for overvoltage. if either output is more than 10 % above the nominal regulation point, all low-side gate drivers are latched high until on a and on b are toggled. this action turns on the synchronous rectifier mosfets with a 100 % du ty cycle, in turn rapidly discharging the output capacitors and forcing all smps outputs to ground. output undervoltage protection in si9139, each of the a and b smps outputs has an undervoltage protection circuit t hat is activated 6,144 clock cycles (20.48 ms) after the smps is enabled. if either smps output is typically under 70 % of the nominal value, all smpss are latched off and their outputs are clamped to ground by the synchronous rectifier mosfets. the smps will not restart until both on a and on b are toggled. stability: buck converters: in order to simplify designs, the a and b supplies do not require external frequency compensation. meanwhile, it achieves excellent regulation and efficiency. the converters are current mode control, wit h a bandwidth substantially higher than the lc tank dominant pole frequency of the output filter. to ensure stability, the minimum capacitance and maximum esr values are: other outputs the si9139 also provides a 3.3 v reference which can be externally loaded up to 1 ma, as well as, a 5 v ldo output which can be loaded up to 30 ma, or even more depending on the system application. for stability, the 3.3 v reference output requires a 1 f capac itor, and the 5 v ldo output requires a 10 f capacitor. vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71841 . c load v ref 2 out xxr cs x vbw esr v out xr cs v ref
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.

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