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integrated silicon solution, inc. www.issi.com 1 rev. 00a 12/16/09 is24c04b is24c04b 2-wire 4kb serial eeprom
2 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b t able of contents 1 f eatures .........................................................................................................3 2 description ....................................................................................................4 3 pin conf iguration .......................................................................................5 4 pin descriptions ..........................................................................................6 5 block diagram .............................................................................................7 6 device operatio n ........................................................................................8 7 timi n g diagrams ..........................................................................................11 8 absolute maximum rati ngs ...................................................................15 9 dc electrical characteristics ..........................................................16 10 ac electrical characteristics ........................................................17 11 ordering inf ormation ...........................................................................18 12 package i nf ormation ..............................................................................19 13 revision history .......................................................................................22
integrated silicon solution, inc. www.issi.com 3 rev. 00a 12/16/09 is24c04b 4k-bit 2-wire serial cmos eeprom 2 description the is24c04b is an industrial standard electrically erasable programmable read only memory (eeprom) device that utilizes the industrial standard 2-wire in - terface for communications. the is24c04b contains a memory array of 4k bits (512x8), which is organized in 16-byte per page. the eeprom operates in a wide voltage range from 1.8v to 5.5v, which fts most application. the product provides low-power operations and low standby current. the device is offered in lead-free, rohs, halogen free or green package. the available package types are 8-pin soic/sop, tssop and udfn. the is24c04b is compatible to the standard 2-wire bus protocol. the simple bus consists of serial clock (scl) and serial data (sda) signals. utilizing such bus protocol, a master device, such as a microcontroller, can usually control one or more slave devices, alike this is24c04b. the bit stream over the sda line includes a series of bytes, which identifes a particular slave de - vice, an instruction, an address within that slave device, and a series of data, if appropriate. the is24c04b also has a write protect function via wp pin to cease from overwriting the data stored inside the memory array. in order to refrain the state machine entering into a wrong state during power-up sequence or a power toggle off-on condition, a power on reset circuit is em - bedded. during power-up, the device does not respond to any instructions until the supply voltage (vcc) has reached an acceptable stable level above the reset threshold voltage. once vcc passes the power on reset threshold, the device is reset and enters into the stand - by mode. this would also avoid any inadvertent write operations during power-up stage. during power-down process, the device will enter into standby mode, once vcc drops below the power on reset threshold voltage. in addition, the device will be in standby mode after receiving the stop command, provided that no internal write operation is in progress. nevertheless, it is illegal to send an command unless the vcc is within its operat - ing level. 1 f eatures ? two-wire serial interface, i 2 c tm compatible C bi-directional data transfer protocol ? wide-voltage operation C vcc = 1.8v to 5.5v ? speed: 400 khz (1.8v) and 1 mhz (2.5v~5.5v) ? standby current: 1 ma (max.), 1.8v ? operating current: 3 ma (max.), 5.5v ? hardware data protection C write protect pin ? sequential & random read features ? memory organization: 4kb (512 x 8) ? page size: 16 bytes ? page write mode C partial page writes allowed ? self timed write cycle: 5 ms (max.) ? noise immunity on inputs, besides schmitt trig- ger ? high-reliability C endurance: 1 million cycles C data retention: 100 years ? industrial temperature grade ? packages: soic/sop, tssop and udfn ? lead-free, rohs, halogen free, green copyright ? 2009 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equip - ment, aerospace or military, or for other applications planned to support or sustain life. it is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and prior placing orders for products. advanced information january 2010
4 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b scl this input clock pin is used to synchronize the data transfer to and from the device. sda the sda is a bi-directional pin used to transfer addresses and data into and out of the device. the sda pin is an open drain output and can be wired with other open drain or open collector outputs. however, the sda pin requires a pull-up resistor connected to the power supply. a0, a1, a2 the a0, a1 and a2 are the device address inputs. for is24c04b, the a1 and a2 pins are address inputs, but a0 is no-connect. internally, the a0 is foated, while a1 and a2 are defaulted to zero. thus, a total of 4 devices can be connected on a single bus system. 3 pin configuration 8-pin soic, tssop 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 4 pin descriptions a0-a2 address inputs sda serial address/data i/o scl serial clock input wp write protect input vcc power supply gnd ground wp wp is the write protect pin. while the wp pin is connected to the power supply of is24c04b, the entire array becomes write protected (i.e. the device becomes read only). when wp is tied to ground or left foating, the normal write operations are allowed. vcc supply voltage gnd ground of supply voltage 8-pad udfn (top view) 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda
integrated silicon solution, inc. www.issi.com 5 rev. 00a 12/16/09 is24c04b > control logic x decoder slave address register & comparator word address counter high voltage generator, timing & control eeprom array y decoder data register clock di/o ack 8 5 6 7 4 gnd wp scl sda vcc nmos 1 2 3 a2 a1 a0 5 functional block diagram
6 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b 6 device operatio n the is24c04b serial interface supports communications using industrial standard 2-wire bus protocol, such as i 2 c tm . 2-wire bus the two-wire bus is defned as serial data (sda), and serial clock (scl). the protocol defnes any device that sends data onto the sda bus as a transmitter, and the receiving devices as receivers. the bus is controlled by master device that generates the scl, controls the bus access, and generates the start and stop conditions. the is24c04b is the slave device. the bus protocol: data transfer may be initiated only when the bus is not busy. during a data transfer, the sda line must remain stable whenever the scl line is high. any changes in the sda line while the scl line is high will be interpreted as a start or stop condition. the state of the sda line represents valid data after a start condition. the sda line must be stable for the duration of the high period of the clock signal. the data on the sda line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated by a stop condition. start condition the start condition precedes all commands to the device and is defned as a high to low transition of sda when scl is high. the eeprom monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defned as a low to high transition of sda when scl is high. all operations must end with a stop condition. acknowledge (ack) after a successful data transfer, each receiving device is required to generate an ack. the acknowledging device pulls down the sda line. reset the is24c04b contains a reset function in case the 2-wire bus transmission is accidentally interrupted (e.g. a power loss), or needs to be terminated mid-stream. the reset is initiated when the master device creates a start condition. to do this, it may be necessary for the master device to monitor the sda line while cycling the scl up to nine times. (for each clock signal transition to high, the master checks for a high level on sda.) standby mode while in standby mode, the power consumption is minimal. the is24c04b enters into standby mode during one of the following conditions: a) after power-up, while no opcode is sent; b) after the completion of an operation and followed by the stop signal, provided that the previous operation is not write related; or c) after the completion of any internal write operations.
integrated silicon solution, inc. www.issi.com 7 rev. 00a 12/16/09 is24c04b page write the is24c04b is capable of 16-byte page-write operation. a page-write is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the frst data word is transferred, the master device can transmit up to 15 more bytes. after the receipt of each data word, the eeprom responds immediately with an ack on sda line, and the four lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. if a byte address is incremented from the last byte of a page, it returns to the frst byte of that page. if the master device should transmit more than 16 bytes prior to issuing the stop condition, the address counter will roll over, and the previously written data will be overwritten. once all 16 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the is24c04b in a single write cycle. all inputs are disabled until completion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the is24c04b initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the eeprom is still busy with the write operation, no ack will be returned. if the is24c04b has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write operatio n byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/w set to zero) to the slave device. after the slave generates an ack, the master sends the byte address that is to be written into the address pointer of the is24c04b. after receiving another ack from the slave, the master device transmits the data byte to be written into the address memory location. the is24c04b acknowledges once more and the master generates the stop condition, at which time the device begins its internal programming cycle. while this internal cycle is in progress, the device will not respond to any request from the master device. device addressing the master begins a transmission by sending a start condition, then sends the address of the particular slave devices to be communicated. the slave device address is 8 bits format as shown in fig. 5. the four most signifcant bits of the slave address are fxed (1010) for is24c04b. the next three bits, a1, a2 and b0 of the slave address are specifcally related to eeprom. up to four is24c04b units may be connected to the 2-wire bus. the bits a1 and a2 are used to compare with the hardwired input values on both a1 and a2 pins. while bit b0 is being employed to address either the upper or the lower 256 bytes of the device. the last bit of the slave address specifes whether a read or write operation is to be performed. when this bit is set to 1, read operation is selected. while it is set to 0, write operation is selected. after the master transmits the start condition and slave address byte appropriately, the associated 2-wire slave device, is24c04b, will respond with ack on the sda line. then is24c04b will pull down the sda on the ninth clock cycle, signaling that it received the eight bits of data. the is24c04b then prepares for a read or write operation by monitoring the bus.
8 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b read operation read operations are initiated in the same manner as write operations, except that the (r/w) bit of the slave address is set to 1. there are three read operation options: current address read, random address read and sequential read. current address read the is24c04b contains an internal address counter which maintains the address of the last byte accessed, incremented by one. for example, if the previous operation is either a read or write operation addressed to the address location n, the internal address counter would increment to address location n+1. when the eeprom receives the slave addressing byte with a read operation (r/w bit set to 1), it will respond an ack and transmit the 8-bit data byte stored at address location n+1. the master should not acknowledge the transfer but should generate a stop condition so the is24c04b discontinues transmission. if 'n' is the last byte of the memory, the data from location '0' will be transmitted. (refer to figure 8. current address read diagram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device frst performs a 'dummy' write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the is24c04b acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/w bit set to one. the eeprom then responds with its ack and sends the data requested. the master device does not send an ack but will generate a stop condition. (refer to figure 9. random address read diagram.) sequential read sequential reads can be initiated as either a current address read or random address read. after the is24c04b sends the initial byte sequence, the master device now responds with an ack indicating it requires additional data from the is24c04b. the eeprom continues to output data for each ack received. the master device terminates the sequential read operation by pulling sda high (no ack) indicating the last data word to be read, followed by a stop condition. the data output is sequential, with the data from address n followed by the data from address n+1,n+2 ... etc. the address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operation. when the memory address boundary of the array is reached, the address counter rolls over to address 0, and the device continues to output data. (refer to figure 10. sequential read diagram).
integrated silicon solution, inc. www.issi.com 9 rev. 00a 12/16/09 is24c04b stop condition scl sda start condition figure 3. start and stop conditions scl sda master transmitter/ receiver is24cxx vcc figure 1. typical system b us conf iguration t aa data output from transmitter scl from master data output from receiver 18 9 ack t aa figure 2. output a ckn owledge 7 timing diagrams
10 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b figure 5. s lave address figure 4. d ata v alidity p rotocol scl sda data stable data stable data change figure 6. byte write sda bus activity s t a r t m s b l s b m s b w r i t e s t o p r/w a c k a c k a c k data device address byte address * 7 bit 4 3 1 2 5 6 0 r/w b0 a1 a2 0 1 0 1 * = don't care bit for is24c01b
integrated silicon solution, inc. www.issi.com 11 rev. 00a 12/16/09 is24c04b figure 9. random address read sda bus activity a c k a c k a c k data n byte address (n) device address dummy write device address s t a r t w r i t e r e a d s t a r t s t o p m s b l s b n o a c k r/w * figure 7. p age w rite sda bus activity s t a r t m s b l s b w r i t e a c k a c k a c k a c k data (n+1) data (n) byte address (n) device address s t o p a c k data (n+7) r/w * figure 8. current address read sda bus activity s t a r t m s b l s b n o a c k r e a d s t o p a c k data device address r/w * = don't care bit for is24c01b * = don't care bit for is24c01b
12 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b figure 10. seq uential read s t o p n o a c k a c k a c k a c k a c k data byte n+x data byte n+1 data byte n data byte n+2 r/w sda bus activity device address r e a d
integrated silicon solution, inc. www.issi.com 13 rev. 00a 12/16/09 is24c04b ac wave forms f igure 11. bus timing t su:sta t f t high t low t r t su:sto t buf t dh t aa t hd:sta t hd:dat t su:dat scl sda in sda out t su:wp t hd:wp wp 8th bit ack word n stop condition start condition t wr scl sda f igure 12. write cycle timing
14 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b 8 absolute maximum rati ngs (1) notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation - al sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability symbol parameter value unit vs supply voltage to v v p a p t b i a s t u b t s t g s t i o u t o a operating range range ambient temperature (t a ) vcc industrial c to c v to v note: issi offers industrial grade for commercial applications (0 capacitance (1,2) symbol parameter conditions max unit c i n i in i / o i /o i/o n 1. tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. test conditions: ta = 25c, f = 1 mhz, vcc = 5.0v.
integrated silicon solution, inc. www.issi.com 15 rev. 00a 12/16/09 is24c04b 9 dc electrical characteristics industrial (t a = -40 o c to +85 o c), vcc = 1.8v ~ 5.5v symbol parameter [1] vcc test conditions min. max. unit vcc supply voltage 1.8 5.5 v v i h input high voltage (sda, scl, wp) 0.7 * vcc vcc + 1 v v i l input low voltage (sda, scl, wp) -1 0.3 * vcc v i l i input leakage current (sda, scl, wp, a0, a1 & a2) 5v v i n = 0v ~ vcc, standby mode 2 a i l o output leakage current 5v v o u t = 0v~vcc, sda in hi-z 2 a v o l 1 output low voltage 1.8v i o l = 0.15 ma 0.2 v v o l 2 output low voltage 3v i o l = 2.1 ma 0.4 v i sb1 standby current 1.8v v i n = vcc or gnd 1 a 2.5v v i n = vcc or gnd 1 a 5.5v v i n = vcc or gnd 3 a icc 1 read current 1.8v read at 400 khz 0.8 ma 4.5v read at 1 mhz 2 ma 5.5v read at 1 mhz 2 ma i c c 2 write current 1.8v write at 400 khz 1 ma 4.5v write at 1 mhz 3 ma 5.5v write at 1 mhz 3 ma notes: [1] the parameters are characterized but not 100% tested.
16 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b 10 ac electrical characteristics industrial (t a = -40 o c to +85 o c), supply voltage = 1.8v to 5.5v symbol parameter [1] [2] 1.8v vcc < 2.5v 2.5v vcc < 4.5v 4.5v vcc 5.5v unit min. max. min. max. min. max. f s c l sck clock frequency 400 1000 1000 khz t l o w clock low period 1200 400 400 ns t h i g h clock high period 600 400 400 ns t r scl and sda rise time 300 300 300 ns t f scl and sda fall time 300 100 100 ns t s u : s t a start condition setup time 500 200 200 ns tsu:sto stop condition setup time 500 200 200 ns t h d : s t a start condition hold time 500 200 200 ns t s u : d a t data in setup time 100 40 40 ns t h d : d a t data in hold time 0 0 0 ns t a a clock to output access time (scl low to sda data out valid) 100 900 50 400 50 400 ns t d h data out hold time (scl low to sda data out change) 100 50 50 ns t w r write cycle time 5 5 5 ms t b u f bus free time before new transmission 1000 400 400 ns t s u : w p wp pin setup time 1000 400 400 ns t h d : w p wp pin hold time 1000 400 400 ns t noise suppression time 100 50 50 ns notes: [1] the parameters are characterized but not 100% tested. [2] ac measurement conditions: r l (connects to vcc): 1.3 k (2.5v, 5.0v), 10 k (1.8v) c l = 100 pf input pulse voltages: 0.3 vcc to 0.7 vcc input rise and fall times: 50 ns timing reference voltages: half vcc level
integrated silicon solution, inc. www.issi.com 17 rev. 00a 12/16/09 is24c04b 11 ordering inf ormation industrial range*: C40c to +85c, lead-free voltage range part number* package type* (8-pin) 1.8v to 5.5v IS24C04B-2GLI-TR 150-mil soic (jedec) is24c04b-2zli-tr 3 x 4.4 mm tssop is24c04b-2udli-tr 2 x 3 x 0.55mm udfn * 1. contact issi sales representatives for availability and other package information. 2. the listed part numbers are packed in tape and reel -tr (4k per reel). udfn is 5k per reel. 3. refer to issi website for related declaration document on lead free, rohs, halogen free or green, whichever is applicable. 4. issi offers industrial grade for commercial applications (0 o c to +70 o c).
18 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b 12 package i nf ormation
integrated silicon solution, inc. www.issi.com 19 rev. 00a 12/16/09 is24c04b
20 integrated silicon solution, inc. www.issi.com rev. 00a 12/16/09 is24c04b

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