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k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 1 nov. 1999 document title 4m ddr synchronous sram revision history rev. no. rev. 0.0 rev.0.5 rev.1.0 remark advance preliminary final history initial document. correction on the miss print and the package size. added 4ns cycle time (500mbps). draft data aug. 1998 july. 1999 nov. 1999
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 2 nov. 1999 pin description pin name pin description pin name pin description k, k differential clocks g asynchronous output enable sa synchronous address input tck jtag test clock sa 0 , sa 1 synchronous burst address input tms jtag test mode select dq synchronous data i/o tdi jtag test data input v dd core power supply tdo jtag test data output v ddq output power supply zq output driver impedance control input v ref hstl input reference voltage lbo linear burst order b 1 load external address mode no connect (reserved) b 2 burst r/ w enable v ss gnd b 3 single/double data selection nc no connection kq, kq differential output echo clocks features functional block diagram ? 128kx36 or 256kx18 organizations. ? 2.5v core/1.5v output power supply. ? hstl input and hstl outputs. ? single differential hstl clock. ? synchronous pipeline mode of operation with self-timed late write. ? free running active high and active low echo clock output pin. ? asynchronous output enable. ? registered addresses, burst control inputs and data inputs. ? registered outputs. ? single and double data rate burst read and write. ? 4 count burst operation ? jtag 1149.1 compatible test access port. ? 153(9x17) pin ball grid array package(14mm x 22mm). ? programmable impedance output drivers. organization part number cycle time access time 128kx36 k7d403671m-h25 4 2.4 k7d403671m-h22 44 2.4 k7d403671m-h20 5 2.7 k7d403671m-h16 6 3.3 256kx18 k7d401871m-h25 4 2.4 k7d401871m-h22 44 2.4 k7d401871m-h20 5 2.7 k7d401871m-h16 6 3.3 k, k b 1 b 3 b 2 g register ce memory array 128kx36 data out data in advance control sd/ dd co synchronous internal clock generator ce r/ w ld data output strobe data output enable state machine strobe_out s/a array 2 : 1 mux data in register write buffer w/d array echo clock output 36(or 18)x2 36(or 18)x2 36(or 18)x2 36(or 18)x2 xdin kq, kq data 36(or 18) select & r/ w control output buffer write ce burst counter register address address comparator 2:1 mux dec. 17(or 18) 15(or 16) 15(or 16) 17(or 18) (burst write sa[0:16]( or sa[0:17]) or (256kx18) (2 stage) (2 stage) (burst address) address) clock buffer
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 3 nov. 1999 package pin configurations (top view) k7d403671 (128kx36) 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b dq dq sa v ss b 1 v ss sa dq dq c v ss v ddq sa sa g sa sa v ddq v ss d dq dq n.c v ss v dd v ss nc dq dq e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f dq kq dq v dd v dd v dd dq kq dq g v ss v ddq v ss v ss k v ss v ss v ddq v ss h dq dq dq v dd k v dd dq dq dq j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k dq dq dq v ss b 2 v ss dq dq dq l v ss v ddq v ss lbo b 3 mode v ss v ddq v ss m dq kq dq v dd v dd v dd dq kq dq n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p dq dq nc v ss v dd v ss sa dq dq r v ss v ddq v dd sa sa 1 sa v dd v ddq v ss t dq dq sa v ss sa 0 v ss sa dq dq u v ss v ddq tms tdi tck tdo nc v ddq v ss k7d401871 (256kx18) 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b nc dq sa v ss b 1 v ss sa nc dq c v ss v ddq sa sa g sa sa v ddq v ss d dq nc nc v ss v dd v ss nc dq nc e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f nc kq nc v dd v dd v dd dq nc dq g v ss v ddq v ss v ss k v ss v ss v ddq v ss h dq nc dq v dd k v dd nc dq nc j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k nc dq nc v ss b 2 v ss dq nc dq l v ss v ddq v ss lbo b 3 mode v ss v ddq v ss m dq nc dq v dd v dd v dd nc kq nc n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p nc dq sa v ss v dd v ss sa nc dq r v ss v ddq v dd sa sa 1 sa v dd v ddq v ss t dq nc sa v ss sa 0 v ss sa dq nc u v ss v ddq tms tdi tck tdo nc v ddq v ss
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 4 nov. 1999 function description read operation(single and double) during single read operation, the address is registered during the first clock edge, the internal array is read between this fir st edge and second edge, it is read again in the following cycle from the address increased by burst counter, and data is captured in th e out- put register driven to the cpu during the second clock high edge and third clock high edge. during double read operation, the address is registered during the first clock edge, the internal array is read twice as much as wider than external bits, transfe red to dout buffer sequentially by burst order and the following cycle the same operation occur from address increased by burst counter , and data is captured in the output register driven to the cpu at active high clock edge and active low clock edge. during consecutive read cycles where the address is the same, the data output must be held constant without any glitches. this characteristic is because the sram will be read by devices that will operate slower than the sram frequency and will require mul ti- ple sram cycles to perform a single read operation. write(store) operation all addresses and r/ w are sampled with b 1 and b 2 on the clock rising edge. b 1 and b 2 are low on the rising clock. write address is sampled on the rising clock, one cycle after write address and din have been sampled by the sram during 2 consecutive cycles at each active high and low clock edge and stored to write buffer for next real writing array. actual write is done by using write data buffer on the sram that capture the write addresses on one address write cycles, and write the array on the next address write cycles. the "next address write cycles" can actually be many cycles away, broken by a series of read cycles. the sram is able to write 72 bits per cycle with 2-prefetched write buffer. this alleviates timing penalty of read after write cycle. e cho clock operation to assure the output tracibility, the sram provides the output echo clock, pair of complement clock, which is synchronized with inter- nal data output. during read and write cycle, the echo clock is triggered by internal output clock signal, and transfered to external through sam e struc- tures as output driver in read cycle. bypass read operation since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be done from the location that has not been written yet. for this case, the address comparator check to see if the new read addr ess is the same as the contents of the stored write address latch. if the contents match, the read data must be supplied from the st ored write data latch with standard read timing. if there is no match, the read data comes from the sram array. programmable impedance output buffer operation the designer can program the sram's output buffer impedance by terminating the zq pin to v ss through a precision resistor(rq). the value of rq is five times the output impedance desired. for example, 250 w resistor will give an output impedance of 50 w . the allowable range of rq is between 175 w and 350 w . impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. they may also occur in cycles initiated with g high. in all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the sram. periodic readjustment is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. impedance updates occur no more often than every 32 clock cycles. clock cycles are counted whether the sram is selected or not and proceed regardless of the type of cycle being exe - cuted. therefore, the user can be assured that after 33 continuous read cycles have occurred, an impedance update will occur the next time g are high at a rising edge of the k clock. there are no power up requirements for the sram. however, to guarantee opti- mum output driver impedance after power up, the sram needs 1024 non-read cycles. the k7d403671m and k7d401871m are 4,718,592 bit synchronous pipeline burst mode sram devices. they are organized as 131,072 words by 36 bits for k7d403671m and 262,144 words by 18 bits for k7d401871m, fabricated using samsung's advanced cmos technology. single differential hstl level k clocks are used to initiate the read/write operation and all internal operations are self-timed . at the rising edge of k clock, all addresses and burst control inputs are registered internally. and data inputs are registered at risi ng edges of k clock for a single data controlled mode, or at rising and falling edges of k clock for a dual data controlled mode, in the following cycle after write addresses are asserted. an internal write data buffer allows write data to be stored before loaded into memory core in the next write cycles. data outpu ts are updated from output registers on the rising edges of k clock for a single data controlled mode, or on the rising and falling edg es of the k clock for a dual data controlled mode. read data is referenced to echo clock outputs. the chip is operated with a single + 2.5v power supply and is compatible with hstl input and hstl output. the package is 9x17(153) ball grid array balls on a 1.27mm pitch.
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 5 nov. 1999 4 burst operation for interleaved burs t ( lbo = high) interleaved burst case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 4 burst operation for linear burst ( lbo = low) interleaved burst case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 truth table note : b(both) is din in write cycle and do ut in read cycle. byte write function is not supported. x means "don't care". k g b1 b2 b3 dq operation l h x x x hi-z clock stop - h h l x hi-z no operation, pipeline high-z - l l h h dout load address, single read - l l h l dout load address, double read - h l l h din load address, single write - h l l l din load address, double write - l h h x b increment address, continue burst sequence table
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 6 nov. 1999 note : 1. state transitions ; b 1 =(load address), b 1 =(increment address, continue) b 2 =(read), b 2 =(write) b 3 =(single data rate), b 3 =(double data rate) bus cycle state diagram load new address increment address increment address increment address increment address read sdr write sdr read ddr write ddr b 2 , b 3 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 no op power up b 2 , b 3 b 1 b 2 , b 3 b 1 b 2 , b 3 b 1 b 1 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 7 nov. 1999 recommended dc operating conditions note :1. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 2. v ih (max)dc= v dd +0.3, v ih (max)ac= v dd +1.5v(pulse width 5ns). 3. v il (min)dc= - 0.3v, v il (min)ac=-1.5v(pulse width 5ns). 4. junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperat ure and mounting site thermal impedance. t j =t a + p d x t heta _ja parameter symbol min typ max unit note core power supply voltage v dd 2.4 2.5 2.6 v output power supply voltage v ddq 1.4 1.5 1.6 v input high level voltage v ih v ref +0.1 - v dd + 0.3 v 1, 2 input low level voltage v il -0.3 - v ref -0.1 v 1, 3 input reference voltage v ref 0.6 0.75 1.0 v operating junction temperature t j 20 - 110 c 4 absolute maximum ratings note : power dissipation capability will be dependent upon package characteristics and use environment. see enclosed thermal impedan ce data. stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.5 to 3.5 v output supply voltage relative to v ss v ddq -0.5 to v dd +0.5 v voltage on any pin relative to v ss v in -0.5 to v dd +0.5 v maximum power dissipation p d - w output short-circuit current(per i/o) i out 25 ma storage temperature t str -55 to 125 c dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 10% @v oh =v ddq /2 for 175 w rq 350 w . 4. |i ol |=(v ddq /2)/(rq/5) 10% @v ol =v ddq /2 for 175 w rq 350 w . 5. minimum impedance mode when zq pin is connected to v dd . parameter symbol min max unit note average power supply operating current(x36) (cycle time = t khkh min) i dd4 i dd44 i dd5 i dd6 - 700 650 600 550 ma 1,2 average power supply operating current(x18) (cycle time = t khkh min) i dd4 i dd44 i dd5 i dd6 - 650 600 550 500 ma 1,2 stop clock standby current (v in =v dd -0.2v or 0.2v fixed, clock=low) i sb1 - 50 ma 1 input leakage current (v in =v ss or v dd ) i li -1 1 m a output leakage current (v out =v ss or v ddq except kqx, kqx ) i lo -1 1 m a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v 3 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4 output high voltage(i oh =-0.1ma ) v oh3 v ddq -0.2 v ddq v 5 output low voltage(i ol =0.1ma) v ol3 v ss 0.2 v 5
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 8 nov. 1999 output load(a) output load(b) (for t kqlz , t kqhz , t glqz & t ghqz ) z0=50 w 50 w 0.75v *capacitive load consists of all components ac test conditions (t j =20 to 110 c , v dd =2.4 -2.6v, v ddq =1.4 - 1.6v) parameter symbol value unit note input high/low level v ih /v il 1.25/0.25 v - input reference level v ref 0.75 v - input rise/fall time t r /t f 1.0/1.0 ns - output timing reference level 0.75 v - clock input timing reference level cross point v - output load see below - ac test output load v ref dout zq device under test 250 w 5 pf* v ref dout zq device under test 250 w 0.75v of the tester environment ac characteristics note : 1. see ac test output load figure 2. design target is 0ns parameter symbol -25 -22 -20 -16 unit note min max min max min max min max clock cycle time t khkh 4.0 - 4.4 - 5.0 - 6.0 - ns clock high pulse width t khkl 1.6 - 1.8 - 2.0 - 2.4 - ns clock low pulse width t klkh 1.6 - 1.8 - 2.0 - 2.4 - ns clock to echo clock(kq, kq ) t khke - 2.2 - 2.2 - 2.5 - 3.0 ns 1 echo clock to output valid t keqv - 0.2 - 0.2 - 0.2 - 0.3 ns 1,2 echo clock to output hold t keqx -0.5 - -0.5 - -0.5 - -0.6 - ns 1 echo clock to output low-z t kqlz -0.5 - -0.5 - -0.5 - -0.6 - ns 1 echo clock to output high-z t kqhz - 0.2 - 0.2 - 0.2 - 0.2 - 1 g low to output low-z t glqx 0.5 - 0.5 - 0.5 - 0.5 - ns 1 g high to output high-z t ghqz - 2.2 - 2.2 - 2.7 - 3.3 ns 1 g low to output valid t glqv - 2.2 - 2.2 - 2.7 - 3.3 ns 1 g high to output hold t ghqx 0.5 - 0.5 - 0.5 - 0.5 - ns address setup time t avkh 0.5 - 0.5 - 0.5 - 0.7 - ns address hold time t khax 0.5 - 0.5 - 0.5 - 0.7 - ns burst control setup time t bvkh 0.5 - 0.5 - 0.5 - 0.7 - ns burst control hold time t khbx 0.5 - 0.5 - 0.5 - 0.7 - ns data setup time t dvkh 0.5 - 0.5 - 0.5 - 0.7 - ns data hold time t khdx 0.5 - 0.5 - 0.5 - 0.7 - ns pin capacitance *note : periodically sampled and not 100% tested. (dv=0v, f=1mhz) parameter symbol typ. max unit input pin capacitance c in - 6 pf i/o pin capacitance c i/o - 7 pf clock pin capacitance c clk - 7 pf 0.75v
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 9 nov. 1999 timing waveforms for double data rate cycles (burst length=4) note 1. q 01 refers to output from address a 0 . q 02 refers to output from the next internal burst address following a 0 , etc. 2. outputs are disabled(high-z) one clock cycle after nop detected. 3. doing more than one read continue or write continue will cause the address to wrap around. 4. the second nop cycle is not necessary for correct device operation. however, at high clock frequencies it may be required to prevent bus contention. nop continue k k b1 g sa t khkl t avkh t khax kq nop 1 2 3 4 5 6 7 8 10 12 11 b2 b3 kq dq read (burst of 2) read (burst of 2) read (burst of 2) nop write continue write (burst of 2) (burst of 2) read 9 continue read (burst of 2) read (burst of 2) continue read (burst of 2) a 0 a 1 a 2 a 3 q x2 q 01 q 02 q 03 q 04 q 51 q 52 q 53 q 54 q 11 q 12 d 21 d 23 d 24 d 22 q 31 t bvkh t khbx t kqhz t khke t kqlz t ceqv t keqx t ghqz t dvkh t khdx t glqx t glqv t klkh t khkh t ghqx undefined don t care a 5
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 10 nov. 1999 timing waveforms for single data rate cycles (burst length= 4 ) note : 1. q 01 refers to output from address a 0 . q 02 refers to output from the next internal burst address following a 0 , etc. 2. outputs are disabled(high-z) one clock cycle after nop detected 3. this devices supports cycle lengths of 1, 2, 4. continue(b1=high, b2=high, b3=x) up to three times following a b1 operation. 4. this device will have an address to wrap around if further continues are applied. 5. the second nop cycle is not necessary for correct device operation. however, at high clock frequencies it may be required to prevent bus contention. nop continue t khkh t avkh t khax nop 1 2 3 4 5 6 7 8 10 12 11 read (burst of 2) read (burst of 2) read (burst of 2) nop write continue write (burst of 2) (burst of 2) read 9 continue read (burst of 2) continue read (burst of 2) continue read (burst of 2) a 0 a 1 a 2 a 3 q x1 d 22 d 21 t bvkh t khbx t kqhz t khke t kqlz t keqv t keqx t ghqz t ghqx t dvkh t khdx t glqx t glqv t klkh q 31 q 01 q 02 q 03 q 04 q 11 undefined don t care t khkl k k b1 g sa b2 b3 dq kq kq
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 11 nov. 1999 ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible teat access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction register, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power- up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controll er without interfacing with normal operation of the sram. tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo sa(5r) sa(4r) tdi tms tck jtag instruction coding note : 1. places dqs,kqx, kqx in hi-z in order to sample all input data regard- less of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction dose not places dqs,kqx, kqx in hi-z. ir2 ir1 ir0 instruction tdo output note 0 0 0 sample-z boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 bypass bypass register 3 1 0 0 sample boundary scan register 4 1 0 1 bypass bypass register 3 1 1 0 bypass bypass register 3 1 1 1 bypass bypass register 3
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 12 nov. 1999 id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit (0) 128kx36 0000 00101 00100 xxxxxx 00001001110 1 256kx18 0000 00110 00011 xxxxxx 00001001110 1 scan register definition part instruction register bypass register id register boundary scan 128kx36 3 bits 1 bits 32 bits 68 bits 256kx18 3 bits 1 bits 32 bits 49 bits boundary scan exit order(x36) 36 4a sa sa 6a 35 37 4c sa sa 6c 34 38 3a sa sa 7a 33 39 3b sa sa 7b 32 40 3c sa sa 7c 31 41 3d nc 1 nc 1 7d 30 42 2b dq dq 8b 29 43 1b dq dq 9b 28 44 2d dq dq 8d 27 45 3f dq dq 7f 26 46 1d dq dq 9d 25 47 2f kq kq 8f 24 48 1f dq dq 9f 23 49 3h dq dq 7h 22 50 2h dq dq 8h 21 51 1h dq dq 9h 20 52 5a zq g 5c 19 53 5b b1 k 5g 18 54 5k b2 k 5h 17 55 5l b3 mode 2 6l 16 56 4l lbo dq 9k 15 57 1k dq dq 8k 14 58 2k dq dq 7k 13 59 3k dq dq 9m 12 60 1m dq kq 8m 11 61 2m kq dq 9p 10 62 1p dq dq 7m 9 63 3m dq dq 8p 8 64 2p dq dq 9t 7 65 1t dq dq 8t 6 66 2t dq sa 7p 5 67 3t sa sa 7t 4 68 4r sa sa 6r 3 sa 0 5t 2 sa 1 5r 1 boundary scan exit order(x18) 26 4a sa sa 6a 25 27 4c sa sa 6c 24 28 3a sa sa 7a 23 29 3b sa sa 7b 22 30 3c sa sa 7c 21 31 3d nc 1 nc 1 7d 20 32 2b dq dq 9b 19 dq 8d 18 dq 7f 17 33 1d dq 34 2f kq dq 9f 16 35 3h dq dq 8h 15 36 1h dq 37 5a zq g 5c 14 38 5b b1 k 5g 13 39 5k b2 k 5h 12 40 5l b3 mode 2 6l 11 41 4l lbo dq 9k 10 42 2k dq dq 7k 9 43 1m dq kq 8m 8 dq 9p 7 44 3m dq 45 2p dq 46 1t dq dq 8t 6 47 3p sa sa 7p 5 48 3t sa sa 7t 4 49 4r sa sa 6r 3 sa 0 5t 2 sa 1 5r 1 note : 1. pins 7d/3d are no connection pins to internal chip and place holders for 8m/16m parts. the scanned data are fixed to ?1? for this 4m part. 2. mode pin 6l is no connection pin to internal chip. the scanned data is fixed to ?1?.
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 13 nov. 1999 jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification. parameter symbol min typ max unit note power supply voltage v dd 2.4 2.5 2.6 v input high level v ih 1.7 - v dd +0.3 v input low level v il -0.3 - 0.7 v output high voltage(i oh =-2ma) v oh 2.0 - v dd v output low voltage(i ol =2ma) v ol v ss - 0.4 v jtag timing diagram jtag ac test conditions note : 1. see sram ac test output load on page 7 . parameter symbol min unit note input high/low level v ih /v il 2.5/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 1.25 v 1 jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5 - ns tms input hold time t chmx 5 - ns tdi input setup time t dvch 5 - ns tdi input hold time t chdx 5 - ns sram input setup time t svch 5 - ns sram input hold time t chsx 5 - ns clock low to output valid t clqv 0 10 ns tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo t svch t chsx (sram)
k7d401871m 128kx36 & 256kx18 sram k7d403671m rev 1.0 14 nov. 1999 note : 1. all dimensions are in millimeters. 2. solder ball to pcs offset : 0.10 max. 3. pcb to cavity offset : 0.10 max. 153 bga package dimensions 1.27 7 6 5 4 3 2 1 0.050 b c d e f g h j k l m n p r t u a 1 . 2 7 0 . 0 5 0 ? bottom view 0.3/0.012max 153- ? 0.030 0.006 14.00 0.10 0.551 0.004 2 2 . 0 0 0 . 1 0 0 . 8 6 6 0 . 0 0 4 12.50 0.10 0.492 0.004 0.60 0.10 0.024 0.004 2 0 . 5 0 0 . 1 0 0 . 8 0 7 0 . 0 0 4 0.56 0.0 4 0.022 0.002 0.90 0.10 0.035 0.004 2.21 0.087 top view 0.006 0.15 max 0.75 0.15 max 9 8

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