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KS0107B 64ch common driver for dot matrix lcd 1 /20 introduction 100 qfp-1420c the KS0107B is an lcd driver lsi with 64 channel outputs for dot matrix liquid crystal graphic display systems. this device provides 64 shift registers and 64 output drivers. it generates the timing signal to control the ks0108b ( 64 channel segment driver). the KS0107B is fabricated by low power cmos high voltage process technology, and is composed of the liquid crystal display system in combination with the ks0108b (64 channel segment driver). features dot matrix lcd common driver with 64 channel output 64-bit shift register at internal lcd driver circuit internal timing generator circuit for dynamic display selection of master/slave mode 100 tqfp-1414 applicable lcd duty : 1/48, 1/64, 1/96, 1/128 power supply voltage: + 5v 10% lcd driving voltage : 8v~17v (v dd -v ee ) interface driver controller common segment other KS0107B ks0108b mpu high voltage cmos process 100qfp / 100tqfp and bare chip available
KS0107B 64ch common driver for dot matrix lcd 2 /20 block diagram data shift direction & phase selection control circuit 64-bit lcd driver 64-bit bi-directional shift register osc timing generator circuit v dd v ss v ee ds1 ds2 ms fs clk2 clk1 frm cl2 m dio2 v5r v4r v1r v0r c62 c63 c64 c1 c2 c3 v5l v4l v1l v0l dio1 pclk2 shl c r cr fig 1. KS0107B functional block diagram
KS0107B 64ch common driver for dot matrix lcd 3 /20 pin configuration 1. 100qfp fig2. 100 qfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 KS0107B 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 dio2 pclk2 nc m frm nc clk1 clk2 ms nc vss shl nc cr nc r nc c ds2 ds1 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c10 fs dio1 v0l v5l v4l v1l vee c1 c2 c3 c4 c5 c6 c7 c9 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 nc cl2 nc v0r v5r v4r v1r vee c64 c63 c62 61 c60 c59 c58 c57 c56 c55 c54 c53 c52 c51 c50 c49 c48 c47 c46 c45 c44 c43 c42 c41 c40 c39 c38 c37 c36 c35 c34 c33 c32 c31 c30 c29 c28 c27 c26 c25 c24 c23 vdd c8
KS0107B 64ch common driver for dot matrix lcd 4 /20 pad diagram ( chip layout for the 100qfp ) 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 40 50 52 49 47 46 44 43 42 39 37 35 33 32 31 30 29 28 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 KS0107B ( 0, 0 ) x y chip size : 3450 4000 pad size : 100 100 unit : m m * there is the mark KS0107B on the center of the chip
KS0107B 64ch common driver for dot matrix lcd 5 /20 pad location (100qfp) unit ( m m) pad name pad name pad name pad number pad number pad number coordinate coordinate coordinate y y x x y x 1380 1505 1630 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1500.9 1500.9 1500.9 1310.5 1185.5 1060.5 935.5 810.5 685.5 560.5 435.5 310.5 185.5 60.5 -64.5 -189.5 -314.5 -439.5 -564.5 -689.5 -814.5 -939.5 -1064.5 -1189.5 c46 c45 c44 c43 c42 c41 c40 c39 c38 c37 c36 c35 c34 c33 c32 c31 c30 c29 c28 c27 c26 c25 c24 c23 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 37 39 40 42 43 44 46 47 49 50 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1495 -1370 -1245 -1120 -995 -870 -745 -620 -495 -370 -245 -120 5 130 255 380 505 630 755 880 1005 1130 1255 -227.6 -77.6 113.8 308.7 458.7 608.7 758.7 908.7 1058.7 1208.7 1358.7 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 cr shl vss ms clk2 clk1 frm m pclk2 dio2 cl2 v0r v5r v4r v1r vee c64 c63 c62 c61 c60 c59 c58 c57 c56 c55 c54 c53 c52 c51 c50 c49 c48 c47 1775.4 1630 1505 1380 1255 1130 1005 880 775 630 505 380 255 130 5 -120 -245 -370 -495 -620 -745 -870 -995 -1120 -1245 -1370 -1495 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1314.5 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1345.6 -1127.6 -979.6 -827.6 -677.6 -527.6 -377.6 c22 c21 c20 c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 vee v1l v4l v5l v0l vdd dio1 fs ds1 ds2 c r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35
KS0107B 64ch common driver for dot matrix lcd 6 /20 2. 100tqfp fig3. 100 tqfp top view 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 nc cl2 nc dio2 pclk2 nc m frm nc clk1 clk2 ms nc vs s shl nc cr nc r nc v0r v5r v4r v1r v ee c64 c63 c62 c61 c60 c59 c58 c57 c56 c55 c54 c53 c52 c51 c50 c49 c48 c47 c46 c45 c39 c38 c37 c36 c35 c34 c33 c32 c31 c30 c29 c28 c27 c26 c25 c24 c23 c22 c21 c20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c7 v dd v0l v5l v4l v1l v ee c1 c2 c3 c4 c6 26 27 28 29 30 c ds2 fs di01 ds1 c5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 79 80 77 78 76 c40 c41 c42 c43 c44 KS0107B
KS0107B 64ch common driver for dot matrix lcd 7 /20 pad diagram (chip layout for the 100tqfp) * there is the mark KS0107Btq on the center of the chip. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 KS0107Btq ( 0, 0 ) x y chip size : 3850 4100 pad size : 100 100 unit : m m 47 49 46 44 43 41 40 39 37 36 34 32 30 29 28 26 27 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
KS0107B 64ch common driver for dot matrix lcd 8 /20 pad location (100tqfp) coordinate coordinate coordinate pad num pad name x y pad num pad name x y pad num pad name x y 1 c19 -1697 1534 47 dio2 1095 -1821 93 c27 -625 1822 2 c18 -1697 1409 48 nc 94 c26 -750 1822 3 c17 -1697 1284 49 cl2 1245 -1821 95 c25 -875 1822 4 c16 -1697 1159 50 nc 96 c24 -1000 1822 5 c15 -1697 1034 51 v0r 1697 -1466 97 c23 -1125 1822 6 c14 -1697 909 52 v5r 1697 -1341 98 c22 -1250 1822 7 c13 -1697 784 53 v4r 1697 -1216 99 c21 -1375 1822 8 c12 -1697 659 54 v1r 1697 -1091 100 c20 -1500 1822 9 c11 -1697 534 55 vee 1697 -966 10 c10 -1697 409 56 c64 1697 -841 11 c9 -1697 284 57 c63 1697 -716 12 c8 -1697 159 58 c62 1697 -591 13 c7 -1697 34 59 c61 1697 -466 14 c6 -1697 -91 60 c60 1697 -341 15 c5 -1697 -216 61 c59 1697 -216 16 c4 -1697 -341 62 c58 1697 -91 17 c3 -1697 -466 63 c57 1697 34 18 c2 -1697 -591 64 c56 1697 159 19 c1 -1697 -716 65 c55 1697 284 20 vee -1697 -841 66 c54 1697 409 21 v1l -1697 -966 67 c53 1697 534 22 v4l -1697 -1091 68 c52 1697 659 23 v5l -1697 -1216 69 c51 1697 784 24 v0l -1697 -1341 70 c50 1697 909 25 vdd -1697 -1466 71 c49 1697 1034 26 dio1 -1245 -1821 72 c48 1697 1159 27 fs -1095 -1821 73 c47 1697 1284 28 ds1 -945 -1821 74 c46 1697 1409 29 ds2 -795 -1821 75 c45 1697 1534 30 c -645 -1821 76 c44 1500 1822 31 nc 77 c43 1375 1822 32 r -495 -1821 78 c42 1250 1822 33 nc 79 c41 1125 1822 34 cr -345 -1821 80 c40 1000 1822 35 nc 81 c39 875 1822 36 shl -195 -1821 82 c38 750 1822 37 vss 0 -1821 83 c37 625 1822 38 nc 84 c36 500 1822 39 ms 195 -1821 85 c35 375 1822 40 clk2 345 -1821 86 c34 250 1822 41 clk1 495 -1821 87 c33 125 1822 42 nc 88 c32 0 1822 43 frm 645 -1821 89 c31 -125 1822 44 m 795 -1821 90 c30 -250 1822 45 nc 91 c29 -375 1822 46 pclk2 945 -1821 92 c28 -500 1822 unit ( m m)
KS0107B 64ch common driver for dot matrix lcd 9 /20 pin description pin num qfp(tqfp) symbol input/output description 28(25) 40(37) 23(20),58(55) v dd v ss v ee power for internal logic circuit (+5v 10%) gnd ( = 0 v) for lcd driver circuit 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) v0l, v0r v1l, v1r v4l, v4r v5l, v5r power bias supply voltage terminals to drive lcd. v0l and v0r (v1l & v1r, v4l & v4r, v5l & v5r) should be connected by the same voltage. 42(39) ms input selection of master/slave mode i) master mode (ms=1) dio1, dio2, cl2 and m is output state. ii) slave mode (ms=0) shl=1 ? dio1 is input state (dio2 is output state) shl=0 ? dio2 is input state (dio1 is output state) cl2 and m are input state. 39(36) shl input selection of data shift direction. 49(46) pclk2 input selection of shift clock (cl2) phase. 30(27) fs input selection of oscillation frequency. i) master mode when the frame frequency is 70 hz, the oscillation frequency should be fosc=430 khz at fs=1 (v dd ) fosc=215 khz at fs=0 (v ss ) ii) slave mode connect to v dd . 31(28) 32(29) ds1 ds2 input selection of display duty. i) master mode ii) slave mode connect to v dd . select level non-select level v0l(r), v5l(r) v1l(r), v4l(r) shl data shift direction h dio1 ? c1 ? ...... ? c64 ? dio2 l dio2 ? c64 ? ...... ? c1 ? dio1 pclk2 shift clock (cl2) phase h data shift at the rising edge of cl2 l data shift at the falling edge of cl2 ds1 ds2 duty l l 1/48 l h 1/64 h l 1/96 h h 1/128
KS0107B 64ch common driver for dot matrix lcd 10 /20 pin description (continued) pin num qfp(tqfp) symbol input/output description 33(30) 35(32) 37(34) c r cr rc oscillator i) master mode : use these terminals as shown below. ii) slave mode : stop the oscillator as shown below. 44(41), 43(40) clk1 clk2 output operating clock output for the ks0108b i) master mode : connection to clk1 and clk2 of the ks0108b ii) slave mode : open 46(43) frm output synchronous frame signal. i) master mode : connection to frm of the ks0108b ii) slave mode : open 47(44) m input / output alternating signal input for lcd driving. i) master mode : output state connection to m of the ks0108b ii) slave mode : input state connection to the controller 52(49) cl2 input / output data shift clock i) master mode : output state connection to cl of the ks0108b ii) slave mode : input state connection to shift clock terminal of the controller. 29(26) 50(47) dio1 dio2 input / output data input/output pin of internal shift register. 22~1 (19~1) 100~59 (100~56) c1~c64 output common signal output for lcd driving. 34(31),36(33) 38(35),41(38) 45(42),48(45) 51(48),53(50) nc no connection ms shl dio1 dio2 h h output output l output output l h input output l output input data m out l l v 1 l h v 4 h l v 5 h h v 0 c cr r KS0107B r f c f c cr r KS0107B open open external clock c cr r KS0107B open v dd open
KS0107B 64ch common driver for dot matrix lcd 11 /20 maximum absolute limit characteristic symbol value unit note operating voltage v dd -0.3~+7.0 v *1 supply voltage v ee v dd -19.0~v dd +0.3 v *4 driver supply voltage v b -0.3~v dd +0.3 v *1,2 v lcd v ee -0.3~v dd +0.3 v *3,4 operating temperature t opr -30~+85 c - storage temperature t stg -55~+125 c - *1. based on v ss =0 v *2. applies to input terminals and i/o terminals at high impedance. (except v0l(r), v1l(r), v4l(r) and v5l(r)) *3. applies to v0l(r), v1l(r), v4l(r) and v5l(r). *4. voltage level: v dd 3 v0l= v0r 3 v1l= v1r 3 v4l= v4r 3 v5l= v5r 3 v ee . electrical characteristics dc characteristics (v dd =+5v 10%, v ss =0v, |v dd -v ee |=8~17v, t a = -30 ~ +85 c) characteristic symbol condition min typ max unit note input high v ih - 0.7v dd - v d d v *1 voltage low v il v ss - 0.3v dd output high v oh i oh =-0.4 ma v dd -0.4 - - v *2 voltage low v ol i ol =0.4 ma - - 0.4 input leakage current i lkg v in =v dd ~v ss -1.0 - 1.0 m a *1 osc frequency f osc rf=47 k w 2% cf=20pf 5% 315 450 585 khz on resistance ( vdiv-ci) r on v dd -v ee =17v load current = 150 m a - - 1.5 k w operating current i dd1 master mode 1/128 duty - - 1.0 ma *3 i dd2 slave mode 1/128 duty - - 200 m a *4 supply current i ee master mode 1/128 duty - - 100 *5 operating f op1 master mode external clock 50 - 600 khz frequency f op2 slave mode 0.5 - 1500 *1. applies to input terminals fs, ds1, ds2, cr, shl, ms and pclk2 and i/o terminals dio1, dio2, m and cl2 in the input state. *2. applies to output terminals clk1, clk2 and frm and i/o terminals dio1, dio2, m and cl2 in the output state. *3. this value is specified at about the current flowing through v ss . internal oscillation circuit: rf=47 k w , cf=20 pf each terminal of ds1, ds2, fs, shl and ms is connected to v dd and out is no load. *4. this value is specified at about the current flowing through v ss . each terminal of ds1, ds2, fs, shl, pclk2 and cr is connected to v dd , and ms is connected to v ss. cl2, m, dio1 is external clock. *5. this value is specified at about the current flowing through v ee . don ? t connect to v lcd (v1~v5).
KS0107B 64ch common driver for dot matrix lcd 12 /20 ac characteristics (vdd=5v 10%, ta=-30 c~+85 c) 1. master mode (ms=v dd , pclk2=v dd , cf=20 pf, rf=47 k w ) characteristic symbol min typ max unit data setup time t su 20 - - data hold time t dh 40 - - data delay time t d 5 - - frm delay time t df -2 - 2 m s m delay time t dm -2 - 2 cl2 low level width t wlc 35 - - cl2 high level width t whc 35 - - clk1 low level width t wl1 700 - - clk2 low level width t wl2 700 - - clk1 high level width t wh1 2100 - - clk2 high level width t wh2 2100 - - ns clk1-clk2 phase difference t d12 700 - - clk2-clk1 phase difference t d21 700 - - clk1, clk2 rise/fall time t r / t f - - 150 t wlc t whc t su t whc t dh t d t d t df t dm t dm 0.7v dd 0.3v dd t wh1 t f t r t d21 t wh2 t r t f t di2 t wl1 cl2 dio1 ( shl = v dd ) dio2 ( shl = v ss ) dio2 ( shl = v dd ) dio1 ( shl = v ss ) frm m clk1 clk2 0.7v dd 0.3v dd t su
KS0107B 64ch common driver for dot matrix lcd 13 /20 2. slave mode (ms=v ss ) characteristics symbol min typ max unit note cl2 low level width t wlc1 450 - - ns pclk2=v ss cl2 high level width t whc1 150 - - ns pclk2=v ss cl2 low level width t wlc2 150 - - ns pclk2=v dd cl2 high level width t whl 450 - - ns pclk2=v dd data setup time t su 100 - - ns data hold time t dh 100 - - ns data delay time t d - - 200 ns *1 output data hold time t h 10 - - ns cl2 rise/fall time t r / t f - - 30 ns *1; connect load cl=30 pf 30pf output 0.7v dd 0.3v dd 0.7v dd 0.3v dd t f t r t wlc1 t whc1 t wlc t whc2 t hcl t d t f t r t su t h cl2 ( plk2 = v ss ) cl2 ( plk2 = v dd ) dio1 ( shl = v dd ) dio2 ( shl = v ss ) input data dio1 ( shl = v dd ) dio2 ( shl = v ss ) output data 0.3v dd 0.7v dd
KS0107B 64ch common driver for dot matrix lcd 14 /20 functional description 1. rc oscillator the rc oscillator generates cl2, m, frm of the KS0107B, and clk1 and clk2 of the ks0108b by the oscillation resister r and capacitor c. when selecting the master/slave mode, the oscillation circuit is as following: 1) master mode : in the master mode, use these terminals as shown below. internal oscillation external clock 2) slave mode : in the slave mode, stop the oscillator as shown below. 2. timing generation circuit it generates cl2, m, frm, clk1 and clk2 by the frequency from the oscillation circuit. 1) selection of master/slave (m/s) mode when m/s is ? h ? , it generates cl2, m, frm, clk1 and clk2 internally. when m/s is ? l ? , it operates by receiving m and cl2 from the master device. 2) frequency selection (fs) to adjust frm frequency by 70 hz, the oscillation frequency should be as follows: fs oscillation frequency h f osc =430 khz l f osc =215 khz in the slave mode, it is connected to v dd . 3) duty selection (ds1, ds2) it provides various duty selections according to ds1 and ds2. ds1 ds2 duty l l 1/48 h 1/64 h l 1/96 h 1/128 KS0107B r cr c open external clock open KS0107B r cr c open open v dd KS0107B r cr c r f c f 47k w 20pf
KS0107B 64ch common driver for dot matrix lcd 15 /20 3. data shift & phase select control 1) phase selection it is a circuit to shift data on synchronization or rising edge, or falling edge of the cl2 according to pclk2. pclk2 phase selection h data shift on rising edge of cl2 l data shift on falling edge of cl2 2) data shift direction selection when m/s is connected to v dd , dio1 and dio2 terminal is only output. when m/s is connected to v ss , it depends on the shl. ms shl dio1 dio2 direction of data h h output output c1 ? c64 l output output c64 ? c1 l h input output dio1 ? c1 ? c64 ? dio2 l output input dio2 ? c64 ? c1 ? dio1
KS0107B 64ch common driver for dot matrix lcd 16 /20 timing diagram 1. 1/48 duty timing (master mode) condition: ds1=l, ds2=l, shl=h(l), pclk2=h - relation of cl2 & dio1 ( dio2 ) c clk1 clk2 cl2 frm dio1 ( dio2 ) m c1 ( c48 ) c2 ( c47 ) c47 ( c2 ) c48 ( c1 ) dio2 ( dio1 ) clk2 cl2 dio1 ( dio2 ) 1 2 3 63 64 1 2 3 46 47 48 1 2 3 46 47 48 v1 v4 v0 v4 v4 v5 v1 v0 v4 v1 v1 v1 v4 v5 v0 v4 v1 v5 v5 v1 v4 v4 v5 v1 v0 v4 v5 v1 v0 v1
KS0107B 64ch common driver for dot matrix lcd 17 /20 2. 1/128 duty timing (master mode) condition: ds1=h, ds2=h, shl=h(l), pclk2=h c clk1 clk2 cl2 frm dio1 ( dio2 ) m c1 ( c48 ) c2 ( c47 ) c47 ( c2 ) c48 ( c1 ) dio2 ( dio1 ) clk2 cl2 dio1 ( dio2 ) 1 2 3 23 24 1 2 3 126 127 128 1 2 3 126 127 128 v0 v1 v1 v4 v0 v4 v4 v5 v1 v0 v4 v1 v1 v1 v4 v5 v0 v4 v1 v5 v5 v1 v4 v4 v5 v1 v0 v4 v5 v1 - relation of cl2 & dio1 ( dio2 )
KS0107B 64ch common driver for dot matrix lcd 18 /20 3. 1/48 duty timing (slave mode) condition: pclk2=l, shl=h(l) 1 2 46 47 48 1 2 46 47 48 v0 v1 v5 v4 v0 v1 v1 v4 v0 v4 v1 v5 v1 v4 v1 v4 v0 v4 v1 v5 v1 v4 v4 v5 v1 v0 v4 v5 cl2 m dio1 ( dio2 ) c1 ( c48 ) c2 ( c47 ) c47 ( c2 ) c48 ( c1 ) dio2 ( dio1 ) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
KS0107B 64ch common driver for dot matrix lcd 19 /20 4. power driver circuit relation of duty & bias duty bias rdiv 1/48 1/8 r2=4r1 1/64 1/9 r2=5r1 1/96 1/11 r2=7r1 1/128 1/12 r2=8r1 *when duty factor is 1/48, the value of r1 & r2 should satisfy. r1/(4r1+r2)=1/8 r1=3 k w , r2=12 k w to ks0108b v0 v1 v2 v3 v4 v5 v dd v ee r1 r1 r2 r1 r1 vr v0l/r v1l/r v4l/r v5l/r v ee v dd KS0107B
KS0107B 64ch common driver for dot matrix lcd 20 /20 application circuit 1/128 duty segment drive(ks0108b) interface circuit v0r/l v2r/l v3r/l v5r/l v ee rs r/w e rstb db0 ~ db7 cs1b cs2b cs3 v dd frm m clk1 clk2 cl ks0108b v ee v0r/l v2r/l v3r/l v5r/l rs r/w e rstb db0 ~ db7 cs1b cs2b cs3 frm m clk1 clk2 cl ks0108b v dd v ss v ss v0r/l v2r/l v3r/l v5r/l v ee rs r/w e rstb db0 ~ db7 cs1b cs2b cs3 v dd frm m clk1 clk2 cl ks0108b v ss v ee v0r/l v2r/l v3r/l v5r/l rs r/w e rstb db0 ~ db7 cs1b cs2b cs3 frm m clk1 clk2 cl ks0108b v dd v ss lcd panel com1 com128 v dd shl fs ms pclk2 ds2 ds1 r cr c c1 c64 v ss v or/l v ir/l v 4r/l v 5r/l v ee c1 c64 pclk2 fs ds1 ds2 shl dio2 dio1 m cl2 v dd vor/l vir/l v4r/l v5r/l v ee v ss ms rs r/w e rstb db0 - db7 cs1b cs2b cs3 open open open open open KS0107B (master) KS0107B (slave) mpu 15 15 5 v dd r f c f 5 2 open open 5 v dd v ee v0 v1 v2 v3 v4 v5 15 15 15 s 1 ~s 64 s 1 ~s 64 s 1 ~s 64 dio1 dio2 cl2 m clk2 clk1 frm clk2 clk1 frm c r cr s 1 ~s 64 seg1 seg128

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