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| rev.3.11 apr 5, 2006 page 1 of 113 rej03b0017-0311 description the 3803 group (spec.h) is the 8-bit microcomputer based on the 740 family core technology. the 3803 group (spec.h) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the a/d converter and d/a converters. features ? basic machine-language instructions ................. ........... ..... 71 ? minimum instruction execution time .......................... 0.24 s (at 16.8 mhz osci llation frequency) ? memory size rom ........................................................ 16 k to 60 k bytes ram ........... ................................. .............. 640 to 2048 bytes ? programmable input/output ports ....................................... 56 ? software pull-up resistors ............................................ built-in ? interrupts 21 sources, 16 vectors............................................................... (external 8, internal 12, software 1) ? timers ...................................................................... 16-bit 1 8-bit 4 (with 8-bit prescaler) ? serial interface ......... 8-bit 2 (uart or clock-synchronized) 8-bit 1 (clock-synchronized) ? pwm ....................................... 8-bit 1 (with 8-bit prescaler) ? a/d converter ........ ...................... .......... 10-bit 16 channels (8-bit reading enabled) ? d/a converter .......... ........... ............ ........... 8-bi t 2 channels currently support products are listed below. ? watchdog timer ...................................................... 16-bit 1 ? led direct drive port ............................................................. 8 ? clock generating circuit ............................. built-in 2 circuits (connect to external ceramic resona tor or quartz-crystal oscillator) ? power source voltage [in high-speed mode] at 16.8 mhz oscillation frequency .................... 4.5 to 5.5 v at 12.5 mhz oscillation frequency .................... 4.0 to 5.5 v at 8.4 mhz oscillation frequency ...................... 2.7 to 5.5 v at 4.2 mhz oscillation frequency ...................... 2.2 to 5.5 v at 2.1 mhz oscillation frequency ...................... 2.0 to 5.5 v [in middle-speed mode] at 16.8 mhz oscillation frequency .................... 4.5 to 5.5 v at 12.5 mhz oscillation frequency .................... 2.7 to 5.5 v at 8.4 mhz oscillation frequency ...................... 2.2 to 5.5 v at 6.3 mhz oscillation frequency ...................... 1.8 to 5.5 v [in low-speed mode] at 32 khz oscillation fre quency......................... 1.8 to 5.5 v ? power dissipation in high-speed mode ........................................... 40 mw (typ.) (at 16.8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................ 45 w (typ.) (at 32 khz oscillation frequency, at 3 v power source voltage) ? operating temperature range ............................. ? 20 to 85 c ? packages sp............ ...prdp0064ba-a (64p4b) (64-pin 750 mil sdip) fp .......prqp0064ga-a (64p6n-a) (64-pin 14 14 mm qfp) hp ......plqp0064kb-a (64p6q-a) (64-pin 10 10 mm lqfp) kp ......plqp0064ga-a (64p6u-a) (64-pin 14 14 mm lqfp) wg ........ptlg0064ja-a (64f 0g) (64-pin 6 6 mm flga) note: 1. electrical characteri stics differ by the 3803 group standard versions and the 3803 group (spec.h). since the 3803 group stand ard versions are not indicated to this data sheet, refer to ?3803/3804 group data sheet?. table 1 support products (mask rom version) product name rom size (bytes) rom size for user in ( ) ram size (bytes) package remarks m38034m4h-xxxsp 16384 (16254) 640 prdp0064ba-a (64p4b) m38034m4h-xxxfp prqp0064ga-a (64p6n-a) m38034m4h-xxxhp plqp0064kb-a (64p6q-a) m38034m4h-xxxkp plqp0064ga-a (64p6u-a) m38037m6h-xxxsp 24576 (24446) 1024 prdp0064ba-a (64p4b) m38037m6h-xxxfp prqp0064ga-a (64p6n-a) m38037m6h-xxxhp plqp0064kb-a (64p6q-a) m38037m6h-xxxkp plqp0064ga-a (64p6u-a) m38037m8h-xxxsp 32768 (32638) 1024 prdp0064ba-a (64p4b) m38037m8h-xxxfp prqp0064ga-a (64p6n-a) m38037m8h-xxxhp plqp0064kb-a (64p6q-a) m38037m8h-xxxkp plqp0064ga-a (64p6u-a) m38039mch-xxxsp 49152 (49022) 2048 prdp0064ba-a (64p4b) m38039mch-xxxfp prqp0064ga-a (64p6n-a) m38039mch-xxxhp plqp0064kb-a (64p6q-a) m38039mch-xxxkp plqp0064ga-a (64p6u-a) m38039mfh-xxxsp 61440 (61310) 2048 prdp0064ba-a (64p4b) m38039mfh-xxxfp prqp0064ga-a (64p6n-a) m38039mfh-xxxhp plqp0064kb-a (64p6q-a) m38039mfh-xxxkp plqp0064ga-a (64p6u-a) m38039mfh-xxxwg ptlg0064ja-a (64f0g) 3803 group (spec.h) single-chip 8-bit cmos microcomputer rej03b0017-0311 rev.3.11 apr 5, 2006 3803 group (spec.h) mask rom version
rev.3.11 apr 5, 2006 page 2 of 113 rej03b0017-0311 3803 group (spec.h) description the 3803 group (spec.h) flash memory version is the 8-bit microcomputer based on the 740 family core technology. the 3803 group (spec.h) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the a/d converter and d/a converters. features ? basic machine-language instructions ................. ........... ..... 71 ? minimum instruction execution time .......................... 0.24 s (at 16.8 mhz osci llation frequency) ? memory size flash memory ....................................................... 60 k bytes ram ........... ............................................ ............ .. 2048 bytes ? programmable input/output ports ....................................... 56 ? software pull-up resistors ............................................ built-in ? interrupts 21 sources, 16 vectors............................................................... (external 8, internal 12, software 1) ? timers ...................................................................... 16-bit 1 8-bit 4 (with 8-bit prescaler) ? serial interface ......... 8-bit 2 (uart or clock-synchronized) 8-bit 1 (clock-synchronized) ? pwm ....................................... 8-bit 1 (with 8-bit prescaler) ? a/d converter ........ ...................... .......... 10-bit 16 channels (8-bit reading enabled) ? d/a converter .......... ........... ............ ........... 8-bi t 2 channels ? watchdog timer ....................................................... 16-bit 1 ? led direct drive port..............................................................8 ? clock generating circuit ............................. built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) currently support products are listed below. ? power source voltage in high-speed mode at 16.8 mhz oscillation frequency .................... 4.5 to 5.5 v at 12.5 mhz oscillation frequency .................... 4.0 to 5.5 v at 8.4 mhz oscillation frequency ...................... 2.7 to 5.5 v in middle-speed mode at 16.8 mhz oscillation frequency .................... 4.5 to 5.5 v at 12.5 mhz oscillation frequency .................... 2.7 to 5.5 v in low-speed mode at 32 khz oscillation fre quency......................... 2.7 to 5.5 v ? power dissipation in high-speed mode ........................................ 27.5 mw (typ.) (at 16.8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode . ............ ...................... ..... 1200 w (typ.) (at 32 khz oscillation frequency, at 3 v power source voltage) ? operating temperature range ............................. ? 20 to 85 c ? packages sp............ ...prdp0064ba-a (64p4b) (64-pin 750 mil sdip) fp .........prqp0064ga- a (64p6n-a) (64-pin 14 14 mm qfp) hp ........ plqp0064kb-a (64p6q-a) (64-pin 10 10 mm lqfp) kp ........ plqp0064ga-a (64p6u-a) (64-pin 14 14 mm lqfp) wg ........ ptlg0064ja-a (64f0g) (64-pin 6 6 mm flga) rev.3.11 apr 5, 2006 page 3 of 113 rej03b0017-0311 3803 group (spec.h) fig 1. pin configuration (top view) prqp0064ga-a (64p 6n-a)/plqp0064kb-a (64p6q-a)/plqp0064ga-a (64p6u-a) note: 1. since description, features, and electrical charactristics etc. of m38039fffp and m38039ffhp are not indicated, refer to ?380 3/ 3804 group data sheet?. 48 p2 0 (led 0 ) m38034m4h-xxxfp/hp/kp m38037m6h-xxxfp/hp/kp m38037m8h-xxxfp/hp/kp m38039mch-xxxfp/hp/kp m38039mfh-xxxfp/hp/kp m38039ffhfp/hp/kp 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p3 5 /t x d 3 p3 4 /r x d 3 p3 1 /da 2 p3 0 /da 1 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p3 7 /s rdy3 p3 6 /s clk3 p3 3 p3 2 v ss x out x in p4 2 /int 1 reset cnv ss p4 0 /int 40 /x cout p4 1 /int 00 /x cin p2 7 (led 7 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 1 (led 1 ) p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p6 2 /an 2 p4 7 /s rdy1 /cntr 2 p5 3 /s rdy2 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 6 p1 4 p1 5 p1 7 package type : prqp0064ga-a (64p6n-a)/plqp0064kb-a (64p6q-a)/plqp0064ga-a (64p6u-a) table 3 list of package (prqp0064ga-a (64p6n-a)/plqp0064kb-a (64p6q-a)/plqp0064ga-a (64p6u-a)) package product name rom size (bytes) rom size for user in ( ) ram size (bytes) remarks prqp0064ga-a (64p6n-a) m38034m4h-xxxfp 16384 (16254) 640 mask rom version m38037m6h-xxxfp 24576 (24446) 1024 m38037m8h-xxxfp 32768 (32638) 1024 m38039mch-xxxfp 49152 (49022) 2048 m38039mfh-xxxfp 61440 (61310) 2048 m38039ffhfp 61440 2048 flash memory version m38039fffp 61440 2048 flash memory version (vcc = 4.0 ? 5.5 v) plqp0064kb-a (64p6q-a) m38034m4h-xxxhp 16384 (16254) 640 mask rom version m38037m6h-xxxhp 24576 (24446) 1024 m38037m8h-xxxhp 32768 (32638) 1024 m38039mch-xxxhp 49152 (49022) 2048 m38039mfh-xxxhp 61440 (61310) 2048 m38039ffhhp 61440 2048 flash memory version m38039ffhp 61440 2048 flash memory version (vcc = 4.0 ? 5.5 v) plqp0064ga-a (64p6u-a) m38034m4h-xxxkp 16384 (16254) 640 mask rom version m38037m6h-xxxkp 24576 (24446) 1024 m38037m8h-xxxkp 32768 (32638) 1024 m38039mch-xxxkp 49152 (49022) 2048 m38039mfh-xxxkp 61440 (61310) 2048 m38039ffhkp 61440 2048 flash memory version rev.3.11 apr 5, 2006 page 4 of 113 rej03b0017-0311 3803 group (spec.h) fig 2. pin configuration (top view) (prdp0064ba-a (64p4b)) note: 1. since description, features, and electrical charactristics etc. of M38039FFSP are not indicated, refer to ?3803/3804 group da ta sheet?. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /s rdy2 p5 2 /s clk2 p5 1 /s out2 p4 7 /s rdy1 / cntr 2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss v ss reset p4 1 /int 00 /x cin p4 0 /int 40 /x cout x in x out p5 0 /s in2 p3 0 /da 1 p3 1 /da 2 p3 2 p3 3 p3 4 /r x d 3 p3 5 /t x d 3 p3 6 / s clk3 p3 7 / s rdy3 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 / int 41 p1 1 / int 01 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 (led 0 ) p2 1 (led 1 ) p2 2 (led 2 ) p1 2 p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) m38034m4h-xxxsp m38037m6h-xxxsp m38037m8h-xxxsp m38039mch-xxxsp m38039mfh -xxxsp m38039ffhsp package type : prdp0064ba-a (64p4b) p2 7 (led 7 ) table 4 list of package (spec.h) package product name rom size (bytes) rom size for user in ( ) ram size (bytes) remarks prdp0064ba-a (64p4b) m38034m4h-xxxsp 16384 (16254) 640 mask rom version m38037m6h-xxxsp 24576 (24446) 1024 m38037m8h-xxxsp 32768 (32638) 1024 m38039mch-xxxsp 49152 (49022) 2048 m38039mfh-xxxsp 61440 (61310) 2048 m38039ffhsp 61440 2048 flash memory version M38039FFSP 61440 2048 flash memory version (vcc = 4.0 ? 5.5 v) rev.3.11 apr 5, 2006 page 5 of 113 rej03b0017-0311 3803 group (spec.h) fig 3. pin configuration (top view) (ptlg0064ja-a (64f0g)) 3 2 1 8 7 6 5 4 p6 1 /an 1 p6 0 /an 0 p5 5 /cntr 1 p5 2 /s clk2 p5 0 /s in2 p4 4 /r x d 1 p4 3 /int 2 cnv ss p6 5 /an 5 p6 4 /an 4 p5 6 /pwm p5 3 /s rdy2 p5 1 /s out2 p4 6 /s clk1 p4 2 /int 1 reset p6 7 /an 7 p6 6 /an 6 p5 7 /int 3 p5 4 /cntr 0 p4 7 /s rdy1 /cntr 2 p4 5 /t x d 1 p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 0 /da 1 p3 1 /da 2 p3 2 p3 7 /s rdy3 p1 7 p1 4 p1 5 p1 6 p3 3 p3 4 /r x d 3 p0 0 /an 8 p0 5 /an 13 p1 2 p1 3 p2 6 (led 6 )p2 7 (led 7 ) p3 5 /t x d 3 p0 1 /an 9 p0 3 /an 11 p0 6 /an 14 p1 1 /int 01 p2 5 (led 5 )p2 3 (led 3 )p2 4 (led 4 ) p3 6 /s clk3 p0 2 /an 10 p0 4 /an 12 p0 7 /an 15 p1 0 /int 41 p2 0 (led 0 )p2 1 (led 1 )p2 2 (led 2 ) p6 2 /an 2 p6 3 /an 3 v ref av ss v cc v ss x in x out abcdefgh 3 2 1 8 7 6 5 4 abcdefgh package (top view) 50 46 44 41 40 32 31 30 51 47 45 42 39 27 29 28 53 52 48 43 38 37 26 25 56 55 54 49 33 36 35 34 1 64 58 59 57 24 22 23 60 61 4 7 12 14 21 20 62 63 5 8 10 13 17 19 2 3 6 9 11 15 16 18 pin configuration (top view) package type : ptlg0064ja-a (64f0g) note : the numbers in circles corresponds with the number on the packages fp/hp/kp. m38039mfh -xxxwg m38039 ffhwg table 5 list of package (ptlg0064ja-a (64f0g)) package product name rom size (bytes) rom size for user in ( ) ram size (bytes) remarks ptlg0064ja-a m38039mfh-xxxwg 61440 (61310) 2048 mask rom version m38039ffhwg 61440 2048 flash memory version rev.3.11 apr 5, 2006 page 6 of 113 rej03b0017-0311 3803 group (spec.h) fig 4. functional block diagram prescaler x (8) timer 1 (8) prescaler 12 (8) timer x (8) timer 2 (8) reset 27 26 cnv ss cntr 0 reset input p1 (8) 41 43 45 47 42 44 46 48 i/o port p 1 prescaler y (8) timer y (8) cntr 1 p2 (8) 33 35 37 39 34 36 38 40 i/o port p 2 (led drive) p0 (8) 49 50 51 52 53 54 55 56 i/o port p 0 d/a converter 1 (8) r a m r o m a x y s pc l pc h ps c p u v ss 32 v cc 1 d/a converter 2 (8) 0 p5 (8) 13 17 14 16 18 15 clock generating circuit x in x out main clock input main clock output functional block diagram (package: prdp0064ba-a (64p4b)) 30 31 a/d converter (10) v ref pwm (8) 2 3 avss x cin x cout sub-clock input sub-clock output 28 29 data bus timer z (16) cntr 2 p6 (8) 46810 57911 i/o port p6 19 12 i/o port p5 int 3 si/o2 (8) si/o1 (8) p4 (8) 21 25 22 24 28 23 29 20 i/o port p4 int 00 int 1 int 2 int 40 p3 (8) 58 62 59 61 63 60 64 57 i/o port p3 si/o3 (8) int 01 int 41 rev.3.11 apr 5, 2006 page 7 of 113 rej03b0017-0311 3803 group (spec.h) pin description table 6 pin description pin name functions function except a port function v cc , v ss power source ? apply voltage of 1.8 v ? 5.5 v to v cc , and 0 v to v ss . in the flash memory version, apply voltage of 2.7 v ? 5.5 v to vcc. cnv ss cnv ss input ? this pin controls the operation mode of the chip. ? normally connected to v ss . v ref reference voltage ? reference voltage input pin for a/d and d/a converters. av ss analog power source ? analog power source input pin for a/d and d/a converters. ? connect to v ss . reset reset input ? reset input pin for active ?l?. x in main clock input ? input and output pi ns for the clock generating circuit. ? connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? when an external clock is used, c onnect the clock source to the x in pin and leave the x out pin open. x out main clock output p0 0 /an 8 ? p0 7 /an 15 i/o port p0 ? 8-bit cmos i/o port. ? i/o direction register allo ws each pin to be individually programmed as either input or output. ? cmos compatible input level. ? cmos 3-state output structure. ? pull-up control is enabled in a bit unit. ?p2 0 ? p2 7 (8 bits) are enabled to output large current for led drive. ? a/d converter input pin p1 0 /int 41 p1 1 /int 01 i/o port p1 ? interrupt input pin p1 2 ? p1 7 p2 0 -p2 7 i/o port p2 p3 0 /da 1 p3 1 / da 2 i/o port p3 ? 8-bit cmos i/o port. ? i/o direction register allo ws each pin to be individually programmed as either input or output. ? cmos compatible input level. ?p3 0 , p3 1 , p3 4 ? p3 7 are cmos 3-state output structure. ?p3 2 , p3 3 are n-channel open-drain output structure. ? pull-up control of p3 0 , p3 1 , p3 4 ? p3 7 is enabled in a bit unit. ? d/a converter input pin p3 2 , p3 3 p3 4 /r x d 3 p3 5 /t x d 3 p3 6 /s clk3 p3 7 /s rdy3 ? serial i/o3 function pin p4 0 /int 40 / x cout p4 1 /int 00 / x cin i/o port p4 ? 8-bit cmos i/o port. ? i/o direction register allo ws each pin to be individually programmed as either input or output. ? cmos compatible input level. ? cmos 3-state output structure. ? pull-up control is enabled in a bit unit. ? interrupt input pin ? sub-clock generating i/o pin (resonator connected) p4 2 /int 1 p4 3 /int 2 ? interrupt input pin p4 4 /r x d 1 p4 5 /t x d 1 p4 6 /s clk1 ? serial i/o1 function pin p4 7 /s rdy1 /cntr 2 ? serial i/o1, timer z function pin p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 i/o port p5 ? serial i/o2 function pin p5 4 /cntr 0 ? timer x function pin p5 5 /cntr 1 ? timer y function pin p5 6 /pwm ? pwm output pin p5 7 /int 3 ? interrupt input pin p6 0 /an 0 ? p6 7 /an 7 i/o port p6 ? a/d converter input pin rev.3.11 apr 5, 2006 page 8 of 113 rej03b0017-0311 3803 group (spec.h) part numbering fig 5. part numbering m3803 7 m 8 h ? xxx sp product name package type sp : prdp0064ba-a (64p4b) fp : prqp0064ga-a (64p6n-a) hp : plqp0064kb-a (64p6q-a) kp : plqp0064ga-a (64p6u-a) wg : ptlg0064ja-a (64f0g) rom number omitted in the flash memory version. rom/prom size 1: 4096 bytes 2: 8192 bytes 3: 12288 bytes 4: 16384 bytes 5: 20480 bytes 6: 24576 bytes 7: 28672 bytes 8: 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used as a user?s rom area. however, they can be programmed or erased in the flash memory version, so that the users can use them. memory type m: mask rom version f: flash memory version ram size 0: 192 bytes 1: 256 bytes 2: 384 bytes 3: 512 bytes 4: 640 bytes ? : standard omitted in the flash memory version. h ? : minner spec. change product 9: 36864 bytes a: 40960 bytes b: 45056 bytes c: 49152 bytes d: 53248 bytes e: 57344 bytes f: 61440 bytes 5: 768 bytes 6: 896 bytes 7: 1024 bytes 8: 1536 bytes 9: 2048 bytes rev.3.11 apr 5, 2006 page 9 of 113 rej03b0017-0311 3803 group (spec.h) group expansion renesas plans to expand the 3803 group (spec.h) as follows. memory size ? flash memory size ....................................................60 k bytes ? mask rom size ...........................................16 k to 60 k bytes ? ram size ......... ............ ........... ......... ........ ..... 640 to 2048 bytes packages ? prdp0064ba-a (64p4b) ..............................................64-pin shrink plastic-molded dip ? prqp0064ga-a (64p6n-a) ............................................. 0.8 mm-pitch plastic molded qfp ? plqp0064kb-a (64p6q-a) ...........................................0.5 mm-pitch plastic molded lqfp ? plqp0064ga-a (64p6u-a) ...........................................0.8 mm-pitch plastic molded lqfp ? ptlg0064ja-a (64f0g) ........................................0.65 mm-pitch plastic molded flga fig 6. memory expansion plan note : refer to ?3803/3804 group data sheet? about 3803 group products other than 3803 group (spec.h) because there are electrical characteristics differences and so on. memory expansion plan 512 12k 16k 20k 24k 28k 32k 384 768640 8k 1024896 1280 1152 1408 2048 1536 rom size (bytes) ram size (bytes) 4032 3072 48k 60k m38037m8h m38037m6h m38034m4h m38039mch m38039mfh m38039ff m38039ffh as of apr. 2006 : mass production rev.3.11 apr 5, 2006 page 10 of 113 rej03b0017-0311 3803 group (spec.h) functional description central processing unit (cpu) the 3803 group (spec.h) uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family in structions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit regist er. data operations such as data transfer, etc. are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit re gister. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit regi ster used during subroutine calls and interrupts. this register indi cates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack address are determined by the st ack page selection bit. if the stack page selection bit is ?0?, the high-order 8 bits becomes ?00 16 ?. if the stack page selection bi t is ?1?, the high-order 8 bits becomes ?01 16 ?. the operations of pushing register contents onto the stack and popping them from the stack are shown in figure.8. store registers other than thos e described in figure.7 with program when the user needs them during interrupts or subroutine calls (see table 7). [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig 7. 740 family cpu register structure processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag b7 b0 b15 program counter stack pointer index register y index register x accumulator a x y s pc l pc h czidbtvn b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 rev.3.11 apr 5, 2006 page 11 of 113 rej03b0017-0311 3803 group (spec.h) fig 8. register push and pop at inte rrupt generation and subroutine call interrupt request (1) m(s) (pc h ) (s) (s) ? 1 m(s) (pc l ) ( s ) ( s ) ? 1 ..... execute rts subroutine (s) (s) + 1 (pc l ) m(s) (s) (s) + 1 (pc h ) m(s) m(s) (pc h ) (s) (s) ? 1 m(s) (pc l ) (s) (s) ? 1 m(s) (ps) (s) (s) ? 1 interrupt service routine (s) (s) + 1 (ps) m(s) (s) (s) + 1 (pc l ) m(s) (s) (s) + 1 (pc h ) m(s) execute jsr ..... execute rti push return address on stack push contents of processor status register on stack i flag is set from ?0? to ?1? fetch the jump vector pop contents of processor status register from stack pop return address from stack pop return address from stack push return address on stack note 1 : condition for acceptance of an interrupt interrupt enable flag is ?1? interrupt disable flag is ?0? on-going routine table 7 push and pop instructions of accumulator or processor status register push instruction to stack p op instruction from stack accumulator pha pla processor status register php plp rev.3.11 apr 5, 2006 page 12 of 113 rej03b0017-0311 3803 group (spec.h) [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 fl ags which decide mcu operation. branch operations can be perf ormed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the resu lt of an immediate arithmetic operation or a data transfer is ?0 ?, and cleared if the result is anything other than ?0?. bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is ?1?. bit 3: decimal mode flag (d) the d flag determines whether additions and s ubtractions are executed in binary or decimal. binary arithmetic is executed when this flag is ?0?; decimal arithmetic is executed when it is ?1?. decimal correction is automati c in decimal mode. only the adc and sbc instructions can execute decimal arithmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always ?0?. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto th e stack with the break flag set to ?1?. bit 5: index x mode flag (t) when the t flag is ?0?, arithmetic operations are performed between accumulator and memory. when the t flag is ?1?, direct arithmetic operations a nd direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to ? 128. when the bit instructio n is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 8 set and clear instructions of each bit of processor status register c flag z flag i flag d flag b flag t flag v flag n flag set instruction sec ? sei sed ? set ?? clear instruction clc ? cli cld ? clt clv ? rev.3.11 apr 5, 2006 page 13 of 113 rej03b0017-0311 3803 group (spec.h) [cpu mode register (cpum)] 003b 16 the cpu mode register contains th e stack page sele ction bit, the internal system clock control bits, etc. the cpu mode register is allocated at address 003b 16 . fig 9. structure of cpu mode register cpu mode register (cpum: address 003b 16 ) b7 b0 stack page selection bit 0 : 0 page 1 : 1 page processor mode bits b1 b0 0 0 : single-chip mode 01: 1 0 : not available 11: main clock division ratio selection bits b7 b6 00: = f(x in )/2 (high-speed mode) 01: = f(x in )/8 (middle-speed mode) 10: = f(x cin )/2 (low-speed mode) 1 1 : not available fix this bit to ?1?. 1 port x c switch bit 0 : i/o port function (stop oscillating) 1:x cin -x cout oscillating function main clock (x in -x out ) stop bit 0 : oscillating 1 : stopped rev.3.11 apr 5, 2006 page 14 of 113 rej03b0017-0311 3803 group (spec.h) misrg (1) bit 0 of address 0010 16 : oscillation stabilizing time set after stp instruction released bit when the mcu stops the clock os cillation by the stp instruction and the stp instruction has been released by an external interrupt source, usually, the fixed values of timer 1 and prescaler 12 (timer 1 = 01 16 , prescaler 12 = ff 16 ) are automatically reloaded in orde r for the oscillation to stabilize. the user can inhibit the automati c setting by settin g ?1? to bit 0 of misrg (address 0010 16 ). however, by setting this bit to ?1?, the previous values, set just before the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you will need to set an appropriate value to each register, in ac cordance with the oscillation stabilizing time, before exec uting the stp instruction. figure.10 shows the structure of misrg. (2) bits 1, 2, 3 of address 0010 16 : middle-speed mode automatic swit ch function in order to switch the clock mode of an mcu which has a sub- clock, the following pr ocedure is necessary: set cpu mode register (003b 16 ) --> start main clock oscillation --> wait for oscillation stabilizat ion --> switch to middle-speed mode (or high-speed mode). however, the 3803 group (spec.h) has the built-in function which automatically switches from low to middle-speed mode by program. ? middle-speed mode automatic switch by program the middle-speed mode can also be automatically switched by program while operating in lo w-speed mode. by setting the middle-speed automatic switch start bit (bit 3) of misrg (address 0010 16 ) to ?1? in the condit ion that the middle-speed mode automatic switch set bit is ?1? while operating in low- speed mode, the mcu will automatically switch to middle-speed mode. in this case, the oscillation stabilizing time of the main clock can be selected by the mi ddle-speed automatic switch wait time set bit (bit 2) of misrg (address 0010 16 ). fig 10. structure of misrg misrg (misrg: address 0010 16 ) b7 b0 oscillation stabilizing time set after stp instruction released bit 0 : automatically set ?01 16 ? to timer 1, ?ff 16 ? to prescaler 12 1 : automatically set disabled middle-speed mode automatic switch set bit 0 : not set automatically 1 : automatic switching enabled (1) middle-speed mode automatic switch wait time set bit 0 : 4.5 to 5.5 machine cycles 1 : 6.5 to 7.5 machine cycles middle-speed mode automatic switch start bit (depending on program) 0 : invalid 1 : automatic switch start (1) not used (return ?0? when read) (do not write ?1? to this bit) note 1 : when automatic switch to middle-speed mode from low-speed mode occurs, the values of cpu mode register (3b 16 ) change. rev.3.11 apr 5, 2006 page 15 of 113 rej03b0017-0311 3803 group (spec.h) memory ? special function register (sfr) area the special function register area in the zero page contains control registers such as i/o ports and timers. ? ram the ram is used for data st orage and for stack area of subroutine calls and interrupts. ?rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. the reserved rom area can prog ram/erase in the flash memory version. ? interrupt vector area the interrupt vector area contai ns reset and interrupt vectors. ? zero page access to this area with only 2 bytes is possible in the zero page addressing mode. ? special page access to this area with only 2 bytes is possible in the special page addressing mode. rev.3.11 apr 5, 2006 page 16 of 113 rej03b0017-0311 3803 group (spec.h) fig 12. memory map of special function register (sfr) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) timer 12, x count source selection register (t12xcss) timer y, z count source selection register (tyzcss) misrg reserved * reserved * reserved * reserved * reserved * reserved * reserved * transmit/receive buffer register 1 (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator (brg1) serial i/o2 control register (sio2con) watchdog timer control register (wdtcon) serial i/o2 register (sio2) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) timer z low-order (tzl) timer z high-order (tzh) timer z mode register (tzm) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) baud rate generator 3 (brg3) transmit/receive buffer register 3 (tb3/rb3) serial i/o3 status register (sio3sts) serial i/o3 control register (sio3con) uart3 control register (uart3con) ad/da control register (adcon) ad conversion register 1 (ad1) da1 conversion register (da1) da2 conversion register (da2) ad conversion register 2 (ad2) interrupt source selection register (intsel) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) *reserved area: do not write any data to these addresses, because these areas are reserved. 0fe0 16 0fe1 16 0fe2 16 0fe3 16 0fe4 16 0fe5 16 0fe6 16 0fe7 16 0fe8 16 0fe9 16 0fea 16 0feb 16 0fec 16 0fed 16 0fee 16 0fef 16 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 flash memory control register 0 (fmcr0) flash memory control register 1 (fmcr1) flash memory control register 2 (fmcr2) reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * port p0 pull-up cont rol register (pull0) port p1 pull-up cont rol register (pull1) port p2 pull-up cont rol register (pull2) port p3 pull-up cont rol register (pull3) port p4 pull-up cont rol register (pull4) port p5 pull-up cont rol register (pull5) port p6 pull-up cont rol register (pull6) rev.3.11 apr 5, 2006 page 17 of 113 rej03b0017-0311 3803 group (spec.h) i/o ports the i/o ports have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. when ?0? is written to the bit corresponding to a pin, that pin becomes an input pin. when ?1? is written to that bit, that pin becomes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the va lue of the pin it self. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. by setting the port p0 pull-up control register (address 0ff0 16 ) to the port p6 pull-up control register (address 0ff6 16 ) ports can control pull-up with a program. however, the contents of these registers do not affect ports programmed as the output ports. notes: 1. refer to the applicable sections how to us e double-function ports as function i/o ports. 2. make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. table 9 i/o port function pin name input/ output i/o structure non-port function related sfrs ref. no. p0 0 /an 8 ? p0 7 /an 15 port p0 input/output, individual bits cmos compatible input level cmos 3-state output a/d converter input ad/da control register (1) p1 0 /int 41 p1 1 /int 01 port p1 external interrupt input interrupt edge selection register (2) p1 2 ? p1 7 (3) p2 0 /led 0 ? p2 7 /led 7 port p2 p3 0 /da 1 p3 1 / da 2 port p3 d/a converter output ad/da control register (4) p3 2 , p3 3 cmos compatible input level n-channel open-drain output (5) p3 4 /r x d 3 p3 5 /t x d 3 p3 6 /s clk3 p3 7 /s rdy3 cmos compatible input level cmos 3-state output serial i/o3 function i/o seri al i/o3 control register uart3 control register (6) (7) (8) (9) p4 0 /int 40 / x cout p4 1 /int 00 / x cin port p4 external interrupt input sub-clock generating circuit interrupt edge selection register cpu mode register (10) (11) p4 2 /int 1 p4 3 /int 2 external interrupt input interrupt edge selection register (2) p4 4 /r x d 1 p4 5 /t x d 1 p4 6 /s clk1 serial i/o1 function i/o seri al i/o1 control register uart1 control register (6) (7) (8) p4 7 /s rdy1 /cntr 2 serial i/o1 function i/o timer z function i/o serial i/o1 control register timer z mode register (12) p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 port p5 serial i/o2 function i/o se rial i/o2 control register (13) (14) (15) (16) p5 4 /cntr 0 p5 5 /cntr 1 timer x, y function i/o timer xy mode register (17) p5 6 /pwm pwm output pwm control register (18) p5 7 /int 3 external interrupt input interrupt edge selection register (2) p6 0 /an 0 ? p6 7 /an 7 port p6 a/d converter input ad/da control register (1) rev.3.11 apr 5, 2006 page 18 of 113 rej03b0017-0311 3803 group (spec.h) fig 13. port block diagram (1) (5) ports p3 2 , p3 3 (7) ports p3 5 , p4 5 (4) ports p3 0 , p3 1 data bus a/d converter input (1) ports p0 , p6 (6) ports p3 4 , p4 4 serial i/o enable bit (2) ports p1 0 , p1 1 , p4 2 , p4 3 , p5 7 (3) ports p1 2 to p1 7 , p2 serial i/o output p-channel output disable bit (8) ports p3 6 , p4 6 pull-up control bit pull-up control bit port latch direction register pull-up control bit data bus port latch direction register data bus port latch direction register analog input pin selection bit data bus interrupt input pull-up control bit port latch direction register data bus pull-up control bit port latch direction register data bus d/a converter output pull-up control bit port latch direction register da 1 output enable bit (p3 0 ) da 2 output enable bit (p3 1 ) data bus port latch direction register serial i/o input receive enable bit serial i/o enable bit transmit enable bit serial i/o mode selection bit serial i/o clock output serial i/o external clock input serial i/o enable bit pull-up control bit data bus port latch direction register serial i/o synchronous clock selection bit serial i/o enable bit rev.3.11 apr 5, 2006 page 19 of 113 rej03b0017-0311 3803 group (spec.h) fig 14. port block diagram (2) (13) port p5 0 (12) port p4 7 (9) port p3 7 (14) port p5 1 (10) port p4 0 (11) port p4 1 int 40 interrupt input serial i/o3 mode selection bit serial i/o3 ready output serial i/o3 enable bit pull-up control bit data bus port latch direction register s rdy3 output enable bit port x c switch bit pull-up control bit data bus port latch direction register port x c switch bit int 00 interrupt input port x c switch bit pull-up control bit data bus port latch direction register sub-clock generating circuit input timer output cntr 2 interrupt input pull-up control bit data bus port latch direction register serial i/o2 output pull-up control bit data bus port latch direction register serial i/o2 transmit completion signal serial i/o2 port selection bit pull-up control bit data bus port latch direction register serial i/o2 input serial i/o1 mode selection bit serial i/o1 enable bit s rdy1 output enable bit bit 2 bit 1 bit 0 timer z operating mode bits serial i/o1 ready output p-channel output disable bit port x c switch bit rev.3.11 apr 5, 2006 page 20 of 113 rej03b0017-0311 3803 group (spec.h) fig 15. port block diagram (3) (18) port p5 6 (15) port p5 2 (16) port p5 3 (17) ports p5 4 , p5 5 cntr interrupt input pull-up control bit data bus port latch direction register pwm output pwm function enable bit pull-up control bit data bus port latch direction register serial i/o2 clock output pull-up control bit data bus port latch direction register serial i/o2 port selection bit serial i/o2 synchronous clock selection bit serial i/o2 external clock input serial i/o2 ready output pull-up control bit data bus port latch direction register s rdy2 output enable bit pulse output mode timer output rev.3.11 apr 5, 2006 page 21 of 113 rej03b0017-0311 3803 group (spec.h) fig 16. structure of port pull-up control register (1) b7 b0 port p0 pull-up control register (pull0: address 0ff0 16 ) p0 0 pull-up control bit 0: no pull-up 1: pull-up p0 1 pull-up control bit 0: no pull-up 1: pull-up p0 2 pull-up control bit 0: no pull-up 1: pull-up p0 3 pull-up control bit 0: no pull-up 1: pull-up p0 4 pull-up control bit 0: no pull-up 1: pull-up p0 5 pull-up control bit 0: no pull-up 1: pull-up p0 6 pull-up control bit 0: no pull-up 1: pull-up p0 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 port p1 pull-up control register (pull1: address 0ff1 16 ) p1 0 pull-up control bit 0: no pull-up 1: pull-up p1 1 pull-up control bit 0: no pull-up 1: pull-up p1 2 pull-up control bit 0: no pull-up 1: pull-up p1 3 pull-up control bit 0: no pull-up 1: pull-up p1 4 pull-up control bit 0: no pull-up 1: pull-up p1 5 pull-up control bit 0: no pull-up 1: pull-up p1 6 pull-up control bit 0: no pull-up 1: pull-up p1 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. rev.3.11 apr 5, 2006 page 22 of 113 rej03b0017-0311 3803 group (spec.h) fig 17. structure of port pull-up control register (2) b7 b0 port p2 pull-up control register (pull2: address 0ff2 16 ) p2 0 pull-up control bit 0: no pull-up 1: pull-up p2 1 pull-up control bit 0: no pull-up 1: pull-up p2 2 pull-up control bit 0: no pull-up 1: pull-up p2 3 pull-up control bit 0: no pull-up 1: pull-up p2 4 pull-up control bit 0: no pull-up 1: pull-up p2 5 pull-up control bit 0: no pull-up 1: pull-up p2 6 pull-up control bit 0: no pull-up 1: pull-up p2 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 port p3 pull-up control register (pull3: address 0ff3 16 ) p3 0 pull-up control bit 0: no pull-up 1: pull-up p3 1 pull-up control bit 0: no pull-up 1: pull-up not used (return ?0? when read) p3 4 pull-up control bit 0: no pull-up 1: pull-up p3 5 pull-up control bit 0: no pull-up 1: pull-up p3 6 pull-up control bit 0: no pull-up 1: pull-up p3 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. rev.3.11 apr 5, 2006 page 23 of 113 rej03b0017-0311 3803 group (spec.h) fig 18. structure of port pull-up control register (3) b7 b0 port p4 pull-up control register (pull4: address 0ff4 16 ) p4 0 pull-up control bit 0: no pull-up 1: pull-up p4 1 pull-up control bit 0: no pull-up 1: pull-up p4 2 pull-up control bit 0: no pull-up 1: pull-up p4 3 pull-up control bit 0: no pull-up 1: pull-up p4 4 pull-up control bit 0: no pull-up 1: pull-up p4 5 pull-up control bit 0: no pull-up 1: pull-up p4 6 pull-up control bit 0: no pull-up 1: pull-up p4 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 port p5 pull-up control register (pull5: address 0ff5 16 ) p5 0 pull-up control bit 0: no pull-up 1: pull-up p5 1 pull-up control bit 0: no pull-up 1: pull-up p5 2 pull-up control bit 0: no pull-up 1: pull-up p5 3 pull-up control bit 0: no pull-up 1: pull-up p5 4 pull-up control bit 0: no pull-up 1: pull-up p5 5 pull-up control bit 0: no pull-up 1: pull-up p5 6 pull-up control bit 0: no pull-up 1: pull-up p5 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. rev.3.11 apr 5, 2006 page 24 of 113 rej03b0017-0311 3803 group (spec.h) fig 19. structure of port pull-up control register (4) b7 b0 port p6 pull-up control register (pull6: address 0ff6 16 ) p6 0 pull-up control bit 0: no pull-up 1: pull-up p6 1 pull-up control bit 0: no pull-up 1: pull-up p6 2 pull-up control bit 0: no pull-up 1: pull-up p6 3 pull-up control bit 0: no pull-up 1: pull-up p6 4 pull-up control bit 0: no pull-up 1: pull-up p6 5 pull-up control bit 0: no pull-up 1: pull-up p6 6 pull-up control bit 0: no pull-up 1: pull-up p6 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. rev.3.11 apr 5, 2006 page 25 of 113 rej03b0017-0311 3803 group (spec.h) interrupts the 3803 group (spec.h)?s interrupts are a type of vector and occur by 16 sources among 21 sour ces: eight external, twelve internal, and one software. ? interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the inte rrupt disable flag except for the software interrupt set by the brk instruction. an interrupt occurs if the corresponding interr upt request and enable bits are ?1? and the interrupt disable flag is ?0?. interrupt enable bits can be set or cleared by software. interrupt request bits can be cl eared by software, but cannot be set by software. the reset and the brk instructio n cannot be disabled with any flag or bit. the i (interrupt disa ble) flag disables all interrupts except the reset and the brk instruction interrupt. when several interrupt requests occur at the same time, the interrupts are received according to priority. ? interrupt operation by acceptance of an interr upt, the following operations are automatically performed: 1. the contents of the program counter and the processor sta- tus register are automatica lly pushed onto the stack. 2. the interrupt disable flag is set and the corresponding inter- rupt request bit is cleared. 3. the interrupt jump destination address is read from the vec- tor table into the program counter. ? interrupt source selection which of each combination of the following interrupt sources can be selected by the interrupt so urce selection re gister (address 0039 16 ). 1. int 0 or timer z 2. cntr 1 or serial i/ o3 reception 3. serial i/o2 or timer z 4. int 4 or cntr 2 5. a/d converter or seri al i/o3 transmission ? external interrupt pin selection the occurrence sources of the external interrupt int 0 and int 4 can be selected from either input from int 00 and int 40 pin, or input from int 01 and int 41 pin by the int 0 , int 4 interrupt switch bit of interrupt edge sel ection register (bit 6 of address 003a 16 ). rev.3.11 apr 5, 2006 page 26 of 113 rej03b0017-0311 3803 group (spec.h) notes: 1. vector addresses contain interrupt jump destination addresses. 2. reset function in the same way as an interrupt with the highest priority. table 10 interrupt vector addresses and priority interrupt source priority vector addresses (1) interrupt request generating conditions remarks high low reset (2) 1fffd 16 fffc 16 at reset non-maskable int 0 2fffb 16 fffa 16 at detection of either rising or falling edge of int 0 input external interrupt (active edge selectable) timer z at timer z underflow int 1 3 fff9 16 fff8 16 at detection of either rising or falling edge of int 1 input external interrupt (active edge selectable) serial i/o1 reception 4 fff7 16 fff6 16 at completion of serial i/o1 data reception valid when serial i/o1 is selected serial i/o1 transmission 5 fff5 16 fff4 16 at completion of serial i/o1 transmission shift or when transmission buffer is empty valid when serial i/o1 is selected timer x 6 fff3 16 fff2 16 at timer x underflow timer y 7 fff1 16 fff0 16 at timer y underflow timer 1 8 ffef 16 ffee 16 at timer 1 underflow stp release timer underflow timer 2 9 ffed 16 ffec 16 at timer 2 underflow cntr 0 10 ffeb 16 ffea 16 at detection of either rising or falling edge of cntr 0 input external interrupt (active edge selectable) cntr 1 11 ffe9 16 ffe8 16 at detection of either rising or falling edge of cntr 1 input external interrupt (active edge selectable) serial i/o3 reception at completion of serial i/o3 data reception valid when serial i/o3 is selected serial i/o2 12 ffe7 16 ffe6 16 at completion of serial i/o2 data transmission or reception valid when serial i/o2 is selected timer z at timer z underflow int 2 13 ffe5 16 ffe4 16 at detection of either rising or falling edge of int 2 input external interrupt (active edge selectable) int 3 14 ffe3 16 ffe2 16 at detection of either rising or falling edge of int 3 input external interrupt (active edge selectable) int 4 15 ffe1 16 ffe0 16 at detection of either rising or falling edge of int 4 input external interrupt (active edge selectable) cntr 2 at detection of either rising or falling edge of cntr 2 input external interrupt (active edge selectable) a/d converter 16 ffdf 16 ffde 16 at completion of a/d conversion serial i/o3 transmission at completion of serial i/o3 transmission shift or when transmission buffer is empty valid when serial i/o3 is selected brk instruction 17 ffdd 16 ffdc 16 at brk instruction execution non-maskable software interrupt rev.3.11 apr 5, 2006 page 27 of 113 rej03b0017-0311 3803 group (spec.h) fig 20. interrupt control interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset rev.3.11 apr 5, 2006 page 28 of 113 rej03b0017-0311 3803 group (spec.h) fig 21. structure of interrupt-related registers interrupt edge selection register (intedge : address 003a 16 ) int 0 interrupt edge selection bit int 1 interrupt edge selection bit not used (returns ?0? when read) int 2 interrupt edge selection bit int 3 interrupt edge selection bit int 4 interrupt edge selection bit int 0 , int 4 interrupt switch bit 0 : int 00 , int 40 interrupt 1 : int 01 , int 41 interrupt not used (returns ?0? when read) 0 : falling edge active 1 : rising edge active interrupt request register 1 (ireq1 : address 003c 16 ) int 0 /timer z interrupt request bit int 1 interrupt request bit serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit interrupt request register 2 (ireq2 : address 003d 16 ) cntr 0 interrupt request bit cntr 1 /serial i/o3 receive interrupt request bit serial i/o2/timer z interrupt request bit int 2 interrupt request bit int 3 interrupt request bit int 4 /cntr 2 interrupt request bit ad converter/serial i/o3 transmit interrupt request bit not used (returns ?0? when read) 0 : no interrupt request issued 1 : interrupt request issued interrupt control register 1 (icon1 : address 003e 16 ) int 0 /timer z interrupt enable bit int 1 interrupt enable bit serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit interrupt control register 2 (icon2 : address 003f 16 ) b7 b0 b7 b0 b7 b0 b7 b0 0 : falling edge active 1 : rising edge active cntr 0 interrupt enable bit cntr 1 /serial i/o3 receive interrupt enable bit serial i/o2/timer z interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit int 4 /cntr 2 interrupt enable bit ad converter/serial i/o3 transmit interrupt enable bit not used (returns ?0? when read) (do not write ?1? to this bit.) 0 : interrupts disabled 1 : interrupts enabled b7 b0 interrupt source selection register (intsel : address 0039 16 ) int 0 /timer z interrupt source selection bit 0 : int 0 interrupt 1 : timer z interrupt serial i/o2/timer z interrupt source selection bit 0 : serial i/o2 interrupt 1 : timer z interrupt not used (do not write ?1? to these bits.) int 4 /cntr 2 interrupt source selection bit 0 : int 4 interrupt 1 : cntr 2 interrupt not used (do not write ?1? to this bit.) cntr 1 /serial i/o3 receive interrupt source selection bit 0 : cntr 1 interrupt 1 : serial i/o3 receive interrupt ad converter/serial i/o3 transmit interrupt source selection bit 0 : a/d converter interrupt 1 : serial i/o3 transmit interrupt (do not write ?1? to these bits simultaneously.) b7 b0 0 : no interrupt request issued 1 : interrupt request issued 0 : interrupts disabled 1 : interrupts enabled rev.3.11 apr 5, 2006 page 29 of 113 rej03b0017-0311 3803 group (spec.h) timers ? 8-bit timers the 3803 group (spec.h) has four 8-bit timers: timer 1, timer 2, timer x, and timer y. the timer 1 and timer 2 use one prescaler in common, and the timer x and timer y use each prescaler. those are 8-bit prescalers. each of the timers and prescalers has a timer latch or a prescaler latch. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are down-counters. when the timer reaches ?00 16 ?, an underflow occurs at the next coun t pulse and the co ntents of the corresponding timer latch are reloaded into the timer and the count is continued. when th e timer underflows, the interrupt request bit corresponding to th at timer is set to ?1?. ? timer divider the divider count source is swit ched by the main clock division ratio selection bits of cpu mode register (bits 7 and 6 at address 003b 16 ). when these bits are ?00? (high-speed mode) or ?01? (middle-speed mode), x in is selected. when these bits are ?10? (low-speed mode), x cin is selected. ? prescaler 12 the prescaler 12 counts the output of the timer divider. the count source is selected by the timer 12, x count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(x in ) or f(x cin ). ? timer 1 and timer 2 the timer 1 and timer 2 counts the output of prescaler 12 and periodically set the in terrupt request bit. ? prescaler x and prescaler y the prescaler x and prescaler y count the output of the timer divider or f(x cin ). the count source is selected by the timer 12, x count source selectio n register (address 000e 16 ) and the timer y, z count source selection register (address 000f 16 ) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/12 8, 1/256, 1/512, and 1/1024 of f(x in ) or f(x cin ); and f(x cin ). ?timer x and timer y the timer x and timer y can each select one of four operating modes by setting the timer xy mode register (address 0023 16 ). (1) timer mode ? mode selection this mode can be selected by setting ?00? to the timer x operating mode bits (bits 1 a nd 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). ? explanation of operation the timer count operati on is started by setting ?0? to the timer x count stop bit (bit 3) and the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ). when the timer reaches ?00 16 ?, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) pulse output mode ? mode selection this mode can be selected by setting ?01? to the timer x operating mode bits (bits 1 a nd 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). ? explanation of operation the operation is the same as the timer mode?s. moreover the pulse which is inverted each time the timer underflows is output from cntr 0 /cntr 1 pin. regardless of the timer counting or not the output of cntr 0 /cntr 1 pin is initialized to the level of specified by their active edge sw itch bits when writing to the timer. when the cntr 0 active edge switch bit (bit 2) and the cntr 1 active edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ) is ?0?, the output starts with ?h? level. when it is ?1?, the output starts with ?l? level. switching the cntr 0 or cntr 1 active edge switch bit will reverse the output level of the corresponding cntr 0 or cntr 1 pin. ? precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 /p5 5 to output in this mode. (3) event counter mode ? mode selection this mode can be selected by setting ?10? to the timer x operating mode bits (bits 1 a nd 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). ? explanation of operation the operation is the same as the timer mode?s except that the timer counts signals input from the cntr 0 or cntr 1 pin. the valid edge for the count operation depends on the cntr 0 active edge switch bit (bit 2) or the cntr 1 active edge sw itch bit (bit 6) of the timer xy mode register (address 0023 16 ). when it is ?0?, the rising edge is valid. when it is ?1?, the falling edge is valid. ? precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 /p5 5 to input in this mode. rev.3.11 apr 5, 2006 page 30 of 113 rej03b0017-0311 3803 group (spec.h) (4) pulse width measurement mode ? mode selection this mode can be selected by setting ?11? to the timer x operating mode bits (bits 1 a nd 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). ? explanation of operation when the cntr 0 active edge switch bit (bit 2) or the cntr 1 active edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ) is ?1?, the timer counts during the term of one falling edge of cntr 0 /cntr 1 pin input until the next rising edge of input (?l? term). when it is ?0?, the timer counts during the term of one rising edge input until the next falling edge input (?h? term). ? precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 /p5 5 to input in this mode. the count operation can be stopped by setting ?1? to the timer x count stop bit (bit 3) and the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ). the interrupt request bit is set to ?1? each time the timer underflows. ? precautions when sw itching count source when switching the count source by the timer 12, x and y count source selection bits, the value of timer count is altered in inconsiderable amount owing to ge nerating of thin pulses on the count input signals. therefore, select the timer count source before setting the value to the prescaler and the timer. rev.3.11 apr 5, 2006 page 31 of 113 rej03b0017-0311 3803 group (spec.h) fig 22. block diagram of timer x, timer y, timer 1, and timer 2 q q ?1? ?0? p5 4 /cntr 0 q q p5 5 /cntr 1 ?0? ?1? r r ?1? ?0? ?0? ?1? t t prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) to timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode to cntr 0 interrupt request bit pulse output mode port p5 4 latch port p5 4 direction register cntr 0 active edge switch bit timer x latch write pulse pulse output mode timer mode pulse output mode prescaler y latch (8) prescaler y (8) timer y latch (8) timer y (8) to timer y interrupt request bit toggle flip-flop timer y count stop bit to cntr 1 interrupt request bit pulse output mode port p5 5 latch port p5 5 direction register cntr 1 active edge switch bit timer y latch write pulse pulse output mode timer mode pulse output mode prescaler 12 latch (8) prescaler 12 (8) timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) to timer 2 interrupt request bit to timer 1 interrupt request bit cntr 0 active edge switch bit cntr 1 active edge switch bit pulse width measurement mode event counter mode clock for timer 12 data bus data bus data bus clock for timer 12 x in (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) divider clock for timer y count source selection bit main clock division ratio selection bits ?00? ?11? ?10? x cin clock for timer x f(x cin ) count source selection bit f(x cin ) clock for timer y rev.3.11 apr 5, 2006 page 32 of 113 rej03b0017-0311 3803 group (spec.h) fig 23. structure of timer xy mode register b7 timer xy mode register (tm : address 0023 16 ) timer x operating mode bits b1 b0 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 0 active edge switch bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode timer x count stop bit 0: count start 1: count stop timer y operating mode bits b5 b4 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 1 active edge switch bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode timer y count stop bit 0: count start 1: count stop b0 rev.3.11 apr 5, 2006 page 33 of 113 rej03b0017-0311 3803 group (spec.h) fig 24. structure of timer 12, x and timer y, z count source selection registers b7 b0 timer 12, x count source selection register (t12xcss : address 000e 16 ) timer 12 count source selection bits b3 b2 b1 b0 0 000:f(x in )/2 or f(x cin )/2 0 001:f(x in )/4 or f(x cin )/4 0 0 1 0 : f(x in )/8 or f(x cin )/8 0 0 1 1 : f(x in )/16 or f(x cin )/16 0 1 0 0 : f(x in )/32 or f(x cin )/32 0 1 0 1 : f(x in )/64 or f(x cin )/64 0 1 1 0 : f(x in )/128 or f(x cin )/128 0 1 1 1 : f(x in )/256 or f(x cin )/256 1 0 0 0 : f(x in )/512 or f(x cin )/512 1 0 0 1 : f(x in )/1024 or f(x cin )/1024 1 0 1 0 : 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : not used timer x count sour ce selection bits b7 b6 b5 b4 0 000:f(x in )/2 or f(x cin )/2 0 001:f(x in )/4 or f(x cin )/4 0 0 1 0 : f(x in )/8 or f(x cin )/8 0 0 1 1 : f(x in )/16 or f(x cin )/16 0 1 0 0 : f(x in )/32 or f(x cin )/32 0 1 0 1 : f(x in )/64 or f(x cin )/64 0 1 1 0 : f(x in )/128 or f(x cin )/128 0 1 1 1 : f(x in )/256 or f(x cin )/256 1 0 0 0 : f(x in )/512 or f(x cin )/512 1 0 0 1 : f(x in )/1024 or f(x cin )/1024 1 0 1 0 : f(x cin ) 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : not used b7 b0 timer y, z count source selection register (tyzcss : address 000f 16 ) timer y count sour ce selection bits b3 b2 b1 b0 0 000:f(x in )/2 or f(x cin )/2 0 001:f(x in )/4 or f(x cin )/4 0 0 1 0 : f(x in )/8 or f(x cin )/8 0 0 1 1 : f(x in )/16 or f(x cin )/16 0 1 0 0 : f(x in )/32 or f(x cin )/32 0 1 0 1 : f(x in )/64 or f(x cin )/64 0 1 1 0 : f(x in )/128 or f(x cin )/128 0 1 1 1 : f(x in )/256 or f(x cin )/256 1 0 0 0 : f(x in )/512 or f(x cin )/512 1 0 0 1 : f(x in )/1024 or f(x cin )/1024 1 0 1 0 : f(x cin ) timer z count sour ce selection bits b7 b6 b5 b4 0 000:f(x in )/2 or f(x cin )/2 0 001:f(x in )/4 or f(x cin )/4 0 0 1 0 : f(x in )/8 or f(x cin )/8 0 0 1 1 : f(x in )/16 or f(x cin )/16 0 1 0 0 : f(x in )/32 or f(x cin )/32 0 1 0 1 : f(x in )/64 or f(x cin )/64 0 1 1 0 : f(x in )/128 or f(x cin )/128 0 1 1 1 : f(x in )/256 or f(x cin )/256 1 0 0 0 : f(x in )/512 or f(x cin )/512 1 0 0 1 : f(x in )/1024 or f(x cin )/1024 1 0 1 0 : f(x cin ) 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : not used 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : not used rev.3.11 apr 5, 2006 page 34 of 113 rej03b0017-0311 3803 group (spec.h) ? 16-bit timer the timer z is a 16-bit timer. when the timer reaches ?0000 16 ?, an underflow occurs at th e next count pulse and the corresponding timer latc h is reloaded into the timer and the count is continued. when the timer unde rflows, the interr upt request bit corresponding to the timer z is set to ?1?. when reading/writing to the timer z, perform reading/writing to both the high-order byte and th e low-order byte. when reading the timer z, read from the high-ord er byte first, followed by the low-order byte. do not perform the writing to the timer z between read operation of the hi gh-order byte and read operation of the low-order byte. when writing to the timer z, write to the low-order byte first, followed by the high-order byte. do not perform the reading to the timer z between write operation of the low-order byte and write opera tion of the high-order byte. the timer z can select the count source by the timer z count source selection bits of timer y, z count source selection register (bits 7 to 4 at address 000f 16 ). timer z can select one of seve n operating modes by setting the timer z mode register (address 002a 16 ). (1) timer mode ? mode selection this mode can be selected by setting ?000? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt when an underflow occurs, the int 0 /timer z interrupt request bit (bit 0) of the interrupt re quest register 1 (address 003c 16 ) is set to ?1?. ? explanation of operation during timer stop, usually write data to a latch and a timer at the same time to set the timer value. the timer count operation is starte d by setting ?0? to the timer z count stop bit (bit 6) of the timer z mode register (address 002a 16 ). when the timer reaches ?0000 16 ?, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the c ount is continued. when writing data to the timer during operation, the data is written only into the latch. then the new latch value is reloaded into the timer at the next underflow. (2) event counter mode ? mode selection this mode can be selected by setting ?000? to the timer z operating mode bits (bits 2 to 0) and setting ?1? to the timer/event counter mode switch bit (bit 7) of the timer z mode register (address 002a 16 ). the valid edge for the count operation depends on the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ). when it is ?0?, the rising edge is valid. when it is ?1?, the falling edge is valid. ? interrupt the interrupt at an underflow is the same as the timer mode?s. ? explanation of operation the operation is the same as the timer mode?s. set the double-function port of cntr 2 pin and port p4 7 to input in this mode. figure.27 shows the timing char t of the timer/event counter mode. (3) pulse output mode ? mode selection this mode can be selected by setting ?001? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. ? explanation of operation the operation is the same as the timer mode?s. moreover the pulse which is inverted each time the timer underflows is output from cntr 2 pin. when the cntr 2 active edge switch bit (bit 5) of the timer z mode re gister (address 002a 16 ) is ?0?, the output starts with ?h? level. when it is ?1?, the output starts with ?l? level. ? precautions the double-function port of cntr 2 pin and port p4 7 is automatically set to the timer pulse output port in this mode. the output from cntr 2 pin is initialized to the level depending on cntr 2 active edge switch bit by writing to the timer. when the value of the cntr 2 active edge switch bit is changed, the output level of cntr 2 pin is inverted. figure.28 shows the timing char t of the pulse output mode. rev.3.11 apr 5, 2006 page 35 of 113 rej03b0017-0311 3803 group (spec.h) (4) pulse period measurement mode ? mode selection this mode can be selected by setting ?010? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. when the pulse period meas urement is completed, the int 4 /cntr 2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003d 16 ) is set to ?1?. ? explanation of operation the cycle of the pulse which is input from the cntr 2 pin is measured. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is ?0?, the timer counts during the term from one falling edge of cntr 2 pin input to the next falling edge. when it is ?1?, the timer counts during the term from one rising e dge input to the next rising edge input. when the valid edge of meas urement completion/start is detected, the 1?s complement of the timer value is written to the timer latch and ?ffff 16 ? is set to the timer. furthermore when the timer unde rflows, the timer z interrupt request occurs and ?ffff 16 ? is set to the timer. when reading the timer z, the value of the timer latch (measured value) is read. the measured value is retained until the next measurement completion. ? precautions set the double-function port of cntr 2 pin and port p4 7 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse period). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. ?ffff 16 ? is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. figure.29 shows the timing chart of the pulse period measurement mode. (5) pulse width measurement mode ? mode selection this mode can be selected by setting ?011? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. when the pulse widths measurement is completed, the int 4 /cntr 2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003d 16 ) is set to ?1?. ? explanation of operation the pulse width which is input from the cntr 2 pin is measured. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is ?0?, the timer counts during the term from one rising edge input to the next falling edge input (?h? term). when it is ?1?, th e timer counts during the term from one falling edge of cntr 2 pin input to the next rising edge of input (?l? term). when the valid edge of measurement completion is detected, the 1?s complement of the timer value is written to the timer latch. when the valid edge of meas urement completion/start is detected, ?ffff 16 ? is set to the timer. when the timer z underflows, the timer z interrupt occurs and ?ffff 16 ? is set to the timer z. when reading the timer z, the value of the timer latch (measure d value) is read. the measured value is retained until the next measurement completion. ? precautions set the double-function port of cntr 2 pin and port p4 7 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse widths). since the timer latch in this mode is specialized for the read-out of measured values, do not pe rform any write operation during measurement. ?ffff 16 ? is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. figure.30 shows the timing chart of the pulse width measurement mode. rev.3.11 apr 5, 2006 page 36 of 113 rej03b0017-0311 3803 group (spec.h) (6) programmable waveform generating mode ? mode selection this mode can be selected by setting ?100? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. ? explanation of operation the operation is the same as the timer mode?s. moreover the timer outputs the data set in the output level latch (bit 4) of the timer z mode register (address 002a 16 ) from the cntr 2 pin each time the timer underflows. changing the value of the output level latch and the timer latch after an underflow makes it pos sible to output an optional waveform from the cntr 2 pin. ? precautions the double-function port of cntr 2 pin and port p4 7 is automatically set to the programmable waveform generating port in this mode. figure.31 shows the timing chart of the programmable waveform generating mode. (7) programmable one-shot generating mode ? mode selection this mode can be selected by setting ?101? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. the trigger to generate one-shot pulse can be selected by the int 1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003a 16 ). when it is ?0?, the falling edge active is selected; when it is ?1?, the rising edge active is selected. when the valid edge of the int 1 pin is detected, the int 1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003c 16 ) is set to ?1?. ? explanation of operation 1. ?h? one-shot pulse; bit 5 of timer z mode register = ?0? the output level of the cntr 2 pin is initialized to ?l? at mode selection. when trigge r generation (input signal to int 1 pin) is detected, ?h? is output from the cntr 2 pin. when an underflow occurs, ?l ? is output. the ?h? one-shot pulse width is set by the setting value to the timer z register low-order and high-order. when trigger generating is detected during timer count st op, although ?h? is output from the cntr 2 pin, ?h? output stat e continues because an underflow does not occur. 2. ?l? one-shot pulse; bit 5 of timer z mode register = ?1? the output level of the cntr 2 pin is initialized to ?h? at mode selection. when trigge r generation (input signal to int 1 pin) is detected, ?l? is output from the cntr 2 pin. when an underflow occurs, ?h? is output. the ?l? one-shot pulse width is set by the setting value to the timer z low- order and high-order. when tr igger generating is detected during timer count stop, although ?l? is output from the cntr 2 pin, ?l? output state c ontinues because an under- flow does not occur. ? precautions set the double-function port of int 1 pin and port p4 2 to input in this mode. the double-function port of cntr 2 pin and port p4 7 is automatically set to the progr ammable one-shot generating port in this mode. this mode cannot be used in low-speed mode. if the value of the cntr 2 active edge swit ch bit is changed during one-shot generating enable d or generating one-shot pulse, then the output level from cntr 2 pin changes. figure.32 shows the timing chart of the programmable one-shot generating mode. rev.3.11 apr 5, 2006 page 37 of 113 rej03b0017-0311 3803 group (spec.h) fig 25. block diagram of timer z p4 7 /cntr 2 ?001? x in output level latch programmable one-shot generating mode cntr 2 active edge switch bit programmable one-shot generating mode data bus to timer z interrupt request bit to int 1 interrupt request bit programmable waveform generating mode pulse output mode cntr 2 active edge switch bit pulse output mode timer z operating mode bits port p4 7 direction register port p4 7 latch pulse period measurement mode pulse width measurement mode timer z count stop bit count source selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) divider clock for timer z cntr 2 active edge switch bit d q t ?1? timer/event counter mode switch bit ?0? ?1? ?1? ?0? p4 2 /int 1 programmable one-shot generating circuit t q s q ?100? ?101? to cntr 2 interrupt request bit ?0? f(x cin ) edge detection circuit ?1? ?0? timer z low-order latch timer z low-order timer z high-order latch timer z high-order x cin rev.3.11 apr 5, 2006 page 38 of 113 rej03b0017-0311 3803 group (spec.h) fig 26. structure of timer z mode register b7 b0 timer z mode register (tzm : address 002a 16 ) timer z operating mode bits b2 b1 b0 0 0 0 : timer/event counter mode 0 0 1 : pulse output mode 0 1 0 : pulse period measurement mode 0 1 1 : pulse width measurement mode 1 0 0 : programmable waveform generating mode 1 0 1 : programmable one-shot generating mode 1 1 0 : not available 1 1 1 : not available timer z write control bit 0 : writing data to both latch and timer simultaneously 1 : writing data only to latch output level latch 0 : ?l? output 1 : ?h? output cntr 2 active edge switch bit 0 : ? event counter mode: count at rising edge ? pulse output mode: start outputting ?h? ? pulse period measurement mode: measurement between two falling edges ? pulse width measurement mode: measurement of ?h? term ? programmable one-shot generating mode: after start outputting ?l?, ?h? one-shot pulse generated ? interrupt at falling edge 1 : ? event counter mode: count at falling edge ? pulse output mode: start outputting ?l? ? pulse period measurement mode: measurement between two rising edges ? pulse width measurement mode: measurement of ?l? term ? programmable one-shot generating mode: after start outputting ?h?, ?l? one-shot pulse generated ? interrupt at rising edge timer z count stop bit 0 : count start 1 : count stop timer/event counter mode switch bit (1) 0 : timer mode 1 : event counter mode note 1 : when selecting the modes except the timer/event counter mode, set ?0? to this bit. rev.3.11 apr 5, 2006 page 39 of 113 rej03b0017-0311 3803 group (spec.h) fig 27. timing chart of timer/event counter mode fig 28. timing chart of pulse output mode ffff 16 0000 16 tl tr tr tr tl : value set to timer latch tr : timer interrupt request tr tr tr tr waveform output from cntr 2 pin cntr 2 cntr 2 ffff 16 0000 16 tl tl : value set to timer latch tr : timer interrupt request cntr 2 : cntr 2 interrupt request (cntr 2 active edge switch bit = ?0?; falling edge active) rev.3.11 apr 5, 2006 page 40 of 113 rej03b0017-0311 3803 group (spec.h) fig 29. timing chart of pulse period measurement mode (measuring term between two rising edges) fig 30. timing chart of pulse width measurement mode (measuring ?l? term) t3 tr tr t2 t1 t2 t3 cntr 2 of rising edge active tr : timer interrupt request cntr 2 : cntr 2 interrupt request signal input from cntr 2 pin cntr 2 ffff 16 0000 16 cntr 2 cntr 2 cntr 2 ffff 16 ffff 16 + t1 t3 tr t2 t1 t1 t3 cntr 2 interrupt of rising edge active; measurement of ?l? width tr : timer interrupt request cntr 2 : cntr 2 interrupt request signal input from cntr 2 pin cntr 2 ffff 16 0000 16 cntr 2 cntr 2 ffff 16 + t2 rev.3.11 apr 5, 2006 page 41 of 113 rej03b0017-0311 3803 group (spec.h) fig 31. timing chart of programmable waveform generating mode fig 32. timing chart of programmable one-shot gen erating mode (?h? one- shot pulse generating) signal output from cntr 2 pin ffff 16 0000 16 t3 t2 t1 t2 t3 l l t1 tr tr tr tr cntr 2 cntr 2 l : timer initial value tr : timer interrupt request cntr 2 : cntr 2 interrupt request (cntr 2 active edge switch bit = ?0?; falling edge active) l tr tr tr l l signal input from int 1 pin ffff 16 l cntr 2 cntr 2 l : one-shot pulse width tr : timer interrupt request cntr 2 : cntr 2 interrupt request (cntr 2 active edge switch bit = ?0?; falling edge active) signal output from cntr 2 pin rev.3.11 apr 5, 2006 page 42 of 113 rej03b0017-0311 3803 group (spec.h) serial interface ? serial i/o1 serial i/o1 can be used as either clock synchronous or asynchronous (uart) serial i/ o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to ?1?. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig 33. block diagram of clock synchronous serial i/o1 fig 34. operation of clock synchronous serial i/o1 serial i/o1 control register receive buffer register 1 receive shift register 1 clock control circuit 1/4 baud rate generator 1 f(x in ) 1/4 clock control circuit falling-edge detector transmit buffer register 1 transmit shift register 1 serial i/o1 status register f/f address 0018 16 receive buffer full flag (rbf) receive interrupt request (ri) shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) address 001c 16 brg count source selection bit address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 address 001a 16 data bus data bus p4 6 /s clk1 p4 4 /r x d 1 p4 5 /t x d 1 p4 7 /s rdy1 (f(x cin ) in low-speed mode) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output t x d 1 serial input r x d 1 write pulse to receive/transmit buffer register 1 (address 0018 16 ) overrun error (oe) detection notes 1 : as the transmit interrupt (ti) , which can be selected, either when the transmit buffer has emptied (tbe =1) or after the transm it shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control regi ster. 2 : if data is written to the transmit buffer register when tsc= 0, the transmit clock is generated continuously and serial data is outpu t continuously from the t x d pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ?1?. receive enable signal s rdy1 rev.3.11 apr 5, 2006 page 43 of 113 rej03b0017-0311 3803 group (spec.h) (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode sele ction bit (b6) of the serial i/o1 control register to ?0?. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift re gisters each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next characte r is being received. fig 35. block diagram of uart serial i/o1 fig 36. operation of uart serial i/o1 f(x in ) 1/4 oe pe fe 1/16 1/16 data bus data bus receive buffer register 1 address 0018 16 receive shift register 1 receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register 1 transmit shift register 1 address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart1 control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 status register serial i/o1 control register p4 6 /s clk1 p4 4 /r x d 1 p4 5 /t x d 1 (f(x cin ) in low-speed mode) tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 tbe=1 tsc=1* st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal serial output t x d 1 receive buffer read signal serial input r x d 1 generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) notes 1: error flag detection occurs at the same time that the rbf flag becomes ?1? (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?1?, can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?1?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changi ng to tsc=0. st d 0 d 1 sp d 0 d 1 st sp rev.3.11 apr 5, 2006 page 44 of 113 rej03b0017-0311 3803 group (spec.h) [transmit buffer register 1/receive buffer register 1 (tb1/rb1)] 0018 16 the transmit buffer register 1 and the receive buffer register 1 are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is ?0?. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to ?0? when the receive buffer register is read. if there is an error, it is detect ed at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a write to the serial i/o1 status register clea rs all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing ?0? to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to ?0? at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to ?1?, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become ?1?. [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register c onsists of eight control bits for the serial i/ o1 function. [uart1 control register (uart1con)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchro nous serial i/o is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the p4 5 /t x d 1 pin. [baud rate generator 1 (brg1)] 001c 16 the baud rate generator determin es the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. rev.3.11 apr 5, 2006 page 45 of 113 rej03b0017-0311 3803 group (spec.h) fig 37. structure of serial i/o1 control registers b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns ?1? when read) uart1 control register (uart1con : address 001b 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d 1 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return ?1? when read) brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o1 is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o1 is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p4 7 pin operates as normal i/o pin 1: p4 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p4 4 to p4 7 operate as normal i/o pins) 1: serial i/o1 enabled (pins p4 4 to p4 7 operate as serial i/o1 pins) serial i/o1 control register (sio1con : address 001a 16 ) serial i/o1 status register (sio1sts : address 0019 16 ) b0 b7 b0 b7 b0 rev.3.11 apr 5, 2006 page 46 of 113 rej03b0017-0311 3803 group (spec.h) rev.3.11 apr 5, 2006 page 47 of 113 rej03b0017-0311 3803 group (spec.h) 3. s rdy1 output of reception side ?note when signals are output from the s rdy1 pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy1 output enable bit, and the transmit enable bit to ?1? (transmit enabled). 4. setting serial i/o1 control register again ?note set the serial i/o1 control register again after the transmission and the reception circuits ar e reset by clearing both the transmit enable bit and the receive enable bit to ?0?. 5.data transmission control with referring to transmit shift register completion flag ? note after the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from ?1? to ?0? with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected ?note when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to ?1? at ?h? of the s clk1 input level. also, write data to the transmit buffer register at ?h? of the s clk1 input level. 7. transmit interrupt request when transmit enable bit is set ?note when using the transmit in terrupt, take the following sequence. 1. set the serial i/o1 transmit interrupt enable bit to ?0? (dis- abled). 2. set the transmit enable bit to ?1?. 3. set the serial i/o1 transmit interrupt request bit to ?0? after 1 or more instruction has executed. 4. set the serial i/o1 transmit interrupt enable bit to ?1? (enabled). ?reason when the transmit enable bit is set to ?1?, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to ?1?. therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. clear both the transmit enable bit (te) and the receive enable bit (re) to ?0? set the bits 0 to 3 and bit 6 of the serial i/o1 control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ?1? can be set with the ldm instruction at the same time rev.3.11 apr 5, 2006 page 48 of 113 rej03b0017-0311 3803 group (spec.h) ? serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/ o2, the transmitter and the receiver must use the same clock. if the internal clock is used, transfer is started by a write signal to the serial i/o2 register (address 001f 16 ). [serial i/o2 control register (sio2con)] 001d 16 the serial i/o2 control register contains eight bits which control various serial i/o2 functions. fig 38. structure of seri al i/o2 control register fig 39. block diagram of serial i/o2 serial i/o2 control register (sio2con : address 001d 16 ) b7 internal synchronous clock selection bits b2 b1 b0 000:f(x in )/8 (f(x cin )/8 in low-speed mode) 001:f(x in )/16 (f(x cin )/16 in low-speed mode) 010:f(x in )/32 (f(x cin )/32 in low-speed mode) 011:f(x in )/64 (f(x cin )/64 in low-speed mode) 110:f(x in )/128 f(x cin )/128 in low-speed mode) 111:f(x in )/256 (f(x cin )/256 in low-speed mode) serial i/o2 port selection bit 0: i/o port 1: s out2 , s clk2 signal output s rdy2 output enable bit 0: i/o port 1: s rdy2 signal output transfer direction selection bit 0: lsb first 1: msb first serial i/o2 synchronous clock selection bit 0: external clock 1: internal clock p5 1 /s out2 p-channel output disable bit 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) b0 f(x in ) serial i/o counter 2 (3) serial i/o2 register (8) synchronization circuit ?1? ?0? ?0? ?1? ?0? ?1? s clk2 ?0? ?1? divider 1/8 1/16 1/32 1/64 1/128 1/256 data bus serial i/o2 interrupt request serial i/o2 port selection bit serial i/o2 port selection bit serial i/o2 synchronous clock selection bit s rdy2 output enable bit external clock internal synchronous clock selection bits p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p5 2 latch p5 1 latch p5 3 latch p5 3 /s rdy2 (f(x cin ) in low-speed mode) s rdy2 address 001f 16 rev.3.11 apr 5, 2006 page 49 of 113 rej03b0017-0311 3803 group (spec.h) fig 40. timing of serial i/o2 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (1) serial i/o2 output s out2 serial i/o2 input s in2 receive enable signal s rdy2 serial i/o2 register write signal (2) serial i/o2 interrupt request bit set notes1 : when the internal clock is selected as th e transfer clock, the divide ratio of f(x in ), or (f(x cin ) in low-speed mode, can be selected by setting bits 0 to 2 of the serial i/o2 control register. 2 : when the internal clock is selected as the transfer clock, the s out2 pin goes to high impedance after transfer completion. rev.3.11 apr 5, 2006 page 50 of 113 rej03b0017-0311 3803 group (spec.h) ? serial i/o3 serial i/o3 can be used as either clock synchronous or asynchronous (uart) serial i/o3. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o3 mode can be selected by setting the serial i/o3 mode selection bit of the serial i/o3 control register (bit 6 of address 0032 16 ) to ?1?. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig 41. block diagram of clock synchronous serial i/o3 fig 42. operation of clock synchronous serial i/o3 serial i/o3 control register receive buffer register 3 receive shift register 3 clock control circuit 1/4 baud rate generator 3 f(x in ) 1/4 clock control circuit falling-edge detector transmit buffer register 3 transmit shift register 3 serial i/o3 status register f/f address 0030 16 receive buffer full flag (rbf) receive interrupt request (ri) shift clock serial i/o3 synchronous clock selection bit frequency division ratio 1/(n+1) address 002f 16 brg count source selection bit address 0030 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0031 16 address 0032 16 data bus data bus p3 6 /s clk3 p3 4 /r x d 3 p3 5 /t x d 3 p3 7 /s rdy3 (f(x cin ) in low-speed mode) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output t x d 3 serial input r x d 3 write pulse to receive/transmit buffer register (address 0030 16 ) overrun error (oe) detection notes 1 : as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transm it shift operation has ended (tsc=1), by setting the transmit interrupt source selection bi t (tic) of the serial i/o3 control regi ster. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is outpu t continuously from the t x d pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ?1?. receive enable signal s rdy3 rev.3.11 apr 5, 2006 page 51 of 113 rej03b0017-0311 3803 group (spec.h) (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o3 mode sele ction bit (b6) of the serial i/o3 control register to ?0?. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift re gisters each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next characte r is being received. fig 43. block diagram of uart serial i/o3 fig 44. operation of uart serial i/o3 f(x in ) 1/4 oe pe fe 1/16 1/16 data bus data bus receive buffer register 3 address 0030 16 receive shift register 3 receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator 3 frequency division ratio 1/(n+1) address 002f 16 st/sp/pa generator transmit buffer register 3 transmit shift register 3 address 0030 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0031 16 st detector sp detector uart3 control register address 0033 16 character length selection bit address 0032 16 brg count source selection bit transmit interrupt source selection bit serial i/o3 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o3 status register serial i/o3 control register p3 6 /s clk3 p3 4 /r x d 3 p3 5 /t x d 3 (f(x cin ) in low-speed mode) tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 tbe=1 tsc=1* st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal serial output t x d 3 receive buffer read signal serial input r x d 3 * generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) notes 1 : error flag detection occurs at the same time that the rbf flag becomes ?1? (at 1st stop bit, during reception). 2 : as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?1?, can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o3 control register. 3 : the receive interrupt (ri) is set when the rbf flag becomes ?1?. 4 : after data is written to the transmit buffer when tsc=1, 0. 5 to 1.5 cycles of the data shift cycle are necessary until changin g to tsc=0. st d 0 d 1 sp d 0 d 1 st sp rev.3.11 apr 5, 2006 page 52 of 113 rej03b0017-0311 3803 group (spec.h) [transmit buffer register 3/receive buffer register 3 (tb3/rb3)] 0030 16 the transmit buffer register 3 and the receive buffer register 3 are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is ?0?. [serial i/o3 status register (sio3sts)] 0031 16 the read-only serial i/o3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o3 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to ?0? when the receive buffer register is read. if there is an error, it is detect ed at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a write to the serial i/o3 status register clea rs all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing ?0? to the serial i/o3 enable bit sioe (bit 7 of the serial i/o3 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o3 status register are initialized to ?0? at reset, but if the transmit enable bit (bit 4) of the serial i/o3 control register has been set to ?1?, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become ?1?. [serial i/o3 control register (sio3con)] 0032 16 the serial i/o3 control register c onsists of eight control bits for the serial i/ o3 function. [uart3 control register (uart3con)] 0033 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchro nous serial i/o is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the p3 5 /t x d 3 pin. [baud rate generator 3 (brg3)] 002f 16 the baud rate generator determin es the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. rev.3.11 apr 5, 2006 page 53 of 113 rej03b0017-0311 3803 group (spec.h) fig 45. structure of serial i/o3 control registers b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns ?1? when read) uart3 control register (uart3con : address 0033 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p3 5 /t x d 3 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return ?1? when read) brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o3 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o3 is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o3 is selected, external clock input divided by 16 when uart is selected. s rdy3 output enable bit (srdy) 0: p3 7 pin operates as normal i/o pin 1: p3 7 pin operates as s rdy3 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o3 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o3 enable bit (sioe) 0: serial i/o3 disabled (pins p3 4 to p3 7 operate as normal i/o pins) 1: serial i/o3 enabled (pins p3 4 to p3 7 operate as serial i/o3 pins) serial i/o3 control register (sio3con : address 0032 16 ) serial i/o3 status register (sio3sts : address 0031 16 ) b0 b7 b0 b7 b0 rev.3.11 apr 5, 2006 page 54 of 113 rej03b0017-0311 3803 group (spec.h) rev.3.11 apr 5, 2006 page 55 of 113 rej03b0017-0311 3803 group (spec.h) 3. s rdy3 output of reception side ?note when signals are output from the s rdy3 pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy3 output enable bit, and the transmit enable bit to ?1? (transmit enabled). 4. setting serial i/o3 control register again ?note set the serial i/o3 control register again after the transmission and the reception circuits ar e reset by clearing both the transmit enable bit and the receive enable bit to ?0?. 5.data transmission control with referring to transmit shift register completion flag ?note after the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from ?1? to ?0? with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected ?note when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to ?1? at ?h? of the s clk3 input level. also, write data to the transmit buffer register at ?h? of the s clk input level. 7. transmit interrupt request when transmit enable bit is set ?note when using the transmit in terrupt, take the following sequence. 1. set the serial i/o3 transmit interrupt enable bit to ?0? (dis- abled). 2. set the transmit enable bit to ?1?. 3. set the serial i/o3 transmit interrupt request bit to ?0? after 1 or more instruction has executed. 4. set the serial i/o3 transmit interrupt enable bit to ?1? (enabled). ?reason when the transmit enable bit is set to ?1?, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to ?1?. therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. clear both the transmit enable bit (te) and the receive enable bit (re) to ?0? set the bits 0 to 3 and bit 6 of the serial i/o3 control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ?1? can be set with the ldm instruction at the same time rev.3.11 apr 5, 2006 page 56 of 113 rej03b0017-0311 3803 group (spec.h) pulse width modulation (pwm) the 3803 group (spec.h qzrom version) has pwm functions with an 8-bit resolution, based on a signal that is the clock input x in or that clock input divided by 2 or the clock input x cin or that clock input divided by 2 in low-speed mode. ? data setting the pwm output pin also functions as port p5 6 . set the pwm period by the pwm prescaler, an d set the ?h? term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255): pwm period = 255 (n+1) / f(x in ) = 31.875 (n+1) s (when f(x in ) = 8 mhz, count source selection bit = ?0?) output pulse ?h? term = pwm period m / 255 = 0.125 (n+1) m s (when f(x in ) = 8 mhz, count source selection bit = ?0?) ? pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to ?1?, operation starts by initializing the pwm output circuit, and pulses are output starting at an ?h?. if the pwm register or pwm pr escaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. fig 46. timing of pwm period fig 47. block diagram of pwm function 31.875 m (n+1) 255 s t = [31.875 (n+1)] s pwm output m : contents of pwm register n : contents of pwm prescaler t : pwm period (when f(x in ) = 8 mhz, count source selection bit = ?0?) data bus count source selection bit ?0? ?1? pwm prescaler pre-latch pwm register pre-latch pwm prescaler latch pwm register latch transfer control circuit pwm register 1/2 x in (x cin at low- speed mode) port p5 6 latch pwm function enable bit port p5 6 pwm prescaler rev.3.11 apr 5, 2006 page 57 of 113 rej03b0017-0311 3803 group (spec.h) fig 48. structure of pwm control register fig 49. pwm output timing when pwm register or pwm prescaler is changed rev.3.11 apr 5, 2006 page 58 of 113 rej03b0017-0311 3803 group (spec.h) a/d converter (successive approximation type) [ad conversion register 1, 2 (ad1, ad2)] 0035 16 , 0038 16 the ad conversion register is a read-only register that stores the result of an a/d conversion. when reading this register during an a/d conversion, the previous conversion result is read. bit 7 of the ad conversion regi ster 2 is the conversion mode selection bit. when this bit is set to ?0?, the a/d converter becomes the 10-bit a/d mode. when this bit is set to ?1?, that becomes the 8-bit a/d mode. the conversion result of the 8-bit a/d mode is stored in the ad c onversion register 1. as for 10-bit a/d mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the ad conv ersion registers 1, 2 after a/d conversion is completed (in figure.51). as for 10-bit a/d mode, the 8-bit reading inclined to msb is performed when reading the ad co nverter register 1 after a/d conversion is started; and when the ad converter register 1 is read after reading the ad converter register 2, the 8-bit reading inclined to lsb is performed. [ad/da control regi ster (adcon)] 0034 16 the ad/da control register controls the a/d conversion process. bits 0 to 2 and bit 4 se lect a specific analog input pin. bit 3 signals the completion of an a/d conversion. the value of this bit remains at ?0? during an a/d conversion, and changes to ?1? when an a/d conversion ends. writing ?0? to this bit starts the a/d conversion. ? comparison voltage generator the comparison voltage generato r divides the voltage between av ss and v ref into 1024, and that outputs the comparison voltage in the 10-bit a/d mode (256 division in 8-bit a/d mode). the a/d converter successive ly compares the comparison voltage vref in each mode, dividing the v ref voltage (see below), with the input voltage. ? 10-bit a/d mode (10-bit reading) vref = n (n = 0 ? 1023) ? 10-bit a/d mode (8-bit reading) vref = n (n = 0 ? 255) ? 8-bit a/d mode vref = (n ? 0.5) (n = 1 ? 255) =0 (n = 0) ? channel selector the channel selector se lects one of ports p6 7 /an 7 to p6 0 /an 0 or p0 7 /an 15 to p0 0 /an 8 , and inputs the voltage to the comparator. ? comparator and control circuit the comparator and control circ uit compares an analog input voltage with the comparison voltage , and then stores the result in the ad conversion registers 1, 2. when an a/d conversion is completed, the control circuit sets the ad conve rsion completion bit and the ad interrupt request bit to ?1?. note that because the comparator consists of a capacitor coupling, set f(x in) to 500 khz or more during an a/d conversion. fig 50. structure of ad/da control register fig 51. structure of 10-bit a/d mode reading v ref 256 ------------- v ref 256 ------------- ad/da control register (adcon : address 0034 16 ) analog input pin selection bits 1 0 0 0: p6 0 /an 0or p0 0 /an 8 0 0 1: p6 1 /an 1or p0 1 /an 9 0 1 0: p6 2 /an 2or p0 2 /an 10 0 1 1: p6 3 /an 3or p0 3 /an 11 1 0 0: p6 4 /an 4or p0 4 /an 12 1 0 1: p6 5 /an 5or p0 5 /an 13 1 1 0: p6 6 /an 6or p0 6 /an 14 1 1 1: p6 7 /an 7or p0 7 /an 15 ad conversion completion bit 0: conversion in progress 1: conversion completed analog input pin selection bit 2 0: an 0 to an 7 side 1: an 8 to an 15 side not used (returns ?0? when read) da 1 output enable bit 0: da 1 output disabled 1: da 1 output enabled da 2 output enable bit 0: da 2 output disabled 1: da 2 output enabled b7 b0 b2 b1 b0 10-bit reading (read address 0038 16 before 0035 16 ) ad conversion register 2 (ad2: address 0038 16 ) ad conversion register 1 (ad1: address 0035 16 ) note : bits 2 to 6 of address 0038 16 become ?0? at reading. 8-bit reading (read only address 0035 16 ) ad conversion register 1 (ad1: address 0035 16 ) b9 b7 b0 b8 b7 b6 b5 b4 b3 b2 b7 b0 b9 b8 b7 b7 b0 b6 b5 b4 b3 b2 b1 b0 0 v ref 1024 ------------- rev.3.11 apr 5, 2006 page 59 of 113 rej03b0017-0311 3803 group (spec.h) fig 52. block diagram of a/d converter c h a n n e l s e l e c t o r a/d control circuit ad conversion register 1 resistor ladder v ref av ss comparator a/d converter interrupt request 10 p6 0 /an 0 p6 1 /an 1 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 b7 b0 4 data bus ad/da control register (address 0034 16 ) ad conversion register 2 (address 0038 16 ) (address 0035 16 ) rev.3.11 apr 5, 2006 page 60 of 113 rej03b0017-0311 3803 group (spec.h) d/a converter the 3803 group (spec.h) has tw o internal d/a converters (da 1 and da 2 ) with 8-bit resolution. the d/a conversion is performed by setting the value in each da conversion register. the resu lt of d/a conversion is output from the da 1 or da 2 pin by setting the da output enable bit to ?1?. when using the d/a converter, th e corresponding port direction register bit (p3 0 /da 1 or p3 1 /da 2 ) must be set to ?0? (input status). the output analog voltage v is determined by the value n (decimal notation) in the da c onversion register as follows: v = v ref n/256 (n = 0 to 255) where v ref is the reference voltage. at reset, the da conversion re gisters are cleared to ?00 16 ?, and the da output enable bits ar e cleared to ?0?, and the p3 0 /da 1 and p3 1 /da 2 pins become high impedance. the da output does not have buffers. accordingly, connect an external buffer when driving a low-impedance load. fig 53. block diagram of d/a converter fig 54. equivalent connection circuit of d/a converter (da1) da 1 conversion register (8) da 1 output enable bit p3 0 /da 1 data bus r-2r resistor ladder da 2 conversion register (8) da 2 output enable bit p3 1 /da 2 r-2r resistor ladder da 1 output enable bit av ss v ref r 2r rr r r r r 2r 2r 2r 2r 2r 2r 2r 2r lsb ?1??0? msb da 1 conversion register p3 0 /da 1 ?0? ?1? rev.3.11 apr 5, 2006 page 61 of 113 rej03b0017-0311 3803 group (spec.h) watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away ). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. ? watchdog timer initial value watchdog timer l is set to ?ff 16 ? and watchdog timer h is set to ?ff 16 ? by writing to the watchdog time r control regi ster (address 001e 16 ) or at a reset. any write instruction that causes a write signal can be used, such as the sta, ldm, clb, etc. data can only be written to bits 6 and 7 of the watchdog timer control register. regardless of the value wr itten to bits 0 to 5, the above- mentioned value will be set to each timer. ? watchdog timer operations the watchdog timer stops at rese t and starts to count down by writing to the watchdog timer control register (address 001e 16 ). an internal reset occurs at an underflow of the watchdog timer h. the reset is released after waiting for a reset release time and the program is processed from the reset vector address. accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an underflow. if writing to the watchdog timer control register is not performed once, the watchdog timer does not function. ? bit 6 of watchdog timer control register ? when bit 6 of the watchdog timer control register is ?0?, the mcu enters the stop mode by ex ecution of stp instruction. just after releasing the stop mode, the watchdog timer restarts counting (note.) . when executing the wit instruction, the watchdog timer does not stop. ? when bit 6 is ?1?, execution of stp instruction causes an internal reset. when this bit is set to ?1? once, it cannot be rewritten to ?0? by program. bit 6 is ?0? at reset. the following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer h. bit 7 of the watchdog timer control register is ?0?: when x cin = 32.768 khz; 32 s when x in = 16 mhz; 65.536 ms bit 7 of the watchdog timer control register is ?1?: when x cin = 32.768 khz; 125 ms when x in = 16 mhz; 256 s note. the watchdog timer continues to count even while waiting for a stop release. therefore, make sure that watchdog timer h does not underflow during this period. fig 55. block diagram of watchdog timer fig 56. structure of watchdog timer control register x in data bus x cin ?10? ?00? ?01? main clock division ratio selection bits (1) ?0? ?1? 1/16 watchdog timer h count source selection bit reset circuit stp instruction function selection bit watchdog timer h (8) ?ff 16 ? is set when watchdog timer control register is written to. internal reset watchdog timer l (8) ?ff 16 ? is set when watchdog timer control register is written to. note 1 : any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. stp instruction reset b7 watchdog timer h (for read-out of high-order 6 bit) stp instruction function selection bit 0: entering stop mode by execution of stp instruction 1: internal reset by execution of stp instruction watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer control register (wdtcon : address 001e 16 ) b0 rev.3.11 apr 5, 2006 page 62 of 113 rej03b0017-0311 3803 group (spec.h) reset circuit to reset the microcomputer, reset pin should be held at an ?l? level for 16 cycles or more of x in . then the reset pin is returned to an ?h? level (the power source voltage should be between 1.8 v and 5.5 v (between 2.7 v to 5.5 v for flash memory version), and the oscillat ion should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage for the mask rom vers ion is less than 0.29 v for v cc of 1.8 v. in the flash memory version, input to the reset pin in the following procedure. ? when power source is stabilized (1) input ?l? level to reset pin. (2) input ?l? level for 16 cycles or more to x in pin. (3) input ?h? level to reset pin. ? at power-on (1) input ?l? level to reset pin. (2) increase the power source voltage to 2.7 v. (3) wait for td(p-r) until intern al power source has stabilized. (4) input ?l? level for 16 cycles or more to x in pin. (5) input ?h? level to reset pin. fig 57. reset circuit example fig 58. reset sequence v cc reset v cc reset power source voltage detection circuit example at v cc = 5 v (1) 0 v 0 v v cc reset 0.2v cc or less 0v 0v v cc reset td(p-r)+x in 16 cycles or more 5v 5v 2.7v notes 1: reset release voltage ? mask rom version: vcc = 1.8 v ? flash memory version: vcc = 2.7 v 2: in the flash memory version, this time is required td(p-r)+x in 16 cycles or more. (2) reset internal reset data address sync x in ? ? ? ? fffc fffd ad h , l ? ? ? ?ad l ad h notes 1: the frequency relation of f(x in ) and f( ) is f(x in ) = 8 ? f( ). 2: the question marks (?) indicate an undefined state that depends on the previous state. reset address from the vector table. x in : 10.5 to 18.5 clock cycles rev.3.11 apr 5, 2006 page 63 of 113 rej03b0017-0311 3803 group (spec.h) fig 59. internal status at reset note : x: not fixed. since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) timer 12, x count source selection register (t12xcss) timer y, z count source selection register (tyzcss) misrg transmit/receive buffer register 1 (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator 1 (brg1) serial i/o2 control register (sio2con) watchdog timer control register (wdtcon) serial i/o2 register (sio2) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) register contents address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 timer z (low-order) (tzl) timer z (high-order) (tzh) timer z mode register (tzm) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) baud rate generator 3 (brg3) transmit/receive buffer register 3 (tb3/rb3) serial i/o3 status register (sio3sts) serial i/o3 control register (sio3con) uart3 control register (uart3con) ad/da control register (adcon) ad conversion register 1 (ad1) da1 conversion register (da1) da2 conversion register (da2) ad conversion register 2 (ad2) interrupt source selection register (intsel) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) flash memory control register 0 (fmcr0) flash memory control register 1 (fmcr1) flash memory control register 2 (fmcr2) port p0 pull-up control register (pull0) port p1 pull-up control register (pull1) port p2 pull-up control register (pull2) port p3 pull-up control register (pull3) port p4 pull-up control register (pull4) port p5 pull-up control register (pull5) port p6 pull-up control register (pull6) processor status register program counter (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) (61) (62) (63) (64) (65) (66) (67) (68) 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0fe0 16 0fe0 16 0fe2 16 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 (ps) (pc h ) (pc l ) register contents address 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 01 16 ff 16 00 16 00 16 ff 16 ff 16 00 16 ff 16 ff 16 00 16 00 16 00 16 00 16 00 16 ff 16 00 16 00 16 ff 16 00 16 00 16 00 16 00 16 x 0 1 1 x 0 1 1 x 0 0 0 x 0 0 0 x 0 1 1 x 0 1 1 x 0 0 0 x 1 0 0 0 x 1 x 0 x 1 x 0 x 1 x 0 x 1 x 0 x 1 x 1 x 1 x 1 x 0 x 1 x 0 x x 0 x 0 0 0 x x x x x 0 0 0 0 0 x x x x x 1 0 1 0 0 x x x x x 0 0 0 0 0 x x x x x 0 x 0 0 0 x x x x x 0 0 0 1 0 x x x x x 1 0 0 1 0 x x x x x 0 0 0 1 1 x x x x 00 16 00 16 00 16 00 16 fffc 16 contents fffd 16 contents 00 16 00 16 00 16 x xx1x xxx 1 0000 000 0 0000 010 1 0010 010 rev.3.11 apr 5, 2006 page 64 of 113 rej03b0017-0311 3803 group (spec.h) clock generating circuit the 3803 group (spec.h) has two bu ilt-in oscillat ion circuits: main clock x in -x out oscillation circuit and sub clock x cin - x cout oscillation circuit. an oscill ation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer?s recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip.(an exte rnal feed-back resistor may be needed depending on conditions.) however, an external feed- back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillatio n circuit starts oscilla ting, and x cin and x cout pins function as i/o ports. ? frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after reset is released, this mode is selected. (2) high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . (4) low power dissipation mode the low power consumption ope ration can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to ?1?. when the main clock x in is restarted (by setting the main clock stop bit to ?0?), set sufficient time for oscillation to stabilize. the sub-clock x cin -x cout oscillating circuit can not directly input clocks that are generated externally. accordingly, make sure to cause an external resonator to oscillate. oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an ?h? level, and x in and x cin oscillators stop. when the oscillation stabilizing time set after stp instruction released bit (bit 0 of address 0010 16 ) is ?0?, the prescaler 12 is set to ?ff 16 ? and timer 1 is set to ?01 16 ?. when the oscillation stabilizing time set after stp instruction released bit is ?1?, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. after stp instruction is released , the input of the prescaler 12 is connected to count source which had set at executing the stp instruction, and the output of the prescaler 12 is connected to timer 1. oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the cpu (remains at ?h?) until timer 1 underfl ows. the internal clock is supplied for the first time, when timer 1 un derflows. this en sures time for the clock oscillation using the ceramic resonators to be stabilized. when the oscillator is restarted by reset, apply ?l? level to the reset pin until the oscillati on is stable since a wait time will not be generated. (2) wait mode if the wit instruction is executed, the internal clock stops at an ?h? level, but the oscillator does not stop. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that the interrupts will be received to release the stp or wit state, their interrupt enable bits must be set to ?1? before executing of the stp or wit instruction. when releasing the stp state, the prescaler 12 and timer 1 will start counting the clock x in divided by 16. accordingly, set the timer 1 interrupt enable bit to ?0? before executing the stp instruction. rev.3.11 apr 5, 2006 page 65 of 113 rej03b0017-0311 3803 group (spec.h) fig 60. ceramic resonator circuit fig 61. external clock input circuit x cin x cout x in x out c in c out c cin c cout rf rd rd (1) note 1 : insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. also, if the oscillator manufacturer?s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between x in and x out following the instruction. x in x out external oscillation circuit v cc v ss open x cin x cout external oscillation circuit open v cc v ss rev.3.11 apr 5, 2006 page 66 of 113 rej03b0017-0311 3803 group (spec.h) fig 62. system clock generating circuit block diagram (single-chip mode) wit instruction stp instruction timing (internal clock) s r q s r q main clock stop bit s r q 1/2 1/4 x in x out x cout x cin interrupt request interrupt disable flag l reset port x c switch bit ?1? ?0? low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (1) main clock division ratio selection bits (1) notes1 : either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. when low-speed mode is selected, set port x c switch bit (b4) to ?1?. 2 :f(x in )/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the stp instruction is supplied as the count source at executing stp instruction. 3 : when bit 0 of misrg is ?0?, timer 1 is set ?01 16 ? and prescaler 12 is set ?ff 16 ? automatically. when bit 0 of misrg is ?1? , set the appropriate value to them in accordance with oscillation stabilizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. 4 : although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. prescaler 12 timer 1 reset or stp instruction (2) reset (3) (4) stp instruction divider rev.3.11 apr 5, 2006 page 67 of 113 rej03b0017-0311 3803 group (spec.h) fig 63. state transiti ons of system clock cm 4 : port x c switch bit 0 : i/o port function (stop oscillating) 1 : x cin- x cout oscillating function cm 5 : main clock (x in -x out ) stop bit 0 : operating 1 : stopped cm 7 , cm 6 : main clock division ratio selection bit b7 b6 00 : = f(x in )/2 (high-speed mode) 01 : = f(x in )/8 (middle-speed mode) 10 : = f(x cin )/2 (low-speed mode) 1 1 : not available reset cm 4 ?1? ?0? c m 4 ? 0 ? ? 1 ? c m 6 ? 1 ? ? 0 ? c m 4 ? 1 ? ? 0 ? c m 6 ? 1 ? ? 0 ? cm 7 ?1? ?0? cm 4 ?1? ?0? cm 5 ?1? ?0? cm 6 ?1? ?0? cm 6 ?1? ?0? cpu mode register (cpum : address 003b 16 ) b7 b4 c m 7 ? 0 ? ? 1 ? c m 6 ? 1 ? ? 0 ? high-speed mode (f( ) = 4 mhz) cm 7 =0 cm 6 =0 cm 5 =0 (8 mhz oscillating) cm 4 =0 (32 khz stopped) high-speed mode (f( ) = 4 mhz) cm 7 =0 cm 6 =0 cm 5 =0 (8 mhz oscillating) cm 4 =1 (32 khz oscillating) notes1 : switch the mode by the allows shown between the mo de blocks. (do not switch between the modes directly without an allow.) 2 : the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : timer operates in the wait mode. 4 : when the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and timer 1 in middle/high- speed mode. 5 : when the stop mode is ended, a delay of approximately 0.25 s occurs by timer 1 and timer 2 in low-speed mode. 6 : wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle/ high-speed mode. 7 : the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. indicates the internal clock. middle-speed mode (f( ) = 1 mhz) cm 7 =0 cm 6 =1 cm 5 =0 (8 mhz oscillating) cm 4 =0 (32 khz stopped) middle-speed mode (f( ) = 1 mhz) cm 7 =0 cm 6 =1 cm 5 =0 (8 mhz oscillating) cm 4 =1 (32 khz oscillating) low-speed mode (f( ) = 16 khz) cm 7 =1 cm 6 =0 cm 5 =0 (8 mhz oscillating) cm 4 =1 (32 khz oscillating) low-speed mode (f( ) = 16 khz) cm 7 =1 cm 6 =0 cm 5 =1 (8 mhz stopped) cm 4 =1 (32 khz oscillating) rev.3.11 apr 5, 2006 page 68 of 113 rej03b0017-0311 3803 group (spec.h) flash memory mode the 3803 group (spec.h)?s flash memory version has the flash memory that can be rewritte n with a single power source. for this flash memory, three flash memory modes are available in which to read, program, an d erase: the parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and the cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). this flash memory version has some blocks on the flash memory as shown in figure 64 and each block can be erased. in addition to the ordinary us er rom area to store the mcu operation control program, the fl ash memory has a boot rom area that is used to store a pr ogram to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode c ontrol program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the user?s application system. this boot rom area can be rewritten in only parallel i/o mode. summary table 11 lists the summary of the 3803 group (spec.h) flash memory version. note: 1. the boot rom area has had a standard serial i/o mode cont rol program stored in it when shipped from the factory. this boot rom area can be erased and written in only parallel i/o mode. table 11 summary of 3803 group (spec.h)?s flash memory version item specifications power source voltage (vcc) v cc = 2.7 to 5.5 v program/erase vpp voltage (v pp )v cc = 2.7 to 5.5 v flash memory mode 3 modes; parallel i/o mode, standard serial i/o mode, cpu rewrite mode erase block division user rom area/data rom area refer to figure.64. boot rom area (1) not divided (4k bytes) program method in units of bytes erase method block erase program/erase control me thod program/erase control by software command number of commands 5 commands number of program/erase times 100 rom code protection available in parallel i/o mode and standard serial i/o mode rev.3.11 apr 5, 2006 page 69 of 113 rej03b0017-0311 3803 group (spec.h) boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure.64 for details a bout the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset and the cnv ss pin high after pulling the p4 5 /txd 1 pin and cnv ss pin high, the cpu starts operating (start address of progr am is stored into addresses fffc 16 and fffd 16 ) using the control program in the boot rom area. this mode is called the ?boot mode?. also, user rom area can be rewritten using the control program in the boot rom area. block address block addresses refer to the maximum address of each block. these addresses are used in the block erase command. cpu rewrite mode in cpu rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure.64 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control program must be transferred to internal ram area before it can be executed. fig 64. block diagram of built-in flash memory data block a: 2k bytes block 3: 24k bytes block 2: 16k bytes block 1: 8 k bytes block 0: 8 k bytes ffff 16 e000 16 c000 16 8000 16 2000 16 1800 16 1000 16 user rom area data block b: 2k bytes sfr area internal ram area (2k bytes) ffff 16 1000 16 0fff 16 0fe0 16 083f 16 0040 16 0000 16 ffff 16 f000 16 boot rom area 4k bytes sfr area internal flash memory area (60k bytes) ram notes1 : the boot rom area can be rewritten in a parallel i/o mode. (access to except boot rom area is disabled.) 2 : to specify a block, use the maximum address in the block. rev.3.11 apr 5, 2006 page 70 of 113 rej03b0017-0311 3803 group (spec.h) outline performance cpu rewrite mode is usable in th e single-chip or boot mode. the only user rom area can be rewritten. in cpu rewrite mode, the cpu erases, programs and reads the internal flash memory as instructed by software commands. this rewrite control program must be transferred to internal ram area before it can be executed. the mcu enters cpu rewrite mode by setting ?1? to the cpu rewrite mode select bit (bit 1 of address 0fe0 16 ). then, software commands can be accepted. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verifi ed by reading the status register. figure.65 shows the flash me mory control register 0. bit 0 of the flash memory control register 0 is the ry/by status flag used exclusively to read the operating status of the flash memory. during programming and erase operations, it is ?0? (busy). otherwise, it is ?1? (ready). bit 1 of the flash memory contro l register 0 is the cpu rewrite mode select bit. when this bit is set to ?1?, the mcu enters cpu rewrite mode. and then, software commands can be accepted. in cpu rewrite mode, the cpu b ecomes unable to access the internal flash memory directly . therefore, use the control program in the internal ram for write to bit 1. to set this bit 1 to ?1?, it is necessary to write ?0? and then write ?1? in succession to bit 1. the bit can be set to ?0? by only writing ?0?. bit 2 of the flash memory control register 0 is the 8 kb user block e/w enable bit. by setting combination of bit 4 of the flash memory control register 2 and this bit as shown in table 12, e/w is disabled to user block in the cpu rewriting mode. bit 3 of the flash memory contro l register 0 is the flash memory reset bit used to reset the control circuit of internal flash memory. this bit is used when flash me mory access has failed. when the cpu rewrite mode select bit is ?1?, setting ?1? for this bit resets the control circuit. to release the reset, it is necessary to set this bit to ?0?. bit 5 of the flash memory control register 0 is the user rom area select bit and is valid only in the boot mode. setting this bit to ?1? in the boot mode switches an accessible area from the boot rom area to the user rom area. to use the cpu rewrite mode in the boot mode, set this bit to ?1 ?. to rewrite bit 5, execute the useroriginal reprogramming contro l software transferred to the internal ram in advance. bit 6 of the flash memory control register 0 is the program status flag. this bit is set to ?1? when writing to flash memory is failed. when program error occurs, the block cannot be used. bit 7 of the flash memory contro l register 0 is the erase status flag. this bit is set to ?1? when erasing flash memory is failed. when erase error occurs, the block cannot be used. figure.66 shows the flash me mory control register 1. bit 0 of the flash memory control register 1 is the erase suspend enable bit. by setting this bit to ?1?, the erase suspend mode to suspend erase processing tempor aly when block erase command is executed can be used. in order to set this bit to ?1?, writing ?0? and ?1? in succession to bit 0. in order to set this bit to ?0?, write ?0? only to bit 0. bit 1 of the flash memory control register 1 is the erase suspend request bit. by setting this bit to ?1? when erase suspend enable bit is ?1?, the erase processing is suspended. bit 6 of the flash memory control register 1 is the erase suspend flag. this bit is cleared to ?0? at the flash erasing. fig 65. structure of flash memory control register 0 fig 66. structure of flash memory control register 1 flash memory control register 0 (fmcr0: address : 0fe0 16 : initial value: 01 16 ) ry/by status flag 0 : busy (being written or erased) 1 : ready cpu rewrite mode select bit (1) 0 : cpu rewrite mode invalid 1 : cpu rewrite mode valid 8kb user block e/w enable bit (1, 2) 0 : e/w disabled 1 : e/w enabled flash memory reset bit (3, 4) 0 : normal operation 1 : reset not used (do not write ?1? to this bit.) user rom area select bit (5) 0 : boot rom area is accessed 1 : user rom area is accessed program status flag 0: pass 1: error erase status flag 0: pass 1: error b7 b0 notes 1 : for this bit to be set to ?1?, the user needs to write a ?0? and then a ?1? to it in succession. for this bit to be set to ?0?, write ?0? only to this bit. 2 : this bit can be written only when cpu rewrite mode select bit is ?1?. 3 : effective only when the cpu rewrite mode select bit = ?1?. fix this bit to ?0? when the cpu rewrite mode select bit is ?0?. 4 : when setting this bit to ?1? (when the control circuit of flash memory is reset), the flash memory cannot be accessed for 10 s. 5 : write to this bit in program on ram flash memory control register 1 (fmcr1: address : 0fe1 16 : initial value: 40 16 ) erase suspend enble bit (1) 0 : suspend invalid 1 : suspend valid erase suspend request bit (2) 0 : erase restart 1 : suspend request not used (do not write ?1? to this bit.) erase suspend flag 0 : erase active 1 : erase inactive (erase suspend mode) not used (do not write ?1? to this bit.) b7 b0 notes 1 : for this bit to be set to ?1?, the user needs to write a ?0? and then a ?1? to it in succession. for this bit to be set to ?0?, write ?0? only to this bit. 2 : effective only when the suspend enable bit = ?1?. rev.3.11 apr 5, 2006 page 71 of 113 rej03b0017-0311 3803 group (spec.h) fig 67. structure of flash memory control register 2 figure.68 shows a flowchart for se tting/releasing cp u rewrite mode. fig 68. cpu rewrite mode set/release flowchart be sure to execute flash memory control register 2 (fmcr2: address : 0fe2 16 : initial value: 45 16 ) not used not used (do not write ?1? to this bit.) not used all user block e/w enable bit (1, 2) 0 : e/w disabled 1 : e/w enabled not used b7 b0 notes 1 : for this bit to be set to ?1?, the user needs to write a ?0? and then a ?1? to it in succession. for this bit to be set to ?0?, write ?0? only to this bit. 2 : effective only when the cpu rewrite mode select bit = ?1?. table 12 state of e/w inhibition function all user block e/w enable bit 8 kb user block e/w enable bit 8 kb 2 block addresses c000 16 to ffff 16 16 kb + 24 kb block addresses 2000 16 to bfff 16 data block addresses 1000 16 to 1fff 16 0 0 e/w disabled e/w disabled e/w enabled 0 1 e/w disabled e/w disabled e/w enabled 1 0 e/w disabled e/w enabled e/w enabled 1 1 e/w enabled e/w enabled e/w enabled start single-chip mode or boot mode set cpu mode register (1) jump to control program transferred to internal ram (subsequent operations are executed by control program in this ram) transfer cpu rewrite mode control program to internal ram set cpu rewrite mode select bit to ?1? (by writing ?0? and then ?1? in succession) using software command executes erase, program, or other operation end write ?0? to cpu rewrite mode select bit set all user block e/w enable bit to ?1? (by writing ?0? and then ?1? in succession) set 8 kb user block e/w enable bit (at e/w disabled; writing ?0? , at e/w enabled; writing ?0? and then ?1? in succession execute read array command (2) set all user block e/w enable bit to ?0? set 8 kb user block e/w enable bit to ?0? notes 1 : set the main clock as follows depending on the clock division ratio selection bits of cpu mode register (bits 6, 7 of address 003b 16 ). 2 : before exiting the cpu rewrite mode after completing erase or program operation, always be sure to execute the read array command. rev.3.11 apr 5, 2006 page 72 of 113 rej03b0017-0311 3803 group (spec.h) rev.3.11 apr 5, 2006 page 73 of 113 rej03b0017-0311 3803 group (spec.h) software commands table 13 lists the so ftware commands. after setting the cpu rewrite mode select bit to ?1?, execute a software command to specify an erase or program operation. each software command is explained below. ? read array command (ff 16 ) the read array mode is entere d by writing the command code ?ff 16 ? in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (d 0 to d 7 ). the read array mode is retained until another command is written. ? read status register command (70 16 ) when the command code ?70 16 ? is written in the first bus cycle, the contents of the status register are read out at the data bus (d 0 to d 7 ) by a read in the second bus cycle. the status register is expl ained in the next section. ? clear status register command (50 16 ) this command is used to clear th e bits sr4 and sr5 of the status register after they have been set. these bits indicate that operation has ended in an error. to use this command, write the command code ?50 16 ? in the first bus cycle. ? program command (40 16 ) program operation starts when the command code ?40 16 ? is written in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and veri fication) will start. whether the write operation is completed can be confirmed by read status register or the ry/by status flag. when the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (d 0 to d 7 ). the status register bit 7 (sr7) is set to ?0? at the same time the write operation starts and is returned to ?1? upon completion of the write operation. in this cas e, the read status register mode remains active until the read array command (ff 16 ) is written. the ry/by status flag of the flash memory control register is ?0? during write operation and ?1? when the write operation is completed as is the status register bit 7. at program end, program result s can be checked by reading the status register. fig 69. program flowchart notes: 1. srd = status register data 2. wa = write address, wd = write data 3. ba = block address to be erased (input the maximum address of each block.) 4. x denotes a given address in the user rom area. start write ?40 16 ? sr7 = ? 1 ? ? or ry/by = ? 1 ? ? read status register program completed no yes write write address write data sr4 = ?0?? program error no yes table 13 list of software commands (cpu rewrite mode) command cycle number first bus cycle second bus cycle mode address data (d 0 to d 7 ) mode address data (d 0 to d 7 ) read array 1 write x (4) ff 16 read status register 2 write x 70 16 read x srd (1) clear status register 1 write x 50 16 program 2 write x 40 16 write wa (2) wd (2) block erase 2 write x 20 16 write ba (3) d0 16 rev.3.11 apr 5, 2006 page 74 of 113 rej03b0017-0311 3803 group (spec.h) ? block erase command (20 16 /d0 16 ) by writing the command code ?20 16 ? in the first bus cycle and the confirmation command code ?d0 16 ? and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. whether the block erase operation is completed can be confirmed by read status register or the ry/by status flag of flash memory control register. at the same tim e the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register ca n be read out. the status register bit 7 (sr7) is set to ?0? at the same time the block erase operation starts and is returned to ?1? upon completion of the block erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is written. the ry/by status flag is ?0? during block erase operation and ?1? when the block erase operation is completed as is the status register bit 7. after the block erase ends, er ase results can be checked by reading the status register. for de tails, refer to the section where the status register is detailed. fig 70. erase flowchart write ?20 16 ? write ?d0 16 ? blockaddress read status register sr7 = ? 1 ? ? or ry/by = ? 1 ? ? erase completed (write read command ?ff 16 ?) no yes start sr5 = ?0?? erase error yes no rev.3.11 apr 5, 2006 page 75 of 113 rej03b0017-0311 3803 group (spec.h) ? status register the status register shows the operating status of the flash memory and whether erase op erations and programs ended successfully or in error. it ca n be read in the following ways: (1) by reading an arbitrary address from the user rom area after writing the read stat us register command (70 16 ) (2) by reading an arbitrary addr ess from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input. also, the status register can be cleared by writing the clear status register command (50 16 ). after reset, the status register is set to ?80 16 ?. table 14 shows the status register. each bit in this register is explained below. ? sequencer status (sr7) the sequencer status indicates th e operating status of the flash memory. this bit is set to ?0 ? (busy) during write or erase operation and is set to ?1? when these ope rations ends. after power-on, the sequencer st atus is set to ?1? (ready). ? erase status (sr5) the erase status indicates the ope rating status of erase operation. if an erase error occurs, it is set to ?1?. when the erase status is cleared, it is reset to ?0?. ? program status (sr4) the program status indicates th e operating status of write operation. when a write error occurs, it is set to ?1?. the program status is reset to ?0? when it is cleared. if ?1? is written for any of the sr5 and sr4 bits, the read array, program, and block erase commands are not accepted. before executing these commands, execute the clear status register command (50 16 ) and clear the status register. also, if any commands are not correct, both sr5 and sr4 are set to ?1?. table 14 definition of each bit in status register each bit of srd bits status name definition ?1? ?0? sr7 (bit7) sequencer status ready busy sr6 (bit6) reserved ?? sr5 (bit5) erase status terminated in error terminated normally sr4 (bit4) program status terminated in error terminated normally sr3 (bit3) reserved ?? sr2 (bit2) reserved ?? sr1 (bit1) reserved ?? sr0 (bit0) reserved ?? rev.3.11 apr 5, 2006 page 76 of 113 rej03b0017-0311 3803 group (spec.h) full status check by performing full status check, it is possible to know the execution results of erase an d program operations. figure.71 shows a full status check flowch art and the action to be taken when each error occurs. fig 71. full status check flowchart and remedial procedure for errors read status register sr4 = ?1? and sr5 = ?1?? command sequence error yes execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. no sr5 = ?0?? yes erase error no should an erase error occur, the block in error cannot be used. sr4 = ?0?? yes program error no end (block erase, program) note: when one of sr5 and sr4 is set to ?1?, none of the read array, program, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used. rev.3.11 apr 5, 2006 page 77 of 113 rej03b0017-0311 3803 group (spec.h) functions to inhibit rewriting flash memory version to prevent the contents of inte rnal flash memory from being read out or rewritten easily, this mcu incorporates a rom code protect function for use in parallel i/o mode and an id code check function for use in standard serial i/o mode. ? rom code protect function the rom code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the rom code protect control address (address ffdb 16 ) in parallel i/o mode. figure.72 shows the rom code protect control address (address ffdb 16 ). (this address exists in the user rom area.) if one or both of the pair of ro m code protect bits is set to ?0?, the rom code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. the ro m code protect is implemented in two levels. if level 2 is selected, the flash memory is protected even against readout by a shipment insp ection lsi tester , etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to ?00?, the rom code protect is turned off, so that the contents of internal flash memory can be readout or modified. once the rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parall el i/o mode. use the serial i/o or cpu rewrite mode to rewrite the contents of the rom code protect reset bits. rewriting of only the rom code protect control address (address ffdb 16 ) cannot be performed. wh en rewriting the rom code protect reset bit, rewrite the whole user rom area (block 0) containing the rom code protect control address. fig 72. structure of rom code protect control address rom code protect contro l address (address ffdb 16 ) romcp (ff 16 when shipped) reserved bits (?1? at read/write) rom code protect level 2 set bits (romcp2) (1, 2) b3b2 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled rom code protect reset bits (romcr) (3) b5b4 0 0: protect removed 0 1: protect set bits effective 1 0: protect set bits effective 1 1: protect set bits effective rom code protect level 1 set bits (romcp1) (1) b7b6 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled b7 1 1 b0 notes 1 : when rom code protect is turned on, the internal flash memory is protected against readout or modificati on in parallel i/o mode. 2 : when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. 3 : the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be modified in parallel i/o mode, they need to be rewritten in serial i/o mode or cpu rewrite mode. rev.3.11 apr 5, 2006 page 78 of 113 rej03b0017-0311 3803 group (spec.h) ? id code check function use this function in standard se rial i/o mode. when the contents of the flash memory are not blank, the id code sent from the programmer is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, and its areas are ffd4 16 to ffda 16 . write a program which has had the id code preset at these addresses to the flash memory. fig 73. id code store addresses id7 id6 id5 id4 id3 id2 id1 address rom code protect control interrupt vector area ffd5 16 ffd4 16 ffd6 16 ffd7 16 ffd8 16 ffd9 16 ffda 16 ffdb 16 rev.3.11 apr 5, 2006 page 79 of 113 rej03b0017-0311 3803 group (spec.h) parallel i/o mode the parallel i/o mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. use the external device (wri ter) only for 3803 group (spec.h) flash memory version. for detail s, refer to the user?fs manual of each writer manufacturer. ? user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 64 can be rewritten. bo th areas of flash memory can be operated on in the same way. the boot rom area is 4 kbytes in size and located at addresses f000 16 through ffff 16 . make sure program and block erase operations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an eras e block operation is applied to only one 4 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the fac-tory. therefore, using th e mcu in standard serial i/o mode, do not rewrite to the boot rom area. rev.3.11 apr 5, 2006 page 80 of 113 rej03b0017-0311 3803 group (spec.h) standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses a nd data needed to operate (read, program, erase, etc.) the internal flash memory. this i/o is clock synchronized serial. this m ode requires a purpose-specific peripheral unit. the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory re write (uses the cpu rewrite mode), rewr ite data input and so forth. the standard serial i/o mode is started by connecting ?h? to the cnv ss pin and ?h? to the p4 5 (bootent) pin, and releasing the reset operation. (in the ordinary microcomputer mode, set cnv ss pin to ?l? level.) this control program is written in the boot rom area when the product is shipped from renesas. accordingly, make note of the fact that the st andard serial i/o mode cannot be used if the boot rom area is re written in parallel i/o mode. the standard serial i/ o mode has st andard serial i/o mode 1 of the clock synchronous serial and standa rd serial i/o mode 2 of the clock asynchronous serial. table 15 and 16 show description of pin function (standard serial i/o mode). figure.74 to 77 show the pin connections for the st andard serial i/o mode. in standard serial i/o mode, only the user rom area shown in figure.64 can be rewritten. the boot rom area cannot be written. in standard serial i/o mode, a 7- byte id code is used. when there is data in the flash memory, this function determines whether the id code sent from the peripheral unit (programmer) and those written in the flash memory match. the commands sent from the peripheral unit (programmer) are not accepted unless the id code matches. rev.3.11 apr 5, 2006 page 81 of 113 rej03b0017-0311 3803 group (spec.h) table 15 description of pin function (flash memory serial i/o mode 1) pin name signal name i/o function v cc ,v ss power supply i apply 2.7 to 5.5 v to the v cc pin and 0 v to the vss pin. cnv ss cnv ss i after input of port is set, input ?h? level. reset reset input i reset input pin. to reset the microcomputer, reset pin should be held at an ?l? level for 16 cycles or more of x in . x in clock input i connect an oscill ation circuit between the x in and x out pins. as for the connection method, refer to the ?clock generating circuit?. x out clock output o av ss analog power supply input connect avss to v ss . v ref reference voltage input i apply reference voltage of a/d to this pin. p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 3 , p5 0 ? p5 7 , p6 0 ? p6 7 i/o port i/o input ?l? or ?h? level, or keep open. p4 4 rxd input i serial data input pin. p4 5 txd output o serial data output pin. p4 6 s clk input i serial clock input pin. p4 7 busy output o busy signal output pin. table 16 description of pin function (flash memory serial i/o mode 2) pin name signal name i/o function v cc ,v ss power supply i apply 2.7 to 5.5 v to the vcc pin and 0 v to the v ss pin. cnv ss cnv ss i after input of port is set, input ?h? level. reset reset input i reset input pin. to reset the microcomputer, reset pin should be held at an ?l? level for 16 cycles or more of x in . x in clock input i connect an oscill ation circuit between the x in and x out pins. as for the connection method, refer to the ?clock generating circuit?. x out clock output o av ss analog power supply input connect avss to v ss . v ref reference voltage input i apply reference voltage of a/d to this pin. p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 3 , p5 0 ? p5 7 , p6 0 ? p6 7 i/o port i/o input ?l? or ?h? level, or keep open. p4 4 rxd input i serial data input pin. p4 5 txd output o serial data output pin. p4 6 s clk input i input ?l? level. p4 7 busy output o busy signal output pin. rev.3.11 apr 5, 2006 page 82 of 113 rej03b0017-0311 3803 group (spec.h) fig 74. connection for standard serial i/o mode 1 (m38039ffhfp/hp/kp) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 44 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 6 p1 4 p1 5 p1 7 p2 7( led 7) p2 0( led 0) p2 1( led 1) p2 2( led 2) p2 3( led 3) p2 4( led 4) p2 5( led 5) p2 6( led 6) v ss x out x in p4 2 /int 1 reset cnv ss p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 5 /t x d 3 p3 4 /r x d 3 p3 1 /da 2 p3 0 /da 1 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p3 7 /s rdy3 p3 6 /s clk3 p3 3 p3 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p6 2 /an 2 p4 7 /s rdy1 /cntr 2 p5 3 /s rdy2 m38039ffhfp/hp/kp 32 30 29 28 25 23 20 19 18 17 27 22 21 31 26 24 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 5 reset cnvss * rxd txd sclk busy * connect oscillation circuit. indicates flash memory pin. package type: prqp0064ga-a (64p6n-a) / plqp0064kb-a (64p6q-a) / plqp0064ga-a (64p6u-a) v cc v ss rev.3.11 apr 5, 2006 page 83 of 113 rej03b0017-0311 3803 group (spec.h) fig 75. connection for standard serial i/o mode 2 (m38039ffhfp/hp/kp) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 44 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 6 p1 4 p1 5 p1 7 p2 7( led 7) p2 0( led 0) p2 1( led 1) p2 2( led 2) p2 3( led 3) p2 4( led 4) p2 5( led 5) p2 6( led 6) v ss x out x in p4 2 /int 1 reset cnv ss p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 5 /t x d 3 p3 4 /r x d 3 p3 1 /da 2 p3 0 /da 1 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p3 7 /s rdy3 p3 6 /s clk3 p3 3 p3 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p6 2 /an 2 p4 7 /s rdy1 /cntr 2 p5 3 /s rdy2 m38039ffhfp/hp/kp 32 30 29 28 25 23 20 19 18 17 27 22 21 31 26 24 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 5 reset cnvss * rxd txd busy * connect oscillation circuit. indicates flash memory pin. package type: prqp0064ga-a (64p6n-a) / plqp0064kb-a (64p6q-a) / plqp0064ga-a (64p6u-a) v cc v ss ?l? input rev.3.11 apr 5, 2006 page 84 of 113 rej03b0017-0311 3803 group (spec.h) fig 76. connection for standard serial i/o mode 1 (m38039ffhsp) p3 0 /da 1 p3 1 /da 2 p3 4 /r x d 3 p3 5 /t x d 3 p0 0 /an 8 p2 0 (led 0 ) p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 1 (led 1 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p3 2 p3 3 p3 6 / s clk3 p3 7 / s rdy3 m38039ffhsp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss p4 0 /int 40 /x cout x in x out v ss reset p5 3 /s rdy2 p6 5 /an 5 p4 1 /int 00 /x cin p4 7 /s rdy1 / cntr 2 * v ss reset cnv ss r x d t x d s clk busy v cc package type: prdp0064ba-a (64p4b) * connect oscillation circuit. indicates flash memory pin. rev.3.11 apr 5, 2006 page 85 of 113 rej03b0017-0311 3803 group (spec.h) fig 77. connection for standard serial i/o mode 2 (m38039ffhsp) p3 0 /da 1 p3 1 /da 2 p3 4 /r x d 3 p3 5 /t x d 3 p0 0 /an 8 p2 0 (led 0 ) p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 1 (led 1 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p3 2 p3 3 p3 6 / s clk3 p3 7 / s rdy3 m38039ffhsp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss p4 0 /int 40 /x cout x in x out v ss reset p5 3 /s rdy2 p6 5 /an 5 p4 1 /int 00 /x cin p4 7 /s rdy1 / cntr 2 * v ss reset cnv ss r x d t x d ?l? input busy v cc packagetype: prdp0064ba-a (64p4b) * connect oscillation circuit. indicates flash memory pin. rev.3.11 apr 5, 2006 page 86 of 113 rej03b0017-0311 3803 group (spec.h) fig 78. connection for standard serial i/o mode 1 (m38039ffhwg) 3 2 1 8 7 6 5 4 p6 1 /an 1 p6 0 /an 0 p5 5 /cntr 1 p5 2 /s clk2 p5 0 /s in2 p4 4 /r x d 1 p4 3 /int 2 cnv ss p6 7 /an 7 p6 6 /an 6 p5 7 /int 3 p5 4 /cntr 0 p4 7 /s rdy1 /cntr 2 p4 5 /t x d 1 p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 0 /da 1 p3 1 /da 2 p3 2 p3 7 /s rdy3 p1 7 p1 4 p1 5 p1 6 p3 3 p3 4 /r x d 3 p0 0 /an 8 p0 5 /an 13 p1 2 p1 3 p2 6 (led 6 )p2 7 (led 7 ) p3 5 /t x d 3 p0 1 /an 9 p0 3 /an 11 p0 6 /an 14 p1 1 /int 01 p2 5 (led 5 )p2 3 (led 3 )p2 4 (led 4 ) p3 6 /s clk3 p0 2 /an 10 p0 4 /an 12 p0 7 /an 15 p1 0 /int 41 p2 0 (led 0 )p2 1 (led 1 )p2 2 (led 2 ) p6 2 /an 2 p6 3 /an 3 v ref av ss v cc v ss x in x out abcdefgh abcdefgh 50 46 44 41 40 32 31 30 51 47 45 42 39 27 29 28 53 52 48 43 38 37 26 25 56 55 54 49 33 36 35 34 1 64 58 59 57 24 22 23 60 61 4 7 12 14 21 20 62 63 5 8 10 13 17 19 2 3 6 9 11 15 16 18 pin configuration (top view) package type: ptlg0064ja-a (64f0g) * connect oscillation circuit. indicates flash memory pin. 3 2 1 8 7 6 5 4 cnv ss reset v cc * v ss busy t x d r x d s clk p6 5 /an 5 p6 4 /an 4 p5 6 /pwm p5 3 /s rdy2 p5 1 /s out2 p4 6 /s clk1 p4 2 /int 1 reset rev.3.11 apr 5, 2006 page 87 of 113 rej03b0017-0311 3803 group (spec.h) fig 79. connection for standard serial i/o mode 2 (m38039ffhwg) 3 2 1 8 7 6 5 4 p6 1 /an 1 p6 0 /an 0 p5 5 /cntr 1 p5 2 /s clk2 p5 0 /s in2 p4 4 /r x d 1 p4 3 /int 2 cnv ss p6 7 /an 7 p6 6 /an 6 p5 7 /int 3 p5 4 /cntr 0 p4 7 /s rdy1 /cntr 2 p4 5 /t x d 1 p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 0 /da 1 p3 1 /da 2 p3 2 p3 7 /s rdy3 p1 7 p1 4 p1 5 p1 6 p3 3 p3 4 /r x d 3 p0 0 /an 8 p0 5 /an 13 p1 2 p1 3 p2 6 (led 6 )p2 7 (led 7 ) p3 5 /t x d 3 p0 1 /an 9 p0 3 /an 11 p0 6 /an 14 p1 1 /int 01 p2 5 (led 5 )p2 3 (led 3 )p2 4 (led 4 ) p3 6 /s clk3 p0 2 /an 10 p0 4 /an 12 p0 7 /an 15 p1 0 /int 41 p2 0 (led 0 )p2 1 (led 1 )p2 2 (led 2 ) p6 2 /an 2 p6 3 /an 3 v ref av ss v cc v ss x in x out abcdefgh abcdefgh 50 46 44 41 40 32 31 30 51 47 45 42 39 27 29 28 53 52 48 43 38 37 26 25 56 55 54 49 33 36 35 34 1 64 58 59 57 24 22 23 60 61 4 7 12 14 21 20 62 63 5 8 10 13 17 19 2 3 6 9 11 15 16 18 pin configuration (top view) package type: ptlg0064ja-a (64f0g) * connect oscillation circuit. indicates flash memory pin. 3 2 1 8 7 6 5 4 cnv ss reset v cc v ss busy t x d r x d ?l?input p6 5 /an 5 p6 4 /an 4 p5 6 /pwm p5 3 /s rdy2 p5 1 /s out2 p4 6 /s clk1 p4 2 /int 1 reset * rev.3.11 apr 5, 2006 page 88 of 113 rej03b0017-0311 3803 group (spec.h) fig 80. operating waveform for standard serial i/o mode 1 fig 81. operating waveform for standard serial i/o mode 2 power source reset cnv ss p4 5 (t x d) p4 6 (s clk ) p4 7 (busy) p4 4 (r x d) td(cnv ss -reset) td(p4 5 -reset) notes: in the standard serial i/o mode 1, input ?h? to the p4 6 pin. be sure to set the cnvss pin to ?h? before rising reset. be sure to set the p4 5 pin to ?h? before rising reset. td(cnv ss -reset) td(p4 5 -reset) symbol min. max. typ. unit 0 0 ?? ms ms limits power source reset cnv ss p4 5 (t x d) p4 7 (busy) p4 4 (r x d) p4 6 (s clk ) td(cnv ss -reset) td(p4 5 -reset) td(cnv ss -reset) td(p4 5 -reset) symbol min. max. typ. unit 0 0 ?? ms ms limits notes: in the standard serial i/o mode 2, input ?h? to the p4 6 pin. be sure to set the cnvss pin to ?h? before rising reset. be sure to set the p4 5 pin to ?h? before rising reset. rev.3.11 apr 5, 2006 page 89 of 113 rej03b0017-0311 3803 group (spec.h) electrical characteristics absolute maximum ratings note: 1. this value is 300 mw except sp package. table 17 absolute maximum ratings symbol parameter conditions ratings unit v cc power source voltages all voltages are based on v ss . when an input voltage is measured, output transistors are cut off. ? 0.3 to 6.5 v v i input voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , v ref ? 0.3 to v cc + 0.3 v v i input voltage p3 2 , p3 3 ? 0.3 to 5.8 v v i input voltage reset , x in ? 0.3 to v cc + 0.3 v v i input voltage cnv ss ? 0.3 to v cc + 0.3 v v o p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , x out ? 0.3 to v cc + 0.3 v output voltage v o output voltage p3 2 , p3 3 ? 0.3 to 5.8 v p d power dissipation ta=25 c 1000 (1) mw t opr operating temperature ? 20 to 85 c t stg storage temperature ? 65 to 125 c rev.3.11 apr 5, 2006 page 90 of 113 rej03b0017-0311 3803 group (spec.h) recommended operating conditions notes: 1. when using a/d converter, see a/d c onverter recommended operating conditions. 2. the start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and o perating temperature range, etc.. particularly a high-frequency oscillator mi ght require some notes in the low voltage operation. 3. when the oscillation frequency has a duty cycle of 50%. 4. when using the microcomputer in low-speed mode, set the s ub-clock input oscillation fr equency on condition that f(x cin ) < f(x in )/3. table 18 recommended operating conditions (1) (mask rom version) (v cc = 1.8 to 5.5 v, v ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. v cc power source voltage (1) when start oscillating (2) 2.2 5.0 5.5 v high-speed mode f( ) = f(x in )/2 f(x in ) 2.1 mhz 2.0 5.0 5.5 v f(x in ) 4.2 mhz 2.2 5.0 5.5 f(x in ) 8.4 mhz 2.7 5.0 5.5 f(x in ) 12.5 mhz 4.0 5.0 5.5 f(x in ) 16.8 mhz 4.5 5.0 5.5 middle-speed mode f( ) = f(x in )/8 f(x in ) 6.3 mhz 1.8 5.0 5.5 v f(x in ) 8.4 mhz 2.2 5.0 5.5 f(x in ) 12.5 mhz 2.7 5.0 5.5 f(x in ) 16.8 mhz 4.5 5.0 5.5 v ss power source voltage 0 v v ih ?h? input voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 1.8 v cc < 2.7 v 0.85 v cc v cc v 2.7 v cc 5.5 v 0.8 v cc v cc v ih ?h? input voltage p3 2 , p3 3 1.8 v cc < 2.7 v 0.85 v cc 5.5 v 2.7 v cc 5.5 v 0.8 v cc 5.5 v ih ?h? input voltage reset , x in , x cin , cnv ss 1.8 v cc < 2.7 v 0.85 v cc v cc v 2.7 v cc 5.5 v 0.8 v cc v cc v il ?l? input voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 1.8 v cc < 2.7 v 0 0.16 v cc v 2.7 v cc 5.5 v 0 0.2 v cc v il ?l? input voltage reset , cnv ss 1.8 v cc < 2.7 v 0 0.16 v cc v 2.7 v cc 5.5 v 0 0.2 v cc v il ?l? input voltage x in , x cin 1.8 v cc 5.5 v 0 0.16 v cc v f(x in ) main clock input oscillation frequency (3) high-speed mode f( ) = f(x in )/2 2.0 v cc < 2.2 v mhz 2.2 v cc < 2.7 v mhz 2.7 v cc < 4.0 v mhz 4.0 v cc < 4.5 v mhz 4.5 v cc 5.5 v 16.8 mhz middle-speed mode f( ) = f(x in )/8 1.8 v cc < 2.2 v mhz 2.2 v cc < 2.7 v mhz 2.7 v cc < 4.5 v mhz 4.5 v cc 5.5 v 16.8 mhz f(x cin ) sub-clock input oscillation frequency (3, 4) 32.768 50 khz 20 v cc 36 ? () 1.05 2 ----------------------------------------------------------- 24 v cc 40.8 ? () 1.05 3 ---------------------------------------------------------------- 9v cc 0.3 ? () 1.05 3 --------------------------------------------------------- - 24 v cc 60 ? () 1.05 3 ----------------------------------------------------------- 15 v cc 9 ? () 1.05 3 -------------------------------------------------------- 24 v cc 28.8 ? () 1.05 3 ---------------------------------------------------------------- 15 v cc 39 + () 1.1 7 -------------------------------------------------------- mask rom version rev.3.11 apr 5, 2006 page 91 of 113 rej03b0017-0311 3803 group (spec.h) notes: 1. when using a/d converter, see a/d c onverter recommended operating conditions. 2. the start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and o perating temperature range, etc.. particularly a high-frequency oscillator mi ght require some notes in the low voltage operation. 3. when the oscillation frequency has a duty cycle of 50%. 4. when using the microcomputer in low-speed mode, set the s ub-clock input oscillation fr equency on condition that f(x cin ) < f(x in )/3. table 19 recommended operating conditions (2) (flash memory version) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. v cc power source voltage (1) when start oscillating (2) 2.2 5.0 5.5 v high-speed mode f( ) = f(x in )/2 f(x in ) 8.4 mhz 2.7 5.0 5.5 v f(x in ) 12.5 mhz 4.0 5.0 5.5 f(x in ) 16.8 mhz 4.5 5.0 5.5 middle-speed mode f( ) = f(x in )/8 f(x in ) 12.5 mhz 2.7 5.0 5.5 v f(x in ) 16.8 mhz 4.5 5.0 5.5 v ss power source voltage 0 v v ih ?h? input voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 0.8 v cc v cc v v ih ?h? input voltage p3 2 , p3 3 0.8 v cc 5.5 v v ih ?h? input voltage reset , x in , cnv ss 0.8 v cc v cc v v ih ?h? input voltage x cin 2v cc v v il ?l? input voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 0 0.2 v cc v v il ?l? input voltage reset , cnv ss 0 0.2 v cc v v il ?l? input voltage x in 0.16 v cc v v il ?l? input voltage x cin 0.4 v f(x in ) main clock input oscillation frequency (3) high-speed mode f( ) = f(x in )/2 2.7 v cc < 4.0 v mhz 4.0 v cc < 4.5 v mhz 4.5 v cc 5.5 v 16.8 mhz middle-speed mode f( ) = f(x in )/8 2.7 v cc < 4.5 v mhz 4.5 v cc 5.5 v 16.8 mhz f(x cin ) sub-clock input oscillation frequency (3, 4) 32.768 50 khz 9v cc 0.3 ? () 1.05 3 --------------------------------------------------------- - 24 v cc 60 ? () 1.05 3 ----------------------------------------------------------- 15 v cc 39 + () 1.1 7 -------------------------------------------------------- flash memory version rev.3.11 apr 5, 2006 page 92 of 113 rej03b0017-0311 3803 group (spec.h) notes: 1. the total output current is the sum of all the currents flowing through all the applicable ports. the total average current i s an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2. the peak output current is the peak current flowing in each port. 3. the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. table 20 recommended operating conditions (3) (mask rom version: v cc = 1.8 to 5.5 v, v ss = 0v, ta = ?20 to 85 c, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. i oh(peak) ?h? total peak output current (1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 ? 80 ma i oh(peak) ?h? total peak output current (1) p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ? 80 ma i ol(peak) ?l? total peak output current (1) p0 0 -p0 7 , p1 0 -p1 7 , p3 0 -p3 7 80 ma i ol(peak) ?l? total peak output current (1) p2 0 -p2 7 80 ma i ol(peak) ?l? total peak output current (1) p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 80 ma i oh(avg) ?h? total average output current (1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 ? 40 ma i oh(avg) ?h? total average output current (1) p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ? 40 ma i ol(avg) ?l? total average output current (1) p0 0 -p0 7 , p1 0 -p1 7 , p3 0 -p3 7 40 ma i ol(avg) ?l? total average output current (1) p2 0 -p2 7 40 ma i ol(avg) ?l? total average output current (1) p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 40 ma i oh(peak) ?h? peak output current (2) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ? 10 ma i ol(peak) ?l? peak output current (2) p0 0 -p0 7 , p1 0 -p1 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 10 ma i ol(peak) ?l? peak output current (2) p2 0 -p2 7 20 ma i oh(avg) ?h? average output current (3) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ? 5ma i ol(avg) ?l? average output current (3) p0 0 -p0 7 , p1 0 -p1 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 5ma i ol(avg) ?l? average output current (3) p2 0 -p2 7 10 ma rev.3.11 apr 5, 2006 page 93 of 113 rej03b0017-0311 3803 group (spec.h) electrical characteristics note: 1. p3 5 is measured when the p3 5 /t x d 3 p-channel output disable bit of the uart3 control register (bit 4 of address 0033 16 ) is ?0?. p4 5 is measured when the p4 5 /t x d 1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is ?0?. table 21 electrical characteristics (1) (mask rom version: v cc = 1.8 to 5.5 v, v ss = 0v, ta = ?20 to 85 c, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v oh ?h? output voltage (1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 i oh = ? 10 ma v cc = 4.0 to 5.5 v v cc ? 2.0 v i oh = ?1.0 ma v cc = 1.8 to 5.5 v v cc ? 1.0 v ol ?l? output voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 i ol = 10 ma v cc = 4.0 to 5.5 v 2.0 v i ol = 1.6 ma v cc = 1.8 to 5.5 v 1.0 v ol ?l? output voltage p2 0 -p2 7 i ol = 20 ma v cc = 4.0 to 5.5 v 2.0 v i ol = 1.6 ma v cc = 1.8 to 5.5 v 0.4 v t+ ? v t ? hysteresis cntr 0 , cntr 1 , cntr 2 , int 0 -int 4 0.4 v v t+ ? v t ? hysteresis rxd 1 , s clk1 , s in2 , s clk2 , rxd 3 , s clk3 0.5 v v t+ ? v t ? hysteresis reset 0.5 v i ih ?h? input current p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 v i = v cc (pin floating, pull-up transistor ?off?) 5.0 a i ih ?h? input current reset , cnv ss v i = v cc 5.0 a i ih ?h? input current x in v i = v cc 4.0 a i il ?l? input current p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 v i = v ss (pin floating, pull-up transistor ?off?) ? 5.0 a i il ?l? input current reset , cnv ss v i = v ss ? 5.0 a i il ?l? input current x in v i = v ss ? 4.0 a i il ?l? input current (at pull-up) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 v i = v ss v cc = 5.0 v ? 80 ? 210 ? 420 a v i = v ss v cc = 3.0 v ? 30 ? 70 ? 140 v ram ram hold voltage when clock stopped 1.8 v cc v rev.3.11 apr 5, 2006 page 94 of 113 rej03b0017-0311 3803 group (spec.h) table 22 electrical characteristics (2) (mask rom version) (v cc = 1.8 to 5.5 v, ta = ?20 to 85 c, f(x cin )=32.768khz (stopped in middle-speed mode), output transistors ?off?, ad converter not operated) symbol parameter test conditions limits unit min. typ. max. i cc power source current high-speed mode v cc = 5.0 v f(x in ) = 16.8 mhz 8.0 15.0 ma f(x in ) = 12.5 mhz 6.5 12.0 f(x in ) = 8.4 mhz 5.0 9.0 f(x in ) = 4.2 mhz 2.5 5.0 f(x in ) = 16.8 mhz (in wit state) 2.0 3.6 v cc = 3.0 v f(x in ) = 8.4 mhz 1.9 3.8 ma f(x in ) = 4.2 mhz 1.0 2.0 f(x in ) = 2.1 mhz 0.6 1.2 middle-speed mode v cc = 5.0 v f(x in ) = 16.8 mhz 4.0 7.0 ma f(x in ) = 12.5 mhz 3.0 6.0 f(x in ) = 8.4 mhz 2.5 5.0 f(x in ) = 16.8 mhz (in wit state) 1.8 3.3 v cc = 3.0 v f(x in ) = 12.5 mhz 1.5 3.0 ma f(x in ) = 8.4 mhz 1.2 2.4 f(x in ) = 6.3 mhz 1.0 2.0 low-speed mode v cc = 5.0 v f(x in ) = stopped 55 200 a in wit state 40 70 v cc = 3.0 v f(x in ) = stopped 15 40 a in wit state 8 15 v cc = 2.0 v f(x in ) = stopped 6 15 a in wit state 3 6 in stp state (all oscillation stopped) ta = 25 c0 . 1 1 . 0 a ta = 85 c1 0 increment when a/d conversion is executed f(x in ) = 16.8 mhz, v cc = 5.0 v in middle-, high-speed mode 500 a mask rom version rev.3.11 apr 5, 2006 page 95 of 113 rej03b0017-0311 3803 group (spec.h) table 23 electrical characteristics (3) (flash memory version) (v cc = 2.7 to 5.5 v, ta = ?20 to 85 c, f(x cin )=32.768khz (stopped in middle-speed mode), output transistors ?off?, ad converter not operated) symbol parameter test conditions limits unit min. typ. max. i cc power source current high-speed mode v cc = 5.0 v f(x in ) = 16.8 mhz 5.5 8.3 ma f(x in ) = 12.5 mhz 4.5 6.8 f(x in ) = 8.4 mhz 3.5 5.3 f(x in ) = 4.2 mhz 2.2 3.3 f(x in ) = 16.8 mhz (in wit state) 2.2 3.3 v cc = 3.0 v f(x in ) = 8.4 mhz 2.7 4.1 ma f(x in ) = 4.2 mhz 1.8 2.7 f(x in ) = 2.1 mhz 1.1 1.7 middle-speed mode v cc = 5.0 v f(x in ) = 16.8 mhz 3.0 4.5 ma f(x in ) = 12.5 mhz 2.4 3.6 f(x in ) = 8.4 mhz 2.0 3.0 f(x in ) = 16.8 mhz (in wit state) 2.1 3.2 v cc = 3.0 v f(x in ) = 12.5 mhz 1.7 2.6 ma f(x in ) = 8.4 mhz 1.5 2.3 f(x in ) = 6.3 mhz 1.3 2.0 low-speed mode v cc = 5.0 v f(x in ) = stopped 410 630 a in wit state 4.5 6.8 v cc = 3.0 v f(x in ) = stopped 400 600 a in wit state 3.7 5.6 in stp state (all oscillation stopped) ta = 25 c 0.55 3.0 a ta = 85 c0 . 7 5 increment when a/d conversion is executed f(x in ) = 16.8 mhz, v cc = 5.0 v in middle-, high-speed mode 1000 a flash memory version rev.3.11 apr 5, 2006 page 96 of 113 rej03b0017-0311 3803 group (spec.h) a/d converter characteristics notes: 1. 8-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?1?. 2. 10-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?0?. notes: 1. 8-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?1?. 2. 10-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?0?. d/a converter characteristics note: 1. using one d/a converter, with the value in the da conversion register of the other d/a converter being ?00 16 ?. table 24 a/d converter recommended o perating conditions (mask rom version) (v cc = 2.0 to 5.5 v, v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. v cc power source voltage (when a/d converter is used) 8-bit a/d mode (1) 2.0 5.0 5.5 v 10-bit a/d mode (2) 2.2 5.0 5.5 v ref analog convert reference voltage 2.0 v cc v a vss analog power source voltage 0 v v ia analog input voltage an 0 -an 15 0v cc v f(x in ) main clock input oscillation frequency (when a/d converter is used) 2.0 v cc = v ref < 2.2 v 0.5 mhz 2.2 v cc = v ref < 2.7 v 0.5 2.7 v cc = v ref < 4.0 v 0.5 4.0 v cc = v ref < 4.5 v 0.5 4.5 v cc = v ref 5.5 v 0.5 16.8 20 v cc 36 ? () 1.05 2 ----------------------------------------------------------- 24 v cc 40.8 ? () 1.05 3 ---------------------------------------------------------------- 9v cc 0.3 ? () 1.05 3 --------------------------------------------------------- - 24.6 v cc 62.7 ? () 1.05 3 --------------------------------------------------------------------- table 25 a/d converter characteristics (mask rom version) (v cc = 2.0 to 5.5 v, v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. ? resolution 8-bit a/d mode (1) 8bit 10-bit a/d mode (2) 10 ? absolute accuracy (excluding quantization error) 8-bit a/d mode (1) 2.0 v ref < 2.2 v 3 lsb 2.2 v ref 5.5 v 2 10-bit a/d mode (2) 2.2 v ref < 2.7 v 5 lsb 2.7 v ref 5.5 v 4 t conv conversion time 8-bit a/d mode (1) 50 2tc(x in ) 10-bit a/d mode (2) 61 r ladder ladder resistor 12 35 100 k ? i vref reference power source input current at a/d converter operated v ref = 5.0 v 50 150 200 a at a/d converter stopped v ref = 5.0 v 5.0 a i i(ad) a/d port input current 5.0 a table 26 d/a converter characteristics (mask rom version) (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. ? resolution 8b i t ? absolute accuracy 4.0 v ref 5.5 v 1.0 % 2.7 v ref < 4.0 v 2.5 tsu setting time 3 s ro output resistor 2 3.5 5 k ? i vref reference power source input current (1) 3.2 ma mask rom version rev.3.11 apr 5, 2006 page 97 of 113 rej03b0017-0311 3803 group (spec.h) a/d converter characteristics notes: 1. 8-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?1?. 2. 10-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?0?. notes: 1. 8-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?1?. 2. 10-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?0?. d/a converter characteristics note: 1. using one d/a converter, with the value in the da conversion register of the other d/a converter being ?00 16 ?. table 27 a/d converter recommended operat ing conditions (flash memory version) (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. v cc power source voltage (when a/d converter is used) 8-bit a/d mode (1) 2.7 5.0 5.5 v 10-bit a/d mode (2) 2.7 5.0 5.5 v ref analog convert reference voltage 2.0 v cc v av ss analog power source voltage 0 v v ia analog input voltage an 0 -an 15 0v cc v f(x in ) main clock input oscillation frequency (when a/d converter is used) 2.7 v cc = v ref < 4.0 v 0.5 mhz 4.0 v cc = v ref < 4.5 v 0.5 4.5 v cc = v ref 5.5 v 0.5 16.8 9v cc 0.3 ? () 1.05 3 --------------------------------------------------------- - 24.6 v cc 62.7 ? () 1.05 3 --------------------------------------------------------------------- table 28 a/d converter characteristics (flash memory version) (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. ? resolution 8-bit a/d mode (1) 8bit 10-bit a/d mode (2) 10 ? absolute accuracy (excluding quantization error) 8-bit a/d mode (1) 2.7 v ref 5.5 v 2 lsb 10-bit a/d mode (2) 2.7 v ref 5.5 v 4 lsb t conv conversion time 8-bit a/d mode (1) 50 2tc(x in ) 10-bit a/d mode (2) 61 r ladder ladder resistor 12 35 100 k ? i vref reference power source input current at a/d converter operated v ref = 5.0 v 50 150 200 a at a/d converter stopped v ref = 5.0 v 5.0 a i i(ad) a/d port input current 5.0 a table 29 d/a converter characteristics (flash memory version) (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. ? resolution 8b i t ? absolute accuracy 4.0 v ref 5.5 v 1.0 % 2.7 v ref < 4.0 v 2.5 tsu setting time 3 s ro output resistor 2 3.5 5 k ? i vref reference power source input current (1) 3.2 ma table 30 power source circuit timing ch aracteristics (flash memory version) (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. td(p ? r) internal power source stable time at power-on 2.7 v cc < 5.5 v 2 ms rev.3.11 apr 5, 2006 page 98 of 113 rej03b0017-0311 3803 group (spec.h) timing requirements and switching characteristics table 31 timing requirements (1) (mask rom version: v cc = 2.0 to 5.5 v, v ss = 0v, ta = ?20 to 85 c, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t w (reset ) reset input ?l? pulse width 16 x in cycle t c (x in ) main clock x in input cycle time 4.5 v cc 5.5 v 59.5 ns 4.0 v cc < 4.5 v 10000/(86 v cc ? 219) 2.7 v cc < 4.0 v 26 10 3 /(82 v cc ? 3) 2.2 v cc < 2.7 v 10000/(84 v cc ? 143) 2.0 v cc < 2.2 v 10000/(105 v cc ? 189) t wh (x in ) main clock x in input ?h? pulse width 4.5 v cc 5.5 v 25 ns 4.0 v cc < 4.5 v 4000/(86 v cc ? 219) 2.7 v cc < 4.0 v 10000/(82 v cc ? 3) 2.2 v cc < 2.7 v 4000/(84 v cc ? 143) 2.0 v cc < 2.2 v 4000/(105 v cc ? 189) t wl (x in ) main clock x in input ?l? pulse width 4.5 v cc 5.5 v 25 ns 4.0 v cc < 4.5 v 4000/(86 v cc ? 219) 2.7 v cc < 4.0 v 10000/(82 v cc ? 3) 2.2 v cc < 2.7 v 4000/(84 v cc ? 143) 2.0 v cc < 2.2 v 4000/(105 v cc ? 189) t c (x cin ) sub-clock x cin input cycle time 20 s t wh (x cin ) sub-clock x cin input ?h? pulse width 5 s t wl (x cin ) sub-clock x cin input ?l? pulse width 5 s t c (cntr) cntr 0 ? cntr 2 input cycle time 4.5 v cc 5.5 v 120 ns 4.0 v cc < 4.5 v 160 2.7 v cc < 4.0 v 250 2.2 v cc < 2.7 v 500 2.0 v cc < 2.2 v 1000 t wh (cntr) cntr 0 ? cntr 2 input ?h? pulse width 4.5 v cc 5.5 v 48 ns 4.0 v cc < 4.5 v 64 2.7 v cc < 4.0 v 115 2.2 v cc < 2.7 v 230 2.0 v cc < 2.2 v 460 t wl (cntr) cntr 0 ? cntr 2 input ?l? pulse width 4.5 v cc 5.5 v 48 ns 4.0 v cc < 4.5 v 64 2.7 v cc < 4.0 v 115 2.2 v cc < 2.7 v 230 2.0 v cc < 2.2 v 460 t wh (int) int 00 , int 01 , int 1 , int 2 , int 3 , int 40 , int 41 input ?h? pulse width 4.5 v cc 5.5 v 48 ns 4.0 v cc < 4.5 v 64 2.7 v cc < 4.0 v 115 2.2 v cc < 2.7 v 230 2.0 v cc < 2.2 v 460 t wl (int) int 00 , int 01 , int 1 , int 2 , int 3 , int 40 , int 41 input ?l? pulse width 4.5 v cc 5.5 v 48 ns 4.0 v cc < 4.5 v 64 2.7 v cc < 4.0 v 115 2.2 v cc < 2.7 v 230 2.0 v cc < 2.2 v 460 rev.3.11 apr 5, 2006 page 99 of 113 rej03b0017-0311 3803 group (spec.h) note: 1. when bit 6 of address 001a 16 and bit 6 of address 0032 16 are ?1? (clock synchronous). divide this value by four when bit 6 of address 001a 16 and bit 6 of address 0032 16 are ?0? (uart). table 32 timing requirements (2) (mask rom version: v cc = 2.0 to 5.5 v, v ss = 0v, ta = ? 20 to 85 c, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t c (s clk1 ) t c (s clk3 ) serial i/o1, serial i/o3 clock input cycle time (1) 4.5 v cc 5.5 v 250 ns 4.0 v cc < 4.5 v 320 2.7 v cc < 4.0 v 500 2.2 v cc < 2.7 v 1000 2.0 v cc < 2.2 v 2000 t wh (s clk1 ) t wh (s clk3 ) serial i/o1, serial i/o3 clock input ?h? pulse width (1) 4.5 v cc 5.5 v 120 ns 4.0 v cc < 4.5 v 150 2.7 v cc < 4.0 v 240 2.2 v cc < 2.7 v 480 2.0 v cc < 2.2 v 950 t wl (s clk1 ) t wl (s clk3 ) serial i/o1, serial i/o3 clock input ?l? pulse width (1) 4.5 v cc 5.5 v 120 ns 4.0 v cc < 4.5 v 150 2.7 v cc < 4.0 v 240 2.2 v cc < 2.7 v 480 2.0 v cc < 2.2 v 950 t su (r x d 1 -s clk1 ) t su (r x d 3 -s clk3 ) serial i/o1, serial i/o3 clock input setup time 4.5 v cc 5.5 v 70 ns 4.0 v cc < 4.5 v 90 2.7 v cc < 4.0 v 100 2.2 v cc < 2.7 v 200 2.0 v cc < 2.2 v 400 t h (s clk1 -r x d 1 ) t h (s clk3 -r x d 3 ) serial i/o1, serial i/o3 clock input hold time 4.5 v cc 5.5 v 32 ns 4.0 v cc < 4.5 v 40 2.7 v cc < 4.0 v 50 2.2 v cc < 2.7 v 100 2.0 v cc < 2.2 v 200 t c (s clk2 )s e r i a l i / o 2 clock input cycle time 4.5 v cc 5.5 v 500 ns 4.0 v cc < 4.5 v 650 2.7 v cc < 4.0 v 1000 2.2 v cc < 2.7 v 2000 2.0 v cc < 2.2 v 4000 t wh (s clk2 )s e r i a l i / o 2 clock input ?h? pulse width 4.5 v cc 5.5 v 200 ns 4.0 v cc < 4.5 v 260 2.7 v cc < 4.0 v 400 2.2 v cc < 2.7 v 950 2.0 v cc < 2.2 v 2000 t wl (s clk2 )s e r i a l i / o 2 clock input ?l? pulse width 4.5 v cc 5.5 v 200 ns 4.0 v cc < 4.5 v 260 2.7 v cc < 4.0 v 400 2.2 v cc < 2.7 v 950 2.0 v cc < 2.2 v 2000 t su (s in2 -s clk2 )serial i/o2 clock input setup time 4.5 v cc 5.5 v 100 ns 4.0 v cc < 4.5 v 130 2.7 v cc < 4.0 v 200 2.2 v cc < 2.7 v 400 2.0 v cc < 2.2 v 800 t h (s clk2 -s in2 )serial i/o2 clock input hold time 4.5 v cc 5.5 v 100 ns 4.0 v cc < 4.5 v 130 2.7 v cc < 4.0 v 150 2.2 v cc < 2.7 v 300 2.0 v cc < 2.2 v 600 rev.3.11 apr 5, 2006 page 100 of 113 rej03b0017-0311 3803 group (spec.h) note: 1. when the p4 5 /t x d 1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is ?0?. table 33 switching characteristics (1) (mask rom version: v cc = 2.0 to 5.5 v, v ss = 0v, ta = ? 20 to 85 c, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter te s t conditions limits unit min. typ. max. t wh (s clk1 ) t wh (s clk3 ) serial i/o1, serial i/o3 clock output ?h? pulse width 4.5 v cc 5.5 v fig.82 t c (s clk1 )/2-30, t c (s clk3 )/2-30 ns 4.0 v cc < 4.5 v t c (s clk1 )/2-35, t c (s clk3 )/2-35 2.7 v cc < 4.0 v t c (s clk1 )/2-40, t c (s clk3 )/2-40 2.2 v cc < 2.7 v t c (s clk1 )/2-45, t c (s clk3 )/2-45 2.0 v cc < 2.2 v t c (s clk1 )/2-50, t c (s clk3 )/2-50 t wl (s clk1 ) t wl (s clk3 ) serial i/o1, serial i/o3 clock output ?l? pulse width 4.5 v cc 5.5 v t c (s clk1 )/2-30, t c (s clk3 )/2-30 ns 4.0 v cc < 4.5 v t c (s clk1 )/2-35, t c (s clk3 )/2-35 2.7 v cc < 4.0 v t c (s clk1 )/2-40, t c (s clk3 )/2-40 2.2 v cc < 2.7 v t c (s clk1 )/2-45, t c (s clk3 )/2-45 2.0 v cc < 2.2 v t c (s clk1 )/2-50, t c (s clk3 )/2-50 t d (s clk1 -t x d 1 ) t d (s clk3 -t x d 3 ) serial i/o1, serial i/o3 output delay time (1) 4.5 v cc 5.5 v 140 ns 4.0 v cc < 4.5 v 200 2.7 v cc < 4.0 v 350 2.2 v cc < 2.7 v 400 2.0 v cc < 2.2 v 420 t v (s clk1 -t x d 1 ) t v (s clk3 -t x d 3 ) serial i/o1, serial i/o3 output valid time (1) 4.5 v cc 5.5 v ? 30 ns 4.0 v cc < 4.5 v ? 30 2.7 v cc < 4.0 v ? 30 2.2 v cc < 2.7 v ? 30 2.0 v cc < 2.2 v ? 30 t r (s clk1 ) t r (s clk3 ) serial i/o1, serial i/o3 rise time of clock output 4.5 v cc 5.5 v 30 ns 4.0 v cc < 4.5 v 35 2.7 v cc < 4.0 v 40 2.2 v cc < 2.7 v 45 2.0 v cc < 2.2 v 50 t f (s clk1 ) t f (s clk3 ) serial i/o1, serial i/o3 fall time of clock output 4.5 v cc 5.5 v 30 ns 4.0 v cc < 4.5 v 35 2.7 v cc < 4.0 v 40 2.2 v cc < 2.7 v 45 2.0 v cc < 2.2 v 50 t wh (s clk2 ) serial i/o2 clock output ?h? pulse width 4.5 v cc 5.5 v t c (s clk2 )/2-160 ns 4.0 v cc < 4.5 v t c (s clk2 )/2-200 2.7 v cc < 4.0 v t c (s clk2 )/2-240 2.2 v cc < 2.7 v t c (s clk2 )/2-260 2.0 v cc < 2.2 v t c (s clk2 )/2-280 t wl (s clk2 ) serial i/o2 clock output ?l? pulse width 4.5 v cc 5.5 v t c (s clk2 )/2-160 ns 4.0 v cc < 4.5 v t c (s clk2 )/2-200 2.7 v cc < 4.0 v t c (s clk2 )/2-240 2.2 v cc < 2.7 v t c (s clk2 )/2-260 2.0 v cc < 2.2 v t c (s clk2 )/2-280 t d (s clk2 -s out2 ) serial i/o2 output delay time 4.5 v cc 5.5 v 200 ns 4.0 v cc < 4.5 v 250 2.7 v cc < 4.0 v 300 2.2 v cc < 2.7 v 350 2.0 v cc < 2.2 v 400 t v (s clk2 -s out2 ) serial i/o2 output valid time 4.5 v cc 5.5 v 0 ns 4.0 v cc < 4.5 v 0 2.7 v cc < 4.0 v 0 2.2 v cc < 2.7 v 0 2.0 v cc < 2.2 v 0 rev.3.11 apr 5, 2006 page 101 of 113 rej03b0017-0311 3803 group (spec.h) note: 1. when the p3 5 /t x d 3 p4-channel output disable bit of the uart 3 control register (bit 4 of address 0033 16 ) is ?0?. fig 82. circuit for measuring output switching characteristics (1) fig 83. circuit for measuring output switching characteristics (2) table 34 switching characteristics (2) (mask rom version: v cc = 2.0 to 5.5 v, v ss = 0v, ta = ? 20 to 85 c, unless otherwise noted) (flash memory version: v cc = 2.7 to 5.5 v, v ss = 0v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter te s t conditions limits unit min. typ. max. t f (s clk2 ) serial i/o2 fall time of clock output 4.5 v cc 5.5 v fig.82 30 ns 4.0 v cc < 4.5 v 35 2.7 v cc < 4.0 v 40 2.2 v cc < 2.7 v 45 2.0 v cc < 2.2 v 50 t r (cmos) cmos rise time of output (1) 4.5 v cc 5.5 v 10 30 ns 4.0 v cc < 4.5 v 12 35 2.7 v cc < 4.0 v 15 40 2.2 v cc < 2.7 v 17 45 2.0 v cc < 2.2 v 20 50 t f (cmos) cmos fall time of output (1) 4.5 v cc 5.5 v 10 30 ns 4.0 v cc < 4.5 v 12 35 2.7 v cc < 4.0 v 15 40 2.2 v cc < 2.7 v 17 45 2.0 v cc < 2.2 v 20 50 measurement output pin 100pf cmos output measurement output pin 100pf n-channel open-drain output 1k ? rev.3.11 apr 5, 2006 page 102 of 113 rej03b0017-0311 3803 group (spec.h) fig 84. timing diagram (in single-chip mode) t c (cntr) t wl (cntr) t wh (cntr) 0.8v cc 0.2v cc cntr 0 , cntr 1 cntr 2 int 1 , int 2 , int 3 int 00 , int 40 int 01 , int 41 reset x in t wl (int) t wh (int) 0.8v cc 0.2v cc 0.8v cc 0.2v cc t w (reset) t c (x in ) t wl (x in ) t wh (x in ) 0.8v cc 0.2v cc t c (s clk1 ), t c (s clk2 ), t c (s clk3 ) t wl (s clk1 ), t wl (s clk2 ), t wl (s clk3 ) 0.8v cc 0.2v cc t wh (s clk1 ), t wh (s clk2 ), t wh (s clk3 ) t f t r t su (r x d 1 -s clk1 ), t su (s in2 -s clk2 ), t su (r x d 3 -s clk3 ) t h (s clk1 -r x d 1 ), t h (s clk2 -s in2 ), t h (s clk3 -r x d 3 ) t d (s clk1 -t x d 1 ), t d (s clk2 -s out2 ), t d (s clk3 -t x d 3 ) t v (s clk1 -t x d 1 ), t v (s clk2 -s out2 ), t v (s clk3 -t x d 3 ) 0.2v cc 0.8v cc s clk1 s clk2 s clk3 r x d 1 r x d 3 s in2 t x d 1 t x d 3 s out2 x cin t c (x cin ) t wl (x cin ) t wh (x cin ) 0.8v cc 0.2v cc single-chip mode timing diagram rev.3.11 apr 5, 2006 page 103 of 113 rej03b0017-0311 3803 group (spec.h) package outline 0.65 0.95 1.0 1.0 z e z d b p a 1 h e h d y 0.10 e 0.8 c 0 10 l 0.4 0.6 0.8 0 0.1 0.2 a 3.05 16.5 16.8 17.1 16.5 16.8 17.1 a 2 2.8 e 13.8 14.0 14.2 d 13.8 14.0 14.2 reference symbol dimension in millimeters min nom max 0.3 0.35 0.45 0.13 0.15 0.2 p-qfp64-14x14-0.80 1.1g mass[typ.] 64p6n-a prqp0064ga-a renesas code jeita package code previous code 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. detail f l a 1 a 2 y index mark *3 *1 *2 f 64 49 48 33 32 17 16 1 z e z d b p e a h d d h e e c 0 3.8 a 2 1.050.750.65 b 2 19.35 18.75 19.05 0.60.50.4 b p previous code jeita package code renesas code prdp0064ba-a 64p4b mass[typ.] 7.9g p-sdip64-17x56.4-1.78 0.320.250.2 maxnommin dimension in millimeters symbol reference 56.656.456.2 d 17.15 17.0 16.85 e a 1.31.00.9 0.38 2.8 l c 1.778 e 15 b 3 a 1 5.08 1.528 2.028 include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. 33 64 32 1 seating plane *1 *2 *3 *3 e c a 1 a 2 d l a b 2 e b 3 b p e 1 e 1 rev.3.11 apr 5, 2006 page 104 of 113 rej03b0017-0311 3803 group (spec.h) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark *3 17 32 64 49 11 6 33 48 f *1 *2 x y b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.250.200.15 max nommin dimension in millimeters symbol reference 10.110.0 9.9 d 10.110.0 9.9 e 1.4 a 2 12.212.011.8 12.212.011.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e terminal cross section b1 c1 bp c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. *3 11 6 17 32 33 48 49 64 f *1 *2 x y index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.420.370.32 maxnommin dimension in millimeters symbol reference 14.114.013.9 d 14.114.013.9 e 1.4 a 2 16.216.015.8 16.216.015.8 1.7 a 0.20.1 0 0.70.50.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 rev.3.11 apr 5, 2006 page 105 of 113 rej03b0017-0311 3803 group (spec.h) 0.15 v 0.20 w previous code jeita package code renesas code ptlg0064ja-a 64f0g mass[typ.] 0.07g p-tflga64-6x6-0.65 0.08 0.470.430.39 maxnommin dimension in millimeters symbol reference 6.0 d 6.0 e 1.05 a x 0.65 e 0.10 y b 1 b 0.31 0.35 0.39 b w s w a s a h g f e d c b 12345678 s ys ab index mark sab v x4 (laser mark) index mark d e a b 1 b e e rev.3.11 apr 5, 2006 page 106 of 113 rej03b0017-0311 3803 group (spec.h) notes notes on programming 1. processor status register (1) initializing of proc essor status register flags which affect program execution must be initialized after a reset. in particular, it is essential to initialize the t and d flags because they have an important effect on calculations. rev.3.11 apr 5, 2006 page 107 of 113 rej03b0017-0311 3803 group (spec.h) notes on peripheral functions notes on input and output ports 1. notes in standby state in standby state *1 for low-power dissipat ion, do not make input levels of an i/o port ?undefined ?. even when an i/o port of nchannel open-drain is set as output mode, if output data is ?1?, the aforementioned not es are necessary. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: ? external circuit ? variation of output levels during the ordinary operation when using built-in pull-up resistor, note on varied current values: ? when setting as an input port : fix its input level ? when setting as an output port : prevent current from flowing out to external rev.3.11 apr 5, 2006 page 108 of 113 rej03b0017-0311 3803 group (spec.h) notes on interrupts 1. change of relevant register settings when the setting of the following re gisters or bits is changed, the interrupt request bit may be set to ?1?. when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? interrupt edge selecti on register (address 003a 16 ) ? timer xy mode register (address 0023 16 ) ? timer z mode register (address 002a 16 ) set the above listed registers or bits as the following sequence. fig 88. sequence of changing relevant register rev.3.11 apr 5, 2006 page 109 of 113 rej03b0017-0311 3803 group (spec.h) notes on 8-bit timer (timer 1, 2, x, y) ? if a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). ? when switching the count sour ce by the timer 12, x and y count source selection bits, the value of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count input signals. therefore, select the timer count source before set the value to the prescaler and the timer. ? set the double-function port of the cntr 0 /cntr 1 pin and port p5 4 /p5 5 to output in the pulse output mode. ? set the double-function port of cntr 0 /cntr 1 pin and port p5 4 /p5 5 to input in the event count er mode and the pulse width measurement mode. notes on 16-bit timer (timer z) 1. pulse output mode ? set the double-function port of the cntr 2 pin and port p4 7 to output. 2. pulse period measurement mode ? set the double-function port of the cntr 2 pin and port p4 7 to input. ? a read-out of timer value is impossible in this mode. the timer can be written to only duri ng timer stop (no measurement of pulse period). ? since the timer latch in this mode is specialized for the read- out of measured values, do not perform any write operation during measurement. ? ?ffff 16 ? is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. 3. pulse width measurement mode ? set the double-function port of the cntr 2 pin and port p4 7 to input. ? a read-out of timer value is impossible in this mode. the timer can be written to only duri ng timer stop (no measurement of pulse period). ? since the timer latch in this mode is specialized for the read- out of measured values, do not perform any write operation during measurement. ? ?ffff 16 ? is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. 4. programmable waveform generating mode ? set the double-function port of the cntr 2 pin and port p4 7 to output. 5. programmable one-shot generating mode ? set the double-function port of cntr 2 pin and port p4 7 to output, and of int 1 pin and port p4 2 to input in this mode. ? this mode cannot be used in low-speed mode. ? if the value of the cntr 2 active edge swit ch bit is changed during one-shot generating en abled or generating one-shot pulse, then the output level from cntr 2 pin changes. 6. all modes ? timer z write control which write control can be selected by the timer z write control bit (bit 3) of the timer z mode register (address 002a 16 ), writing data to both the latch and the timer at the same time or writing data only to the latch. when the operation ?writing data only to the latch? is selected, the value is set to the timer latch by writing data to the address of timer z and the timer is updated at next underflow. after reset release, the operation ?w riting data to both th e latch and the timer at the same time? is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer z. in the case of writing data only to the latch, if writing data to the latch and an underflow are perform ed almost at the same time, the timer value may become undefined. ? timer z read control a read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. in the other modes, a read-out of timer value is possible regardless of count operating or stopped. however, a read-out of time r latch value is impossible. ? switch of interrupt active edge of cntr 2 and int 1 each interrupt active edge de pends on setting of the cntr 2 active edge switch bit and the int 1 active edge selection bit. ? switch of count source when switching the count sour ce by the timer z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. therefore, select the timer count source before setting the value to the prescaler and the timer. rev.3.11 apr 5, 2006 page 110 of 113 rej03b0017-0311 3803 group (spec.h) notes on serial interface 1. notes when selecting clock synchronous serial i/o (1) stop of transmission operation as for serial i/oi (i = 1, 3) th at can be used as either a clock synchronous or an asynchronous (uart) serial i/o, clear the serial i/oi enable bit and the transmit enable bit to ?0? (serial i/oi and transmit disabled). rev.3.11 apr 5, 2006 page 111 of 113 rej03b0017-0311 3803 group (spec.h) notes on pwm the pwm starts from ?h? level af ter the pwm enable bit is set to enable and ?l? level is te mporarily output from the pwm pin. the length of this ?l? leve l output is as follows: n + 1 2 ? f(x in ) (s) (count source selection bit = ?0?, where n is the value set in the prescaler) n + 1 f(x in ) (s) (count source selection bit = ?1?, where n is the value set in the prescaler) notes on a/d converter 1. analog input pin make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 f to 1 f. further, be sure to verify the operation of application products on the user side. rev.3.11 apr 5, 2006 page 112 of 113 rej03b0017-0311 3803 group (spec.h) notes on restarting oscillation ? restarting oscillation usually, when the mcu stops the clock oscillation by stp instruction and the stp instruct ion has been released by an external interrupt source, the fixed values of timer 1 and prescaler 12 (timer 1 = ?01 16 ?, prescaler 12 = ?ff 16 ?) are automatically reloaded in orde r for the oscillation to stabilize. the user can inhibit the automatic setting by writing ?1? to bit 0 of misrg (address 0010 16 ). however, by setting this bit to ?1?, the previous values, set just before the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you will need to set an appropriate value to each register, in ac cordance with the oscillation stabilizing time, before executing the stp instruction. rev.3.11 apr 5, 2006 page 113 of 113 rej03b0017-0311 3803 group (spec.h) notes on handling of power source pins in order to avoid a latch-up oc currence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin), and between power source pin (v cc pin) and analog power source input pin (av ss pin). besides, connect the capacito r to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f?0.1 f is recommended. power source voltage when the power source voltage va lue of a microcomputer is less than the value which is indicat ed as the recommended operating conditions, the microc omputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the sy stem by this unstable operation. (1/3) revision history 3803 group (spec.h) data sheet rev. date description page summary first edition issued ?elete the following :?:kp package is under development. ?able 4 pin description v cc ,v ss apply voltage of 2.7?.5v 1.8v?.5v ?ig.5 memory expansion plan as of dec. 2002 as of mar. 2003 ?otes (address 3a 16 ) (address 003a 16 ), (address 23 16 ) (address 0023 16 ), (address 2a 16 ) (address 002a 16 ), (address 39 16 ) (address 0039 16 ) ?ig.61 system clock generating circuit block diagram ?able 10 recommended operating conditions add : v il ??input voltage x in , x cin 1.8 v cc 5.5v min. 0 ?able 11 recommended operating conditions f(x in ) high-speed mode f( )=f(x in )/2 2.2 v cc 4.0v 2.7 v cc 4.0v ?able 16 a/d converter characteristics v cc 8bit a/d mode, 10bit a/d mode max. 5.0 5.5 ?able 17 d/a converter characteristics v cc = 4.0 to 5.5v 4.0 v cc 5.5v, v cc = 2.7 to 4.0v 2.7 v cc <4.0v ?able 16 a/d converter characteristics, table 17 d/a converter characteristics resolution unit bits bit ?able 18 timing requirements (1) (in high-speed mode) t c (x in ) main clock x in input cycle time 2.7 v cc <4.0 min. 2.6 ? 10 3 /(82v cc -3) 26 ? 10 3 /(82v cc -3) ?able 18 timing requirements (1) (in high-speed mode), table 20 timing requirements (3) (in middle-speed mode) t wh (x cin ) sub-clock input ??pulse width sub-clock x cin input ??pulse width t wl (x cin ) sub-clock input ??pulse width sub-clock x cin input ??pulse width ?able 19 timing requirements (2) (in high-speed mode), table 20 timing requirements (4) (in middle-speed mode) t cl (s clk2 ) t wl (s clk2 ) ?ig.63 timing diagram (in single-chip mode) delete the following underline parts : s clk1 s clk2 s clk3 t f , t r t x d 1 t x d 3 s out2 t d (s clk1 -t x d 1 ), t d (s clk2 -s out2 ), t d (s clk3 -t x d 3 ) t v (s clk1 -t x d 1 ), t v (s clk2 -s out2 ), t v (s clk3 -t x d 3 ) 1,2,6,7 5 7 23 64 68 69 73 75 75,77 76,78 79 stp instruction timing (internal clock) s r q middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note 1) prescaler 12 timer 1 reset or stp instruction (note 2) divider (note 3) ff 16 01 16 stp instruction timing (internal clock) s r q middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note 1) prescaler 12 timer 1 reset or stp instruction (note 2) divider (note 3) reset 1.00 sep. 3, 2001 2.00 may. 28, 2003 3.00 oct. 14, 2003 3.01 jun.25, 2004 flash memory version is added. 6 15 16 table 5 pin description is partly revised. figure 11 memory map of special function register (sfr) is partly revised. table 8 i/o port function is partly revised. revision history (2/3) revision history 3803 group (spec.h) data sheet rev. date description page summary 3.01 jun.25, 2004 61 61 63 65 69 69 70 70 70 80 86 87 88 97 97 98 98 98 99 101 explanations of ?eset circuit?are partly revised. figure 56 reset circuit example is partly revised. explanations of ?1) stop mode?of ?scillation control?are partly added. figure 56 reset circuit example is partly revied. explanations of ?utline performance?are partly revised. figure 64 structure of flash memory control register 0 is partly revised. figure 66 is partly revised. table 11 is partly revised. figure 67 is partly revised. p4 6 of table 15 is revised. ?otes on programming?is added. ?ata required for mask orders?is added. note of table 16 is partly revised. table 26 a/d converter characteristics (mask rom version) is partly revised. table 27 d/a converter characteristics (mask rom version) is partly revised. table 29 a/d converter characteristics (flash memory version) is partly revised. table 30 d/a converter characteristics (flash memory version) is partly revised. table 31 power source circuit timing characteristics (flash memory version) is added. ____________ tw(reset) of table 32 is revised. table 33 and table 34 of rev.3.00 are eliminated. 3.02 nov.05, 2004 1 1,2,5,8,9 9 35 62 64 65 66 77 80 95 100,101 102,103 104 105 108 memory size rom....16 k to 32 k bytes 16 k to 60 k bytes ram....640 to 1024 bytes 640 to 2048 bytes wg version is added. fig.6 is partly eliminated. (5) pulse width measurement mode is partly revised. fig.58 is partly revised. clock generating circuit is partly revised. fig.60 is partly revised. note 4 of fig.62 is added. functions to inhibit rewriting flash memory version is partly added. standard serial i/o mode is partly revised. outline performance (standard serial i/o mode) is eliminated. table 23 electrical characteristics (1) ? ol ??output voltage p2 0 ?2 7 ?is added. table 33 timing requirements (1), table 34 timing requirements (2) (in high-speed mode) is deleted. mask rom versoin: vcc = 1.8 to 5.5v vcc = 2.0 to 5.5v table 35 switching characteristics (1), table 36 switching characteristics (2) are added. fig.80 circuit for measuring output switching characteristics (1), fig.81 circuit for measuring output switching characteristics (2) are added. fig.82 timing diagram (in single-chip mode) is revised. package outline 64f0g is added. 3.03 jun.17, 2005 all pages delete the following: ?nder development? 1 packages, table 1 package name revised. 2 packages, table 2 package name revised. 3 fig.1, table 3 package name revised. 4 fig.2, table 4 package name revised. (3/3) revision history 3803 group (spec.h) data sheet rev. date description page summary 3.03 jun.17, 2005 5 fig.3, table 5 package name revised. 9 ?packages? package name revised. 74 to 85 fig.74 to fig.77 package name revised. 89 table 17 is partly revised. 106 to 108 package outline revised. 3.10 nov.14, 2005 - bit name revised: stp instruction disable bit stp instruction function selection bit 20 fig.15 port block diagram (18) port p56 revised. 61 watchdog timer operations revised. bit 6 of watchdog timer control register added. fig.55: block diagram of watchdog timer revised. fig.56: structure of watchdog timer control register revised. bit name and its description revised. (bit function is not changed.) stp instruction function selection bit 0 : entering stop mode by execution of stp instruction 1 : internal reset by execution of stp instruction 88 flash memory version revised. fig.80: wiring for the cnvss pin added. 106 to 108 package outline revised. 109 to 116 appendix added. 3.11 apr.5, 2006 1, 5 table 1, table 5, fig.3; m38037m8h-xxxwg deleted. 7 table 6 functions revised. 9 packages; ?lga? ?flga? 13 [cpu mode register (cpum)] ?the cpu mo de register .... selection bit, etc.? ?the cpu mode register ....selection bit, t he internal system clo ck control bits, etc.? 15 memory keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to "http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 2006. renesas technology corp., all rights reserved. printed in japan. colophon .6.0 |
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