View LC87F6032A_6733196.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

22504 tn im no no.7371-1/16 ver.1.00 n 0501 preliminary overview the LC87F6032A is an 8-bit single chip microcontroller with the following one-chip features : ? cpu : operable at a minimum bus cycle time of 100 ns ? on-chip flash rom capacity : 32k bytes (on-board rewritable) ? on-chip ram capacity : 768 bytes ? vfd automatic display controller / driver ? 16-bit timer / counter (can be divided into two 8 bit timers) ? system clock divider ? synchronous serial i/o port (with automatic block tran smit / receive function) ? asynchronous / synchronous serial i/o port ? 8-channel 8-bit ad converter ? 11-source 9-vectored interrupt system features (1) read only memory (flash rom) ? single 5v power supply, on-board rewritable ? block erase in 128 byte units ? 32768 8 bits (LC87F6032A) (2) random access memory (ram) : 768 9 bits (LC87F6032A) (3) minimum bus cycle time : 100 ns (10mhz) note: bus cycle time indicates the speed to read rom. (4) minimum instruction cycle time : 300 ns (10mhz) ordering number : enn*7371 8 bit single chip microcontroller with 32k-byte from and 768-byte ram on chip LC87F6032A cmos ic *this product incorporates technology lic ensed from silicon storage technology inc package dimensions unit: mm 3159a [ LC87F6032A ]
LC87F6032A no.7371-2/16 (5) ports ? input / output ports input / output programmable for each bit individually : 9 (p1n, p70) data direction programmable in nibble units : 8 (p0n) (when n-channel open drain output is selected, data can be input by bit.) ? vfd output ports large current outputs for digits : 9 (s0 / t0 to s8 / t8) large current outputs for digits / segments : 7 (s9 / t9 to s15 / t15) digit / segment outputs : 8 (s16 to s23) segment outputs : 16 (s24 to s39) other function input ports : 16 (pcn, pdn,) ? oscillator pins : 2 (cf1, cf2) ? reset pin : 1 (res#) ? power supply : 3 (v ss 1, v dd 1, v dd 2) ? vfd power supply : 1 (vp) (6) vfd automatic display controller ? programmable segment / digit output pattern output can be toggled between digit / segment waveform output. (pins 9 - 24 can be used for the digit output) parallel-drive available for large current vfd ? 16-step dimmer function available (7) timers ? timer 0 : 16 bit timer / counter with capture register mode 0 : two 8-bit timers with 8-bit programmable prescaler and 8-bit capture register mode 1 : 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with 8-bit capture register mode 2 : 16-bit timer with 8-bit programmable prescaler and 16-bit capture register mode 3 : 16-bit counter with 16-bit capture register (8) serial interface ? sio 0 : 8 bit synchronous serial interface 1) lsb first / msb first function available 2) an internal 8-bit baud-rate generator (maximum transmit clock period 4 / 3 tcyc) 3) consecutive automatic data communication (1 - 256 bits) ? sio 1 : 8 bit asynchronous / synchronous serial interface mode 0 : synchronous 8 bit serial i o (2-wire or 3-wire, transmit clock 2 - 512 tcyc) mode 1 : asynchronous serial i o (half duplex, 8 data bits, 1 stop bit, baud rate 8 ? 2048 tcyc) mode 2 : bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 tcyc) mode 3 : bus mode 2 (start detection, 8 data bits, stop detection) (9) ad converter ? 8 channels 8-bit ad converter (10) remote receiver circuit (share with p15 / int3 / t0in terminal) ? noise rejection function (the filtering time of the noise rejection filter (1 / 32 / 128 tcyc) can be switched by program) (11) watchdog timer ? external rc circuit is required. ? interrupt or system reset is activated when the timer overflows. (12) system clock divider ? operable on the lowest power consumption ? minimum instruction cycle time (300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, 76.8 s can be switched by program (when using 10 mhz main clock)
LC87F6032A no.7371-3/16 (13) interrupts : 11-source and 9-vectored interrupt function 1) three interrupt priorities, low (l), high (h) a nd highest (x) are supported with multi-level nesting. during interrupt handling, an equal or lo wer level interrupt request is refused. 2) if interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. in the case of equal prio rity levels, the vector with th e lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2 / t0l 4 0001bh h or l int3 5 00023h h or l t0h 6 00033h h or l sio0 7 0003bh h or l sio1 8 00043h h or l adc 9 0004bh h or l vfd automatic display controller / port 0 ? priority level : x > h > l ? for equal priority levels, vector with lowest address takes precedence. (14) subroutine stack levels ? a maximum of 384 levels (set stack inside ram) (15) multiplication and division ? 16 bits 8 bits (5 instruction-cycle times) ? 24 bits 16 bits (12 instruction-cycle times) ? 16 bits 8 bits (8 instruction-cycle times) ? 24 bits 16 bits (12 instruction-cycle times) (16) oscillation circuits ? built-in rc oscillation circuit used for the system clock ? cf oscillation circuit used for the system clock. (rf built in) ? frequency-variable rc oscillation circuits for system clock use. (17) standby function ? halt mode the halt mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. (vfd display and some serial transfer operations stop). this operation mode can be released by a system reset or an interrupt request. ? hold mode the hold mode stops program execution and cf and rc oscillation circuits. this mode can be released by the following conditions. (1) supply "l" level to the reset terminal (2) supply the selected level to at least one of int0, int1, int2 (3) supply an interrupt condition to port 0 (18) shipping form ? qip64e (19) development tools ? evaluation (eva) chip : lc876093 ? emulator : eva62s + ecb876600 (evaluation chip board) + sub876000 + pod64qfp : ice-b877300 + sub876000 + pod64qfp (20) same package and pin assignment as mask rom version. 1) lc876000 series options can be set using flash rom data. thus testing and evaluation of mass production boards is possible. 2) the flash version has the ability to emulate the ram and rom capacity of the mask rom version.
LC87F6032A no.7371-4/16 pin assignment s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 v dd 2 vp s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 s0/t0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 41 48 47 46 45 44 43 42 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p06/an6 p07/an7 res v ss 1 cf cf2 v dd 1 p70/int0/t0lcp p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/int3/t0in/sck1 p16/int1/t0hcp p17/int2/t0in s30/pd6 s31/pd7 s32 s33 s34 s35 s36 s37 s38 s39 p00/an0 p01/an1 p02/an2 p03/an3 p04/an4 p05/an5 LC87F6032A top view sanyo : qip64e
LC87F6032A no.7371-5/16 system block diagram interrupt control standby control ir pla flash rom pc acc b register c register psw rar ram stack pointer watchdog timer alu sio0 sio1 timer 0 vfd controller int0 - 3 noise rejection adc port 7 port 1 port 0 bus interface clock generator cf mrc rc
LC87F6032A no.7371-6/16 pin functions name i/o function description option v ss 1 - power terminal (-) no v dd 1, v dd 2 - power terminal (+) no vp - power terminal (-) no port 0 p00 to p07 i/o ? 8-bit input / output port ? data direction programmable in nibble units ? pull-up resistor provided / not provided (s pecified in three bits for p01 to p03 and specified in nibble units for p04 to p07) ? hold release input ? port 0 interrupt input ? other function ad converter input port : an0 to an7 yes (p00 has no option) port 1 p10 to p17 i/o ? 8-bit input / output port ? data direction programmable for each bit individually ? pull-up resistor provided / not provided (specified by bit) ? other functions p10 : sio0 data output p11 : sio0 data input, bus input / output p12 : sio0 clock input / output p13 : sio1 data output p14 : sio1 data input, bus input / output p15 : sio1 clock input / output / int3 input with noise filter / timer 0 event input / timer 0h capture input p16 : int1 input / hold release input / timer 0h capture input p17 : int2 input / hold release input / ti mer 0 event input / timer 0l capture input yes port 7 ? 1-bit input / output port ? data direction programmable ? pull-up resistor provided / not provided ? other functions p70 : int0 input / hold release input / timer 0l capture input / output for watchdog timer ? interrupt detection style rising falling rising / falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 i/o no s0/t0 to s8/t8 o ? large current output for vfd di splay controller digit (c an be used for segment) no s9/t9 to s15/t15 o ? large current output for vfd display controller segment / digit no s16 to s23 i/o ? output for vfd display controller segment / digit ? other function high voltage input port : pc0 to pc7 no s24 to s31 i/o ? output for vfd display controller segment ? other function high voltage input port : pd0 to pd7 no s32 to s39 o ? output for vfd displa y controller segment no res i reset terminal no cf1 i input terminal for ceramic resonator no cf2 o output terminal for ceramic resonator no
LC87F6032A no.7371-7/16 port output configuration output configuration and pull-up / pull-down resistor options are shown in the following table. input /output is possible even when port is in output mode. terminal option applies to : options output format pull-up resistor pull-down resistor p00 ? none nch-open drain none ? 1 cmos programmable (note 1) ? p01 to p07 each bit 2 nch-open drain none ? 1 cmos programmable ? p10 to p17 each bit 2 nch-open drain programmable ? p70 ? none nch-open drain programmable ? s0/t0 to s6/t6 ? none high voltage pch-open drain ? none s7/t7 to s15/t15 ? none high voltage pch-open drain ? fixed s16 to s31 ? none high voltage pch-open drain ? none s32 to s39 ? none high voltage pch-open drain ? fixed note 1. programmable pull-up resisters of port 0 is specified in three bits (p01 - p03) and specified in nibble units (p04 - p07). * note 1 : connect as follows to reduce v dd signal noise and to increase the duration of the backup battery supply. absolute maximum ratings / ta=25 c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2 v dd 1=v dd 2 -0.3 +6.5 v i 1 ? cf1 ? res -0.3 v dd +0.3 input voltage v i 2 vp v dd -45 v dd +0.3 output voltage v o 1 ? s0/t0 to s15/t15 ? s32 to s39 v dd -45 v dd +0.3 v io 1 ? port 0 ? port 1 ? port 7 -0.3 v dd +0.3 input / output voltage v io 2 s16 to s31 v dd -45 v dd +0.3 v [high level output current] ioph1 port 0, 1 ? cmos output ? for each pin -10 ioph2 s0/t0 to s15/t15 for each pin -30 peak output current ioph4 s16 to s39 for each pin -15 ioah1 port 0 total of all pins -30 ioah2 port 1 total of all pins -30 ioah3 s0/t0 to s15/t15 total of all pins -65 total output current ioah4 s16 to s39 total of all pins -120 ma continued on next page. lsi v dd 1 v dd 2 v ss 1 power supply
LC87F6032A no.7371-8/16 continued from preceding page. parameter symbol pins conditions v dd [v] min typ max unit [low level output current] iopl1 port 0, 1 for each pin 20 peak output current iopl3 port 7 for each pin 5 ioal1 port 0 total of all pins 60 total output current ioal2 port 1, 7 total of all pins 60 ma maximum power consumption pd max qip64e ta = -20 to +70c 390 mw operating temperature range topr -20 +70 storage temperature range tstg -55 +125 c recommended operating range / ta=-20c to +70c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit operating supply voltage range v dd 1 v dd 1=v dd 2 0.294 s tcyc 200 s 4.5 5.5 hold voltage vhd v dd 1 ram and register data are kept in hold mode. 2.0 5.5 pull-down voltage vp vp 4.5 - 5.5 -35 v dd v ih 1 port 0 output disable 4.5 - 5.5 0.3v dd +0.7 v dd v ih 2 ? port 1 ? p70 port input / interrupt output disable 4.5 - 5.5 0.3v dd +0.7 v dd v ih 3 s16 to s31 output p-channel tr. off 4.5 - 5.5 0.33v dd +1.0 v dd v ih 4 port 70 watchdog timer output disable 4.5 - 5.5 0.9v dd v dd input high voltage v ih 5 ? cf1 ? res 4.5 - 5.5 0.75v dd v dd v il 1 port 0 output disable 4.5 - 5.5 v ss 0.15v dd +0.4 v il 2 ? port 1 ? p70 port input / interrupt output disable 4.5 - 5.5 v ss 0.1v dd +0.4 v il 3 s16 to s31 output p-channel tr. off 4.5 - 5.5 -35 0.2v dd v il 4 port 70 watchdog timer output disable 4.5 - 5.5 v ss 0.8v dd -1.0 input low voltage v il 5 ? cf1 ? res 4.5 - 5.5 v ss 0.25v dd v operation cycle time tcyc 4.5 - 5.5 0.294 200 s ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty= 505% 4.5 - 5.5 0.1 10 external system clock frequency fexcf1 cf1 ? leave cf2 pin open ? system clock divider set to 1/2 4.5 - 5.5 0.2 20 fmcf1 cf1, cf2 ? 10mhz (ceramic resonator) ? refer to figure 1 4.5 - 5.5 10 fmcf2 cf1, cf2 ? 4mhz (ceramic resonator) ? refer to figure 1 4.5 - 5.5 4 oscillation frequency range (note 1) fmrc internal rc oscillation 4.5 - 5.5 0.3 1.0 2.0 mhz (note 1) the oscillation parameters are shown on table 1 and 2.
LC87F6032A no.7371-9/16 electrical characteristics / ta=-20c to +70c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit i ih 1 ports 0, 1, 7 ? output disable ? pull-up resistor off ? v in =v dd (including the off-leak current of the output tr.) 4.5 - 5.5 1 i ih 2 s16 to s31 (port c, d) ? using as an input port ? v in =v dd 4.5 - 5.5 60 i ih 3 res v in =v dd 4.5 - 5.5 1 input high current i ih 4 cf1 v in =v dd 4.5 - 5.5 15 i il 1 port 0, 1 ,7 ? output disable ? pull-up resistor off ? v in =v ss (including the off-leak current of the output tr.) 4.5 - 5.5 -1 i il 2 res v in =v ss 4.5 - 5.5 -1 input low current i il 3 cf1 v in =v ss 4.5 - 5.5 -15 a v oh 1 i oh =-1.0ma 4.5 - 5.5 v dd -1 v oh 2 port 0, 1 : cmos output option i oh =-0.1ma 4.5 - 5.5 v dd -0.5 v oh 3 i oh =-20ma 4.5 - 5.5 v dd -1.8 v oh 4 s0/t0 to s15/t15 i oh =-1.0ma i oh at any single pin is not over 1ma. 4.5 - 5.5 v dd -1 v oh 5 i oh =-5.0ma 4.5 - 5.5 v dd -1.8 output high voltage v oh 6 s16 to s39 i oh =-1.0ma i oh at any single pin is not over 1ma. 4.5 - 5.5 v dd -1 v ol 1 i ol =9ma 4.5 - 5.5 1.5 v ol 2 port 0, 1 i ol =1.5ma 4.5 - 5.5 0.4 output low voltage v ol 3 port 7 i ol =1ma 4.5 - 5.5 0.4 v pull-up mos tr. resistor rpu port 0, 1, 7 v oh =0.9v dd 4.5 - 5.5 15 40 70 k ? i off 1 ? output p-ch tr. off ? v out =v ss 4.5 - 5.5 -1 off-leak current of the output tr. i off 2 ? s0/t0 to s6/t6 ? s16 to s31 ? output p-ch. tr. off ? v out =v dd - 40v 4.5 - 5.5 -30 a resistance of the low level hold tr. rinpd s16 to s31 output p-ch tr. off 4.5 - 5.5 200 high voltage pull-down resistor rpd ? s7/t7 to s15/t15 ? s32 to s39 ? output p-ch tr. off ? v out =3v ? vp=-30v 5.0 60 100 200 k ? hysteresis voltage vh is1 ? port 1, 7 ? res 4.5 - 5.5 0.1v dd v pin capacitance cp all pins ? all pins except the measured terminal : v in =v ss ? f=1mhz ? ta=25c 4.5 - 5.5 10 pf
LC87F6032A no.7371-10/16 serial input / output characteristics / ta=-20c to +70c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit [serial clock] [input clock] cycle tsck1 4/3 tsckl1 2/3 low level pulse width tsckla1 2/3 tsckh1 2/3 high level pulse width tsckha1 sck0 (p12) refer to figure 5 4.5 - 5.5 5 cycle tsck2 2 low level pulse width tsckl2 1 high level pulse width tsckh2 sck1 (p15) refer to figure 5 4.5 - 5.5 1 tcy c [output clock] cycle tsck3 4/3 tcy c tsckl3 1/2 low level pulse width tsckla2 3/4 tsckh3 1/2 high level pulse width tsckha2 sck0 (p12) ? cmos output ? refer to figure 5 4.5 - 5.5 2 tsck cycle tsck4 2 tcy c low level pulse width tsckl4 1/2 high level pulse width tsckh4 sck1 (p15) ? cmos output ? refer to figure 5 4.5 - 5.5 1/2 tsck [serial input] data set-up time tsdi 0.03 data hold time thdi si0 (p11), si1 (p14), sb0 (p11), sb1 (p14) ? data set-up to si0clk ? data hold from si0clk ? refer to figure 5 4.5 - 5.5 0.03 s [serial output] output delay time tddo so0 (p10), so1 (p13), sb0 (p11), sb1 (p14) ? data hold from si0clk ? time delay from si0clk trailing edge to the so data change in the open drain ? refer to figure 5 4.5 - 5.5 1/3 tcyc +0.05 s pulse input conditions / ta=-20c to +70c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit tpih1 tpil1 int0 (p70), int1 (p16), int2 (p17) ? interrupt acceptable ? timer 0 event input acceptable 4.5 - 5.5 1 tpih2 tpil2 int3 (p15) (the noise rejection clock is selected to 1/1) ? interrupt acceptable ? timer 0 event input acceptable 4.5 - 5.5 2 tpih3 tpil3 int3 (p15) (the noise rejection clock is selected to 1/32) ? interrupt acceptable ? timer 0 event input acceptable 4.5 - 5.5 64 tpih4 tpil4 int3 (p15) (the noise rejection clock is selected to 1/128) ? interrupt acceptable ? timer 0 event input acceptable 4.5 - 5.5 256 tcy c high / low level pulse width tpil7 res reset acceptable 4.5 - 5.5 200 s
LC87F6032A no.7371-11/16 ad converter characteristics / ta=-20c to + 70c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit resolution n 4.5 - 5.5 8 bit absolute precision et (note 2) 4.5 - 5.5 1.5 lsb ad conversion time = 32 tcyc (adcr2=0) (note 3) 15.62 (tcyc = 0.488 s) 97.92 (tcyc = 3.06 s) conversion time tcad ad conversion time = 64 tcyc (adcr2=1) (note 3) 4.5 - 5.5 18.82 (tcyc = 0.294 s) 97.92 (tcyc = 1.53 s) s analog input voltage range vain 4.5 - 5.5 v ss v dd v iainh vain=v dd 4.5 - 5.5 1 analog port input current iainl an0 (p00) to an7 (p07) vain=v ss 4.5 - 5.5 -1 a (note 2) absolute precision excludes the quantizing error (1/2 lsb). (note 3) the conversion time is the time from executing the ad conversion instruction to setting the complete digital conversion value in the register. current consumption characteristics / ta=-20c to +70c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit iddop1 ? fmcf = 10mhz for ceramic resonator oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stopped. ? frequency variable rc oscillation halted. ? divider set to 1/1 4.5 - 5.5 16 35 iddop2 ? cf1 = 20mhz for external clock ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stopped. ? frequency variable rc oscillation halted. ? divider set to 1/2 4.5 - 5.5 17 36 iddop3 ? fmcf = 4mhz ceramic resonator oscillation ? system clock : cf oscillation (4mhz) ? internal rc oscillation stopped. ? frequency variable rc oscillation halted. ? divider set to 1/1 4.5 - 5.5 7.5 21 current dissipation during basic operation (note 4) iddop4 v dd 1 = v dd 2 ? fmcf = 0hz (no oscillation) ? frequency variable rc oscillation halted. ? system clock : internal rc oscillation ? divider set to 1/2 4.5 - 5.5 1.5 11 ma continued on next page.
LC87F6032A no.7371-12/16 continued from preceding page. parameter symbol pins conditions v dd [v] min typ max unit current dissipation during basic operation (note 4) iddop5 v dd 1 = v dd 2 ? fmcf = 0hz (no oscillation) ? internal rc oscillation stopped. ? system clock = 1mhz with the frequency variable rc oscillation ? divider set to 1/2 4.5 - 5.5 2.7 13 ma iddhalt 1 halt mode ? fmcf = 10mhz for ceramic resonator oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stopped. ? frequency variable rc oscillation halted. ? divider : 1/1 4.5 - 5.5 3.5 12 iddhalt 2 halt mode ? cf1 = 20mhz for external clock ? system clock : cf1 oscillation ? internal rc oscillation stopped. ? frequency variable rc oscillation halted. ? divider : 1/2 4.5 - 5.5 4 13 iddhalt 3 halt mode ? fmcf = 4mhz for ceramic resonator oscillation ? system clock : cf oscillation (4mhz) ? internal rc oscillation ? frequency variable rc oscillation halted. ? divider : 1/1 4.5 - 5.5 2 6 ma iddhalt 4 halt mode ? fmcf = 0hz (when oscillation stops.) ? system clock : internal rc oscillation ? frequency variable rc oscillation halted. ? divider : 1/2 4.5 - 5.5 500 1600 current dissipation halt mode (note 4) iddhalt 5 v dd 1 = v dd 2 halt mode ? fmcf = 0hz (when oscillation stops.) ? internal rc oscillation stopped. ? system clock = 1mhz with the frequency variable rc oscillation ? divider : 1/2 4.5 - 5.5 1500 3600 a current dissipation hold mode iddhold1 v dd 1 hold mode ? cf1 = v dd or open circuit (when using external clock) 4.5 - 5.5 0.05 25 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
LC87F6032A no.7371-13/16 f-rom write characteristics / ta=+10 to +55c v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit on-board writing current iddfw1 v dd 1 ? 128-byte writing ? including erase time current 4.5 - 5.5 30 65 ma writing time tfw1 ? 128-byte writing ? including data erase time ? excluding time to fetch 128 byte data 4.5 - 5.5 5 10 ms main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. using the standard oscillation evaluation board s anyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacture. table 1. recommended circuit parameters for the main system clock using the ceramic resonator recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rd1 operating supply voltage range typ max notes cstls10m0g53-b0 (15pf) (15pf) 150 ? 4.5v - 5.5v 0.03ms 0.25ms 10mhz murata factory cstcc10m0g53-r0 (15pf) (15pf) 150 ? 4.5v - 5.5v 0.03ms 0.25ms c1 and c2 are built-in. cstls4m00g53-b0 (15pf) (15pf) 330 ? 4.5v - 5.5v 0.03ms 0.25ms 4mhz murata factory cstcr4m00g53-r0 (15pf) (15pf) 330 ? 4.5v - 5.5v 0.03ms 0.25ms c1 and c2 are built-in. *the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (refer to figure 3) (notes) ? since the oscillation frequency pr ecision is affected by the circuit patte rn, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 ac timing point c1 c2 cf cf2 cf1 rd1 0.5v dd
LC87F6032A no.7371-14/16 reset time and oscillation stabilization time hold release signal and oscillation stabilization time figure 3 oscillation stabilization time p ower s upp ly res internal rc oscillation cf1 , cf2 reset time tmscf o perat i on mo d e u n fi xe d r eset i nstruct i on execut i on v dd v dd li m i t 0v hold re l ease s i gna l internal rc oscillation cf1 , cf2 without hold release signal hold re l ease s i gna l valid tmscf o perat i on mo d e hold halt
LC87F6032A no.7371-15/16 figure 4 reset circuit figure 5 serial input / output test condition (note) select c res and r res value to assure that at least 200s reset time is generated after the v dd becomes higher than the minimum operating voltage. c res v dd r res res sioclk datain dataout di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transmission period (only sio0) sioclk datain dataout tsck tsckl tsckh tsdi thdi tddo sioclk datain dataout tddo tsdi thdi tsckla tsckha data ram transmission period (only sio0)
LC87F6032A no.7371-16/16 figure 6 pulse input timing condition ps tpil tpih

▲Up To Search▲

Price & Availability of LC87F6032A

	To Download LC87F6032A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .