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general description the max5510/max5511 are single, 8-bit, ultra-low- power, voltage-output, digital-to-analog converters (dacs) offering rail-to-rail buffered voltage outputs. the dacs operate from a 1.8v to 5.5v supply and consume less than 6?, making them desirable for low-power and low-voltage applications. a shutdown mode reduces overall current, including the reference input current, to just 0.18?. the max5510/max5511 use a 3-wire serial interface that is compatible with spi, qspi, and microwire. at power-up, the max5510/max5511 outputs are dri- ven to zero scale, providing additional safety for appli- cations that drive valves or for other transducers that must be off during power-up. the zero-scale outputs enable glitch-free power-up. the max5510 accepts an external reference input. the max5511 contains an internal reference and provides an external reference output. both devices have force- sense-configured output buffers. the max5510/max5511 are available in a 4mm x 4mm x 0.8mm, 12-pin, thin qfn package and are guaranteed over the extended -40 c to +85 c temperature range. for 12-bit compatible devices, refer to the max5530/ max5531 data sheet. for 10-bit compatible devices, refer to the max5520/max5521 data sheet. applications portable battery-powered devices instrumentation automatic trimming and calibration in factory or field programmable voltage and current sources industrial process control and remote industrial devices remote data conversion and monitoring chemical sensor cell bias for gas monitors programmable liquid crystal display (lcd) bias features ? single +1.8v to +5.5v supply ? ultra-low 6 a supply current ? shutdown mode reduces supply current to 0.18 a (max) ? small 4mm x 4mm x 0.8mm thin qfn package ? flexible force-sense-configured rail-to-rail output buffers ? internal reference sources 8ma of current (max5511) ? fast 16mhz 3-wire spi-/qspi-/microwire- compatible serial interface ? ttl- and cmos-compatible digital inputs with hysteresis ? glitch-free outputs during power-up max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs ________________________________________________________________ maxim integrated products 1 12 fb 11 n.c. 10 out 45 n.c. 6 n.c. 1 2 sclk 3 9 8 7 din gnd v dd n.c. max5510 max5511 cs refin (max5510) refout(max5511) thin qfn top view pin configuration ordering information selector guide 19-3120; rev 1; 2/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part reference top mark max5510etc external aaco max5511etc internal aacp part temp range pin-package pkg code max5510 etc -40? to +85? 12 thin qfn-ep* t1244-4 max5511 etc -40? to +85? 12 thin qfn-ep* t1244-4 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. * ep = exposed paddle (internally connected to gnd).
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +1.8v to +5.5v, out unloaded, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v out to gnd ...............................................-0.3v to (v dd + 0.3v) fb to gnd ..................................................-0.3v to (v dd + 0.3v) sclk, din, cs to gnd ..............................-0.3v to (v dd + 0.3v) refin, refout to gnd ............................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70 c) thin qfn (derate 16.9mw/ c above +70 c).............1349mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ..................................................... +150? lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units static accuracy (max5510 external reference) resolution n 8 bits v dd = 5v, v ref = 4.096v ?.25 1 integral nonlinearity (note 1) inl v dd = 1.8v, v ref = 1.024v ?.25 1 lsb guaranteed monotonic, v dd = 5v, v ref = 4.096v ?.2 1 differential nonlinearity (note 1) dnl guaranteed monotonic, v dd = 1.8v, v ref = 1.024v ?.2 1 lsb v dd = 5v, v ref = 4.096v 1 20 offset error (note 2) v os v dd = 1.8v, v ref = 1.024v 1 20 mv offset-error temperature drift 2 ?/ c v dd = 5v, v ref = 4.096v 0.5 1 gain error (note 3) ge v dd = 1.8v, v ref = 1.024v 0.5 1 lsb gain-error temperature coefficient 4 ppm/ c power-supply rejection ratio psrr 1.8v v dd 5.5v 85 db static accuracy (max5511 internal reference) resolution n 8 bits v dd = 5v, v ref = 3.9v ?.25 1 integral nonlinearity (note 1) inl v dd = 1.8v, v ref = 1.2v ?.25 1 lsb guaranteed monotonic, v dd = 5v, v ref = 3.9v ?.2 1 differential nonlinearity (note 1) dnl guaranteed monotonic, v dd = 1.8v, v ref = 1.2v ?.2 1 lsb v dd = 5v, v ref = 3.9v ? 20 offset error (note 2) v os v dd = 1.8v, v ref = 1.2v ? 20 mv offset-error temperature drift 2 ?/ c v dd = 5v, v ref = 3.9v ?.5 1 gain error (note 3) ge v dd = 1.8v, v ref = 1.2v ?.5 1 lsb gain-error temperature coefficient 4 ppm/ c
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +1.8v to +5.5v, out unloaded, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units power-supply rejection ratio psrr 1.8v v dd 5.5v 85 db reference input (max5510) reference-input voltage range v refin 0 v dd v normal operation 4.1 m ? reference-input impedance r refin in shutdown 2.5 g ? reference output (max5511) no external load, v dd = 1.8v 1.197 1.214 1.231 no external load, v dd = 2.5v 1.913 1.940 1.967 no external load, v dd = 3v 2.391 2.425 2.459 initial accuracy v refout no external load, v dd = 5v 3.828 3.885 3.941 v output-voltage temperature coefficient v tempco t a = -40 c to +85 c (note 4) 12 30 ppm/ c line regulation v refout < v dd - 200mv (note 5) 2 200 ?/v 0 i refout 1ma, sourcing, v dd = 1.8v, v ref = 1.2v 0.3 2 0 i refout 8ma, sourcing, v dd = 5v, v ref = 3.9v 0.3 2 load regulation -150? i refout 0, sinking 0.2 ?/? 0.1hz to 10hz, v refout = 3.9v 150 10hz to 10khz, v refout = 3.9v 600 0.1hz to 10hz, v refout = 1.2v 50 output noise voltage 10hz to 10khz, v refout = 1.2v 450 ? p-p v dd = 5v 30 short-circuit current (note 6) v dd = 1.8v 14 ma capacitive load stability range (note 7) 0 to 10 nf thermal hysteresis (note 8) 200 ppm refout unloaded, v dd = 5v 5.4 reference power-up time (from shutdown) refout unloaded, v dd = 1.8v 4.4 ms long-term stability 200 ppm/ 1khrs dac output (out) capacitive driving capability c l 1000 pf v dd = 5v, v out set to full scale, out shorted to gnd, source current 65 v dd = 5v, v out set to 0v, out shorted to v dd , sink current 65 v dd = 1.8v, v out set to full scale, out shorted to gnd, source current 14 short-circuit current (note 6) v dd = 1.8v, v out set to 0v, out shorted to v dd , sink current 14 ma
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +1.8v to +5.5v, out unloaded, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units v dd = 5v 3 coming out of shutdown (max5510) v dd = 1.8v 3.8 dac power-up time coming out of standby (max5511) v dd = 1.8v to 5.5v 0.4 ms output power-up glitch c l = 100pf 10 mv fb_ input current 10 pa digital inputs (sclk, din, cs ) 4.5v v dd 5.5v 2.4 2.7v < v dd 3.6v 2.0 input high voltage v ih 1.8v v dd 2.7v 0.7 x v d d v 4.5v v dd 5.5v 0.8 2.7v < v dd 3.6v 0.6 input low voltage v il 1.8v v dd 2.7v 0.3 x v dd v input leakage current i in (note 9) 0.05 0.5 ? input capacitance c in 10 pf dynamic performance voltage-output slew rate sr positive and negative (note 10) 10 v/ms voltage-output settling time 0.1 to 0.9 of full scale to within 0.5 lsb (note 10) 660 ? v dd = 5v 80 0.1hz to 10hz v dd = 1.8v 55 v dd = 5v 620 output noise voltage 10hz to 10khz v dd = 1.8v 476 ? p-p power requirements supply voltage range v dd 1.8 5.5 v v dd = 5v 2.6 4 v dd = 3v 2.6 4 max5510 v dd = 1.8v 3.6 5 v dd = 5v 5.3 6.5 v dd = 3v 4.8 6.0 supply current (note 9) i dd max5511 v dd = 1.8v 5.4 7.0 ? v dd = 5v 3.3 4.0 v dd = 3v 2.8 3.4 standby supply current i ddsd (note 9) v dd = 1.8v 2.4 3.0 ? shutdown supply current i ddpd (note 9) 0.05 0.18 ?
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units timing characteristics (v dd = 4.5v to 5.5v) serial clock frequency f sclk 0 16.7 mhz din to sclk rise setup time t ds 15 ns din to sclk rise hold time t dh 0ns sclk pulse-width high t ch 24 ns sclk pulse-width low t cl 24 ns cs pulse-width high t csw 100 ns sclk rise to cs rise hold time t csh 0ns cs fall to sclk rise setup time t css 20 ns sclk fall to cs fall setup t cso 0ns cs rise to sck rise hold time t cs1 20 ns timing characteristics (v dd = +4.5v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) timing characteristics (v dd = +1.8v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) note 1: linearity is tested within codes 6 to 255. note 2: offset is tested at code 6. note 3: gain is tested at code 250. fb is connected to out. note 4: guaranteed by design. not production tested. note 5: v dd must be a minimum of 1.8v. note 6: outputs can be shorted to v dd or gnd indefinitely, provided that the package power dissipation is not exceeded. note 7: optimal noise performance is at 2nf load capacitance. note 8: thermal hysteresis is defined as the change in the initial +25? output voltage after cycling the device from t max to t min . note 9: all digital inputs at v dd or gnd. note 10: load = 10k ? in parallel with 100pf, v dd = 5v, v ref = 4.096v (max5510) or v ref = 3.9v (max5511). parameter symbol conditions min typ max units timing characteristics (v dd = 1.8v to 5.5v) serial clock frequency f sclk 010 mhz in clk s tm 24 ns din to sclk rise hold time t dh 0 ns sclk pulse-width high t ch 40 ns sclk pulse-width low t cl 40 ns cs pulse-width high t csw 150 ns clk s cs rise hold time t csh 0 ns cs fall to sclk rise setup time t css 30 ns sclk fall to cs fall setup t cso 0 ns cs rise to sck rise hold time t cs1 30 ns
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs 6 _______________________________________________________________________________________ typical operating characteristics (v dd = 5.0v, v ref = 4.096v (max5510) or v ref = 3.9v (max5511), t a = +25?, unless otherwise noted.) supply current vs. supply voltage (max5511) max5510 toc01 supply voltage (v) supply current ( a) 5.5 5.0 4.0 4.5 2.5 3.0 3.5 2.0 1 2 3 4 5 6 7 8 9 10 0 1.5 6.0 supply current vs. temperature (max5511) max5510 toc02 temperature ( c) supply current ( a) 60 35 10 -15 1 2 3 4 5 6 7 8 9 10 0 -40 85 shutdown supply current vs. temperature (max5511) max5510 toc03 temperature ( c) shutdown supply current (na) 60 35 10 -15 1 10 100 1000 0.1 -40 85 standby supply current vs. temperature (max5511) max5510 toc04 temperature ( c) standby supply current ( a) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 v dd = 5v v ref = 3.9v v ref = 2.4v v ref = 1.9v v ref = 1.2v supply current vs. clock frequency max5510 toc05 frequency (khz) supply current ( a) 10000 1000 100 10 1 0.1 10 100 1000 1 0.01 100000 cs = logic low code = 0 v dd = 5v v dd = 1.8v supply current vs. logic input voltage max5510 toc06 logic input voltage (v) supply current (ma) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 05.0 all digital inputs shorted together inl vs. input code (v dd = v ref = 1.8v) max5510 toc07 digital input code inl (lsb) 250 200 50 100 150 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 -0.30 0300 inl vs. input code (v dd = v ref = 5v) max5510 toc08 digital input code inl (lsb) 250 200 50 100 150 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 -0.30 0300 dnl vs. input code (v dd = v ref = 1.8v) max5510 toc09 digital input code dnl (lsb) 250 200 150 100 50 -0.004 -0.002 0 0.002 0.004 0.006 0.008 0.010 0.012 0.014 -0.006 0300
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs _______________________________________________________________________________________ 7 dnl vs. input code (v dd = v ref = 5v) max5510 toc10 digital input code dnl (lsb) 250 200 150 100 50 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -0.03 0300 offset voltage vs. temperature max5510 toc11 temperature ( c) offset voltage (mv) 60 35 10 -15 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40 85 v dd = 5v v ref = 3.9v gain-error change vs. temperature max5510 toc12 temperature ( c) gain-error change (lsb) 60 35 10 -15 -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 0.025 -0.025 -40 85 v dd = 5v v ref = 3.9v digital feedthrough response (dac output set to 0) max5510 toc13 20 s/div cs 5v/div sclk 5v/div din 5v/div out 50mv/div zero scale dac output load regulation vs. output current max5510 toc14 dac output current ( a) dac output voltage (v) 800 600 400 200 0 -200 -400 -600 -800 0.6042 0.6044 0.6046 0.6048 0.6050 0.6040 -1000 1000 v dd = 1.8v dac code = midscale v ref = 1.2v dac output load regulation vs. output current max5510 toc15 dac output current (ma) dac output voltage (v) 8 6 -8 -6 -4 0 2 -2 4 1.9405 1.9410 1.9415 1.9420 1.9425 1.9430 1.9435 1.9440 1.9400 -10 10 v dd = 5.0v dac code = midscale v ref = 3.9v dac output voltage vs. output source current max5510 toc16 output source current (ma) output voltage (v) 10 1 0.1 0.01 1 2 3 4 5 0 0.001 100 v ref = v dd code = midscale v dd = 5v v dd = 3v v dd = 1.8v dac output voltage vs. output sink current max5510 toc17 output sink current (ma) dac output voltage (v) 10 1 0.1 0.01 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.001 100 v dd = 5v v dd = 3v v dd = 1.8v v ref = v dd code = midscale output large-signal step response (v dd = 1.8v, v ref = 1.219v) max5510 toc18 100 s/div v out 200mv/div typical operating characteristics (continued) (v dd = 5.0v, v ref = 4.096v (max5510) or v ref = 3.9v (max5511), t a = +25?, unless otherwise noted.)
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs 8 _______________________________________________________________________________________ output large-signal step response (v dd = 5v, v ref = 3.9v) max5510 toc19 200 s/div v out 500mv/div output minimum series resistance vs. load capacitance max5510 toc20 capacitance ( f) minimum series resistance ( ? ) 10 1 0.1 0.01 0.001 100 200 300 400 500 600 0 0.0001 100 for no overshoot power-up output voltage glitch max5510 toc21 20ms/div v out 10mv/div v dd 2v/div major carry output voltage glitch (code 7ffh to 800h) (v dd = 5v, v ref = 3.9v) max5510 toc22 100 s/div v out ac-coupled 5mv/div reference output voltage vs. temperature max5510 toc23 temperature ( c) reference output voltage (v) 60 35 -15 10 3.905 3.910 3.915 3.920 3.925 3.930 3.935 3.940 3.900 -40 85 v dd = 5v reference output voltage vs. reference output current max5510 toc24 reference output current ( a) reference output voltage (v) 7500 5500 3500 1500 1.215 1.216 1.217 1.218 1.219 1.220 1.214 -500 v dd = 1.8v reference output voltage vs. reference output current max5510 toc25 reference output current ( a) reference output voltage (v) 14,500 12,000 9500 7000 4500 2000 3.89 3.90 3.91 3.92 3.88 -500 v dd = 5v reference output voltage vs. supply voltage max5510 toc26 supply voltage (v) reference output voltage (v) 5.5 5.0 4.0 4.5 2.5 3.0 3.5 2.0 1.21732 1.21734 1.21736 1.21738 1.21740 1.21742 1.21744 1.21746 1.21748 1.21750 1.21730 1.5 6.0 no load reference line-transient response (v ref = 1.2v) max5510 toc27 100 s/div 2.8v v dd 1.8v v ref 500mv/div typical operating characteristics (continued) (v dd = 5.0v, v ref = 4.096v (max5510) or v ref = 3.9v (max5511), t a = +25?, unless otherwise noted.)
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs _______________________________________________________________________________________ 9 reference line-transient response (v ref = 3.9v) max5510 toc28 100 s/div 5.5v v dd 4.5v v ref 500mv/div 3.9v reference load transient (v dd = 1.8v) max5510 toc29 200 s/div refout source current 0.5ma/div v refout 500mv/div reference load transient (v dd = 5v) max5510 toc30 200 s/div refout source current 0.5ma/div v refout 500mv/div 3.9v reference load transient (v dd = 1.8v) max5510 toc31 200 s/div refout sink current 50 a/div v refout 500mv/div reference load transient (v dd = 5v) max5510 toc32 200 s/div refout sink current 100 a/div v refout 500mv/div 3.9v reference psrr vs. frequency max5510 toc33 frequency (khz) power-supply rejection ratio (db) 100 10 0.1 1 10 20 30 40 50 60 70 80 0 0.01 1000 v dd = 1.8v reference psrr vs. frequency max5510 toc34 frequency (khz) power-supply rejection ratio (db) 100 10 0.1 1 10 20 30 40 50 60 70 80 0 0.01 1000 v dd = 5v reference output noise (0.1hz to 10hz) (v dd = 1.8v, v ref = 1.2v) max5510 toc35 1s/div 100 v/div reference output noise (0.1hz to 10hz) (v dd = 5v, v ref = 3.9v) max5510 toc36 1s/div 100 v/div typical operating characteristics (continued) (v dd = 5.0v, v ref = 4.096v (max5510) or v ref = 3.9v (max5511), t a = +25?, unless otherwise noted.)
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs 10 ______________________________________________________________________________________ 8-bit dac dac register out refin gnd max5510 input register power- down control control logic and shift register fb sclk v dd din cs pin description max5510 functional diagram pin max5510 max5511 name function 11 cs active-low digital-input chip select 2 2 sclk serial-interface clock 3 3 din serial-interface data input 4 refin reference input 4 refout reference output 5, 6, 7, 11 5, 6, 7, 11 n.c. no connection. leave n.c. inputs unconnected (floating), or connect to gnd. 88v dd power input. connect v dd to a 1.8v to 5.5v power supply. bypass v dd to gnd with a 0.1? capacitor. 9 9 gnd ground 10 10 out analog voltage output 12 12 fb feedback input ep ep exposed paddle exposed paddle. connect ep to gnd.
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs ______________________________________________________________________________________ 11 detailed description the max5510/max5511 single, 8-bit, ultra-low-power, voltage-output dacs offer rail-to-rail buffered voltage outputs. the dacs operate from a 1.8v to 5.5v supply and require only 6? (max) supply current. these devices feature a shutdown mode that reduces overall current, including the reference input current, to just 0.18?. the max5511 includes an internal reference that saves additional board space and can source up to 8ma, making it functional as a system reference. the 16mhz, 3-wire serial interface is compatible with spi, qspi, and microwire protocols. when v dd is applied, all dac outputs are driven to zero scale with virtually no output glitch. the max5510/max5511 out- put buffers are configured in force sense allowing users to externally set voltage gains on the output (an output- amplifier inverting input is available). these devices come in a 4mm x 4mm thin qfn package. digital interface the max5510/max5511 use a 3-wire serial interface compatible with spi, qspi, and microwire protocols (figures 1 and 2). the max5510/max5511 include a single, 16-bit, input shift register. data loads into the shift register through the serial interface. cs must remain low until all 16 bits are clocked in. data loads msb first, d9?0. the 16 bits consist of 4 control bits (c3?0), 8 data bits (d7?0), and 4 sub-bits. (see table 1). d7?0 are the dac data bits and s3?0 are the sub-bits. the sub-bits must be set to zero for proper operation. the control bits c3?0 control the max5510/max5511, as outlined in table 2. each dac channel includes two registers: an input reg- ister and a dac register. the input register holds input data. the dac register contains the data updated to the dac output. the double-buffered register configuration allows any of the following: loading the input registers without updating the dac registers updating the dac registers from the input registers updating all the input and dac registers simultaneously 8-bit dac 2-bit programmable reference dac register out ref buf gnd max5511 refout input register power- down control control logic and shift register fb sclk v dd din cs max5511 functional diagram
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs 12 ______________________________________________________________________________________ t csw t css t cs0 t dh t cl t cs1 t csh t ch t ds sclk din cs c2 c1 c3 s0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sclk c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 s3 s2 s1 s0 din control bits data bits sub-bits command executed cs figure 1. timing diagram figure 2. register loading diagram control data bits msb lsb c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 s3 s2 s1 s0 table 1. serial write data format sub-bits s3?0 must be set to zero for proper operation.
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs ______________________________________________________________________________________ 13 control bits input data sub-bits c3 c2 c1 c0 d7?0 s3?0 function 0 0 0 0 xxxxxxxx 0000 no operation; command is ignored. 0 0 0 1 8-bit data 0000 load input register from shift register; dac register unchanged; dac output unchanged. 0 0 1 0 command reserved; do not use. 0 0 1 1 command reserved; do not use. 0 1 0 0 command reserved; do not use. 0 1 0 1 command reserved; do not use. 0 1 1 0 command reserved; do not use. 0 1 1 1 command reserved; do not use. 1 0 0 0 xxxx xxxx 0000 load dac register from input register; dac output updated; max5510 enters normal operation if in shutdown; max5511 enters normal operation if in standby or shutdown. 1 0 0 1 8-bit data 0000 load input register and dac register from shift register; dac output updated; max5510 enters normal operation if in shutdown; max5511 enters normal operation if in standby or shutdown. 1 0 1 0 command reserved; do not use. 1 0 1 1 command reserved; do not use. 11 0 0 d7, d6, xxxxxx 0000 max5510 enters shutdown; max5511 enters standby*. for the max5511, d7 and d6 configure the internal reference voltage (table 3). 11 0 1 d7, d6, xxxxxx 0000 max5510/max5511 enter normal operation; dac output reflects existing contents of dac register. for the max5511, d7 and d6 configure the internal reference voltage (table 3). 11 1 0 d7, d6, xxxxxx 0000 max5510/max5511 enter shutdown; dac output set to high impedance. for the max5511, d7 and d6 configure the internal reference voltage (table 3). 1 1 1 1 8-bit data 0000 load input register and dac register from shift register; dac output updated; max5510 enters normal operation if in shutdown; max5511 enters normal operation if in standby or shutdown. table 2. serial-interface programming commands x = don? care. *standby mode can be entered from normal operation only. it is not possible to enter standby mode from shutdown.
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs 14 ______________________________________________________________________________________ power modes the max5510/max5511 feature two power modes to conserve power during idle periods. in normal opera- tion, the device is fully operational. in shutdown mode, the device is completely powered down, including the internal voltage reference in the max5511. the max5511 also offers a standby mode where all circuitry is powered down except the internal voltage reference. standby mode keeps the reference powered up while the remaining circuitry is shut down, allowing it to be used as a system reference. standby mode also helps reduce the wake-up delay by not requiring the refer- ence to power up when returning to normal operation. shutdown mode the max5510/max5511 feature a software-program- mable shutdown mode that reduces the typical supply current and the reference input current to 0.18? (max). writing an input control word with control bits c[3:0] = 1110 places the device in shutdown mode (table 2). in shutdown, the max5510 reference input and dac output buffers go high impedance. placing the max5511 into shutdown turns off the internal refer- ence, and the dac output buffers go high impedance. the serial interface remains active for all devices. table 2 shows several commands that bring the max5510/max5511 back to normal operation. the power-up time from shutdown is required before the dac outputs are valid. note: for the max5511, standby mode cannot be entered directly from shutdown mode. the device must be brought into normal operation before entering stand- by mode. standby mode (max5511 only) the max5511 features a software-programmable standby mode that reduces the typical supply current to 6?. standby mode powers down all circuitry except the internal voltage reference. place the device in standby mode by writing an input control word with control bits c[3:0] = 1100 (table 2). the internal refer- ence and serial interface remain active while the dac output buffers go high impedance. if the max5511 is coming out of standby, the power-up time from standby is required before the dac outputs are valid. for the max5511, standby mode cannot be entered directly from shutdown mode. the device must be brought into normal operation before entering standby mode. to enter standby from shutdown, issue the com- mand to return to normal operation, followed immedi- ately by the command to go into standby. table 2 shows several commands that bring the max5511 back to normal operation. when transitioning from standby mode to normal operation, only the dac power-up time is required before the dac outputs are valid. reference input the max5510 accepts a reference with a voltage range extending from 0 to v dd . the output voltage (v out ) is represented by a digitally programmable voltage source as: v out = (v ref x n / 256) x gain where n is the numeric value of the dac? binary input code (0 to 255), v ref is the reference voltage and gain is the externally set voltage gain for the max5510/ max5511. in shutdown mode, the reference input enters a high- impedance state with an input impedance of 2.5g ? (typ). reference output the max5511 internal voltage reference is software configurable to one of four voltages. upon power-up, the default reference voltage is 1.214v. configure the reference voltage using the d6 and d7 data bits (table 3) when the control bits are as follows: c[3:0] = 1100, 1101, or 1110 (table 2). v dd must be kept at a mini- mum of 200mv above v ref for proper operation. d7 d6 reference voltage (v) 0 0 1.214 0 1 1.940 1 0 2.425 1 1 3.885 table 3. reference output voltage programming
applications information 1-cell and 2-cell circuit see figure 3 for an illustration of how to power the max5510/max5511 with either one lithium-ion battery or two alkaline batteries. the low current consumption of the devices makes the max5510/max5511 ideal for battery-powered applications. programmable current source see the circuit in figure 4 for an illustration of how to configure the max5510 as a programmable current source for driving an led. the max5510 drives a stan- dard npn transistor to program the current source. the current source (i led ) is defined in the equation in figure 4. voltage biasing a current-output transducer see the circuit in figure 5 for an illustration of how to con- figure the max5510 to bias a current-output transducer. in figure 5, the output voltage of the max5510 is a func- tion of the voltage drop across the transducer added to the voltage drop across the feedback resistor r. self-biased two-electrode potentiostat application see the circuit in figure 6 for an illustration of how to use the max5511 to bias a two-electrode potentiostat on the input of an adc. max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs ______________________________________________________________________________________ 15 refin max5510 max6006 (1 a, 1.25v shunt reference) gnd +1.25v 0.01 f 536k ? v dd dac vout n dac is the numeric value of the dac input code. v out (4.88mv / lsb) 1.8v v alkaline 3.3v 2.2v v lithium 3.3v v out = v refin n dac 256 0.1 f figure 3. portable application using two alkaline cells or one lithium coin cell r 2n3904 n dac is the numeric value of the dac input code. i led refin led max5510 v+ dac vout i led = v refin n dac 256 r fb figure 4. programmable current source driving an led r fb n dac is the numeric value of the dac input code. i t refin max5510 dac vout v out = v bias + (i t r) v out v bias transducer v bias = v refin n dac 256 figure 5. transimpedance configuration for a voltage-biased current-output transducer
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs 16 ______________________________________________________________________________________ unipolar output figure 7 shows the max5510 in a unipolar output con- figuration with unity gain. table 4 lists the unipolar out- put codes. bipolar output the max5510 output can be configured for bipolar operation, as shown in figure 8. the output voltage is given by the following equation: v out = v ref x [(n a - 128) / 128] where na represents the numeric value of the dac? binary input code. table 5 shows digital codes (offset binary) and the corresponding output voltage for the circuit in figure 4. configurable output gain the max5510/max5511 have a force-sense output, which provides a connection directly to the inverting ter- minal of the output op amp, yielding the most flexibility. the advantage of the force-sense output is that specific gains can be set externally for a given application. the gain error for the max5510/max5511 is specified in a unity-gain configuration (op-amp output and inverting ter- minals connected), and additional gain error results from external resistor tolerances. another advantage of the force-sense dac is that it allows many useful circuits to be created with only a few simple external components. figure 8. bipolar output circuit dac contents msb lsb analog output 1111 1111 0000 +v ref (127/128) 1000 0001 0000 +v ref (1/128) 1000 0000 0000 0v 0111 1111 0000 -v ref (1/128) 0000 0001 0000 -v ref (127/128) 0000 0000 0000 -v ref (128/128) = -v ref table 5. bipolar code table (gain = +1) refin max5510 out v out fb v+ 10k ? 10k ? v- dac dac band gap to adc out refout max5511 to adc to adc fb we sensor ce i f r f c l ref figure 6. self-biased two-electrode potentiostat application n a is the dac input code (0 to 255 decimal). refin max5510 out fb v out = v refin n a 256 dac figure 7. unipolar output circuit dac contents msb lsb analog output 1111 1111 0000 +v ref (255/256) 1000 0001 0000 +v ref (129/256) 1000 0000 0000 +v ref (128/256) = +v ref /2 0111 1111 0000 +v ref (127/256) 0000 0001 0000 +v ref (1/256) 0000 0000 0000 0v table 4. unipolar code table (gain = +1)
an example of a custom fixed gain using the force-sense output of the max5510/max5511 is shown in figure 9. in this example r1 and r2 set the gain for v out . v out = [(v refin x n a ) / 256] x [1 + (r2 / r1)] where n a represents the numeric value of the dac input code. power supply and bypassing considerations bypass the power supply with a 0.1? capacitor to gnd. minimize lengths to reduce lead inductance. if noise becomes an issue, use shielding and/or ferrite beads to increase isolation. for the thin qfn package, connect the exposed paddle to ground. layout considerations digital and ac transient signals coupling to gnd can create noise at the output. use proper grounding tech- niques, such as a multilayer board with a low-inductance ground plane. wire-wrapped boards and sockets are not recommended. for optimum system performance, use printed circuit (pc) boards. good pc board ground lay- out minimizes crosstalk between dac outputs, reference inputs, and digital inputs. reduce crosstalk by keeping analog lines away from digital lines. max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs ______________________________________________________________________________________ 17 figure 9. separate force-sense outputs create unity and greater-than-unity dac gains using the same reference refin dac v out out max5510 fb r2 r1 figure 10. software-configurable output gain h l fb w n dac is the numeric value of the dac input code. n pot is the numeric value of the pot input code. refin max5510 max5401 sot-pot 100k ? dac vout 5ppm/ c ratiometric tempco 1.8v v dd 5.5v v out v out = v refin n dac 256 ( 1 + 255 - n pot ) 255 sclk din cs2 cs1 chip information transistor count: 10,688 process: bicmos revision history pages changed at rev 1: 1, 13, 17, 18
max5510/max5511 +1.8v to +5.5v, ultra-low-power, 8-bit, voltage-output dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm

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