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1999 pcibus solutions data manual
printed in u.s.a., 12/99 scps051
pci2250 pci-to-pci bridge data manual literature number: scps051 december 1999 printed on recycled paper
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
iii contents section title page 1 introduction 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 description 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 features 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 related documents 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ordering information 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 terminal descriptions 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 feature/protocol descriptions 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 introduction to the pci2250 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 pci commands 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 configuration cycles 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 special cycle generation 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 secondary clocks 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 bus arbitration 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 primary bus arbitration 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 internal secondary bus arbitration 35 . . . . . . . . . . . . . . . . . . . . 3.6.3 external secondary bus arbitration 36 . . . . . . . . . . . . . . . . . . . 3.7 decode options 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 extension windows with programmable decoding 36 . . . . . . . . . . . . . . 3.9 system error handling 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 posted write parity error 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 posted write timeout 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 target abort on posted writes 37 . . . . . . . . . . . . . . . . . . . . . . . . 3.9.4 master abort on posted writes 37 . . . . . . . . . . . . . . . . . . . . . . . 3.9.5 master delayed write timeout 37 . . . . . . . . . . . . . . . . . . . . . . . . 3.9.6 master delayed read timeout 37 . . . . . . . . . . . . . . . . . . . . . . . 3.9.7 secondary serr 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 parity handling and parity error reporting 37 . . . . . . . . . . . . . . . . . . . . . . 3.10.1 address parity error 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 data parity error 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 master and target abort handling 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 discard timer 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 delayed transactions 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 multifunction pins 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.1 compact pci hot swap support 39 . . . . . . . . . . . . . . . . . . . . . . 3.14.2 pci clock run feature 310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 pci power management 310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.1 behavior in low power states 310 . . . . . . . . . . . . . . . . . . . . . . . .
iv 4 bridge configuration header 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 vendor id register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 device id register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 command register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 status register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 revision id register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 class code register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 cache line size register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 primary latency timer register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 header type register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 bist register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 base address register 0 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 base address register 1 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 primary bus number register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 secondary bus number register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 subordinate bus number register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 secondary bus latency timer register 48 . . . . . . . . . . . . . . . . . . . . . . . . 4.17 i/o base register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 i/o limit register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 secondary status register 410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 memory base register 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 memory limit register 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 prefetchable memory base register 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 prefetchable memory limit register 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 prefetchable base upper 32 bits register 412 . . . . . . . . . . . . . . . . . . . . . . 4.25 prefetchable limit upper 32 bits register 412 . . . . . . . . . . . . . . . . . . . . . . 4.26 i/o base upper 16 bits register 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 i/o limit upper 16 bits register 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 capability pointer register 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.29 expansion rom base address register 414 . . . . . . . . . . . . . . . . . . . . . . . . 4.30 interrupt line register 414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 interrupt pin register 414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 bridge control register 415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 extension registers 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 chip control register 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 extended diagnostic register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 arbiter control register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 extension window base 0, 1 registers 54 . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 extension window limit 0, 1 registers 54 . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 extension window enable register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 extension window map register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 secondary decode control register 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 primary decode control register 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 port decode enable register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v 5.11 buffer control register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 port decode map register 510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 clock run control register 511 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 diagnostic control register 511 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 diagnostic status register 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 arbiter request mask register 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 arbiter timeout status register 515 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.18 p_serr event disable register 516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.19 secondary clock control register 517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 p_serr status register 518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 pm capability id register 518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.22 pm next item pointer register 519 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.23 power management capabilities register 519 . . . . . . . . . . . . . . . . . . . . . . 5.24 power management control/status register 520 . . . . . . . . . . . . . . . . . . . . 5.25 pmcsr bridge support register 521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.26 data register 521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.27 hs capability id register 522 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.28 hs next item pointer register 522 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.29 hot swap control status register 523 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical characteristics 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 absolute maximum ratings over operating temperature ranges 61 . 6.2 recommended operating conditions 62 . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 recommended operating conditions for pci interface 62 . . . . . . . . . . . 6.4 electrical characteristics over recommended operating conditions 63 6.5 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature 64 . . . . . . . . . . . 6.6 pci timing requirements over recommended ranges of supply voltage and operating free-air temperature 65 . . . . . . . . . . . . . . . . . . . . 6.7 parameter measurement information 66 . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 pci bus parameter measurement information 67 . . . . . . . . . . . . . . . . . . . 7 mechanical data 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi list of illustrations figure title page 21 pci2250 pgf lqfp terminal diagram 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pci2250 pcm pqfp terminal diagram 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 system block diagram 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 pci ad31ad0 during address phase of a type 0 configuration cycle 32 33 pci ad31ad0 during address phase of a type 1 configuration cycle 33 34 bus hierarchy and numbering 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 secondary clock block diagram 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 load circuit and voltage waveforms 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 pclk timing waveform 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 rstin timing waveforms 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 shared-signals timing waveforms 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii list of tables table title page 21 pgf lqfp signal names sorted by terminal number 23 . . . . . . . . . . . . . . . 22 pcm lqfp signals sorted by terminal number 24 . . . . . . . . . . . . . . . . . . . . 23 signal names sorted alphabetically to pgf terminal number 25 . . . . . . . . 24 signal names sorted alphabetically to pcm terminal number 26 . . . . . . . . 25 primary pci system 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 primary pci address and data 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 primary pci interface control 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 secondary pci system 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 secondary pci address and data 210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 secondary pci interface control 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 miscellaneous terminals 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 power supply 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 pci command definition 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 bridge configuration header 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 bit field access tag descriptions 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 command register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 status register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 secondary status register 410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 bridge control register 415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 chip control register 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 extended diagnostic register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 arbiter control register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 extension window enable register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 extension window map register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 secondary decode control register 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 primary decode control register 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 port decode enable register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 buffer control register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 port decode map register 510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 clock run control register 511 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 diagnostic control register 512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 diagnostic status register 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 arbiter request mask register 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 arbiter timeout status register 515 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 p_serr event disable register 516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 secondary clock control register 517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 p_serr status register 518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii 519 power management capabilities register 519 . . . . . . . . . . . . . . . . . . . . . . . . . . 520 power management capabilities register 520 . . . . . . . . . . . . . . . . . . . . . . . . . . 521 pmcsr bridge support register 521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 hot swap control status register 523 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 1 introduction 1.1 description the texas instruments pci2250 pci-to-pci bridge provides a high performance connection path between two peripheral component interconnect (pci) buses. transactions occur between masters on one pci bus and targets on another pci bus, and the pci2250 allows bridged transactions to occur concurrently on both buses. the bridge supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently. the pci2250 bridge is compliant with the pci local bus specification , and can be used to overcome the electrical loading limits of 10 devices per pci bus and one pci device per expansion slot by creating hierarchical buses. the pci2250 provides two-tier internal arbitration for up to four secondary bus masters and may be implemented with an external secondary pci bus arbiter. the pci2250 provides compact-pci (cpci) hot-swap extended capability, which makes it an ideal solution for multifunction compact-pci cards and adapting single function cards to hot-swap compliance. the pci2250 bridge is compliant with the pci-to-pci bridge specification . it can be configured for positive decoding or subtractive decoding on the primary interface, and provides several additional decode options that make it an ideal bridge to custom pci applications. two extension windows are included, and the pci2250 provides decoding of serial and parallel port addresses. the pci2250 is compliant with pci power management interface specification revisions 1.0 and 1.1 . also, the pci2250 offers pci clkrun bridging support for low-power mobile and docking applications. the pci2250 has been designed to lead the industry in power conservation. an advanced cmos process is utilized to achieve low system power consumption while operating at pci clock rates up to 33 mhz. 1.2 features the pci2250 supports the following features: ? configurable for pci power management interface specification revision 1.0 or 1.1 support ? compact-pci friendly silicon as defined in the compact-pci hot swap specification ? 3.3-v core logic with universal pci interface compatible with 3.3-v and 5-v pci signaling environments ? two 32-bit, 33-mhz pci buses ? provides internal two-tier arbitration for up to four secondary bus masters and supports an external secondary bus arbiter ? burst data transfers with pipeline architecture to maximize data throughput in both directions ? provides programmable extension windows and port decode options ? independent read and write buffers for each direction ? provides five secondary pci clock outputs ? predictable latency per pci local bus specification ? propagates bus locking ? secondary bus is driven low during reset ? provides vga palette memory and i/o, and subtractive decoding options ? advanced submicron, low-power cmos technology
12 ? fully compliant with pci-to-pci bridge architecture specification ? packaged in 160-pin qfp (pcm) and 176-pin thin qfp (pgf) 1.3 related documents ? advanced configuration and power interface (acpi) revision 1.0 ? pci local bus specification revision 2.2 ? pci mobile design guide, revision 1.0 ? pci-to-pci bridge architecture specification revision 1.1 ? pci power management interface specification revision 1.1 ? picmg compact-pci hot swap specification revision 1.0 1.4 ordering information ordering number name voltage package pci2250 pcipci bridge 3.3 v, 5-v tolerant i/os 160-pin qfp 176-pin lqfp
21 2 terminal descriptions gnd nc s_par nc s_serr s_perr s_mfunc s_stop s_devsel s_trdy s_irdy s_frame gnd s_c/be2 s_ad16 s_ad17 s_ad18 s_ad19 gnd s_ad20 s_ad21 s_ad22 s_ad23 s_c/be3 s_ad24 gnd s_ad25 s_ad26 s_ad27 s_ad28 s_ad29 gnd s_ad30 s_ad31 s_req0 s_req1 nc s_req2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 nc ms1/bpcc nc s_c/be1 gnd s_ad15 s_ad14 s_ad13 s_ad12 gnd s_ad11 s_ad10 s_ad9 s_ad8 s_c/be0 s_ad7 gnd s_ad6 s_ad5 s_ad4 s_ad3 s_ad2 s_ad1 gnd s_ad0 p_ad0 p_ad1 p_ad2 p_ad3 gnd p_ad4 p_ad5 v p_ad6 p_ad7 nc p_c/be0 nc gnd ms0 nc gnd nc p_ad8 p_ad9 p_ad10 p_ad11 p_ad12 gnd p_ad13 p_ad14 p_ad15 p_c/be1 p_par p_serr p_perr gnd p_mfunc p_stop p_devsel p_trdy p_irdy p_frame p_c/be2 gnd p_ad16 p_ad17 p_ad18 v p_ad19 p_ad20 p_ad21 gnd p_ad22 p_ad23 p_idsel nc p_c/be3 nc gnd 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 gnd nc s_req3 nc s_gnt0 s_gnt1 s_gnt2 v s_gnt3 s_rst s_cfn gnd s_clk s_v s_clkout0 gnd s_clkout1 s_clkout2 gnd s_clkout3 s_clkout4 no/hsled goz p_rst gnd p_clk p_gnt p_req p_ad31 gnd p_ad30 p_ad29 p_ad28 p_ad27 p_ad26 p_ad25 nc p_ad24 nc 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 v cc cc ccp p_v ccp cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc cc v cc v cc v cc v cc v cc 12 nc figure 21. pci2250 pgf lqfp terminal diagram
22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 131 132 70 30 91 ms1/bpcc s_c/be1 gnd s_ad15 s_ad14 s_ad13 s_ad12 gnd s_ad11 s_ad9 s_ad8 s_c/be0 s_ad7 gnd s_ad6 s_ad5 s_ad4 s_ad3 s_ad2 gnd s_ad0 p_ad0 p_ad1 gnd s_req3 s_gnt0 s_gnt1 s_gnt2 s_gnt3 s_cfn gnd s_clk s_clkout0 gnd s_clkout1 gnd s_clkout3 s_clkout4 no/hsled goz p_rst gnd p_clk p_gnt p_req cc v cc v s_clkout2 cc v 123 124 125 126 127 128 129 130 121 122 p_ad2 p_ad3 gnd p_ad4 p_ad6 p_ad7 p_c/be0 gnd cc v 79 78 77 76 75 74 73 72 71 80 gnd p_ad30 p_ad29 p_ad28 p_ad27 p_ad25 cc v 32 33 34 35 36 37 38 39 90 89 88 87 86 85 84 83 82 40 81 31 p_ad24 p_ad26 gnd s_par s_serr s_perr s_mfunc s_stop s_devsel s_trdy s_irdy s_frame gnd s_c/be2 s_ad16 a_ad17 s_ad19 gnd s_ad21 s_ad22 s_ad23 s_c/be3 s_ad24 gnd s_ad25 s_ad26 cc v s_ad18 cc v s_ad27 s_ad28 s_ad29 gnd s_ad30 s_ad31 s_req1 cc v s_req2 s_req0 ms0 gnd p_ad8 p_ad9 p_ad10 p_ad11 p_ad12 gnd p_ad13 p_c/be1 p_par p_serr p_perr gnd p_mfunc p_stop p_devsel p_trdy p_irdy p_c/be2 gnd p_ad16 p_ad17 p_ad18 p_ad19 p_ad20 p_ad21 p_ad22 p_ad23 p_idsel p_c/be3 gnd cc v s_ad20 cc v cc v p_ad14 p_ad15 cc v cc v p_frame cc v gnd cc v p_ad31 ccp p_v cc v ccp s_v s_rst cc v p_ad5 s_ad1 s_ad10 cc v cc v cc v figure 22. pci2250 pcm pqfp terminal diagram
23 table 21. pgf lqfp signal names sorted by terminal number term. no. signal name term. no. signal name term. no. signal name term. no. signal name 1 gnd 45 gnd 89 gnd 133 gnd 2 nc 46 nc 90 nc 134 nc 3 s_par 47 s_req3 91 p_c/be3 135 p_c/be0 4 nc 48 nc 92 nc 136 nc 5 s_serr 49 s_gnt0 93 p_idsel 137 p_ad7 6 s_perr 50 s_gnt1 94 p_ad23 138 p_ad6 7 s_mfunc 51 s_gnt2 95 p_ad22 139 v cc 8 s_stop 52 v cc 96 gnd 140 p_ad5 9 s_devsel 53 s_gnt3 97 p_ad21 141 p_ad4 10 v cc 54 s_rst 98 p_ad20 142 gnd 11 s_trdy 55 s_cfn 99 p_ad19 143 p_ad3 12 s_irdy 56 gnd 100 v cc 144 p_ad2 13 s_frame 57 s_clk 101 p_ad18 145 v cc 14 gnd 58 s_v ccp 102 p_ad17 146 p_ad1 15 s_c/be2 59 s_clkout0 103 p_ad16 147 p_ad0 16 s_ad16 60 gnd 104 gnd 148 s_ad0 17 v cc 61 s_clkout1 105 p_c/be2 149 gnd 18 s_ad17 62 v cc 106 p_frame 150 s_ad1 19 s_ad18 63 s_clkout2 107 p_irdy 151 s_ad2 20 s_ad19 64 gnd 108 v cc 152 s_ad3 21 gnd 65 s_clkout3 109 p_trdy 153 v cc 22 s_ad20 66 v cc 110 p_devsel 154 s_ad4 23 s_ad21 67 s_clkout4 111 p_stop 155 s_ad5 24 s_ad22 68 no/hsled 112 p_mfunc 156 s_ad6 25 v cc 69 goz 113 gnd 157 gnd 26 s_ad23 70 p_rst 114 p_perr 158 s_ad7 27 s_c/be3 71 gnd 115 p_serr 159 s_c/be0 28 s_ad24 72 p_clk 116 p_par 160 s_ad8 29 gnd 73 p_v ccp 117 p_c/be1 161 v cc 30 s_ad25 74 p_gnt 118 v cc 162 s_ad9 31 s_ad26 75 p_req 119 p_ad15 163 s_ad10 32 v cc 76 p_ad31 120 p_ad14 164 s_ad11 33 s_ad27 77 gnd 121 p_ad13 165 gnd 34 s_ad28 78 p_ad30 122 gnd 166 s_ad12 35 s_ad29 79 p_ad29 123 p_ad12 167 s_ad13 36 gnd 80 p_ad28 124 p_ad11 168 v cc 37 s_ad30 81 v cc 125 p_ad10 169 s_ad14 38 s_ad31 82 p_ad27 126 v cc 170 s_ad15 39 s_req0 83 p_ad26 127 p_ad9 171 gnd 40 s_req1 84 p_ad25 128 p_ad8 172 s_c/be1 41 nc 85 nc 129 nc 173 nc 42 s_req2 86 p_ad24 130 gnd 174 ms1/bpcc 43 nc 87 nc 131 nc 175 nc 44 v cc 88 v cc 132 ms0 176 v cc
24 table 22. pcm lqfp signals sorted by terminal number term. no. signal name term. no. signal name term. no. signal name term. no. signal name 1 gnd 41 gnd 81 gnd 121 gnd 2 s_par 42 s_req3 82 p_c/be3 122 p_c/be0 3 s_serr 43 s_gnt0 83 p_idsel 123 p_ad7 4 s_perr 44 s_gnt1 84 p_ad23 124 p_ad6 5 s_mfunc 45 s_gnt2 85 p_ad22 125 v cc 6 s_stop 46 v cc 86 gnd 126 p_ad5 7 s_devsel 47 s_gnt3 87 p_ad21 127 p_ad4 8 v cc 48 s_rst 88 p_ad20 128 gnd 9 s_trdy 49 s_cfn 89 p_ad19 129 p_ad3 10 s_irdy 50 gnd 90 v cc 130 p_ad2 11 s_frame 51 s_clk 91 p_ad18 131 v cc 12 gnd 52 s_v ccp 92 p_ad17 132 p_ad1 13 s_c/be2 53 s_clkout0 93 p_ad16 133 p_ad0 14 s_ad16 54 gnd 94 gnd 134 s_ad0 15 v cc 55 s_clkout1 95 p_c/be2 135 gnd 16 s_ad17 56 v cc 96 p_frame 136 s_ad1 17 s_ad18 57 s_clkout2 97 p_irdy 137 s_ad2 18 s_ad19 58 gnd 98 v cc 138 s_ad3 19 gnd 59 s_clkout3 99 p_trdy 139 v cc 20 s_ad20 60 v cc 100 p_devsel 140 s_ad4 21 s_ad21 61 s_clkout4 101 p_stop 141 s_ad5 22 s_ad22 62 no/hsled 102 p_mfunc 142 s_ad6 23 v cc 63 goz 103 gnd 143 gnd 24 s_ad23 64 p_rst 104 p_perr 144 s_ad7 25 s_c/be3 65 gnd 105 p_serr 145 s_c/be0 26 s_ad24 66 p_clk 106 p_par 146 s_ad8 27 gnd 67 p_v ccp 107 p_c/be1 147 v cc 28 s_ad25 68 p_gnt 108 v cc 148 s_ad9 29 s_ad26 69 p_req 109 p_ad15 149 s_ad10 30 v cc 70 p_ad31 110 p_ad14 150 s_ad11 31 s_ad27 71 gnd 111 p_ad13 151 gnd 32 s_ad28 72 p_ad30 112 gnd 152 s_ad12 33 s_ad29 73 p_ad29 113 p_ad12 153 s_ad13 34 gnd 74 p_ad28 114 p_ad11 154 v cc 35 s_ad30 75 v cc 115 p_ad10 155 s_ad14 36 s_ad31 76 p_ad27 116 v cc 156 s_ad15 37 s_req0 77 p_ad26 117 p_ad9 157 gnd 38 s_req1 78 p_ad25 118 p_ad8 158 s_c/be1 39 s_req2 79 p_ad24 119 gnd 159 ms1/bpcc 40 v cc 80 v cc 120 ms0 160 v cc
25 table 23. signal names sorted alphabetically to pgf terminal number signal name term. no. signal name term. no. signal name term. no. signal name term. no. gnd 1 p_ad1 146 p_req 75 s_clkout0 59 gnd 14 p_ad2 144 p_rst 70 s_clkout1 61 gnd 21 p_ad3 143 p_serr 115 s_clkout2 63 gnd 29 p_ad4 141 p_stop 111 s_clkout3 65 gnd 36 p_ad5 140 p_trdy 109 s_clkout4 67 gnd 45 p_ad6 138 p_v ccp 73 s_devsel 9 gnd 56 p_ad7 137 s_ad0 148 s_frame 13 gnd 60 p_ad8 128 s_ad1 150 s_gnt0 49 gnd 64 p_ad9 127 s_ad2 151 s_gnt1 50 gnd 71 p_ad10 125 s_ad3 152 s_gnt2 51 gnd 77 p_ad11 124 s_ad4 154 s_gnt3 53 gnd 89 p_ad12 123 s_ad5 155 s_irdy 12 gnd 96 p_ad13 121 s_ad6 156 s_mfunc 7 gnd 104 p_ad14 120 s_ad7 158 s_par 3 gnd 113 p_ad15 119 s_ad8 160 s_perr 6 gnd 122 p_ad16 103 s_ad9 162 s_req0 39 gnd 130 p_ad17 102 s_ad10 163 s_req1 40 gnd 133 p_ad18 101 s_ad11 164 s_req2 42 gnd 142 p_ad19 99 s_ad12 166 s_req3 47 gnd 149 p_ad20 98 s_ad13 167 s_rst 54 gnd 157 p_ad21 97 s_ad14 169 s_serr 5 gnd 165 p_ad22 95 s_ad15 170 s_stop 8 gnd 171 p_ad23 94 s_ad16 16 s_trdy 11 goz 69 p_ad24 86 s_ad17 18 s_v ccp 58 ms0 132 p_ad25 84 s_ad18 19 v cc 10 ms1/bpcc 174 p_ad26 83 s_ad19 20 v cc 17 nc 2 p_ad27 82 s_ad20 22 v cc 25 nc 4 p_ad28 80 s_ad21 23 v cc 32 nc 41 p_ad29 79 s_ad22 24 v cc 44 nc 43 p_ad30 78 s_ad23 26 v cc 52 nc 46 p_ad31 76 s_ad24 28 v cc 62 nc 48 p_c/be0 135 s_ad25 30 v cc 66 nc 85 p_c/be1 117 s_ad26 31 v cc 81 nc 87 p_c/be2 105 s_ad27 33 v cc 88 nc 90 p_c/be3 91 s_ad28 34 v cc 100 nc 92 p_clk 72 s_ad29 35 v cc 108 nc 129 p_devsel 110 s_ad30 37 v cc 118 nc 131 p_frame 106 s_ad31 38 v cc 126 nc 134 p_gnt 74 s_c/be0 159 v cc 139 nc 136 p_idsel 93 s_c/be1 172 v cc 145 nc 173 p_irdy 107 s_c/be2 15 v cc 153 nc 175 p_mfunc 112 s_c/be3 27 v cc 161 no/hsled 68 p_par 116 s_cfn 55 v cc 168 p_ad0 147 p_perr 114 s_clk 57 v cc 176
26 table 24. signal names sorted alphabetically to pcm terminal number signal name term. no. signal name term. no. signal name term. no. signal name term. no. gnd 1 p_ad13 111 s_ad2 137 s_clkout4 61 gnd 12 p_ad14 110 s_ad3 138 s_devsel 7 gnd 19 p_ad15 109 s_ad4 140 s_frame 11 gnd 27 p_ad16 93 s_ad5 141 s_gnt0 43 gnd 34 p_ad17 92 s_ad6 142 s_gnt1 44 gnd 41 p_ad18 91 s_ad7 144 s_gnt2 45 gnd 50 p_ad19 89 s_ad8 146 s_gnt3 47 gnd 54 p_ad20 88 s_ad9 148 s_irdy 10 gnd 58 p_ad21 87 s_ad10 149 s_mfunc 5 gnd 65 p_ad22 85 s_ad11 150 s_par 2 gnd 71 p_ad23 84 s_ad12 152 s_perr 4 gnd 81 p_ad24 79 s_ad13 153 s_req0 37 gnd 86 p_ad25 78 s_ad14 155 s_req1 38 gnd 94 p_ad26 77 s_ad15 156 s_req2 39 gnd 103 p_ad27 76 s_ad16 14 s_req3 42 gnd 112 p_ad28 74 s_ad17 16 s_rst 48 gnd 119 p_ad29 73 s_ad18 17 s_serr 3 gnd 121 p_ad30 72 s_ad19 18 s_stop 6 gnd 128 p_ad31 70 s_ad20 20 s_trdy 9 gnd 135 p_c/be0 122 s_ad21 21 s_v ccp 52 gnd 143 p_c/be1 107 s_ad22 22 v cc 8 gnd 151 p_c/be2 95 s_ad23 24 v cc 15 gnd 157 p_c/be3 82 s_ad24 26 v cc 23 goz 63 p_clk 66 s_ad25 28 v cc 30 ms0 120 p_devsel 100 s_ad26 29 v cc 40 ms1/bpcc 159 p_frame 96 s_ad27 31 v cc 46 no/hsled 62 p_gnt 68 s_ad28 32 v cc 56 p_ad0 133 p_idsel 83 s_ad29 33 v cc 60 p_ad1 132 p_irdy 97 s_ad30 35 v cc 75 p_ad2 130 p_mfunc 102 s_ad31 36 v cc 80 p_ad3 129 p_par 106 s_c/be0 145 v cc 90 p_ad4 127 p_perr 104 s_c/be1 158 v cc 98 p_ad5 126 p_req 69 s_c/be2 13 v cc 108 p_ad6 124 p_rst 64 s_c/be3 25 v cc 116 p_ad7 123 p_serr 105 s_cfn 49 v cc 125 p_ad8 118 p_stop 101 s_clk 51 v cc 131 p_ad9 117 p_trdy 99 s_clkout0 53 v cc 139 p_ad10 115 p_v ccp 67 s_clkout1 55 v cc 147 p_ad11 114 s_ad0 134 s_clkout2 57 v cc 154 p_ad12 113 s_ad1 136 s_clkout3 59 v cc 160
27 table 25. primary pci system terminal name pcm number pgf number i/o description p_clk 66 72 i primary pci bus clock. p_clk provides timing for all transactions on the primary pci bus. all primary pci signals are sampled at rising edge of p_clk. p_rst 64 70 i pci reset. when the primary pci bus reset is asserted, p_rst causes the bridge to put all output buffers in a high-impedance state and reset all internal registers. when asserted, the device is completely nonfunctional. during p_rst , the secondary interface is driven low and no/hsled is driven high if hot-swap is enabled. after p_rst is deasserted, the bridge is in its default state. table 26. primary pci address and data terminal name pcm number pgf number i/o description p_ad31 p_ad30 p_ad29 p_ad28 p_ad27 p_ad26 p_ad25 p_ad24 p_ad23 p_ad22 p_ad21 p_ad20 p_ad19 p_ad18 p_ad17 p_ad16 p_ad15 p_ad14 p_ad13 p_ad12 p_ad11 p_ad10 p_ad9 p_ad8 p_ad7 p_ad6 p_ad5 p_ad4 p_ad3 p_ad2 p_ad1 p_ad0 70 72 73 74 76 77 78 79 84 85 87 88 89 91 92 93 109 110 111 113 114 115 117 118 123 124 126 127 129 130 132 133 76 78 79 80 82 83 84 86 94 95 97 98 99 101 102 103 119 120 121 123 124 125 127 128 137 138 140 141 143 144 146 147 i/o primary address/data bus. these signals make up the multiplexed pci address and data bus on the primary interface. during the address phase of a primary bus pci cycle, p_ad31p_ad0 contain a 32-bit address or other destination information. during the data phase, p_ad31p_ad0 contain data. p_c/be3 p_c/be2 p_c/be1 p_c/be0 82 95 107 122 91 105 117 135 i/o primary bus commands and byte enables. these signals are multiplexed on the same pci terminals. during the address phase of a primary bus cycle, p_c/be3 p_c/be0 define the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. p_c/be0 applies to byte 0 (p_ad7p_ad0), p_c/be1 applies to byte 1 (p_ad15p_ad8), p_c/be2 applies to byte 2 (p_ad23p_ad16), and p_c/be3 applies to byte 3 (p_ad31p_ad24).
28 table 27. primary pci interface control terminal name pcm number pgf number i/o description p_devsel 100 110 i/o primary device select. the bridge asserts p_devsel to claim a pci cycle as the target device. as a pci initiator on the primary bus, the bridge monitors p_devsel until a target responds. if no target responds before a time-out occurs, then the bridge terminates the cycle with a master abort. p_frame 96 106 i/o primary cycle frame. p_frame is driven by the initiator of a primary bus cycle. p_frame is asserted to indicate that a bus transaction is beginning, and data transactions continue while this signal is asserted. when p_frame is deasserted, the primary bus transaction is in the final data phase. p_gnt 68 74 i primary bus grant to bridge. p_gnt is driven by the primary pci bus arbiter to grant the bridge access to the primary pci bus after the current data transaction has completed. p_gnt may or may not follow a primary bus request, depending on the primary bus parking algorithm. p_idsel 83 93 i primary initialization device select. p_idsel selects the bridge during configuration space accesses. p_idsel can be connected to one of the upper 16 pci address lines on the primary pci bus. note: there is no idsel signal interfacing the secondary pci bus; thus, the entire configuration space of the bridge can only be accessed from the primary bus. p_irdy 97 107 i/o primary initiator ready. p_irdy indicates the ability of the primary bus initiator to complete the current data phase of the transaction. a data phase is completed on a rising edge of p_clk where both p_irdy and p_trdy are asserted. until p_irdy and p_trdy are both sampled asserted, wait states are inserted. p_par 106 116 i/o primary parity. in all primary bus read and write cycles, the bridge calculates even parity across the p_ad and p_c/be buses. as an initiator during pci write cycles, the bridge outputs this parity indicator with a one-p_clk delay. as a target during pci read cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (p_perr ). p_perr 104 114 i/o primary parity error indicator. p_perr is driven by a primary bus pci device to indicate that calculated parity does not match p_par when p_perr is enabled through bit 6 of the command register (offset 04h, see section 4.3). p_req 69 75 o primary pci bus request. p_req is asserted by the bridge to request access to the primary pci bus as an initiator. p_serr 105 115 o primary system error. output pulsed from the bridge when enabled through the command register (offset 04h, see section 4.3) indicating a system error has occurred. the bridge need not be the target of the primary pci cycle to assert this signal. when bit 1 is enabled in the bridge control register (offset 3eh, see section 4.32), this signal will also pulse indicating that a system error has occurred on one of the subordinate buses downstream from the bridge. p_stop 101 111 i/o primary cycle stop signal. this signal is driven by a pci target to request the initiator to stop the current primary bus transaction. this signal is used for target disconnects and is commonly asserted by target devices which do not support burst data transfers. p_trdy 99 109 i/o primary target ready. p_trdy indicates the ability of the primary bus target to complete the current data phase of the transaction. a data phase is completed on the rising edge of p_clk where both p_irdy and p_trdy are asserted. until p_irdy and p_trdy are both sample asserted, wait states are inserted.
29 table 28. secondary pci system terminal name pcm number pgf number i/o description s_clkout4 s_clkout3 s_clkout2 s_clkout1 s_clkout0 61 59 57 55 53 67 65 63 61 59 o secondary pci bus clocks. provide timing for all transactions on the secondary pci bus. each secondary bus device samples all secondary pci signals at the rising edge of its corresponding s_clkout input. s_clk 51 57 i secondary pci bus clock input. this input syncronizes the pci2250 to the secondary bus clocks. s_cfn 49 55 i secondary external arbiter enable. when this signal is high, the secondary external arbiter is enabled. when the external arbiter is enabled, the s_req0 pin is reconfigured as a secondary bus grant input to the bridge and s_gnt0 is reconfigured as a secondary bus master request to the external arbiter on the secondary bus. s_rst 48 54 o secondary pci reset. s_rst is a logical or of p_rst and the state of the secondary bus reset bit of the bridge control register (offset 3eh, see section 4.32). s_rst is asynchronous with respect to the state of the secondary interface clk signal.
210 table 29. secondary pci address and data terminal name pcm number pgf number i/o description s_ad31 s_ad30 s_ad29 s_ad28 s_ad27 s_ad26 s_ad25 s_ad24 s_ad23 s_ad22 s_ad21 s_ad20 s_ad19 s_ad18 s_ad17 s_ad16 s_ad15 s_ad14 s_ad13 s_ad12 s_ad11 s_ad10 s_ad9 s_ad8 s_ad7 s_ad6 s_ad5 s_ad4 s_ad3 s_ad2 s_ad1 s_ad0 36 35 33 32 31 29 28 26 24 22 21 20 18 17 16 14 156 155 153 152 150 149 148 146 144 142 141 140 138 137 136 134 38 37 35 34 33 31 30 28 26 24 23 22 20 19 18 16 170 169 167 166 164 163 162 160 158 156 155 154 152 151 150 148 i/o secondary address/data bus. these signals make up the multiplexed pci address and data bus on the secondary interface. during the address phase of a secondary bus pci cycle, s_ad31s_ad0 contain a 32-bit address or other destination information. during the data phase, s_ad31s_ad0 contain data. s_c/be3 s_c/be2 s_c/be1 s_c/be0 25 13 158 145 27 15 172 159 i/o secondary bus commands and byte enables. these signals are multiplexed on the same pci terminals. during the address phase of a secondary bus cycle, s_c/be3 s_c/be0 define the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. s_c/be0 applies to byte 0 (s_ad7s_ad0), s_c/be1 applies to byte 1 (s_ad15s_ad8), s_c/be2 applies to byte 2 (s_ad23s_ad16), and s_c/be3 applies to byte 3 (s_ad31s_ad24).
211 table 210. secondary pci interface control terminal name pcm number pgf number i/o description s_devsel 7 9 i/o secondary device select. the bridge asserts s_devsel to claim a pci cycle as the target device. as a pci initiator on the secondary bus, the bridge monitors s_devsel until a target responds. if no target responds before a timeout occurs, then the bridge terminates the cycle with a master abort. s_frame 11 13 i/o secondary cycle frame. s_frame is driven by the initiator of a secondary bus cycle. s_frame is asserted to indicate that a bus transaction is beginning and data transfers continue while s_frame is asserted. when s_frame is deasserted, the secondary bus transaction is in the final data phase. s_gnt3 s_gnt2 s_gnt1 s_gnt0 47 45 44 43 53 51 50 49 o secondary bus grant to the bridge. the bridge provides internal arbitration and these signals are used to grant potential secondary pci masters access to the bus. five potential initiators (including the bridge) can be located on the secondary pci bus. when the internal arbiter is disabled, s_gnt0 is reconfigured as an external secondary bus request signal for the bridge. s_irdy 10 12 i/o secondary initiator ready. s_irdy indicates the ability of the secondary bus initiator to complete the current data phase of the transaction. a data phase is completed on a rising edge of s_clk where both s_irdy and s_trdy are asserted. until s_irdy and s_trdy are both sample asserted, wait states are inserted. s_par 2 3 i/o secondary parity. in all secondary bus read and write cycles, the bridge calculates even parity across the s_ad and s_c/be buses. as an initiator during pci write cycles, the bridge outputs this parity indicator with a one-s_clk delay. as a target during pci read cycles, the calculated parity is compared to the initiator parity indicator. a miscompare can result in a parity error assertion (s_perr ). s_perr 4 6 i/o secondary parity error indicator. s_perr is driven by a secondary bus pci device to indicate that calculated parity does not match s_par when s_perr is enabled through bit 6 of the command register (offset 04h, see section 4.3). s_req3 s_req2 s_req1 s_req0 42 39 38 37 47 42 40 39 i secondary pci bus request signals. the bridge provides internal arbitration, and these signals are used as inputs from secondary pci bus initiators requesting the bus. five potential initiators (including the bridge) can be located on the secondary pci bus. when the internal arbiter is disabled, the s_req0 signal is reconfigures as an external secondary bus grant for the bridge. s_serr 3 5 i secondary system error. s_serr is passed through the primary interface by the bridge if enabled through the bridge control register (offset 3eh, see section 4.32). s_serr is never asserted by the bridge. s_stop 6 8 i/o secondary cycle stop signal. s_stop is driven by a pci target to request the initiator to stop the current secondary bus transaction. s_stop is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. s_trdy 9 11 i/o secondary target ready. s_trdy indicates the ability of the secondary bus target to complete the current data phase of the transaction. a data phase is completed on a rising edge of s_clk where both s_irdy and s_trdy are asserted. until s_irdy and s_trdy are both sample asserted, wait states are inserted.
212 table 211. miscellaneous terminals terminal name pcm number pgf number i/o description goz 63 69 i nand tree enable pin. no/hsled 62 68 i/o nand tree out when goz is asserted. hot-swap led when goz is deasserted. ms0 120 132 i mode select 0 ms1/bpcc 159 174 i mode select 1 when mode select 0 is low, bus power clock control when mode select 0 is high. p_mfunc 102 112 i/o primary multifunction terminal. this terminal can be configured as p_clkrun, p_lock , or hs_enum depending on the values of ms0 and ms1. s_mfunc 5 7 i/o secondary multifunction terminal. this terminal can be configured as s_clkrun, s_lock , or hs_switch depending on the values of ms0 and ms1. table 212. power supply terminal description name pcm number pgf number description gnd 1, 12, 19, 27, 34, 41, 50, 54, 58, 65, 71, 81, 86, 94, 103, 112, 119, 121, 128, 135, 143, 151, 157 1, 14, 21, 29, 36, 45, 56, 60, 64, 71, 77, 89, 96, 104, 113, 122, 130, 133, 142, 149, 157, 165, 171 device ground terminals v cc 8, 15, 23, 30, 40, 46, 56, 60, 75, 80, 90, 98, 108, 116, 125, 131, 139, 147, 154, 160 10, 17, 25, 32, 44, 52, 62, 66, 81, 88, 100, 108, 118, 126, 139, 145, 153, 161, 168, 176 power-supply terminal for core logic (3.3 v) p_v ccp 67 73 primary bus-signaling environment supply. p_v ccp is used in protection circuitry on primary bus i/o signals. s_v ccp 52 58 secondary bus-signaling environment supply. s_v ccp is used in protection circuitry on secondary bus i/o signals.
31 3 feature/protocol descriptions the following sections give an overview of the pci2250 pci-to-pci bridge features and functionality. figure 31 shows a simplified block diagram of a typical system implementation using the pci2250. pci option card cpu memory host bridge pci2250 pci device pci device pci bus 0 pci bus 1 host bus pci option slot pci2250 pci device pci device pci bus 2 (option) pci option card figure 31. system block diagram 3.1 introduction to the pci2250 the pci2250 is a bridge between two pci buses and is compliant with both the pci local bus specification and the pci-to-pci bridge specification . the bridge supports two 32-bit pci buses operating at a maximum of 33 mhz. the primary and secondary buses operate independently in either a 3.3-v or 5-v signaling environment. the core logic of the bridge, however, is powered at 3.3 v to reduce power consumption. host software interacts with the bridge through internal registers. these internal registers provide the standard pci status and control for both the primary and secondary buses. many vendor-specific features that exist in the ti extension register set are included in the bridge. the pci configuration header of the bridge is only accessible from the primary pci interface. the bridge provides internal arbitration for the four possible secondary bus masters, and provides each with a dedicated active low request/grant pair (req /gnt ). the arbiter features a two-tier rotational scheme with the pci2250 bridge defaulting to the highest priority tier. the bus parking scheme is also configurable and can be set to either park grant (gnt ) on the bridge or on the last mastering device. upon system power up, power-on self-test (post) software configures the bridge according to the devices that exist on subordinate buses, and enables the performance-enhancing features of the pci2250. in a typical system, this is the only communication with the bridge internal register set.
32 3.2 pci commands the bridge responds to pci bus cycles as a pci target device based on the decoding of each address phase and internal register settings. table 31 lists the valid pci bus cycles and their encoding on the command/byte enables (c/be ) bus during the address phase of a bus cycle. table 31. pci command definition c/be3 c/be0 command 0000 interrupt acknowledge 0001 special cycle 0010 i/o read 0011 i/o write 0100 reserved 0101 reserved 0110 memory read 0111 memory write 1000 reserved 1001 reserved 1010 configuration read 1011 configuration write 1100 memory read multiple 1101 dual address cycle 1110 memory read line 1111 memory write and invalidate the bridge never responds as a pci target to the interrupt acknowledge, special cycle, dual address cycle, or reserved commands. the bridge does, however, initiate special cycles on both interfaces when a type 1 configuration cycle issues the special cycle request. the remaining pci commands address either memory, i/o, or configuration space. the bridge accepts pci cycles by asserting devsel as a medium-speed device, i.e., devsel is asserted two clock cycles after the address phase. the pci2250 converts memory write and invalidate commands to memory write commands when forwarding transactions from either the primary or secondary side of the bridge. 3.3 configuration cycles the pci local bus specification defines two types of pci configuration read and write cycles: type 0 and type 1. the bridge decodes each type differently. type 0 configuration cycles are intended for devices on the primary bus, while type 1 configuration cycles are intended for devices on some hierarchically subordinate bus. the difference between these two types of cycles is the encoding of the primary pci (p_ad) bus during the address phase of the cycle. figure 32 shows the p_ad bus encoding during the address phase of a type 0 configuration cycle. the 6-bit register number field represents an 8-bit address with the two lower bits masked to 0, indicating a doubleword boundary. this results in a 256-byte configuration address space per function per device. individual byte accesses may be selected within a doubleword by using the p_c/be signals during the data phase of the cycle. reserved register number 31 function number 11 10 7 8 00 10 2 figure 32. pci ad31ad0 during address phase of a type 0 configuration cycle
33 the bridge claims only type 0 configuration cycles when its p_idsel terminal is asserted during the address phase of the cycle and the pci function number encoded in the cycle is 0. if the function number is 1 or greater, the bridge does not recognize the configuration command. in this case, the bridge does not assert devsel and the configuration transaction results in a master abort. the bridge services valid type 0 configuration read or write cycles by accessing internal registers from the configuration header. because type 1 configuration cycles are issued to devices on subordinate buses, the bridge claims type 1 cycles based on the bus number of the destination bus. figure 33 shows the p_ad bus encoding during the address phase of a type 1 cycle. the device number and bus number fields define the destination bus and device for the cycle. reserved register number 31 function number 11 10 7 8 00 10 2 24 bus number 23 16 device number 15 figure 33. pci ad31ad0 during address phase of a type 1 configuration cycle several bridge configuration registers shown in table 41 are significant when decoding and claiming type 1 configuration cycles. the destination bus number encoded on the p_ad bus is compared to the values programmed in the bridge configuration registers 18h, 19h, and 1ah, which are the primary bus number, secondary bus number, and subordinate bus number registers, respectively. these registers default to 00h and are programmed by host software to reflect the bus hierarchy in the system (see figure 34 for an example of a system bus hierarchy and how the pci2250 bus number registers would be programmed in this case). when the pci2250 claims a type 1 configuration cycle that has a bus number equal to its secondary bus number, the pci2250 converts the type 1 configuration cycle to a type 0 configuration cycle and asserts the proper s_ad line as the idsel (see table 32). all other type 1 transactions that access a bus number greater than the bridge secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1 configuration cycles. table 32. pci s_ad31s_ad16 during address phase of a type 0 configuration cycle device number secondary idsel s_ad31s_ad16 s_ad asserted 0h 0000 0000 0000 0001 16 1h 0000 0000 0000 0010 17 2h 0000 0000 0000 0100 18 3h 0000 0000 0000 1000 19 4h 0000 0000 0001 0000 20 5h 0000 0000 0010 0000 21 6h 0000 0000 0100 0000 22 7h 0000 0000 1000 0000 23 8h 0000 0001 0000 0000 24 9h 0000 0010 0000 0000 25 ah 0000 0100 0000 0000 26 bh 0000 1000 0000 0000 27 ch 0001 0000 0000 0000 28 dh 0010 0000 0000 0000 29 eh 0100 0000 0000 0000 30 fh 1000 0000 0000 0000 31 10h1eh 0000 0000 0000 0000
34 pci bus 0 primary bus 00h secondary bus 01h subordinate bus 02h pci2250 primary bus 00h secondary bus 03h subordinate bus 03h pci2250 pci bus 1 pci bus 3 primary bus 01h secondary bus 02h subordinate bus 02h pci2250 pci bus 2 figure 34. bus hierarchy and numbering 3.4 special cycle generation the bridge is designed to generate special cycles on both buses through a type 1 cycle conversion. during a type 1 configuration cycle, if the bus number field matches the bridge secondary bus number, then the device number field is 1fh, the function number field is 07h, and the bridge generates a special cycle on the secondary bus with a message that matches the type 1 configuration cycle data. if the bus number is a subordinate bus and not the secondary bus, then the bridge passes the type 1 special cycle request through to the secondary interface along with the proper message. special cycles are never passed through the bridge. type 1 configuration cycles with a special cycle request can propagate in both directions. 3.5 secondary clocks the pci2250 provides five secondary clock outputs (s_clkout[0:4]). four are provided for clocking secondary devices. the fifth clock should be routed back into the pci2250 s_clk input to ensure all secondary bus devices see the same clock.
35 pci2250 pci device s_clkout3 pci device pci device pci device s_clkout2 s_clkout1 s_clkout0 s_clkout4 s_clk figure 35. secondary clock block diagram 3.6 bus arbitration the pci2250 implements bus request (p_req ) and bus grant (p_gnt ) terminals for primary bus arbitration. four secondary bus requests and four secondary bus grants are provided on the secondary of the pci2250. five potential initiators, including the bridge, can be located on the secondary bus. the pci2250 provides a two-tier arbitration scheme on the secondary bus for priority bus-master handling. the two-tier arbitration scheme improves performance in systems in which master devices do not all require the same bandwidth. any master that requires frequent use of the bus can be programmed to be in the higher priority tier. 3.6.1 primary bus arbitration the pci2250, acting as an initiator on the primary bus, asserts p_req when forwarding transactions upstream to the primary bus. in the upstream direction, as long as a posted write data or a delayed transaction request is in the queue, the pci2250 keeps p_req asserted. if a target disconnect, a target retry, or a target abort is received in response to a transaction initiated on the primary bus by the pci2250, p_req is deasserted for two pci clock cycles. when the primary bus arbiter asserts p_gnt in response to a p_req from the pci2250, the device initiates a transaction on the primary bus during the next pci clock cycle after the primary bus is sampled idle. when p_req is not asserted and the primary bus arbiter asserts p_gnt to the pci2250, the device responds by parking the p_ad31p_ad0 bus, the c/be 3c/be 0 bus, and primary parity (p_par) by driving them to valid logic levels. if the pci2250 is parking the primary bus and wants to initiate a transaction on the bus, then it can start the transaction on the next pci clock by asserting the primary cycle frame (p_frame ) while p_gnt is still asserted. if p_gnt is deasserted, then the bridge must rearbitrate for the bus to initiate a transaction. 3.6.2 internal secondary bus arbitration s_cfn controls the state of the secondary internal arbiter. the internal arbiter can be enabled by pulling s_cfn low or disabled by pulling s_cfn high. the pci2250 provides four secondary bus request terminals and four secondary
36 bus grant terminals. including the bridge, there are a total of five potential secondary bus masters. these request and grant signals are connected to the internal arbiter. when an external arbiter is implemented, s_req3 s_req0 and s_gnt3 s_gnt0 are placed in a high impedance mode. 3.6.3 external secondary bus arbitration an external secondary bus arbiter can be used instead of the pci2250 internal arbiter. when using an external arbiter, the pci2250's internal arbiter should be disabled by pulling s_cfn high. when an external secondary bus arbiter is used, the pci2250 internally reconfigures the s_req0 and s_gnt0 signals so that s_req0 becomes the secondary bus grant for the bridge and s_gnt0 becomes the secondary bus request for the bridge. this is done because s_req0 is an input and can thus be used to provide the grant input to the bridge, and s_gnt0 is an output and can thus provide the request output from the bridge. when an external arbiter is used, all unused secondary bus grant outputs (s_gnt3 s_gnt1 ) are placed in a high impedance mode. any unused secondary bus request inputs (s_req3 s_req1 ) should be pulled high to prevent the inputs from oscillating. 3.7 decode options the pci2250 supports positive, subtractive, and negative decoding but defaults to positive decoding on the primary interface and negative decoding on the secondary bus. positive decoding is a method of address decoding in which a device responds only to accesses within an assigned address range. negative decoding is a method of address decoding in which a device responds only to accesses outside an assigned address range. subtractive decoding is a method of address decoding in which a device responds to accesses not claimed by any other devices on the bus. subtractive decoding can be enabled on the primary bus or the secondary bus. 3.8 extension windows with programmable decoding the pci2250 provides two programmable 32-bit extension windows. each window can be programmed to be a prefetchable memory window, a nonprefetchable memory window, or an i/o window. the ti extension memory windows have a 4k-byte granularity, and the i/o windows have a doubleword granularity. these extension windows can be positively decoded on either the primary bus or secondary bus. the standard pci-to-pci bridge memory and i/o windows specified by the pci-to-pci bridge specification have a 1m-byte and 4k-byte granularity, respectively (see section 4.20, memory base register and section 4.26, i/o base upper 16 bits register ). the ti extension windows provide smaller granularity for memory and i/o windows. the extension windows' granularity matches the requirements of cardbus card windows, which also have 4k-byte granularity for memory windows and doubleword granularity for i/o windows. when a cardbus i/o card is sitting behind the bridge, the smaller doubleword i/o window granularity with the extension windows allows a smaller i/o window than the 4k-byte window with the standard i/o base and limit registers. a common i/o base address for popular sound cards is 300h303h. using the ti extension windows and configuring the base i/o address for 300h establishes a 4-byte i/o address window from 300h303h for communicating with the sound card. using the bridge's standard i/o base register requires a minimum 4k-byte window of memory. the extension windows can be excluded from the primary bus decoding, thus creating a hole in a primary window address range. 3.9 system error handling the pci2250 can be configured to signal a system error (serr ) under a variety of conditions. the p_serr event disable register (offset 64h, see section 5.18) and the p_serr status register (offset 6ah, see section 5.20) provide control and status bits for each condition for which the bridge can signal serr . these individual bits enable serr reporting for both downstream and upstream transactions. by default, the pci2250 will not signal serr . if the pci2250 is configured to signal serr by setting bit 8 of the command register (offset 04h, see section 4.3), then the bridge signals serr if any of the error conditions in the
37 p_serr event disable register occur and that condition is enabled. by default, all error conditions are enabled in the p_serr event disable register. when the bridge signals serr , bit 14 of the secondary status register (offset 1eh, see section 4.19) is set. 3.9.1 posted write parity error if bit 1 in the p_serr event disable register (offset 64h, see section 5.18) is 0, then parity errors on the target bus during a posted write are passed to the initiating bus as an serr . when this occurs, bit 1 of the p_serr status register (offset 6ah, see section 5.20) is set. the status bit is cleared by writing a 1. 3.9.2 posted write timeout if bit 2 in the p_serr event disable register (offset 64h, see section 5.18) is 0 and the retry timer expires while attempting to complete a posted write, then the pci2250 signals serr on the initiating bus. when this occurs, bit 2 of the p_serr status register (offset 6ah, see section 5.20) is set. the status bit is cleared by writing a 1. 3.9.3 target abort on posted writes if bit 3 in the p_serr event disable register (offset 64h, see section 5.18) is 0 and the bridge gets a target abort during a posted write transaction, then the pci2250 signals serr on the initiating bus. when this occurs, bit 3 of the p_serr status register (offset 6ah, see section 5.20) is set. the status bit is cleared by writing a 1. 3.9.4 master abort on posted writes if bit 4 in the p_serr event disable register (offset 64h, see section 5.18) is 0 and a posted write transaction results in a master abort, then the pci2250 signals serr on the initiating bus. when this occurs, bit 4 of the p_serr status register (offset 6ah, see section 5.20) is set. the status bit is cleared by writing a 1. 3.9.5 master delayed write timeout if bit 5 in the p_serr event disable register (offset 64h, see section 5.18) is 0 and the retry timer expires while attempting to complete a delayed write, then the pci2250 signals serr on the initiating bus. when this occurs, bit 5 of the p_serr status register (offset 6ah, see section 5.20) is set. the status bit is cleared by writing a 1. 3.9.6 master delayed read timeout if bit 6 in the p_serr event disable register (offset 64h, see section 5.18) is 0 and the retry timer expires while attempting to complete a delayed read, then the pci2250 signals serr on the initiating bus. when this occurs, bit 6 of the p_serr status register (offset 6ah, see section 5.20) is set. the status bit is cleared by writing a 1. 3.9.7 secondary serr the pci2250 passes serr from the secondary bus to the primary bus if it is enabled for serr response (bit 8 in the command register is 1) and bit 1 in the bridge control register (offset 3eh, see section 4.32) is set. 3.10 parity handling and parity error reporting the pci2250 can be configured to pass parity or provide parity via bit 14 of the diagnostic control register (offset 5ch, see section 5.14). when this bit is cleared to 0, the bridge is enabled for passing parity errors. parity error passing is the default mode in the bridge. the following parity conditions result in the bridge signaling an error. 3.10.1 address parity error if the parity error response bit (bit 6) in the command register (offset 04h, see section 4.3) is set, then the pci2250 signals serr on address parity errors and target abort transactions.
38 3.10.2 data parity error if the parity error response bit (bit 6) in the command register (offset 04h, see section 4.3) is set, then the pci2250 signals perr when it receives bad data. when the bridge detects bad parity, bit 15 (detected parity error) in the status register (offset 06h, see section 4.4) is set. if the bridge is configured to respond to parity errors via bit 6 in the command register, then the data parity error detected bit (bit 8 in the status register) is set when the bridge detects bad parity. the data parity error detected bit is also set when the bridge, as a bus master, asserts perr or detects perr . 3.11 master and target abort handling if the pci2250 receives a target abort during a write burst, then it signals target abort back on the initiator bus. if it receives a target abort during a read burst, then it provides all of the valid data on the initiator bus and disconnects. target aborts for posted and nonposted transactions are reported as specified in the pci-to-pci bridge specification . master aborts for posted and nonposted transactions are reported as specified in the pci-to-pci bridge specification . if a transaction is attempted on the primary bus after a secondary reset is asserted, then the pci2250 follows bit 5 (master abort mode bit setting) in the bridge control register (offset 3eh, see section 4.32) for reporting errors. 3.12 discard timer the pci2250 is free to discard the data or status of a delayed transaction that was completed with a delayed transaction termination when a bus master has not repeated the request within 2 10 or 2 15 pci clocks (approximately 30 m s and 993 m s, respectively). the pci local bus specification recommends that a bridge wait 2 15 pci clocks before discarding the transaction data or status. the pci2250 implements a discard timer for use in delayed transactions. after a delayed transaction is completed on the destination bus, the bridge may discard it under two conditions. the first condition occurs when a read transaction is made to a region of memory that that is inside a defined prefetchable memory region, or when the command is a memory read line or a memory read multiple, implying that the memory region is prefetchable. the other condition occurs when the master originating the transaction (either a read or a write, prefetchable or nonprefetchable) has not retried the transaction within 2 10 or 2 15 clocks. the number of clocks is tracked by a timer referred to as the discard timer. when the discard timer expires, the bridge is required to discard the data. the pci2250 default value for the discard timer is 2 15 clocks; however, this value can be set to 2 10 clocks by setting bit 9 in the bridge control register (offset 3eh, see section 4.32). for more information on the discard timer, see error conditions in pci local bus specification . 3.13 delayed transactions the bridge supports delayed transactions as defined in the pci local bus specification . a target must be able to complete the initial data phase in 16 pci clocks or less from the assertion of the cycle frame (frame ), and subsequent data phases must complete in 8 pci clocks or less. a delayed transaction consists of three phases: ? an initiator device issues a request. ? the target completes the request on the destination bus and signals the completion to the initiator. ? the initiator completes the request on the originating bus. if the bridge is the target of a pci transaction and it must access a slow device to write or read the requested data, and the transaction takes longer than 16 clocks, then the bridge must latch the address, the command, and the byte enables, and then issue a retry to the initiator. the initiator must end the transaction without any transfer of data and is required to retry the transaction later using the same address, command, and byte enables. this is the first phase of the delayed transaction. during the second phase, if the transaction is a read cycle, then the bridge fetches the requested data on the destination bus, stores it internally, and obtains the completion status, thus completing the transaction on the
39 destination bus. if it is a write transaction, then the bridge writes the data and obtains the completion status, thus completing the transaction on the destination bus. the bridge stores the completion status until the master on the initiating bus retries the initial request. during the third phase, the initiator rearbitrates for the bus. when the bridge sees the initiator retry the transaction, it compares the second request to the first request. if the address, command, and byte enables match the values latched in the first request, then the completion status (and data if the request was a read) is transferred to the initiator. at this point, the delayed transaction is complete. if the second request from the initiator does not match the first request exactly, then the bridge issues another retry to the initiator. when bit 2 of the diagnostic control register (offset 5ch, see section 5.14) is 0, the pci2250 is configured for immediate retry mode. in immediate retry mode, the bridge issues a retry immediately, instead of after 16 clocks, on delayed transactions. the pci2250 supports one delayed transaction in each direction at any given time. 3.14 multifunction pins the pci2250 has two multifunction pins that can be configured as lock , clkrun or compact-pci hot-swap enum and switch . the configuration of p_mfunc and s_mfunc is controlled by ms0 and ms1 and is shown in table 33. the pci2250 has two modes of operation: intel-compatible mode and ti mode. in the intel mode, the pci2250 is pin compatible with the intel 21152 bridge. table 33. multifunction pin definitions based on mode select pins ms0 ms1 p_mfunc s_mfunc mode 0 0 hs_enum hs_switch ti hot-swap 0 1 p_clkrun s_clkrun ti clock run 1 bpcc p_lock s_lock intel 3.14.1 compact-pci hot-swap support the pci2250 is hot-swap friendly silicon that supports all the cpci hot-swap capable features, contains support for software control, and integrates circuitry required by the cpci hot-swap specification . to be hot-swap capable, the pci2250 supports the following: ? compliance with pci local bus specification ? tolerance of v cc from early power ? asynchronous reset ? tolerance of precharge voltage ? i/o buffers must meet modified v/i requirements ? limited i/o pin voltage at precharge voltage ? hot-swap control and status programming via extended pci capabilities linked list ? hot-swap terminals: hs_enum , hs_switch , and hs_led. cpci hot-swap defines a process for installing and removing pci boards without adversely affecting a running system. the pci2250 provides this functionality such that it can be implemented on a board that can be removed and inserted in a hot-swap system. the pci2250 provides three terminals to support hot-swap when configured to be in hot-swap mode: hs_enum (output), hs_switch (input), and hs_led (output). the hs_enum output indicates to the system that an insertion event occurred or that a removal event is about to occur. the hs_switch input indicates the state of a board ejector handle, and the hs_led output lights a blue led to signal insertion and removal ready status.
310 3.14.2 pci clock run feature the pci2250 supports the pci clock run protocol when in clock run mode, as defined in the pci mobile design guide . when the system's central resource signals to the system that it wants to stop the pci clock (p_clk) by driving the primary clock run (p_clkrun ) signal high, the bridge either signals that it is ok to stop the pci clock by leaving p_clkrun deasserted (high) or signals to the system to keep the clock running by driving p_clkrun low. the pci2250 clock run control register provides a clock run enable bit for the primary bus and a separate clock run enable bit for the secondary bus. the bridge's p_clkrun and secondary clock run (s_clkrun ) features are enabled by setting bits 3 and 1, respectively, in the clock run control register (offset 5bh, see section 5.13). bit 2 of the clock run control register allows software to enable the bridge's keep clock running mode to prevent the system from stopping the primary pci clock. there are two conditions for restarting the secondary clock: a downstream transaction restarts the secondary clock or s_clkrun is asserted. two clock run modes are supported on the secondary bus. the bridge can be configured to stop the secondary pci clock only in response to a request from the primary bus to stop the clock, or it can be configured to stop the secondary clock whenever the secondary bus is idle and there are no transaction requests from the primary bus, regardless of the primary clock (see section 5.13, clock run control register ). 3.15 pci power management the pci power management interface specification establishes the infrastructure required to let the operating system control the power of pci functions. this is done by defining a standard pci interface and operations to manage the power of pci functions on the bus. the pci bus and the pci functions can be assigned one of four software visible power management states, which result in varying levels of power savings. the four power management states of pci functions are d0efully on state, d1 and d2eintermediate states, and d3eoff state. similarly, bus power states are b0b3. the bus power states b0b3 are derived from the device power state of the originating device. the power state of the secondary bus is derived from the power state of the pci2250. for the operating system to manage the device power states on the pci bus, the pci function supports four power management operations: ? capabilities reporting ? power status reporting ? setting the power state ? system wakeup the operating system identifies the capabilities of the pci function by traversing the new capabilities list. the presence of the new capabilities list is indicated by a bit in the status register (offset 06h, see section 4.4) which provides access to the capabilities list. 3.15.1 behavior in low power states the pci2250 supports d0, d1, d2, and d3 hot power states when in ti mode. the pci2250 only supports d0 and d3 hot power states when in intel mode. the pci2250 is fully functional only in the d0 state. in the lower power states, the bridge does not accept any i/o or memory transactions. these transactions are aborted by the master. the bridge accepts type 0 configuration cycles in all power states. the bridge also accepts type 1 configuration cycles but does not pass these cycles to the secondary bus in any of the low power states. type 1 configuration writes are discarded and reads return all 1s. all error reporting is done in the low power states. when in d2 and d3 hot states, the bridge turns off all secondary clocks for further power savings when in ti mode or if bpcc is pulled high in the intel mode. when going from d3 hot to d0, an internal reset is generated. this reset initializes all pci configuration registers to their default values. all ti extension registers (40hffh) are not reset. the power management registers (offset e0h) are also not reset.
41 4 bridge configuration header the pci2250 bridge is a single-function pci device. the configuration header is in compliance with the pci-to-pci bridge architecture specification . table 41 shows the pci configuration header, which includes the predefined portion of the bridge's configuration space. the pci configuration offset is shown in the right column under the offset heading. table 41. bridge configuration header register name offset device id vendor id 00h status command 04h class code revision id 08h bist header type primary latency timer cache line size 0ch base address register 0 10h base address register 1 14h secondary bus latency timer subordinate bus number secondary bus number primary bus number 18h secondary status i/o limit i/o base 1ch memory limit memory base 20h prefetchable memory limit prefetchable memory base 24h prefetchable base upper 32 bits 28h prefetchable limit upper 32 bits 2ch i/o limit upper 16 bits i/o base upper 16 bits 30h reserved capability pointer 34h expansion rom base address 38h bridge control interrupt pin interrupt line 3ch arbiter control extended diagnostic chip control 40h extension window base 0 44h extension window limit 0 48h extension window base 1 4ch extension window limit 1 50h primary decode control secondary decode control extension window map extension window enable 54h clock run control port decode map buffer control port decode enable 58h diagnostic status diagnostic control 5ch arbiter timeout status arbiter mask control reserved 60h reserved p_serr event disable 64h reserved p_serr status secondary clock control 68h reserved 6chd8h power management capabilities pm next item pointer pm capability id dch data pmcsr bridge support power management control/status e0h reserved hot-swap control status hs next item pointer hs capability id e4h reserved e8hffh
42 a bit description table is typically included that indicates bit field names, a detailed field description, and field access tags. table 42 describes the field access tags. table 42. bit field access tag descriptions access tag name meaning r read field may be read by software. w write field may be written by software to any value. s set field may be set by a write of 1. writes of 0 have no effect. c clear field may be cleared by a write of one. writes of 0 have no effect. u update field may be autonomously updated by pci2040. 4.1 vendor id register this 16-bit value is allocated by the pci special interest group (sig) and identifies ti as the manufacturer of this device. the vendor id assigned to ti is 104ch. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vendor id type r r r r r r r r r r r r r r r r default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 register: vendor id type: read-only offset: 00h default: 104ch 4.2 device id register this 16-bit value is allocated by the vendor and identifies the pci device. the device id for the pci2250 is ac23h. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name device id type r r r r r r r r r r r r r r r r default 1 0 1 0 1 1 0 0 0 0 1 0 0 0 1 1 register: device id type: read-only offset: 02h default: ac23h
43 4.3 command register the command register provides control over the bridge interface to the primary pci bus. vga palette snooping is enabled through this register, and all other bits adhere to the definitions in the pci local bus specification . table 43 describes the bit functions in the command register. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name command type r r r r r r r/w r/w r r/w r/w r r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: command type: read-only, read/write (see individual bit descriptions) offset: 04h default: 0000h table 43. command register bit type function 1510 r reserved. bits 1510 return 0s when read. 9 r/w fast back-to-back enable. the bridge does not generate fast back-to-back transactions on the primary pci bus. bit 9 is read/write, but does not affect the bridge when set. this bit defaults to 0. 8 r/w system error (serr ) enable. bit 8 controls the enable for the serr driver on the primary interface. 0 = disable serr driver on primary interface (default) 1 = enable the serr driver on primary interface 7 r wait cycle control. bit 7 controls address/data stepping by the bridge on both interfaces. the bridge does not support address/data stepping and this bit is hardwired to 0. 6 r/w parity error response enable. bit 6 controls the bridge response to parity errors. 0 = parity error response disabled (default) 1 = parity error response enabled 5 r/w vga palette snoop enable. when set, the bridge passes i/o writes on the primary pci bus with addresses 3c6h, 3c8h, and 3c9h inclusive of isa aliases (i.e., only bits ad9ad0 are included in the decode). 4 r memory write and invalidate enable. in a pci-to-pci bridge, bit 4 must be read-only and return 0 when read. 3 r special cycle enable. a pci-to-pci bridge cannot respond as a target to special cycle transactions, so bit 3 is defined as read-only and must return 0 when read. 2 r/w bus master enable. bit 2 controls the ability of the bridge to initiate a cycle on the primary pci bus. when bit 2 is 0, the br idge does not respond to any memory or i/o transactions on the secondary interface since they cannot be forwarded to the primary pci bus. 0 = bus master capability disabled (default) 1 = bus master capability enabled 1 r/w memory space enable. bit 1 controls the bridge response to memory accesses for both prefetchable and nonprefetchable memory spaces on the primary pci bus. only when bit 1 is set will the bridge forward memory accesses to the secondary bus from a primary bus initiator. 0 = memory space disabled (default) 1 = memory space enabled 0 r/w i/o space enable. bit 0 controls the bridge response to i/o accesses on the primary interface. only when bit 0 is set will the bridge forward i/o accesses to the secondary bus from a primary bus initiator. 0 = i/o space disabled (default) 1 = i/o space enabled
44 4.4 status register the status register provides device information to the host system. this register is read-only. bits in this register are cleared by writing a 1 to the respective bit; writing a 0 to a bit location has no effect. table 44 describes the status register. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name status type r/c/ u r/c/ u r/c/ u r/c/ u r/c/ u r r r/c/ u r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 register: status type: read-only, read/clear/update offset: 06h default: 0210h table 44. status register bit type function 15 r/c/u detected parity error. bit 15 is set when a parity error is detected. 14 r/c/u signaled system error (serr ). bit 14 is set if serr is enabled in the command register (offset 04h, see section 4.3) and the bridge signals a system error (serr). see section 3.9, system error handling . 0 = no serr signaled (default) 1 = signals serr 13 r/c/u received master abort. bit 13 is set when a cycle initiated by the bridge on the primary bus has been terminated by a master abort. 0 = no master abort received (default) 1 = master abort received 12 r/c/u received target abort. bit 12 is set when a cycle initiated by the bridge on the primary bus has been terminated by a target abort. 0 = no target abort received (default) 1 = target abort received 11 r/c/u signaled target abort. bit 11 is set by the bridge when it terminates a transaction on the primary bus with a target abort. 0 = no target abort signaled by the bridge (default) 1 = target abort signaled by the bridge 109 r devsel timing. these read-only bits encode the timing of p_devsel and are hardwired 01b, indicating that the bridge asserts this signal at a medium speed. 01 = hardwired (default) 8 r/c/u data parity error detected. bit 8 is encoded as: 0 = the conditions for setting this bit have not been met. no parity error detected. (default) 1 = a data parity error occurred and the following conditions were met: a. p_perr was asserted by any pci device including the bridge. b. the bridge was the bus master during the data parity error. c. bit 6 (parity error response enable) is set in the command register (offset 04h, see section 4.3). 7 r fast back-to-back capable. the bridge does not support fast back-to-back transactions as a target; therefore, bit 7 is hardwired to 0. 6 r user-definable feature (udf) support. the pci2250 does not support the user-definable features; therefore, bit 6 is hardwired to 0. 5 r 66-mhz capable. the pci2250 operates at a maximum p_clk frequency of 33 mhz; therefore, bit 5 is hardwired to 0. 4 r capabilities list. bit 4 is read-only and is hardwired to 1, indicating that capabilities additional to standard pci are implemented. the linked list of pci power management capabilities is implemented by this function. 30 r reserved. bits 30 return 0s when read.
45 4.5 revision id register the revision id register indicates the silicon revision of the pci2250. bit 7 6 5 4 3 2 1 0 name revision id type r r r r r r r r default 0 0 0 0 0 0 0 1 register: revision id type: read-only offset: 08h default: 01h (reflects the current revision of the silicon) 4.6 class code register this register categorizes the pci2250 as a pci-to-pci bridge device (0604h) with a 01h or 00h programming interface. bit 0 is read-only but its value is aliased with bit 0 of the primary decode control register (offset 57h, see section 5.9). bit 0 of the primary decode control register defaults to 1b which means the primary interface is set for subtractive decode. if software writes a 0 to bit 0 of the primary decode control register, then this value is aliased to bit 0 of the class code register and the bridge will positively decode the primary interface. bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name class code base class sub class programming interface type r r r r r r r r r r r r r r r r r r r r r r r r default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 register: class code type: read-only offset: 09h default: 060401h 4.7 cache line size register the cache line size register is programmed by host software to indicate the system cache line size needed by the bridge on memory read line and memory read multiple transactions. bit 7 6 5 4 3 2 1 0 name cache line size type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cache line size type: read/write offset: 0ch default: 00h
46 4.8 primary latency timer register the latency timer register specifies the latency timer for the bridge in units of pci clock cycles. when the bridge is a primary pci bus initiator and asserts p_frame , the latency timer begins counting from 0. if the latency timer expires before the bridge transaction has terminated, then the bridge terminates the transaction when its p_gnt is deasserted. bit 7 6 5 4 3 2 1 0 name latency timer type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: latency timer type: read/write offset: 0dh default: 00h 4.9 header type register the header type register is read-only and returns 01h when read, indicating that the pci2250 configuration space adheres to the pci-to-pci bridge configuration. only the layout for bytes 10h3fh of configuration space is considered. bit 7 6 5 4 3 2 1 0 name header type type r r r r r r r r default 0 0 0 0 0 0 0 1 register: header type type: read-only offset: 0eh default: 01h 4.10 bist register the pci2250 does not support built-in self test (bist). the bist register is read-only and returns the value 00h when read. bit 7 6 5 4 3 2 1 0 name bist type r r r r r r r r default 0 0 0 0 0 0 0 0 register: bist type: read-only offset: 0fh default: 00h
47 4.11 base address register 0 the bridge requires no additional resources. base address register 0 is read-only and returns 0s when read. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name base address register 0 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base address register 0 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: base address register 0 type: read-only offset: 10h default: 0000 0000h 4.12 base address register 1 the bridge requires no additional resources. base address register 1 is read-only and returns 0s when read. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name base address register 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name base address register 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: base address register 1 type: read-only offset: 14h default: 0000 0000h 4.13 primary bus number register the primary bus number register indicates the primary bus number to which the bridge is connected. the bridge uses this register, in conjunction with the secondary bus number and subordinate bus number registers, to determine when to forward pci configuration cycles to the secondary buses. bit 7 6 5 4 3 2 1 0 name primary bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: primary bus number type: read/write offset: 18h default: 00h
48 4.14 secondary bus number register the secondary bus number register indicates the secondary bus number to which the bridge is connected. the pci2250 uses this register, in conjunction with the primary bus number and subordinate bus number registers, to determine when to forward pci configuration cycles to the secondary buses. configuration cycles directed to the secondary bus are converted to type 0 configuration cycles. bit 7 6 5 4 3 2 1 0 name secondary bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: secondary bus number type: read/write offset: 19h default: 00h 4.15 subordinate bus number register the subordinate bus number register indicates the bus number of the highest numbered bus beyond the primary bus existing behind the bridge. the pci2250 uses this register, in conjunction with the primary bus number and secondary bus number registers, to determine when to forward pci configuration cycles to the subordinate buses. configuration cycles directed to a subordinate bus (not the secondary bus) remain type 1 cycles as the cycle crosses the bridge. bit 7 6 5 4 3 2 1 0 name subordinate bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: subordinate bus number type: read/write offset: 1ah default: 00h 4.16 secondary bus latency timer register the secondary bus latency timer specifies the latency timer for the bridge in units of pci clock cycles. when the bridge is a secondary pci bus initiator and asserts s_frame , the latency timer begins counting from 0. if the latency timer expires before the bridge transaction has terminated, then the bridge terminates the transaction when its s_gnt is deasserted. the pci-to-pci bridge s_gnt is an internal signal and is removed when another secondary bus master arbitrates for the bus. bit 7 6 5 4 3 2 1 0 name secondary bus latency timer type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: secondary bus latency timer type: read/write offset: 1bh default: 00h
49 4.17 i/o base register the i/o base register is used in decoding i/o addresses to pass through the bridge. the bridge supports 32-bit i/o addressing; thus, bits 30 are read-only and default to 0001b. the upper four bits are writable and correspond to address bits ad15ad12. the lower 12 address bits of the i/o base address are considered 0. thus, the bottom of the defined i/o address range is aligned on a 4k-byte boundary. the upper 16 address bits of the 32-bit i/o base address corresponds to the contents of the i/o base upper 16 bits register (offset 30h, see section 4.26). bit 7 6 5 4 3 2 1 0 name i/o base type r/w r/w r/w r/w r r r r default 0 0 0 0 0 0 0 1 register: i/o base type: read-only, read/write offset: 1ch default: 01h 4.18 i/o limit register the i/o limit register is used in decoding i/o addresses to pass through the bridge. the bridge supports 32-bit i/o addressing; thus, bits 30 are read-only and default to 0001b. the upper four bits are writable and correspond to address bits ad15ad12. the lower 12 address bits of the i/o limit address are considered fffh. thus, the top of the defined i/o address range is aligned on a 4k-byte boundary. the upper 16 address bits of the 32-bit i/o limit address corresponds to the contents of the i/o limit upper 16 bits register (offset 32h, see section 4.27). bit 7 6 5 4 3 2 1 0 name i/o limit type r/w r/w r/w r/w r r r r default 0 0 0 0 0 0 0 1 register: i/o limit type: read-only, read/write offset: 1dh default: 01h
410 4.19 secondary status register the secondary status register is similar in function to the status register (offset 06h, see section 4.4); however, its bits reflect status conditions of the secondary interface. bits in this register are cleared by writing a 1 to the respective bit. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name secondary status type r/c/ u r/c/ u r/c/ u r/c/ u r/c/ u r r r/c/ u r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 register: secondary status type: read-only, read/clear/update offset: 1eh default: 0200h table 45. secondary status register bit type function 15 r/c/u detected parity error. bit 15 is set when a parity error is detected on the secondary interface. 0 = no parity error detected on the secondary bus (default) 1 = parity error detected on the secondary bus 14 r/c/u received system error. bit 14 is set when the secondary interface detects s_serr asserted. note that the bridge never asserts s_serr . 0 = no s_serr detected on the secondary bus (default) 1 = s_serr detected on the secondary bus 13 r/c/u received master abort. bit 13 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a master abort. 0 = no master abort received (default) 1 = bridge master aborted the cycle 12 r/c/u received target abort. bit 12 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a target abort. 0 = no target abort received (default) 1 = bridge received a target abort 11 r/c/u signaled target abort. bit 11 is set by the bridge when it terminates a transaction on the secondary bus with a target abort. 0 = no target abort signaled (default) 1 = bridge signaled a target abort 109 r devsel timing. bits 10 and 9 encode the timing of s_devsel and are hardwired to 01b, indicating that the bridge asserts this signal at a medium speed. 8 r/c/u data parity error detected. 0 = the conditions for setting this bit have not been met 1 = a data parity error occurred and the following conditions were met: a. s_perr was asserted by any pci device including the bridge. b. the bridge was the bus master during the data parity error. c. the parity error response bit (bit 0) is set in the bridge control register (offset 3eh, se section 4.32). 7 r fast back-to-back capable. bit 7 is hardwired to 0. 6 r user-definable feature (udf) support. bit 6 is hardwired to 0. 5 r 66-mhz capable. bit 5 is hardwired to 0. 40 r reserved. bits 40 return 0s when read.
411 4.20 memory base register the memory base register defines the base address of a memory-mapped i/o address range used by the bridge to determine when to forward memory transactions from one interface to the other. the upper 12 bits of this register are read/write and correspond to the address bits ad31ad20. the lower 20 address bits are considered 0s; thus, the address range is aligned to a 1m-byte boundary. the bottom four bits are read-only and return 0s when read. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory base type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory base type: read-only, read/write offset: 20h default: 0000h 4.21 memory limit register the memory limit register defines the upper-limit address of a memory-mapped i/o address range used to determine when to forward memory transactions from one interface to the other. the upper 12 bits of this register are read/write and correspond to the address bits ad31ad20. the lower 20 address bits are considered 1s; thus, the address range is aligned to a 1m-byte boundary. the bottom four bits are read-only and return 0s when read. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory limit type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory limit type: read-only, read/write offset: 22h default: 0000h 4.22 prefetchable memory base register the prefetchable memory base register defines the base address of a prefetchable memory address range used by the bridge to determine when to forward memory transactions from one interface to the other. the upper 12 bits of this register are read/write and correspond to the address bits ad31ad20. the lower 20 address bits are considered 0; thus, the address range is aligned to a 1m-byte boundary. the bottom four bits are read-only and return 0s when read. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prefetchable memory base type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: prefetchable memory base type: read-only, read/write offset: 24h default: 0000h
412 4.23 prefetchable memory limit register the prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used to determine when to forward memory transactions from one interface to the other. the upper 12 bits of this register are read/write and correspond to the address bits ad31ad20. the lower 20 address bits are considered 1s; thus, the address range is aligned to a 1m-byte boundary. the bottom four bits are read-only and return 0s when read. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prefetchable memory limit type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: prefetchable memory limit type: read-only, read/write offset: 26h default: 0000h 4.24 prefetchable base upper 32 bits register the pci2250 does not support 64-bit addressing; thus, the prefetchable base upper 32-bit register is read-only and returns 0s when read. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name prefetchable base upper 32 bits type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prefetchable base upper 32 bits type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: prefetchable base upper 32 bits type: read-only offset: 28h default: 0000 0000h 4.25 prefetchable limit upper 32 bits register the pci2250 does not support 64-bit addressing; thus the prefetchable limit upper 32-bit register is read-only and returns 0s when read. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name prefetchable limit upper 32 bits type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name prefetchable limit upper 32 bits type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: prefetchable limit upper 32 bits type: read-only offset: 2ch default: 0000 0000h
413 4.26 i/o base upper 16 bits register the i/o base upper 16 bits register specifies the upper 16 bits corresponding to ad31ad16 of the 32-bit address that specifies the base of the i/o range to forward from the primary pci bus to the secondary pci bus. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o base upper 16 bits type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o base upper 16 bits type: read/write offset: 30h default: 0000h 4.27 i/o limit upper 16 bits register the i/o limit upper 16-bits register specifies the upper 16 bits corresponding to ad31ad16 of the 32-bit address that specifies the upper limit of the i/o range to forward from the primary pci bus to the secondary pci bus. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o limit upper 16 bits type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o limit upper 16 bits type: read/write offset: 32h default: 0000h 4.28 capability pointer register the capability pointer register provides the pointer to the pci configuration header where the pci power management register block resides. the capability pointer provides access to the first item in the linked list of capabilities. the capability pointer register is read-only and returns dch when read, indicating the power management registers are located at pci header offset dch. bit 7 6 5 4 3 2 1 0 name capability pointer register type r r r r r r r r default 1 1 0 1 1 1 0 0 register: capability pointer type: read-only offset: 34h default: dch
414 4.29 expansion rom base address register the pci2250 does not implement the expansion rom remapping feature. the expansion rom base address register returns all 0s when read. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name expansion rom base address type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name expansion rom base address type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: expansion rom base address type: read-only offset: 38h default: 0000 0000h 4.30 interrupt line register the interrupt line register is read/write and is used to communicate interrupt line routing information. since the bridge does not implement an interrupt signal terminal, this register defaults to ffh. bit 7 6 5 4 3 2 1 0 name interrupt line type r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 register: interrupt line type: read/write offset: 3ch default: ffh 4.31 interrupt pin register the bridge default state does not implement any interrupt terminals. reads from bits 70 of this register return 0s. bit 7 6 5 4 3 2 1 0 name interrupt pin type r r r r r r r r default 0 0 0 0 0 0 0 0 register: interrupt pin type: read-only offset: 3dh default: 00h
415 4.32 bridge control register the bridge control register provides many of the same controls for the secondary interface that are provided by the command register (offset 04h, see section 4.3) for the primary interface. some bits affect the operation of both interfaces. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bridge control type r r r r r/w rcu r/w r/w r r/w r/w r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: bridge control type: read-only, read/write (see individual bit descriptions) offset: 3eh default: 0000h table 46. bridge control register bit type function 1512 r reserved. bits 1512 return 0s when read. 11 r/w discard timer serr enable. 0 = serr signaling disabled for primary discard timeouts (default) 1 = serr signaling enabled for primary discard timeouts 10 rcu discard timer status. once set, this bit must be cleared by writing 1 to this bit. 0 = no discard timer error (default) 1 = discard timer error. either primary or secondary discard timer expired and a delayed transaction was discarded from the queue in the bridge. 9 r/w secondary discard timer. selects the number of pci clocks that the bridge will wait for a master on the secondary interface to repeat a delayed transaction request. 0 = secondary discard timer counts 2 15 pci clock cycles (default) 1 = secondary discard timer counts 2 10 pci clock cycles 8 r/w primary discard timer. selects the number of pci clocks that the bridge will wait for a master on the primary interface to repeat a delayed transaction request. 0 = the primary discard timer counts 2 15 pci clock cycles (default) 1 = the primary discard timer counts 2 10 pci clock cycles 7 r fast back-to-back capable. the bridge never generates fast back-to-back transactions to different secondary devices. bit 7 returns 0 when read. 6 r/w secondary bus reset. when bit 6 is set, the secondary reset signal (s_rst ) is asserted. s_rst is deasserted by resetting this bit. bit 6 is encoded as: 0 = do not force the assertion of s_rst (default). 1 = force the assertion of s_rst . 5 r/w master abort mode. bit 5 controls how the bridge responds to a master abort that occurs on either interface when the bridge is the master. if this bit is set and the posted write transaction has completed on the requesting interface, and serr enable (bit 8) of the command register (offset 04h, see section 4.3) is 1, then p_serr is asserted when a master abort occurs. if the transaction has not completed, then a target abort is signaled. if the bit is cleared, then all 1s are returned on reads and write data is accepted and discarded when a transaction that crosses the bridge is terminated with master abort. the default state of bit 5 after a reset is 0. 0 = do not report master aborts (return ffff ffffh on reads and discard data on writes) (default). 1 = report master aborts by signaling target abort if possible, or if serr is enabled via bit 1 of this register, by asserting serr . 4 r reserved. bit 4 returns 0 when read. 3 r/w vga enable. when bit 3 is set, the bridge positively decodes and forwards vga-compatible memory addresses in the video frame buffer range 000a 0000h000b ffffh, i/o addresses in the range 03b0h03bbh, and 03c003dfh from the primary to the secondary interface, independent of the i/o and memory address ranges. when this bit is set, the bridge blocks forwarding of these addresses from the secondary to the primary. reset clears this bit. bit 3 is encoded as: 0 = do not forward vga-compatible memory and i/o addresses from the primary to the secondary interface (default). 1 = forward vga-compatible memory and i/o addresses from the primary to the secondary, independent of the i/o and memory address ranges and independent of the isa enable bit.
416 table 46. bridge control register (continued0) bit type function 2 r/w isa enable. when bit 2 is set, the bridge blocks the forwarding of isa i/o transactions from the primary to the secondary, addressing the last 768 bytes in each 1k-byte block. this applies only to the addresses (defined by the i/o window registers) that are located in the first 64k bytes of pci i/o address space. from the secondary to the primary, i/o transactions are forwarded if they address the last 768 bytes in each 1k-byte block in the address range specified in the i/o window registers. bit 2 is encoded as: 0 = forward all i/o addresses in the address range defined by the i/o base and i/o limit registers (default). 1 = block forwarding of isa i/o addresses in the address range defined by the i/o base and i/o limit registers when these i/o addresses are in the first 64k bytes of pci i/o address space and address the top 768 bytes of each 1k-byte block. 1 r/w serr enable. bit 1 controls the forwarding of secondary interface serr assertions to the primary interface. only when this bit is set will the bridge forward s_serr to the primary bus signal p_serr . for the primary interface to assert serr , bit 8 of the command register (offset 04h, see section 4.3) must be set. 0 = serr disabled (default) 1 = serr enabled 0 r/w parity error response enable. bit 0 controls the bridge response to parity errors on the secondary interface. when this bit is set, the bridge asserts s_perr to report parity errors on the secondary interface. 0 = ignore address and parity errors on the secondary interface (default). 1 = enable parity error reporting and detection on the secondary interface.
51 5 extension registers the ti extension registers are those registers that lie outside the standard pci-to-pci bridge device configuration space (i.e., registers 40hffh in pci configuration space in the pci2250). these registers can be accessed through configuration reads and writes. the ti extension registers add flexibility and performance benefits to the standard pci-to-pci bridge. the ti extension registers are not reset on the transition from d3 to d0. 5.1 chip control register the chip control register is read/write and has a default value of 00h. this register is used to control the functionality of certain pci transactions. see table 51 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name chip control type r r r r/w r r r/w r default 0 0 0 0 0 0 0 0 register: chip control type: read/write, readonly offset: 40h default: 00h table 51. chip control register bit type function 75 r reserved. bits 75 return 0s when read. 4 r/w memory read prefetch. when cleared, bit 4 enables the memory read prefetch. 0 = upstream memory reads are enabled (default) 1 = upstream memory reads are disabled 32 r reserved. bits 3 and 2 return 0s when read. 1 r/w reserved 0 r reserved. bit 0 returns 0 when read.
52 5.2 extended diagnostic register the extended diagnostic register is read or write and has a default value of 00h. bit 0 of this register is used to reset both the pci2250 and the secondary bus. bit 7 6 5 4 3 2 1 0 name extended diagnostic type r r r r r r r w default 0 0 0 0 0 0 0 0 register: extended diagnostic type: read-only, write-only offset: 41h default: 00h table 52. extended diagnostic register bit type function 71 r reserved. bits 71 return 0s when read. 0 w writing a 1 to this bit causes the pci2250 to set bit 6 of the bridge control register (offset 3eh, see section 4.32) and then internally reset the pci2250. bit 6 of the bridge control register will not be reset by the internal reset. bit 0 is self-clear ing.
53 5.3 arbiter control register the arbiter control register is used for the bridge's internal arbiter. the arbitration scheme used is a two-tier rotational arbitration. the pci2250 bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name arbiter control type r r r r r r r/w r r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 register: arbiter control type: read-only, read/write offset: 42h default: 0200h table 53. arbiter control register bit type function 1510 r reserved. bits 1510 return 0s when read. 9 r/w bridge tier select. this bit determines in which tier the bridge is placed in the two-tier arbitration scheme. 0 = lowest priority tier 1 = highest priority tier (default) 84 r reserved. bits 84 return 0s when read. 3 r/w gnt3 tier select. this bit determines in which tier the s_gnt3 is placed in the arbitration scheme. this bit is encoded as: 0 = lowest priority tier (default) 1 = highest priority tier 2 r/w gnt2 tier select. this bit determines in which tier the s_gnt2 is placed in the arbitration scheme. this bit is encoded as: 0 = lowest priority tier (default) 1 = highest priority tier 1 r/w gnt1 tier select. this bit determines in which tier the s_gnt1 is placed in the arbitration scheme. this bit is encoded as: 0 = lowest priority tier (default) 1 = highest priority tier 0 r/w gnt0 tier select. this bit determines in which tier the s_gnt0 is placed in the arbitration scheme. this bit is encoded as: 0 = lowest priority tier (default) 1 = highest priority tier
54 5.4 extension window base 0, 1 registers the bridge supports two extension windows that define an address range decoded as described in the window enable register and window map register. the extension window base registers define the 32-bit base address of the window. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name extension window base 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name extension window base 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: extension window base 0, 1 type: read-only, read/write offset: 44h, 4ch default: 0000 0000h 5.5 extension window limit 0, 1 registers the bridge supports two extension windows. each window defines an address range that is decoded as described in the window enable register and window map register. the extension window limit registers define the 32-bit limit address of the window. bits 0 and 1 of this register determine whether the extension window is a prefetchable memory window, a nonprefetchable window, or an i/o window. these bits are encoded as: 00 = nonprefetchable memory 01 = prefetchable memory 1x = i/o memory windows have a 4kbyte granularity and i/o windows have a doubleword (4-byte) granularity. when a memory window is selected, bits 112 have no effect and are assumed to be 1s for the limit register and 0s for the base register. this is consistent with the 4k-byte granularity of the memory windows. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name extension window limit 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name extension window limit 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: extension window limit 0, 1 type: read/write offset: 48h, 50h default: 0000 0000h
55 5.6 extension window enable register the decode of the extension windows is enabled through bits 0 and 1 of this register. see table 54 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name extension window enable type r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 register: extension window enable type: read-only, read/write offset: 54h default: 00h table 54. extension window enable register bit type function 72 r reserved. bits 72 return 0s when read. 1 r/w extension window 1 interface enable 0 = disable window 1 (default) 1 = enable window 1 0 r/w extension window 0 interface enable 0 = disable window 0 (default) 1 = enable window 0 5.7 extension window map register the inclusion or exclusion of the extension windows on the primary interface is selected through bits 0 and 1 of this register. the bit descriptions discuss the decode in reference to the primary interface. the secondary interface is the negative decode of the primary interface. regions excluded on the primary interface can be positively decoded on the secondary interface if negative decoding is disabled on the secondary interface. see table 55 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name extension window map type r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 register: extension window map type: read-only, read/write offset: 55h default: 00h table 55. extension window map register bit type function 72 r reserved. bits 72 return 0s when read. 1 r/w extension window 1 interface include/exclude 0 = extension window 1 included in primary interface decode (default) 1 = extension window 1 excluded in primary interface decode 0 r/w extension window 0 interface include/exclude 0 = extension window 0 included in primary interface decode (default) 1 = extension window 0 excluded in primary interface decode
56 5.8 secondary decode control register the secondary decode control register is used to enable/disable the secondary-bus negative decoding. only through this register can an extension window be defined for positive decoding or excluded from negative decoding from the secondary bus to the primary bus. the window interface bits in the window control registers must be set for the extension window definitions in this register to have meaning. bit 7 6 5 4 3 2 1 0 name secondary decode control type r r r r r r/w r/w r/w default 0 0 0 0 0 1 1 0 register: secondary decode control type: read-only, read/write offset: 56h default: 06h table 56. secondary decode control register bit type function 73 r reserved. bits 73 return 0s when read. 2 r/w secondary-bus subtractive decode speed. the bridge defaults to subtractive decoding after slow decode speed (four clocks after frame is asserted). bit 0 must be set to enable subtractive decoding. when bit 0 and this bit are set, subtractive decoding is enabled at slow decode speed. this bit is encoded as: 0 = selects normal subtractive decode speed. 1 = selects subtractive decode in the slow decode time slot (default). 1 r/w secondary bus negative decode enable. the bridge defaults to negative decoding on the secondary pci bus. all transactions that do not fall into windows positively decoded from the primary to the secondary are passed through to the primary bus. this bit is encoded as: 0 = disable secondary-bus negative decoding. 1 = enable secondary-bus negative decoding (default). 0 r/w secondary-bus subtractive decode enable. the bridge defaults to negative decoding on the secondary pci bus. when bit 0 is set, the bridge uses subtractive decoding on the secondary bus. when the bridge is using negative decoding on the secondary, all transactions not claimed by a slow device on the secondary bus are passed through the bridge to the primary bus. this bit is encoded as: 0 = disable secondary bus subtractive decoding (default). 1 = enable secondary bus subtractive decoding.
57 5.9 primary decode control register this register is used to enable and disable the primary bus subtractive decoding and to select the primary bus subtractive decode speed. the bridge defaults to primary bus subtractive decoding enabled (bit 0 is set to 1b). bit 0 of this register is aliased to bit 0 of the class code register (offset 09h, see section 4.6) so that the class code register reflects whether or not subtractive decoding is enabled on the primary interface. see table 57 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name primary decode control type r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 register: primary decode control type: read-only, read/write offset: 57h default: 00h table 57. primary decode control register bit type function 72 r reserved. bits 72 return 0s when read. 1 r/w primary-bus subtractive decode speed. the bridge defaults to subtractive decoding after slow decode speed (four clocks after frame is asserted). bit 0 must be set to enable subtractive decoding. when bit 0 and this bit are set, subtractive decoding is enabled at slow decode speed. this bit is encoded as: 0 = selects normal subtractive decode speed on primary bus (default) 1 = selects subtractive decode in the slow decode time slot on the primary bus 0 r/w primary-bus subtractive decode enable. the bridge defaults to subtractive decoding disabled from the primary to secondary pci bus. each pci bus may only have one subtractive decode device. 0 = disable primary bus subtractive decoding 1 = enable primary bus subtractive decoding (default)
58 5.10 port decode enable register the port decode enable register is used to select which serial and parallel port addresses are positively decoded from the bridge primary bus to the secondary bus. see table 58 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name port decode enable type r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: port decode enable type: read-only, read/write offset: 58h default: 00h table 58. port decode enable register bit type function 7 r reserved. bit 7 returns 0 when read. 6 r/w lpt3 enable. when bit 6 is set, the address ranges 278h27fh and 678h67bh are positively decoded and the cycles passed to the secondary bus based on the setting of bit 6 of the port decode map register (offset 5ah, see section 5.12). 5 r/w lpt2 enable. when bit 5 is set, the address ranges 378h37fh and 778h77bh are positively decoded and the cycles passed to the secondary bus based on the setting of bit 5 of the port decode map register (offset 5ah, see section 5.12). 4 r/w lpt1 enable. when bit 4 is set, the address ranges 3bch3bfh and 7bch7bfh are positively decoded and the cycles passed to the secondary bus based on the setting of bit 4 of the port decode map register (offset 5ah, see section 5.12). 3 r/w com4 enable. when bit 3 is set, the address range 2e8h2efh is positively decoded and the cycles passed to the secondary bus based on the setting of bit 3 of the port decode map register (offset 5ah, see section 5.12). 2 r/w com3 enable. when bit 2 is set, the address range 3e8h3efh is positively decoded and the cycles passed to the secondary bus based on the setting of bit 2 of the port decode map register (offset 5ah, see section 5.12). 1 r/w com2 enable. when bit 1 is set, the address range 2f8h2ffh is positively decoded and the cycles passed to the secondary bus based on the setting of bit 1 of the port decode map register (offset 5ah, see section 5.12). 0 r/w com1 enable. when bit 0 is set, the address range 3f8h3ffh is positively decoded and the cycles passed to the secondary bus based on the setting of bit 0 of the port decode map register (offset 5ah, see section 5.12).
59 5.11 buffer control register the buffer control register allows software to enable/disable write posting and control memory read burst prefetching. the buffer control register also enables/disables the posted memory write reconnect feature. see table 59 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name buffer control type r r r r/w r r/w r/w r/w default 0 0 0 0 0 1 1 1 register: buffer control type: read-only, read/write offset: 59h default: 07h table 59. buffer control register bit type function 75 r reserved. bits 7 through 5 return 0s when read. 4 r/w upstream mrm/mrl read burst enable. by default, the pci2250 is set to memory read burst a single cache line. by setting this bit to 1, the pci2250 will memory read burst multiple cache lines or until the fifo is full. to utilize this feature, bit 4 of the chip control register (offset 40h, see section 5.1) must be set to 0. 0 = disabled (default) 1 = enabled 3 r reserved. bit 3 returns 0 when read. 2 r/w downstream memory read burst enable. the bridge defaults to downstream memory read bursting enabled. bit 2 enables downstream memory read bursting in prefetchable windows. this bit is encoded as: 0 = disabled 1 = enabled (default) 1 r/w secondary-to-primary write posting enable. enables posting of write data to and from the primary interface. if bit 1 is not set, the bridge must drain any data in its buffers before accepting data to or from the primary interface. each data word must then be accepted by the target before the bridge can accept the next word from the source master. the bridge must not release the source master until the last word is accepted by the target. operating with the write posting enabled enhances system performance. 0 = write posting disabled 1 = write posting enabled (default) 0 r/w primary-to-secondary write posting enable. enables posting of write data to and from the secondary interface. if bit 0 is not set, then the bridge must drain any data in its buffers before accepting data to or from the secondary interface. each data word must then be accepted by the target before the bridge can accept the next word from the source master. the bridge must not release the source master until the last word is accepted by the target. operating with the write posting enabled enhances system performance. 0 = write posting disabled 1 = write posting enabled (default)
510 5.12 port decode map register the port decode map register is used to select whether the serial- and parallel-port address ranges positively decoded from the primary bridge interface to the secondary interface are included or excluded from the primary interface. for example, if bit 0 is set, then addresses in the range of 3f8h3ffh are positively decoded on the primary bus. if bit 0 is cleared and an i/o window is enabled that covers the range from 3f8h3ffh, then these addresses are not claimed by the bridge. see table 510 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name port decode map type r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: port decode map type: read-only, read/write offset: 5ah default: 00h table 510. port decode map register bit type function 7 r reserved. bit 7 returns 0 when read. 6 r/w lpt3 include/exclude. bit 6 is encoded as: 0 = 278h27fh and 678h67bh excluded from the primary bus (default) 1 = 278h27fh and 678h67bh positively decoded on the primary bus 5 r/w lpt2 include/exclude. bit 5 is encoded as: 0 = 378h37fh and 778h77bh excluded from the primary bus (default) 1 = 378h37fh and 778h77bh positively decoded on the primary bus 4 r/w lpt1 include/exclude. bit 4 is encoded as: 0 = 3bch3bfh and 7bch7bfh excluded from the primary bus (default) 1 = 3bch3bfh and 7bch7bfh positively decoded on the primary bus 3 r/w com4 include/exclude. bit 3 is encoded as: 0 = 2e8h2efh excluded from the primary bus (default) 1 = 2e8h2efh positively decoded on the primary bus 2 r/w com3 include/exclude. bit 2 is encoded as: 0 = 3e8h3efh excluded from the primary bus (default) 1 = 3e8h3efh positively decoded on the primary bus 1 r/w com2 include/exclude. bit 1 is encoded as: 0 = 2f8h2ffh excluded from the primary bus (default) 1 = 2f8h2ffh positively decoded on the primary bus 0 r/w com1 include/exclude. bit 0 is encoded as: 0 = 3f8h3ffh excluded from the primary bus (default) 1 = 3f8h3ffh positively decoded on the primary bus
511 5.13 clock run control register the clock run control register controls the pci clock-run mode enable/disable. it is also used to enable the keep-clock-running feature. bit 0 reflects the status of the secondary clock. there are two clock run modes supported on the secondary bus. the bridge can be configured to stop the secondary pci clock only in response to a request from the primary bus to stop the clock or it can be configured to stop the secondary clock whenever the secondary bus is idle and there are no transaction requests from the primary bus. there are two conditions for restarting the secondary clock. a downstream transaction restarts the secondary clock, or if the s_clkrun signal is asserted, the secondary clock is restarted. see table 511 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name clock run control type r r r r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 register: clock run control type: read-only, read/write offset: 5bh default: 00h table 511. clock run control register bit type function 75 r reserved. bits 75 return 0s when read. 4 r/w clock run mode. bit 4 is encoded as: 0 = stop the secondary clock only on request from the primary bus (default). 1 = stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus. 3 r/w primary clock run enable. bit 3 must be enabled for the bridge to respond to requests by the central resource on the primary bus to stop the clock. 0 = disable clock run (default) 1 = enable clock run 2 r/w primary keep clock. when bit 2 is set, it causes the bridge to request that the central resource keep the pci clock running. 0 = allow primary clock to stop if secondary clock stopped (default) 1 = always keep primary clock running 1 r/w secondary clock run enable 0 = disable clock run for secondary (default) 1 = enable clock run for secondary 0 r secondary clock status bit. if the clock is stopped, this bit is 1. if the clock is running, this bit is 0. 0 = secondary clock not stopped (default) 1 = secondary clock stopped 5.14 diagnostic control register the diagnostic control register is used for bridge diagnostics. see table 512 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name diagnostic control type r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 register: diagnostic control type: read/write, read-only offset: 5ch5dh default: 1040h
512 table 512. diagnostic control register bit type function 15 r/w arbiter performance enhancement feature. when enabled, this feature provides automatic tier operation for bus masters that have been retried or that have pending delayed transactions. in this case, the bus master gets promoted to the highest priority tier. 0 = disabled (default) 1 = enabled 14 r/w parity mode. bit 14 is encoded as: 0 = parity error passing enabled (default) 1 = parity error passing disabled 13 r/w upstream lock enable. the bridge default is to disable upstream lock. when set, bit 13 enables upstream resource locking. this bit is encoded as: 0 = selects upstream lock disabled (default) 1 = selects upstream lock enabled 12 r/w downstream lock enable. the bridge default is to enable downstream lock. when set, bit 12 enables downstream resource locking. this bit is encoded as: 0 = selects downstream lock disabled 1 = selects downstream lock enabled (default) 11 r/w secondary-bus decode speed. the bridge defaults to medium decode speed on the secondary bus. bit 11 selects between medium and slow decode speed. this bit is encoded as: 0 = secondary bus decodes at medium decode speed (default) 1 = secondary bus decodes at slow decode speed 10 r/w primary-bus decode speed. the bridge defaults to medium decode speed on the primary bus. bit 10 selects between medium and slow decode speed. this bit is encoded as: 0 = primary bus decodes at medium decode speed (default) 1 = primary bus decodes at slow decode speed 98 r reserved. bits 9 and 8 return 0s when read. 7 r/w arbiter timeout. when set, bit 0 enables serr reporting when the arbiter timer expires (times out). 0 = serr on arbiter timeout disabled (default) 1 = serr on arbiter timeout enabled 6 r/w transaction ordering enable 0 = disabled 1 = enabled (default) 5 r/w secondary initial data phase counter extension 0 = normal 16 clock to initial data phase (default) 1 = extends initial data phase to 64 clocks 4 r/w primary initial data phase counter disable 0 = enable 16 clocks initial data phase counter (default) 1 = disable 16 clock initial data phase counter note: the secondary initial data phase counter is always enabled. 3 r/w primary initial data phase counter extension 0 = normal 16 clocks to initial data phase (default) 1 = extends initial data phase to 64 clocks 2 r/w immediate retry mode 0 = immediate retry mode enabled (default) 1 = immediate retry mode disabled 1 r/w bus parking bit. this bit determines where the pci2250 internal arbiter parks the secondary bus. when this bit is set, the arbiter parks the secondary bus on the bridge. when this bit is cleared, the arbiter parks the bus on the last device mastering the secondary bus. this bit is encoded as: 0 = park the secondary bus on the last secondary bus master (default) 1 = park the secondary bus on the bridge 0 r/w ti internal test mode bit.
513 5.15 diagnostic status register the diagnostic status register is used to reflect the bridge diagnostic status. see table 513 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name diagnostic status type r r r r r/c/ u r/c/ u r r r/c/ u r r r r r r r/c/ u default 0 0 0 0 x x 0 0 0 0 0 0 0 x x x register: diagnostic status type: read-only, read/write offset: 5eh default: 0x0xh table 513. diagnostic status register bit type function 1512 r reserved. bits 1512 return 0s when read. 11 r/c/u bridge detected a parity error while mastering on the secondary bus. when set, bit 11 indicates that the secondary bus master detected a parity error. writing a 1 to this bit clears it. 0 = no parity error detected 1 = parity error detected 10 r/c/u bridge detected a parity error while mastering on the primary bus. when set, bit 10 indicates that the primary bus master detected a parity error. writing a 1 to this bit clears it. 0 = no parity error detected 1 = parity error detected 9 r ms1 status. returns the logical value of the ms1/bpcc input. 8 r ms0 status. returns the logical value of the ms0 input. 7 r/c/u arbiter timeout serr status. when set, bit 0 indicates that serr has occurred due to the expiration of the arbiter timer. writing a 1 to this bit clears it. 0 = no serr (default) 1 = serr occurred due to an arbiter timeout 6 r reserved. bit 6 returns 0 when read. 5 r hs_switch status. this registers returns the logical value of the s_mfunc input regardless of the value of ms0/ms1. 43 r reserved 2 r external arbiter enable pin status. bit 2 contains the current state of the external pin external arbiter enable. 0 = signal low 1 = signal high 1 r serial eeprom block status. bit 1 indicates the status of the serial eeprom block. when set, bit 1 indicates that the serial eeprom block is busy. 0 = serial eeprom block not busy 1 = serial eeprom block busy 0 r/c/u arbiter timeout status. bit 0 indicates the status of the arbiter timer. when set, bit 0 indicates that a bus master did not be gin the cycle within 16 clocks. writing a 1 to this bit clears it. this bit is encoded as: 0 = no timeout (default). 1 = master requesting the bus did not start cycle within 16 clocks.
514 5.16 arbiter request mask register the arbiter request mask register contains the serr enable on arbiter timeouts and the request mask controls. see table 514 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name arbiter request mask type r r/w r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: arbiter request mask type: read-only, read/write offset: 62h default: 00h table 514. arbiter request mask register bit type function 7 r reserved. bit 7 returns 0 when read. 6 r/w timeout automatic masking enable 0 = masking not automatic (default) 1 = allow masking after 16-clock timeout 54 r reserved. bits 5 and 4 return 0s when read. 3 r/w request 3 (req3 ) mask bit 0 = use request 3 (default) 1 = ignore request 3 2 r/w request 2 (req2 ) mask bit 0 = use request 2 (default) 1 = ignore request 2 1 r/w request 1 (req1 ) mask bit 0 = use request 1 (default) 1 = ignore request 1 0 r/w request 0 (req0 ) mask bit 0 = use request 0 (default) 1 = ignore request 0
515 5.17 arbiter timeout status register the arbiter timeout status register contains the status of each request (request 50) timeout. the timeout status bit for the respective request is set if the device did not assert frame after 16 clocks. see table 515 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name arbiter timeout status type r r r r r/c/u r/c/u r/c/u r/c/u default 0 0 0 0 0 0 0 0 register: arbiter timeout status type: read-only offset: 63h default: 00h table 515. arbiter timeout status register bit type function 74 r reserved. bits 74 return 0s when read. 3 r/c/u request 3 timeout status. cleared by writing a 1. 0 = no timeout (default) 1 = timeout has occurred 2 r/c/u request 2 timeout status. cleared by writing a 1. 0 = no timeout (default) 1 = timeout has occurred 1 r/c/u request 1 timeout status. cleared by writing a 1. 0 = no timeout (default) 1 = timeout has occurred 0 r/c/u request 0 timeout status. cleared by writing a 1. 0 = no timeout (default) 1 = timeout has occurred
516 5.18 p_serr event disable register the p_serr event disable register is used to enable/disable serr event on the primary interface. all events are enabled by default. see table 516 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name p_serr event disable type r r/w r/w r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 register: p_serr event disable type: read-only, read/write offset: 64h default: 00h table 516. p_serr event disable register bit type function 7 r reserved. bit 7 returns 0 when read. 6 r/w master delayed read time-out 0 = p_serr signaled on a master time-out after 2 24 retries on a delayed read (default). 1 = p_serr is not signaled on a master time-out. 5 r/w master delayed write time-out. 0 = p_serr signaled on a master time-out after 2 24 retries on a delayed write (default). 1 = p_serr is not signaled on a master time-out. 4 r/w master abort on posted write transactions. when set, bit 4 enables p_serr reporting on master aborts on posted write transactions. 0 = master aborts on posted writes enabled (default) 1 = master aborts on posted writes disabled 3 r/w target abort on posted writes. when set, bit 3 enables p_serr reporting on target aborts on posted write transactions. 0 = target aborts on posted writes enabled (default). 1 = target aborts on posted writes disabled. 2 r/w master posted write time-out 0 = p_serr signaled on a master time-out after 2 24 retries on a posted write (default). 1 = p_serr is not signaled on a master time-out. 1 r/w posted write parity error 0 = p_serr signaled on a posted write parity error (default). 1 = p_serr is not signaled on a posted write parity error. 0 r reserved. bit 0 returns 0 when read.
517 5.19 secondary clock control register the secondary clock control register is used to control the secondary clock outputs. see table 517 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name secondary clock control type r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: secondary clock control type: read-only, read/write offset: 68h default: 0000h table 517. secondary clock control register bit type function 159 r reserved. bits 159 return 0s when read. 8 r/w clockout4 disable. 0 = clockout4 enabled (default) 1 = clockout4 disabled and driven high 76 r/w clockout3 disable. 00, 01, 10 = clockout3 enabled (00 default) 11 = clockout3 disabled and driven high 54 r/w clockout2 disable. 00, 01, 10 = clockout2 enabled (00 default) 11 = clockout2 disabled and driven high 32 r/w clockout1 disable. 00, 01, 10 = clockout1 enabled (00 default) 11 = clockout1 disabled and driven high 10 r/w clockout0 disable. 00, 01, 10 = clockout0 enabled (00 default) 11 = clockout0 disabled and driven high
518 5.20 p_serr status register the p_serr status register indicates what caused a serr event on the primary interface. see table 518 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name p_serr status type r r/c/u r/c/u r/c/u r/c/u r/c/u r/c/u r default 0 0 0 0 0 0 0 0 register: p_serr status type: read-only, read/clear/update offset: 6ah default: 00h table 518. p_serr status register bit type function 7 r reserved. bit 7 returns 0 when read. 6 r/c/u master delayed read time-out. a 1 indicates that p_serr was signaled because of a master time-out after 2 24 retries on a delayed read. 5 r/c/u master delayed write time-out. a 1 indicates that p_serr was signaled because of a master time-out after 2 24 retries on a delayed write. 4 r/c/u master abort on posted write transactions. a 1 indicates that p_serr was signaled because of a master abort on a posted write. 3 r/c/u target abort on posted writes. a 1 indicates that p_serr was signaled because of a target abort on a posted write. 2 r/c/u master posted write time-out. a 1 indicates that p_serr was signaled because of a master time-out after 2 24 retries on a posted write. 1 r/c/u posted write parity error. a 1 indicates that p_serr was signaled because of parity error on a posted write. 0 r reserved. bit 0 returns 0 when read. 5.21 pm capability id register the capability id register identifies the linked list item as the register for pci power management. the capability id register returns 01h when read, which is the unique id assigned by the pci sig for the pci location of the capabilities pointer and the value. bit 7 6 5 4 3 2 1 0 name capability id type r r r r r r r r default 0 0 0 0 0 0 0 1 register: capability id type: read-only offset: dch default: 01h
519 5.22 pm next item pointer register the next item pointer register is used to indicate the next item in the linked list of pci power management capabilities. the next item pointer returns e4h in compact pci mode, indicating that the pci2250 supports more than one extended capability, but in all other modes returns 00h, indicating that only one extended capability is supported. bit 7 6 5 4 3 2 1 0 name next item pointer type r r r r r r r r default 1 1 1 0 0 1 0 0 register: next item pointer type: read-only offset: ddh default: e4h compact pci mode 00h all other modes 5.23 power management capabilities register the power management capabilities register contains information on the capabilities of the pci2250 functions related to power management. the pci2250 function supports d0, d1, d2, and d3 power states when ms1 is low. the pci2250 does not support any power states when ms1 is high. see table 519 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management capabilities type r r r r r r r r r r r r r r r r default 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 register: power management capabilities type: read-only offset: deh default: 0602h or 0001h table 519. power management capabilities register bit type function 1511 r pme support. this five-bit field indicates the power states that the device supports asserting pme . a 0 for any of these bits indicates that the pci2250 cannot assert pme signal from that power state. for the pci2250, these five bits return 00000b when read, indicating that pme is not supported. 10 r d2 support. this bit returns 1 when ms0 is 0, indicating that the bridge function supports the d2 device power state. this bit returns 0 when ms0 is 1, indicating that the bridge function does not support the d2 device power state. 9 r d1 support. this bit returns 1 when ms0 is 0, indicating that the bridge function supports the d1 device power state. this bit returns 0 when ms0 is 1, indicating that the bridge function does not support the d1 device power state. 86 r reserved. bits 86 return 0s when read. 5 r device specific initialization. this bit returns 0 when read, indicating that the bridge function does not require special initialization (beyond the standard pci configuration header) before the generic class device driver is able to use it. 4 r auxiliary power source. this bit returns a 0 because the pci2250 does not support pme signaling. 3 r pmeclk. this bit returns a 0 because the pme signaling is not supported. 20 r version. this three-bit register returns the pci bus power management interface specification revision. 001 = revision 1.0, ms0 = 1 010 = revision 1.1, ms0 = 0
520 5.24 power management control/status register the power management control/status register determines and changes the current power state of the pci2250. the contents of this register are not affected by the internally generated reset caused by the transition from d3 hot to d0 state. see table 520 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management control/status type r r r r r r r r r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: power management control/status type: read-only, read/write offset: e0h default: 0000h table 520. power management capabilities register bit type function 15 r pme status. this bit returns a 0 when read because the pci2250 does not support pme . 1413 r data scale. this two-bit read-only field indicates the scaling factor to be used when interpreting the value of the data register. these bits return only 00b, because the data register is not implemented. 129 r data select. this four-bit field is used to select which data is to be reported through the data register and data-scale field. these bits return only 0000b, because the data register is not implemented. 8 r pme enable. this bit returns a 0 when read because the pci2250 does not support pme signaling. 72 r reserved. bits 72 return 0s when read. 10 r/w power state. this two-bit field is used both to determine the current power state of a function and to set the function into a new power state. the definition of the two-bit field is given below: 00 d0 01 d1 10 d2 11 d3 hot
521 5.25 pmcsr bridge support register the pmcsr bridge support register is required for all pci bridges and supports pci bridge specific functionality. see table 521 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name pmcsr bridge support type r r r r r r r r default x x 0 0 0 0 0 0 register: pmcsr bridge support type: read-only offset: e2h default: x0h table 521. pmcsr bridge support register bit type function 7 r bus power control enable. this bit returns the value of the ms1/bcc input. 0 = bus power/ clock control disabled 1 = bus power/clock control enabled 6 r b2/b3 support for d3 hot . this bit returns the value of ms1/bcc input. when this bit is 1, the secondary clocks are stopped when the device is placed in d3 hot . when this bit is 0, the secondary clocks remain on in all device states. note: if the primary clock is stopped, then the secondary clocks will stop because the primary clock is used to generate the secondary clocks. 50 r reserved. bits 50 return 0s when read. 5.26 data register the data register is an optional, 8-bit readonly register that provides a mechanism for the function to report state-dependent operating data such as power consumed or heat dissipatin. the pci2050 does not implement the data register. bit 7 6 5 4 3 2 1 0 name data type r r r r r r r r default 0 0 0 0 0 0 0 0 register: data type: read-only offset: e3h default: 00h
522 5.27 hs capability id register the hs capability id register identifies the linked list item as the register for cpci hot swap capabilities. the register returns 06h when read, which is the unique id assigned by the picmg for pci location of the capabilities pointer and the value. bit 7 6 5 4 3 2 1 0 name hs capability id type r r r r r r r r default 0 0 0 0 0 1 1 0 register: hs capability id type: read-only offset: e4h default: 06h 5.28 hs next item pointer register the hs next item pointer register is used to indicate the next item in the linked list of cpci hot swap capabilities. since the pci2250 functions only include two capabilities list item, this register returns 0s when read. bit 7 6 5 4 3 2 1 0 name hs next item pointer type r r r r r r r r default 0 0 0 0 0 0 0 0 register: hs next item pointer type: read-only offset: e5h default: 00h
523 5.29 hot swap control status register the hot swap control status register contains control and status information for cpci hot swap resources. see table 522 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name hot swap control status type r/c/u r/c/u r r r/w r r/w r default 0 0 0 0 0 0 0 0 register: hot swap control status type: read-only, read/write offset: e6h default: 00h table 522. hot swap control status register bit type function 7 r/c/u enum insertion status. when set, the enum output is driven by the pci2250. this bit defaults to 0, and will be set after a pci reset occurs, the ejector handle is closed, and bit 6 is 0. thus, this bit is set following an insertion when the board implementing the pci2250 is ready for configuration. this bit cannot be set under software control. 6 r/c/u enum extraction status. when set, the enum output is driven by the pci2250. this bit defaults to 0, and is set when the ejector handle is opened and bit 7 is 0. thus, this bit is set when the board implementing the pci2250 is about to be removed. this bit cannot be set under software control. 54 r reserved. bits 5 and 4 return 0s when read. 3 r/w led on/off. this bit defaults to 0, and controls the external led indicator (hsled) under normal conditions. however, for a duration following a pci_rst , the hsled output is driven high by the pci2250 and this bit is ignored. when this bit is interpreted, a 1 will cause hsled high and a 0 will cause hsled low. following pci_rst , the hsled output is driven high by the pci2250 until the ejector handle is closed. when these conditions are met, the hsled is under software control via this bit. 2 r reserved. bit 2 returns 0 when read. 1 r/w enum interrupt mask. this bit allows the hsenum output to be masked by software. bits 6 and 7 are set independently from this bit. 0 = enable hsenum output 1 = mask hsenum output 0 r reserved. bit 0 returns 0 when read.
524
61 6 electrical characteristics 6.1 absolute maximum ratings over operating temperature ranges 2 supply voltage range: v cc 0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : sv ccp 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : pv ccp 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : pci 0.5 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : ttl 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o : pci 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 2) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . virtual junction temperature, t j 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. applies for external input and bidirectional buffers. v i > v cc does not apply to fail-safe terminals. 2. applies to external output and bidirectional buffers. v o > v cc does not apply to fail-safe terminals.
62 6.2 recommended operating conditions (see note 3) operation min nom max unit v cc supply voltage (core) commercial 3.3 v 3 3.3 3.6 v pv pci primary bus i/o clamping rail voltage commercial 3.3 v 3 3.3 3.6 v pv ccp pci primary bus i/o clamping rail voltage commercial 5 v 4.75 5 5.25 v sv pci secondary bus i/o clamping rail voltage commercial 3.3 v 3 3.3 3.6 v sv ccp pci secondary bus i/o clamping rail voltage commercial 5 v 4.75 5 5.25 v pci 3.3 v 0.5 v ccp v ccp v ih 2 high-level input voltage pci 5 v 2 v ccp v v ih 2 high level in ut voltage ttl 3 3.3 v 2.25 v cc v pci 3.3 v 0 0.3 v ccp v il 2 high-level input voltage pci 5 v 0 0.8 v v il gg ttl 3 0 0.75 v input voltage pci 0 v ccp v v i input voltage ttl 3 0 v cc v v output voltage 3.3 v 0 v cc v v o output voltage 5 v 0 v cc v t input transition time (t and t f ) pci 1 4 ns t t input transition time (t r and t f ) ttl 3 0 6 ns t a operating ambient temperature range 3.3 v 0 25 70 c t j ? virtual junction temperature 5 v 0 25 115 c notes: 3. unused or floating pins (input or i/o) must be held high or low. 2 applies for external input and bidirectional buffers without hysteresis 3 ttl terminals are schmitt-trigger input-only terminals: 55, 69, 132, 174 for pgf-packaged device; and 49, 63, 120, 159 for pcm- packaged device. applies for external output buffers ? these junction temperatures reflect simulation conditions. the customer is responsible for verifying junction temperature. 6.3 recommended operating conditions for pci interface operation min nom max unit v cc core voltage commercial 3.3 v 3 3.3 3.6 v v pci supply voltage commercial 3.3 v 3 3.3 3.6 v v ccp pci supply voltage commercial 5 v 4.75 5 5.25 v v input voltage 3.3 v 0 v ccp v v i input voltage 5 v 0 v ccp v v output voltage 3.3 v 0 v ccp v v o output voltage 5 v 0 v ccp v v ? high le el inp t oltage cmos compatible 3.3 v 0.5 v ccp v v ih ? high-level input voltage cmos compatible 5 v 2 v v ? low level input voltage cmos compatible 3.3 v 0.3 v ccp v v il ? low-level input voltage cmos compatible 5 v 0.8 v applies to external output buffers ? applies to external input and bidirectional buffers without hysteresis
63 6.4 electrical characteristics over recommended operating conditions parameter terminals operation test conditions min max unit v 2 high le el o tp t oltage 3.3 v i oh = 0.5 ma 0.9 v cc v v oh 2 high-level output voltage 5 v i oh = 2 ma 2.4 v v low level output voltage 3.3 v i ol = 1.5 ma 0.1 v cc v v ol low-level output voltage 5 v i ol = 6 ma 0.55 v input terminals ttl v i = v cc 1 i ih 3 high-level input current input terminals pci v i = v ccp 10 m a i ih 3 high level in ut current i/o terminals ? vv 10 m a i/o terminals ? v i = v ccp 10 input terminals ttl 1 i il 3 low-level input current input terminals pci v i = gnd 1 m a i il 3 low level in ut current i/o terminals ? v i gnd 10 m a i oz high-impedance output current v o = v ccp or gnd 10 m a 2 v oh is not tested on pserr due to open-drain configuration. 3 i ih and i il are not tested on no_hsled dur to its active ourput-only configuration. ttl terminals are 55, 69, 132, 174 for pgf-packaged device; and 49, 63, 120, 159 for pcm-packaged device. ? for i/o terminals, the input leakage current includes the off-state output current i oz .
64 6.5 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see figure 62 and figure 63) alternate symbol min max unit t c cycle time, pclk t cyc 30 ns t wh pulse duration, pclk high t high 11 ns t wl pulse duration, pclk low t low 11 ns d v/ d t slew rate, pclk t r , t f 1 4 v/ns t w pulse duration, rstin t rst 1 ms t su setup time, pclk active at end of rstin (see note 4 ) t rst-clk 100 s note 4: the setup and hold times for the secondary are identical to those for the primary; however, the times are relative to th e secondary pci close.
65 6.6 pci timing requirements over recommended ranges of supply voltage and operating free-air temperature (see note 5 and figure 61 and figure 64) alternate symbol test conditions min max unit t propagation delay time pclk to shared signal valid delay time t val c 50 pf see note 6 11 ns t pd propagation delay time pclk to shared signal invalid delay time t inv c l = 50 pf, see note 6 2 ns t en enable time, high-impedance-to-active delay time from pclk t on 2 ns t dis disable time, active-to-high-impedance delay time from pclk t off 28 ns t su setup time before pclk valid t su , see note 4 7 ns t h hold time after pclk high t h , see note 4 0 ns 5. this data sheet uses the following conventions to describe time (t) intervals. the format is: t a , where subscript a indicates the type of dynamic parameter being represented. one of the following is used: t pd = propagation delay time, t d = delay time, t su = setup time, and t h = hold time. 6. pci shared signals are ad31ad0, c/be3 c/be0 , frame , trdy , irdy , stop , idsel, devsel , and par.
66 6.7 parameter measurement information 2 c load includes the typical load-circuit distributed capacitance. c load test point timing input (see note a ) out-of-phase output t pd 50% v cc 50% v cc v cc 0 v 0 v 0 v 0 v 0 v v ol t h t su v oh v oh v ol high-level input low-level input t w voltage waveforms propagation delay times load circuit voltage waveforms setup and hold times input rise and fall times voltage waveforms pulse duration t pd t pd t pd v load i oh i ol from output under test 90% v cc 10% v cc t f t r output control (low-level enabling) waveform 1 (see note b) waveform 2 (see note b) v ol v oh v oh 0.3 v t pzl t pzh t plz t phz voltage waveforms enable and disable times, 3-state outputs v ol + 0.3 v 0 v 0 v 50% v cc 50% v cc t en t dis t pd t pzh t pzl t phz t plz c load 2 (pf) i ol (ma) timing parameter 50 8 8 0 3 1.5 3 50 8 8 8 8 load circuit parameters = 50 w , where v ol = 0.6 v, i ol = 8 ma i ol 50 3 v load v ol i oh (ma) v load (v) data input in-phase output input (see note a) v cc v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc notes: a. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by pulse generators having the following characteristics: prr = 1 mhz, z o = 50 w , t r 6 ns, t f 6 ns. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. for t plz and t phz , v ol and v oh are measured values. 50% v cc figure 61. load circuit and voltage waveforms
67 6.8 pci bus parameter measurement information t wh 2 v 0.8 v t r t f t c t wl 2 v min peak to peak figure 62. pclk timing waveform t w t su pclk rstin figure 63. rstin timing waveforms 1.5 v t pd t pd valid 1.5 v t on t off valid t su t h pclk pci output pci input figure 64. shared-signals timing waveforms
68
71 7 mechanical data pgf (s-pqfp-g176) plastic quad flatpack 0,13 nom 89 0,17 0,27 88 45 0,45 0,25 0,75 44 seating plane 0,05 min 4040134 / b 11/96 gage plane 132 133 176 sq 24,20 sq 25,80 26,20 23,80 21,50 sq 1 1,45 1,35 1,60 max m 0,08 0,50 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
72 pcm (s-pqfp-g***) plastic quad flatpack 4040024 / b 10/94 144 pins shown a 73 144 160 0,38 0,22 72 37 no. of pins*** 22,75 typ 25,35 typ 0,16 nom 0,25 0,73 1,03 36 seating plane 0,25 min gage plane 108 109 144 a sq sq 31,45 1 28,20 30,95 27,80 3,60 3,20 4,10 max 0,10 0,65 m 0,13 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-022 d. the 144 pcm is identical to the 160 pcm except that four leads per corner are removed.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated

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