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1 features linear regulator 5v 2% @ 100ma switching regulator 1.4a peak internal switch 120khz maximum switching frequency 5v to 26v operating supply range smart functions watchdog protection overtemperature current limit enable reset package options 24 lead so wide (internally fused leads) cs5112 1.4a switching regulator with 5v, 100ma linear regulator with watchdog, reset and enable 1 v reg v lin i bias gnd gnd gnd gnd reset c delay wdi c osc v in nc nc v sw gnd gnd gnd gnd v fb1 v fb2 select comp enable cs5112 description over temperature v in linear error amplifier 1.25v v reg 1.4a v sw comp v fb1 v fb2 select v lin i bias c delay reset & watchdog timer current limit wdi c osc base drive reset gnd bandgap reference oscillator multiplexer + - comp logic + - + - + - switcher shutdown switcher error amplifier current sense amplifier enable block diagram june, 1999 - rev. 5 the cs5112 is a dual output power sup- ply integrated circuit. it contains a 5v 2%, 100ma linear regulator, a watchdog timer, a linear output voltage monitor to provide a power on reset (por) and a 1.4a current mode pwm switching reg- ulator. the 5v linear regulator is comprised of an error amplifier, reference, and super- visory functions. it has low internal sup- ply current consumption and provides 1.2v (typical) dropout voltage at maxi- mum load current. the watchdog timer circuitry monitors an input signal (wdi) from the micro- processor. it responds to the falling edge of this watchdog signal. if a correct watchdog signal is not received within the externally programmable time, a reset signal is issued. the externally programmable active reset circuit operates correctly for an out- put voltage (v lin ) as low as 1v. during power up, or if the output voltage shifts below the regulation limit, tog- gles low and remains low for the duration of the delay after proper output voltage regulation is restored. additionally a reset pulse is issued if the correct watchdog is not received within the programmed time. reset pulses continue until the cor- rect watchdog signal is received. the reset pulse width and frequency, as well as the power on reset delay, are set by one external rc network. the current mode pwm switching regu- lator is comprised of an error amplifier with selectable feedback inputs, a cur- rent sense amplifier, an adjustable oscil- lator, and a 1.4a output power switch with anti-saturation control. the switch- ing regulator can be configured in a variety of topologies. the cs5112 is load dump capable and has protection circuitry which includes current limit on the linear and switcher outputs, and an overtemperature limiter. reset on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?600 fax: (401)885?786 n. american technical support: 800-282-9855 web site: www.cherry?emi.com
2 cs5112 parameter test conditions min typ max unit absolute maximum ratings logic inputs/outputs ( , select, wdi, ) ................................................................................-0.3v to v lin v lin ............................................................................................................................... .................................................-0.3v to 10v v in , v reg: dc input voltage ............................................................................................................... ..................................-0.3v to 26v peak transient voltage (26v load dump @ 14v v in )....................................................................................-0.3v to 40v v sw peak transient voltage ......................................................................................................... ............................................54v c osc , c delay , comp,v fb1 , v fb2 ............................................................................................................................... ...-0.3v to v lin power dissipation.............................................................................................................. ...............................internally limited v lin output current ................................................................................................................. .......................internally limited v sw output current ................................................................................................................. ........................internally limited output sink current ............................................................................................................ ......................................5ma esd susceptibility (human body model).......................................................................................... ....................................2kv esd susceptibility (machine model).............................................................................................. .......................................200v storage temperature ............................................................................................................ .......................................-65 to 150? lead temperature soldering: reflow (smd styles only) ..........................................60 sec. max above 183?, 230? pe ak reset reset enable electrical characteristics: 5v v in 26v and -40? t j 150?, -40? t a 125?, c out = 100f (esr 8 ? ), c delay = 0.1f, r bias = 64.9k ? , c osc = 390 pf, c comp = 0.1f; unless otherwise specified. general i in off current 6.6v v in 26v, i sw = 0a 2.0 ma i in on current 6.6v v in 26v, i sw = 1.4a 30 70 ma i reg current i lin = 100ma, 6.6v v reg 26v 6 ma thermal limit guaranteed by design 160 210 ? 5v regulator section v lin output voltage 6.6v v reg 26v, 1ma i lin 100ma 4.9 5.0 5.1 v dropout voltage (v reg - v lin ) @ i lin = 100ma 1.2 1.5 v line regulation 6.6v v reg 26v, i lin = 5ma 5 25 mv load regulation v reg = 19v, 1ma i lin 100ma 5 25 mv current limit 6.6v v reg 26v 120 ma dc ripple rejection 14v v reg 24v 60 75 db section low threshold (v rtl )v lin decreasing 4.05 4.25 4.45 v high threshold (v rth )v lin increasing 4.20 4.45 4.70 v hysteresis v rth - v rtl 140 190 240 mv active high v lin > v rth , i reset = -25a v lin - 0.5 v active low v lin = 1v, 10k ? pullup from to v lin 0.4 v v lin = 4v, i reset = 1ma 0.7 v delay invalid wdi 6.25 8.78 11.0 ms power on delay v lin crossing v rth 6.25 ms reset reset
3 parameter test conditions min typ max unit cs5112 watchdog input (wdi) vih peak wdi needed to activate 2.0 v vil 0.8 v hysteresis note 1 25 50 mv pull-up resistor wdi=0v 20 50 100 k ? low threshold 6.25 8.78 11.0 ms floating input voltage 3.5 v wdi pulse width 5s switcher section minimum operating 5.0 v input voltage switching frequency refer to figure 1d. 80 95 110 khz switch saturation voltage i sw = 1.4a 0.7 1.1 1.6 v output current limit 1.4 2.5 a max switching frequency v sw = 7.5v with 50 ? load, 120 khz refer to figure 1d. v fb1 regulation voltage 1.206 1.25 1.294 v v fb2 regulation voltage 1.206 1.25 1.294 v v fb1 , v fb2 input current v fb1 = v fb2 = 5v 1 a oscillator charge current c osc = 0v 35 40 45 a oscillator discharge current c osc = 4v 270 320 370 a c delay charge current c delay = 0v 35 40 45 a switcher max duty cycle v sw = 5v with 50 ? load, 72 85 95 % v fb1 = v fb2 = 1v current sense amp gain i sw = 2.3a 7 error amp dc gain 67 db error amp transconductance 2700 a/v input vil 0.8 1.24 v vih 1.30 2.0 v hysteresis 60 mv input impedance 10 20 40 k ? select input vil (selects v fb1 ) 4.9 v lin 5.1 0.8 1.25 v vih (selects v fb2 ) 4.9 v lin 5.1 1.25 2.0 v select pull-up select = 0v 10 24 50 k ? floating input voltage 3.5 4.5 v note 1: guaranteed by design, not 100% tested in production. enable reset electrical characteristics: 5v v in 26v and -40? t j 150?, -40? t a 125?, c out = 100f (esr 8 ? ), c delay = 0.1f, r bias = 64.9k ? , c osc = 390 pf, c comp = 0.1f; unless otherwise specified.
4 typical performance characteristics 0a 20ma 40ma 60ma 80ma 100ma 3.5ma 4.0ma 4.5ma i lin i reg - i lin -30ma -40ma 0a 0.5a i sw -20ma -10ma 0a 1.0a 1.5a 2.0a i in i sw 0a 0.5a 1.0a 1.5a 2.0a 0.4v 0.0v 0.6v 0.8v 1.2v 1.0v v sw 0.2v 1.4v package lead description package lead # lead symbol function cs5112 40 0 0 c osc (pf) 80 120 160 1000 frequency (khz) 20 60 100 140 2000 3000 500 1500 2500 180 figure 1a. 5v regulator bias current vs. load current. figure 1b. supply current vs. switch current. figure 1c. switch saturation voltage. figure 1d. oscillator frequency (khz) vs. c osc (pf), assuming r bias = 64.9k ? . 24 lead so wide 1v in supply voltage. 2, 3 nc no connection. 4v sw collector of npn power switch for switching regulator section. 5,6,7,8,17,18,19,20 gnd connected to the heat removing leads. 9v fb1 feedback input voltage 1 (referenced to 1.25v) 10 v fb2 feedback input voltage 2 (referenced to 1.25v) 11 select logic level input that selects either v fb1 or v fb2 . an open selects v fb2 . connect to gnd to select v fb1 . 12 comp output of the transconductance error amplifier. 13 c osc a capacitor connected to gnd sets the switching frequency. refer to figure 1d. 14 wdi watchdog input. active on falling edge. 15 c delay a capacitor connected to gnd sets the power on reset and watchdog time. 16 output. active low if v lin is below the regulation limit. if watchdog timeout is reached, a reset pulse train is issued. 21 i bias a resistor connected to gnd sets internal bias currents as well as the c osc and c delay charge currents. 22 v lin regulated 5v output from the linear regulator section. 23 v reg input voltage to the linear regulator and the internal supply cir- cuitry. 24 logic level input to shut down the switching regulator. enable reset reset
circuit description cs5112 5 the 5v linear regulator consists of an error amplifier, bandgap voltage reference, and a composite pass transistor. the 5v linear regulator circuitry is shown in figure 2. when an unregulated voltage greater than 6.6v is applied to the v reg input, a 5v regulated dc voltage will be pre- sent at v lin . for proper operation of the 5v linear regula- tor, the i bias lead must have a 64.9k ? pull down resistor to ground. a 100f or larger capacitor with an esr <8 ? must be connected between v lin and ground. to operate the 5v linear regulator as an independent regulator (i.e. separate from the switching supply), the input voltage must be tied to the v reg lead. as the voltage at the v reg input is increased, q 1 is turned on. q 1 provides base drive for q 2 which in turn provides base current for q 3 . as q 3 is turned on, the output voltage, v lin , begins to rise as q 3 ? output current charges the out- put capacitor, c out . once v lin rises to a certain level, the error amplifier becomes biased and provides the appropri- ate amount of base current to q 1 . the error amplifier mon- itors the scaled output voltage via an internal voltage divider, r 2 through r 5 , and compares it to the bandgap voltage reference. the error amplifier output or error sig- nal is an output current equal to the error amplifier? input differential voltage times the transconductance of the amplifier. therefore, the error amplifier varies the base current to q 1 , which provides bias to q 2 and q 3 , based on the difference between the reference voltage and the scaled v lin output voltage. the watchdog timer circuitry monitors an input signal (wdi) from the microprocessor. it responds to the falling edge of this watchdog signal which it expects to see within an externally programmable time (see figure 3). the watchdog time is given by: t wdi = 1.353 c delay r bias using c delay = 0.1f and r bias = 64.9k ? gives a time rang- ing from 6.25ms to 11ms assuming ideal components. based on this, the software must be written so that the watchdog arrives at least every 6.25ms. in practice, the tolerance of c delay and r bias must be taken into account when calculat- ing the minimum watchdog time (t wdi ). figure 3. timing diagram for normal regulator operation. figure 4. timing diagram when wdi fails to appear within the preset time interval, t wdi . v lin wdi reset v reg t por a b a: watchdog waiting for low-going transition on wdi 50% duty cycle b: reset stays low for t wdi time. v lin wdi reset v reg t por normal operation control functions 5v linear regulator over temperature linear error amplifier 1.25v v reg v lin c delay reset & watchdog timer current limit wdi reset bandgap reference + - i bias r bias 64.9k ? r 1 r 2 r 3 r 4 r 5 c out = 100 f esr < 8 ? q 1 q 2 q 3 figure 2. block diagram of 5v linear regulator portion of the cs5112.
6 circuit description: continued cs5112 if a correct watchdog signal is not received within the specified time a reset pulse train is issued until the correct watchdog signal is received. the nominal reset signal in this case is a 5 volt square wave with a 50% duty cycle as shown in figure 4. the signal frequency is given by: f reset = the power on reset (por) and low voltage use the same circuitry and issue a reset when the linear output voltage is below the regulation limit. after v lin rises above the minimum specified value, remains low for a fixed period t por as shown in figure 5. the por delay (t por ) is given by: t por = 1.353 c delay r bias figure 5a. the power on reset time interval (t por ) begins when v lin rises above 4.45v (typical). figure 5b. signal is issued whenever v lin falls below 4.25v (typical). the current mode pwm switching voltage regulator con- tains an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator and a 1.4a output power switch with antisaturation control. the switching regulator and external components, connected in a boost configuration, are shown in figure 6. the switching regulator begins operation when v reg and v in are raised above 5 volts. v reg is required since the switching supply? control circuitry is powered through v lin . v in supplies the base drive to the switcher output transistor. the output transistor turns on when the oscillator starts to charge the capacitor on c osc . the output current will develop a voltage drop across the internal sense resistor (r s ). this voltage drop produces a proportional voltage at the output of the current sense amplifier, which is com- pared to the output of the error amplifier. the error ampli- fier generates an output voltage which is proportional to the difference between the scaled down output boost volt- age (v fb1 or v fb2 ) and the internal bandgap voltage refer- ence. once the current sense amplifier output exceeds the error amplifier? output voltage, the output transistor is turned off. the energy stored in the inductor during the output tran- sistor on time is transferred to the load when the output transistor is turned off. the output transistor is turned back on at the next rising edge of the oscillator. on a cycle by cycle basis, the current mode controller in a discontinu- ous mode of operation charges the inductor to the appro- priate amount of energy, based on the energy demand of the load. figure 7 shows the typical current and voltage waveforms for a boost supply operating in the discontinu- ous mode. notes: 1. refer to figure 1d to determine oscillator frequency. 2. the switching regulator can be disabled by providing a logic high at the input. 3. the boost output voltage can be controlled dynamically by the feedback select input. if select is open, v fb2 is selected. if select is low, then v fb1 is selected. the current out of v lin is sensed in order to limit exces- sive power dissipation in the linear output transistor over the output range of 0v to regulation. also, the current into v sw is sensed in order to provide the current limit func- tion in the switcher output transistor. if the die temperature is increased above 160?, either due to excessive ambient temperature or excessive power dis- sipation, the drive to the linear output transistor is reduced proportionally with increasing die temperature. therefore, v lin will decrease with increasing die tempera- ture above 160?. since the switcher control circuitry is powered through v lin , the switcher performance, includ- ing current limit, will be affected by the decrease in v lin . protection circuitry enable current mode pwm switching circuitry reset 5v 4.25v reset 5v t por v lin v lin 4.45v 4.25v v r lo t por reset v r peak reset reset 1 2(t wdi ) reset
7 application notes cs5112 circuit description: continued figure 6: block diagram of the 1.4a current mode control switching regulator portion of the cs5112 in a boost configuration. v out r 1 v fb1 v fb2 r 2 r 3 v r2 r eq { figure 8. feedback sense resistor divider connected between v out and ground. -1 v out v fb1 this section outlines a procedure for designing a boost switch- ing power supply operating in the discontinuous mode. step 1 determine the output power required by the load. p out = i out v out (1) step 2 choose c osc based on the target oscillator frequency with an external resistor value, r bias = 64.9k ? . (see figure 1d). figure 7: voltage and current waveforms for boost topology in cs5112. step 3 next select the output voltage feedback sense resistor divider as follows (figure 8). for v fb1 active, choose a value for r 1 and then solve for r eq where: r eq = . (3a) for v fb2 active, find: v fb1 = v out , (3b) and then calculate r 2 where: r 2 = = . (3c) then find r 3 , where: r 3 = r eq - r 2 . (3d) v fb1 - v fb2 v fb1 /r eq v r2 i r2 ) r eq r 1 + r eq ( r 1 0 v sw v in v sat t 0 i sw i peak t 0 i d i peak t v out design procedure for boost topology v in 1.4a v sw comp v fb1 v fb2 select v lin i bias c osc gnd bandgap reference oscillator + - switcher shutdown switcher error amplifier current sense amplifier enable multiplexer + - + - comp base drive logic r bias 64.9k ? r s r 3 r 2 r 1 1.25v v out c out
8 application notes: continued cs5112 step 4 determine the maximum on time at the minimum oscilla- tor frequency and v in . for discontinuous operation, all of the stored energy in the inductor is transferred to the load prior to the next cycle. since the current through the inductor cannot change instantaneously and the induc- tance is constant, a volt-second balance exists between the on time and off time. the voltage across the inductor dur- ing the on cycle is v in and the voltage across the inductor during the off cycle is v out - v in . therefore: v in t on = (v out -v in )t off (4a) where the maximum on time is: t on(max) . (4b) step 5 calculate the maximum inductance allowed for discontin- uous operation: l (max) = (5) where = efficiency. usually = 0.75 is a good starting point. the ic? power dissipation should be calculated after the peak current has been determined in step 6. if the efficiency is less than originally assumed, decrease the efficiency and recalculate the maximum inductance and peak current. step 6 determine the peak inductor current at the minimum inductance, minimum v in and maximum on time to make sure the inductor current doesn? exceed 1.4a. i pk = (6) step 7 determine the minimum output capacitance and maxi- mum esr based on the allowable output voltage ripple. c out(min) = (7a) esr (min) = (7b) in practice, it is normally necessary to use a larger capaci- tance value to obtain a low esr. by placing capacitors in parallel, the equivalent esr can be reduced. step 8 compensate the feedback loop to guarantee stability under all operating conditions. to do this, we calculate the modulator gain and the feedback resistor network attenu- ation and set the gain of the error amplifier so that the overall loop gain is 0db at the crossover frequency, f co . in addition, the gain slope should be -20db/decade at the crossover frequency. the low frequency gain of the modulator (i.e. error ampli- fier output to output voltage) is: = , (8a) where i pk(max) = = =2.3a. the v out /v ea transfer function has a pole at: f p = 1/( r load c out ) , (8b) and a zero due to the output capacitor? esr at: f z = 1/(2 esr c out ). (8c) since the error amplifier reference voltage is 1.25v, the output voltage must be divided down or attenuated before being applied to the input of the error amplifier. the feedback resistor divider attenuation is: . the error amplifier in the cs5112 is an operational transcon- ductance amplifier (ota), with a gain given by: g ota = gmz out (8d) where: gm = . (8e) for the cs5112, gm = 2700a/v typical. one possible error amplifier compensation scheme is shown in figure 9. this gives the error amplifier a gain plot as shown in figure 10. for the error amplifier gain shown in figure 10, a low fre- quency pole is generated by the error amplifier output impedance and c 1 . this is shown by the line ab with a - 20db/decade slope in figure 12. the slope changes to zero at point b due to the zero at: f z = 1/(2 r 4 c 1 ). (8f) figure 9. rc network used to compensate the error amplifier (ota). v out v fb1 v fb2 m u x select error amplifier 1.25v + c 1 r 4 c 2 r 1 r 2 r 3 ? i out ? v in 1.25v v out (2.4v)/(7) 150m ? v ea(max) /g csa r s r load lf 2 i pk(max) v ea(max) ? v out ? v ea ? v ripple i pk i pk 8f ? v ripple v in(min) t on(max) l (min) f sw(min) v in 2 (min) t on 2 (max) 2 p out / ] 1 f sw(min) [ ] 1 - v in(min) v out(max) [
9 cs5112 application notes: continued 25 0 05 v reg (v) 50 75 100 10 20 25 i lin (ma) 15 30 ja = 35 c/w v in = 14v max total power = 1.86w 25 0 05 v reg (v) 50 75 100 10 20 25 i lin (ma) 15 30 ja = 55 c/w v in = 14v max total power = 1.18w linear regulator output current vs. input voltage * subjecting the cs5112 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it in to thermal limit. figure 10. bode plot of error amplifier (ota) gain and modulator gain added to the feedback resistor divider attenuation. a pole at point c: f p = 1/( r 4 c 2 ), (8g) offsets the zero set by the esr of the output capacitors. an alternative scheme uses a single capacitor as shown in figure 11, to roll the gain off at a relatively low frequency. figure 11. a typical application diagram with external components con- figured in a boost topology. step 9 finally the watchdog timer period and power on reset time is determined by: t delay = 1.353 c delay r bias . (9) v in nc nc v sw gnd gnd gnd gnd v fb1 v fb2 select comp v reg v lin i bias gnd gnd gnd gnd c delay wdi c osc r bias = 64.9k ? 100 f esr<8 ? 0.1 f c comp 0.33 f l=33 h v in c out 88 f (2) 100k ? 946 ? 7.5k ? r 1 r 2 r 3 c delay 390pf c osc cs5112 reset enable (1) v out = 18v, select > 2v v out = 16v, select < 0.8v microprocessor 5v pole due to error amplifier output impedance and c 1 g 0 f z = 1/2 r 4 c 1 +g b a c f p = 1/ r load c out error amplifier gain f co f z = 1/2 esr c out f p = 1/ r 4 c 2 -20db/dec -g gain (db) modulator gain + feedback resistor divider attenuation worst case switcher worst case switcher linear power power available power available v reg v in i lin dissipation ( ja = 55?/w) ( ja = 35?/w) (v) (v) (ma) (w) (w) (w) 20 14 25 0.44 0.74 1.42 20 14 50 0.83 0.35 1.03 20 14 75 1.22 * 0.64 20 14 100 1.60 * 0.26 25 14 25 0.60 0.58 1.26 25 14 50 1.11 0.07 0.75 25 14 75 1.62 * 0.24 25 14 100 2.14 * * figure 12: the shaded area shows the safe operating area of the cs5112 as a function of i lin , v reg , and ja . refer to the table below for typical loads and voltages.
10 part number description CS5112YDWF24 24 lead so wide (internally fused leads) cs5112ydwfr24 24 lead so wide (internally fused leads) (tape & reel) thermal 24 lead so wide data (internally fused leads) r jc typ 9 ?/w r ja typ 55 ?/w package specification package thermal data ordering information d lead count metric english max min max min 24 lead so wide 15.60 15.20 .614 .598 (internally fused leads) package dimensions in mm (inches) cs5112 surface mount wide body (dw); 300 mil wide 1.27 (.050) bsc 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) d 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) ref: jedec ms-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004) on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ?semiconductor components industries, llc, 2000
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