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1 tm file number 4840 hip6304 microprocessor core voltage regulator multi-phase buck pwm controller the hip6304 multi-phase pwm control ic together with its companion gate drivers, the hip6601, hip6602 or hip6603 and intersil mosfets provides a precision voltage regulation system for advanced microprocessors. multiphase power conversion is a marked departure from earlier single phase converter con?urations previously employed to satisfy the ever increasing current demands of modern microprocessors. multi-phase convertors, by distributing the power and load current results in smaller and lower cost transistors with fewer input and output capacitors. these reductions accrue from the higher effective conversion frequency with higher frequency ripple current due to the phase interleaving process of this topology. for example, a two phase convertor operating at 350khz will have a ripple frequency of 700khz. moreover, greater convertor bandwidth of this design results in faster response to load transients. outstanding features of this controller ic include programmable vid codes from the microprocessor that range from 1.30v to 2.05v with a system accuracy of 1%. pull up currents on these vid pins eliminates the need for external pull up resistors. in addition ?roop?compensation, used to reduce the overshoot or undershoot of the core voltage, is easily programmed with a single resistor. another feature of this controller ic is the pgood monitor circuit which is held low until the core voltage increases, during its soft-start sequence, to within 10% of the programmed voltage. over-voltage, 15% above programmed core voltage, results in the converter shutting down and turning the lower mosfets on to clamp and protect the microprocessor. under voltage is also detected and results in pgood low if the core voltage falls 10% below the programmed level. over-current protection reduces the regulator current to less than 25% of the programmed trip value. these features provide monitoring and protection for the microprocessor and power system. features amd athlon ? compatible multi-phase power conversion precision channel current sharing - loss less current sampling - uses r ds(on) precision core voltage regulation - 1% system accuracy over temperature microprocessor voltage identi?ation input - 4-bit vid input - 1.30v to 2.05v in 50mv steps - programmable ?roop?voltage fast transient recovery time over current protection high ripple frequency, (channel frequency) times number channels . . . . . . . . . . . . . . . . . 100khz to 3mhz pinout hip6304 (soic) top view ordering information part number temp. ( o c) package pkg. no. hip6304cb 0 to 70 16 ld soic m16.15 hip6304cb-t 16 ld soic tape and reel hip6304eval1 evaluation platform vid3 vid2 vid1 vid0 en fs/dis vsen pgood pwm1 pwm2 v cc fb isen1 comp isen2 gnd 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 data sheet march 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. athlon is a trademark of advanced micro devices, inc. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000
2 block diagram simpli?d power system diagram d/a current correction ov latch power-on reset (por) x1.15 + - + - uv ovp + - e/a + - pwm pwm oc + - pwm1 pwm2 isen1 isen2 gnd pgood v cc fb i_trip fs/en s state i_tot + - + - + + - clock and three vid0 vid1 vid2 vid3 comp vsen generator sawtooth + x 0.9 en soft- start and fault logic synchronous hip6304 microprocessor vsen vid rectified buck channel synchronous rectified buck channel pwm 1 pwm 2 hip6304
3 typical application - two phase converter using hip6601 gate drivers typical application - two phase converter using a hip6602 gate driver main control hip6304 vid3 vid0 pgood fb +5v comp pwm2 pwm1 isen2 isen1 vsen driver hip6601 pwm vcc boot ugate phase lgate v in = +5v pvcc pwm vcc boot ugate phase lgate v in = +5v driver hip6601 pvcc fs/dis gnd gnd gnd v cc +v core +12v +12v vid2 en vid1 main control hip6304 vid3 vid2 vid1 vid0 fb +5v comp pwm1 pwm2 isen2 vsen fs/dis isen1 gnd v in +12v boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 pwm1 pvcc +5v vcc v in = +12v +12v dual driver hip6602 pgood pgnd v cc +v core pwm2 en gnd hip6304
4 functional pin description vid3 (pin 1), vid2 (pin 2), vid1 (pin 3) and vid0 (pin 4) voltage identification inputs from microprocessor. these pins respond to ttl and 3.3v logic signals. the hip6304 decodes vid bits to establish the output voltage. see table 1. en (pin 5) enable pin normal operation is with input open or high. a low input disables the regulator and three states the pwm outputs. comp (pin 6) output of the internal error ampli?r. connect this pin to the external feedback and compensation network. fb (pin 7) inverting input of the internal error ampli?r. fs/dis (pin 8) channel frequency, f sw , select and disable. a resistor from this pin to ground sets the switching frequency of the converter. pulling this pin to ground disables the converter and three states the pwm outputs. see figure 10. gnd (pin 9) bias and reference ground. all signals are referenced to this pin. vsen (pin 10) power good monitor input. connect to the microprocessor- core voltage. isen2 (pin 11) and isen1 (pin 14) current sense inputs from the individual converter channels phase nodes. pwm2 (pin 12) and pwm1 (pin 13) pwm outputs for each driven channel in use. connect these pins to the pwm input of a hip6601/2/3 driver. pgood (pin 15) power good. this pin provides a logic-high signal when the microprocessor core voltage (vsen pin) is within speci?d limits and soft-start has timed out. v cc (pin 16) bias supply. connect this pin to a 5v supply. figure 1. simplified block diagram of the hip6304 voltage and current control loops for a two power channel regulator current sensing comparator pwm circuit + r isen1 + correction error amplifier fb reference i sen1 r in v core q3 q4 l 02 phase pwm1 i l2 dac hip6304 c out r load v in hip6601 - q1 q2 l 01 phase i l1 v in hip6601 current sensing comparator pwm circuit correction pwm2 - i average + + + - programmable r isen2 i sen2 - - - - + + current averaging vid3 vid2 vid1 vid0 en fs/dis vsen pgood pwm1 pwm2 v cc fb isen1 comp isen2 gnd 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 hip6304
5 absolute maximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7v input, output, or i/o voltage . . . . . . . . . . gnd -0.3v to v cc + 0.3v esd classi?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class tbd recommended operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal information thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stress above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation o f the device at these or any other conditions above those indicated in the operational section of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations operating conditions: v cc = 5v, t a = 0 o c to 70 o c, unless otherwise speci?d parameter test conditions min typ max units input supply power input supply current r t = 100k ? , active and disabled maximum limit - 10 15 ma por (power-on reset) threshold v cc rising 4.25 4.38 4.5 v v cc falling 3.75 3.88 4.00 v reference and dac system accuracy percent system deviation from programmed vid codes -1 - 1 % dac (vid0 - vid3) input low voltage dac programming input low threshold voltage - - 0.8 v dac (vid0 - vid3) input high voltage dac programming input high threshold voltage 2.0 - - v vid pull-up vidx = 0v or vidx = 3v 10 20 40 a channel generator frequency, f sw r t = 100k ? , 1% 245 275 305 khz adjustment range see figure 10 0.05 - 1.5 mhz disable voltage maximum voltage at fs/dis to disable controller. i fs/dis = 1ma. - - 1.0 v error amplifier dc gain r l = 10k to ground - 72 - db gain-bandwidth product c l = 100pf, r l = 10k to ground - 18 - mhz slew rate c l = 100pf, load = 400 a - 5.3 - v/ s maximum output voltage r l = 10k to ground, load = 400 a 3.6 4.1 - v minimum output voltage r l = 10k to ground, load = -400 a - 0.16 0.5 v i sen full scale input current -50- a over-current trip level - 82.5 - a power good monitor under-voltage threshold vsen rising - 0.92 - v dac under-voltage threshold vsen falling - 0.90 - v dac pgood low output voltage i pgood = 4ma - 0.18 0.4 v protection over-voltage threshold vsen rising 1.12 1.15 1.2 v dac percent over-voltage hysteresis vsen falling after over-voltage - 2 - % hip6304
6 operation figure 1 shows a simpli?d diagram of the voltage regulation and current control loops. both voltage and current feedback are used to precisely regulate voltage and tightly control output currents, i l1 and i l2 , of the two power channels. the voltage loop comprises the error ampli?r, comparators, gate drivers and output mosfets. the error ampli?r is essentially connected as a voltage follower that has as an input, the programmable reference dac and an output that is the core voltage. voltage loop feedback from the core voltage is applied via resistor r in to the inverting input of the error ampli?r. this signal can drive the error ampli?r output either high or low, depending upon the core voltage. low core voltage makes the ampli?r output move towards a higher output voltage level. ampli?r output voltage is applied to the positive inputs of the comparators via the correction summing networks. out- of-phase sawtooth signals are applied to the two comparators inverting inputs. increasing error ampli?r voltage results in increased comparator output duty cycle. this increased duty cycle signal is passed through the pwm circuit with no phase reversal and on to the hip6601, again with no phase reversal for gate drive to the upper mosfets, q1 and q3. increased duty cycle or on time for the mosfet transistors results in increased output voltage to compensate for the low output voltage sensed. current loop the current control loop works in a similar fashion to the voltage control loop, but with current control information applied individually to each channels comparator. the information used for this control is the voltage that is developed across r ds(on) of each lower mosfet, q2 and q4, when they are conducting. a single resistor converts and scales the voltage across the mosfets to a current that is applied to the current sensing circuit within the hip6304. output from these sensing circuits is applied to the current averaging circuit. each pwm channel receives the difference current signal from the summing circuit that compares the average sensed current to the individual channel current. when a power channels current is greater than the average current, the signal applied via the summing correction circuit to the comparator, reduces the output pulse width of the comparator to compensate for the detected ?bove average?current in that channel. droop compensation in addition to control of each power channels output current, the average channel current is also used to provide core voltage ?roop?compensation. average full channel current is de?ed as 50 a. by selecting an input resistor, r in , the amount of voltage droop required at full load current can be programmed. the average current driven into the fb pin results in a voltage increase across resistor r in that is in the direction to make the error ampli?r ?ee?a higher voltage at the inverting input, resulting in the error ampli?r adjusting the output voltage lower. the voltage developed across r in is equal to the ?roop?voltage. see the ?urrent sensing and balancing?section for more details. applications and convertor start-up each pwm power channels current is regulated. this enables the pwm channels to accurately share the load current for enhanced reliability. the hip6601, hip6602 or hip6603 mosfet driver interfaces with the hip6304. for more information, see the hip6601, hip6602 or hip6603 data sheets. the hip6304 controls the two pwm power channels 180 degrees out of phase. figure 2 shows the out of phase relationship between the two pwm channels. power supply ripple frequency is determined by the channel frequency, f sw , multiplied by the number of active channels. for example, if the channel frequency is set to 250khz, the ripple frequency is 500khz. the ic monitors and precisely regulates the core voltage of a microprocessor. after initial start-up, the controller also provides protection for the load and the power supply. the following section discusses these features. initialization the hip6304 usually operates from an atx power supply. many functions are initiated by the rising supply voltage to the v cc pin of the hip6304. oscillator, sawtooth generator, soft- start and other functions are initialized during this interval. these circuits are controlled by por, power-on reset. during this interval, the pwm outputs are driven to a three state condition that makes these outputs essentially open. this state results in no gate drive to the output mosfets. once the v cc voltage reaches 4.375v ( +125mv), a voltage level to insure proper internal function, the pwm outputs are enabled and the soft-start sequence is initiated. if for any reason, the v cc voltage drops below 3.875v ( +125mv). the por circuit shuts the converter down and again three states the pwm outputs. soft-start after the por function is completed with v cc reaching 4.375v, the soft-start sequence is initiated. soft-start, by its slow rise in core voltage from zero, avoids an over-current pwm 1 pwm 2 figure 2. two phase pwm output at 500khz hip6304
7 condition by slowly charging the discharged output capacitors. this voltage rise is initiated by an internal dac that slowly raises the reference voltage to the error ampli?r input. the voltage rise is controlled by the oscillator frequency and the dac within the hip6304, therefore, the output voltage is effectively regulated as it rises to the ?al programmed core voltage value. for the ?st 32 pwm switching cycles, the dac output remains inhibited and the pwm outputs remain three stated. from the 33rd cycle and for another, approximately 150 cycles the pwm output remains low, clamping the lower output mosfets to ground, see figure 3. the time variability is due to the error ampli?r, sawtooth generator and comparators moving into their active regions. after this short interval, the pwm outputs are enabled and increment the pwm pulse width from zero duty cycle to operational pulse width, thus allowing the output voltage to slowly reach the core voltage. the core voltage will reach its programmed value before the 2048 cycles, but the pgood output will not be initiated until the 2048th pwm switching cycle. the soft-start time or delay time, dt = 2048/f sw . for an oscillator frequency, f sw , of 200khz, the first 32 cycles or 160 s, the pwm outputs are held in a three state level as explained above. after this period and a short interval described above, the pwm outputs are initiated and the voltage rises in 10.08ms, for a total delay time dt of 10.24ms. figure 3 shows the start-up sequence as initiated by a fast rising 5v supply, v cc, applied to the hip6304. note the short rise to the three state level in pwm 1 output during ?st 32 pwm cycles. figure 4 shows the waveforms when the regulator is operating at 200khz. note that the soft-start duration is a function of the channel frequency as explained previously. also note the pulses on the comp terminal. these pulses are the current correction signal feeding into the comparator input (see the block diagram on page 2). figure 5 shows the regulator operating from an atx supply. in this ?ure, note the slight rise in pgood as the 5v supply rises. the pgood output stage is made up of nmos and pmos transistors. on the rising v cc , the pmos device becomes active slightly before the nmos transistor pulls ?own? generating the slight rise in the pgood voltage. note that figure 5 shows the 12v gate driver voltage available before the 5v supply to the hip6304 has reached its threshold level. if conditions were reversed and the 5v supply was to rise ?st, the start-up sequence would be different. in this case the hip6303 will sense an over-current condition due to charging the output capacitors. the supply will then restart and go through the normal soft-start cycle. . pwm 1 pgood v core 5v output v cc v in = 12v delay time figure 3. start-up of a system operating at 500khz pgood v core 5v v comp v cc v in = 12v delay time figure 4. start-up a system operating at 200khz 12v atx supply pgood 5 v atx v core supply atx supply activated by atx ?s-on pin frequency 200khz v in = 5v, core load current = 31a figure 5. supply powered by atx supply hip6304
8 fault protection the hip6304 protects the microprocessor and the entire power system from damaging stress levels. within the hip6304 both over-voltage and over-current circuits are incorporated to protect the load and regulator. over-voltage the vsen pin is connected to the microprocessor core voltage. a core over-voltage condition is detected when the vsen pin goes more than 15% above the programmed vid level. the over-voltage condition is latched, disabling normal pwm operation, and causing pgood to go low. the latch can only be reset by lowering and returning v cc high to initiate a por and soft-start sequence. during a latched over-voltage, the pwm outputs will be driven either low or three state, depending upon the vsen input. pwm outputs are driven low when the vsen pin detects that the core voltage is 15% above the programmed vid level. this condition drives the pwm outputs low, resulting in the lower or synchronous recti?r mosfets to conduct and shunt the core voltage to ground to protect the load. if after this event, the core voltage falls below the over- voltage limit (plus some hysteresis), the pwm outputs will three state. the hip6601 family drivers pass the three state information along, and shuts off both upper and lower mosfets. this prevents ?umping of the output capacitors back through the lower mosfets, avoiding a possibly destructive ringing of the capacitors and output inductors. if the conditions that caused the over-voltage still persist, the pwm outputs will be cycled between three state and v core clamped to ground, as a hysteretic shunt regulator. under-voltage the vsen pin also detects when the core voltage falls more than 10% below the vid programmed level. this causes pgood to go low, but has no other effect on operation and is not latched. there is also hysteresis in this detection point. over-current in the event of an over-current condition, the over-current protection circuit reduces the average current delivered to less than 25% of the current limit. when an over-current condition is detected, the controller forces all pwm outputs into a three state mode. this condition results in the gate driver removing drive to the output stages. the hip6304 goes into a wait delay timing cycle that is equal to the soft- start ramp time. pgood also goes ?ow?during this time due to vsen going below its threshold voltage. to lower the average output dissipation, the soft-start initial wait time is increased from 32 to 2048 cycles, then the soft-start ramp is initiated. at a pwm frequency of 200khz, for instance, an over-current detection would cause a dead time of 10.24ms, then a ramp of 10.08ms. at the end of the delay, pwm outputs are restarted and the soft-start ramp is initiated. if a short is present at that time, the cycle is repeated. this is the hiccup mode. figure 6 shows the supply shorted under operation and the hiccup operating mode described above. note that due to the high short circuit current, over-current is detected before completion of the start-up sequence so the delay is not quite as long as the normal soft-start cycle. core voltage programming the voltage identi?ation pins (vid0, vid1, vid2, and vid3) set the core output voltage. each vid pin is pulled to v cc by an internal 20 a current source and accepts open-collector/open-drain/open-switch-to-ground or standard low-voltage ttl or cmos signals. table 1 shows the nominal dac voltage as a function of the vid codes. the power supply system is 1% accurate over the operating temperature and voltage range. table 1. voltage identification codes vid3 vid2 vid1 vid0 vdac 1111 1.30 1110 1.35 1101 1.40 1100 1.45 1011 1.50 1010 1.55 1001 1.60 1000 1.65 0111 1.70 0110 1.75 0101 1.80 0100 1.85 0011 1.90 0010 1.95 0001 2.00 0000 2.05 pgood short 50a/div current atx supply activated by atx ?s-on pin supply frequency = 200khz, v in = 12v hiccup mode. supply powered by atx supply core load current = 31a, 5v load = 5a short applied here figure 6. short applied to supply after power-up hip6304
9 current sensing and balancing overview the hip6304 samples the on-state voltage drop across each synchronous recti?r fet, q2, as an indication of the inductor current in that phase, see figure 7. neglecting ac effects (to be discussed later), the voltage drop across q2 is simply r ds(on) (q2) x inductor current (i l ). note that i l , the inductor current, is 1/2 of the total current (i lt ). the voltage at q2s drain, the phase node, is applied to the r isen resistor to develop the i isen current to the hip6304 isen pin. this pin is held at virtual ground, so the current through r isen is i l x r ds(on) (q2) / r isen . the i isen current provides information to perform the following functions: 1. detection of an over-current condition 2. reduce the regulator output voltage with increasing load current (droop) 3. balance the i l currents in the two phases over-current, selecting r isen the current detected through the r isen resistor is averaged with the current detected in the other channel. the averaged current is compared with a trimmed, internally generated current, and used to detect an over-current condition. the nominal current through the r isen resistor should be 50 a at full output load current, and the nominal trip point for over-current detection is 165% of that value, or 82.5 a. therefore, r isen = i l xr ds(on) (q2) / 50 a. for a full load of 25a per phase, and an r ds(on) (q2) of 4m ? , r isen = 2k ? . the over-current trip point would be 165% of 25a, or ~ 41a per phase. the r isen value can be adjusted to change the over-current trip point, but it is suggested to stay within 25% of nominal. droop, selection of r in the average of the currents detected through the r isen resistors is also steered to the fb pin. there is no dc return path connected to the fb pin except for r in , so the average current creates a voltage drop across r in . this drop increases the apparent v core voltage with increasing load current, causing the system to decrease v core to maintain balance at the fb pin. this is the desired ?roop voltage used to maintain v core within limits under transient conditions. with a high dv/dt load transient, typical of high performance microprocessors, the largest deviations in output voltage occur at the leading and trailing edges of the load transient. in order to fully utilize the output-voltage tolerance range, the output voltage is positioned in the upper half of the range when the output is unloaded and in the lower half of the range when the controller is under full load. this droop compensation allows larger transient voltage deviations and thus reduces the size and cost of the output filter components. figure 7. simplified functional block diagram showing current and voltage sampling current sensing comparator pwm circuit averaging current from other channel sawtooth generator + difference r isen + correction error amplifier fb comp reference to other channel i sen r in r fb c c v core q1 q2 comparator reference to over current trip l 01 phase inductor current from other channel pwm i l dac hip6304 c out r load v in only one output hip6601 - - stage shown - + sensing - + - + hip6304
10 r in should be selected to give the desired ?roop voltage at the normal full load current 50 a applied through the r isen resistor (or at a different full load current if adjusted as under ?ver-current, selecting r isen ?above). r in = vdroop / 50 a for a vdroop of 80mv, r in = 1.6k ? the ac feedback components, r fb and cc, are scaled in relation to r in . current balancing the detected currents are also used to balance the phase currents. each phases current is compared to the average of the two phase currents, and the difference is used to create an offset in that phases pwm comparator. the offset is in a direction to reduce the imbalance. the balancing circuit can not make up for a difference in r ds(on) between synchronous rectifiers. if a fet has a higher r ds(on) , the current through that phase will be reduced. figures 8 and 9 show the inductor current of a two phase system without and with current balancing. inductor current the inductor current in each phase of a multi-phase buck converter has two components. there is a current equal to the load current divided by the number of phases (i lt / n), and a sawtooth current, (i pk-pk ) resulting from switching. the sawtooth component is dependent on the size of the inductors, the switching frequency of each phase, and the values of the input and output voltage. ignoring secondary effects, such as series resistance, the peak to peak value of the sawtooth current can be described by: i pk-pk = (v in x v core - v core 2 ) / (l x f sw x v in ) where: v core = dc value of the output or v id voltage v in = dc value of the input or supply voltage l = value of the inductor f sw = switching frequency example: for v core = 1.6v, v in = 12v, l = 1.3 h, f sw = 250khz, then i pk-pk = 4.3a the inductor, or load current, ?ws alternately from v in through q1 and from ground through q2. the hip6304 samples the on-state voltage drop across each q2 transistor to indicate the inductor current in that phase. the voltage drop is sampled 1/3 of a switching period, 1/f sw , after q1 is turned off and q2 is turned on. because of the sawtooth current component, the sampled current is different from the average current per phase. neglecting secondary effects, the sampled current (i sample ) can be related to the load current (i lt ) by: i sample = i lt /n+ (v in v core -3v core 2 ) / (6l x f sw xv in ) where: i lt = total load current n = the number of channels 0 5 10 15 20 25 amperes figure 8. two channel multiphase system with current balancing disabled 0 5 10 15 20 25 amperes figure 9. two channel multiphase system with current balancing enabled hip6304 hip6304
11 example: using the previously given conditions, and for i lt = 50a, n= 2 then i sample = 25.49a as discussed previously, the voltage drop across each q2 transistor at the point in time when current is sampled is r dson (q2) x i sample . the voltage at q2s drain, the phase node, is applied through the r isen resistor to the hip6304 isen pin. this pin is held at virtual ground, so the current into isen is: i sense = i sample x r ds(on) (q2) / r isen . r isen = i sample x r ds(on) (q2) / 50 a example: from the previous conditions, where i lt = 50a, i sample = 25.49a, r ds(on) (q2) = 4m ? then: r isen = 2.04k and i current trip = 165% short circuit i lt = 82.5a. channel frequency oscillator the channel oscillator frequency is set by placing a resistor, r t , to ground from the fs/dis pin. figure 10 is a curve showing the relationship between frequency, f sw, and resistor r t . to avoid pickup by the fs/dis pin, it is important to place this resistor next to the pin. if this pin is also used to disable the converter, it is also important to locate the pull- down device next to this pin. layout considerations mosfets switch very fast and ef?iently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade ef?iency, radiate noise into the circuit and lead to device over-voltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current stops ?wing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. contact intersil for evaluation board drawings of the component placement and printed circuit board. there are two sets of critical components in a dc-dc converter using a hip6304 controller and a hip6601 gate driver. the power components are the most critical because they switch large amounts of energy. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. the power components should be placed ?st. locate the input capacitors close to the power switches. minimize the length of the connections between the input capacitors, c in , and the power switches. locate the output inductors and output capacitors between the mosfets and the load. locate the gate driver close to the mosfets. the critical small components include the bypass capacitors for vcc and pvcc on the gate driver ics. locate the bypass capacitor, c bp , for the hip6304 controller close to the device. it is especially important to locate the resistors associated with the input to the ampli?rs close to their respective pins, since they represent the input to feedback ampli?rs. resistor r t , that sets the oscillator frequency should also be located next to the associated pin. it is especially important to place the r sen resistor(s) at the respective terminals of the hip6304. a multi-layer printed circuit board is recommended. figure 11 shows the connections of the critical components for one output channel of the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually the middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to inductor l o1 short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for 50 100 10 20 200 500 1,000 5,000 10,000 2,000 1 2 5 10 20 50 100 200 500 1,000 r t (k ? ) channel oscillator frequency, f sw (khz) figure 10. resistance r t vs frequency hip6304
12 the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring traces from the driver ic to the mosfet gate and source should be sized to carry at least one ampere of current. component selection guidelines output capacitor selection the output capacitor is selected to meet both the dynamic load requirements and the voltage ripple requirements. the load transient for the microprocessor core is characterized by high slew rate (di/dt) current demands. in general, multiple high quality capacitors of different size and dielectric are paralleled to meet the design constraints. modern microprocessors produce severe transient load rates. high frequency capacitors supply the initially transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on speci? decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitors esr determines the output ripple voltage and the initial voltage drop following a high slew-rate transients edge. in most cases, multiple capacitors of small case size perform better than a single large case capacitor. bulk capacitor choices include aluminum electrolytic, os- con, tantalum and even ceramic dielectrics. an aluminum electrolytic capacitors esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a speci?d parameter. consult the capacitor manufacturer and measure the capacitors impedance with frequency to select a suitable component. output inductor selection one of the parameters limiting the converters response to a load transient is the time required to change the inductor current. small inductors in a multi-phase converter reduces the response time without signi?ant increases in total ripple current. the output inductor of each power channel controls the ripple current. the control ic is stable for channel ripple current (peak-to-peak) up to twice the average current. a single channels ripple current is approximately: the current from multiple channels tend to cancel each other and reduce the total ripple current. figure 12 gives the total ripple current as a function of duty cycle, normalized to the parameter at zero duty cycle. to determine the total ripple current from the number of channels and the duty cycle, multiply the y-axis value by . small values of output inductance can cause excessive power dissipation. the hip6303 is designed for stable operation for ripple currents up to twice the load current. however, for this condition, the rms current is 115% above the value shown in the following mosfet selection and considerations section. with all else fixed, decreasing the inductance could increase the power dissipated in the mosfets by 30%. ? i v in v out f sw xl ------------------------------- - v out v in --------------- - = vo () lf s ? () ? vo () lxf sw () ? v core +12v via connection to ground plane island on power plane layer island on circuit plane layer l o1 c out c in +5v in phase vcc use individual metal runs comp hip6304 pwm r t r in r fb c bp fb vsen isen r sen hip6601 c boot c bp c t v cc fs/dis pvcc locate next to ic pin locate next to fb pin locate next to ic pin(s) isolate output stages for each channel to help locate near transistor figure 11. printed circuit board power planes and islands legend hip6304
13 input capacitor selection the important parameters for the bulk input capacitors are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current required for a multi-phase converter can be approximated with the aid of figure 13. first determine the operating duty ratio as the ratio of the output voltage divided by the input voltage. find the current multiplier from the curve with the appropriate power channels. multiply the current multiplier by the full load output current. the resulting value is the rms current rating required by the input capacitor. use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors should be placed very close to the drain of the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for bulk capacitance, several electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge- current at power-up. the tps series available from avx, and the 593d series from sprague are both surge current tested. mosfet selection and considerations in high-current pwm applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty factor (see the following equations). the conduction losses are the main component of power dissipation for the lower mosfets, q2 and q4 of figure 1. only the upper mosfets, q1 and q3 have signi?ant switching losses, since the lower device turns on and off into near zero voltage. the equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfets body diode. the gate-charge losses are dissipated by the driver ic and don't heat the mosfets. however, large gate-charge increases the switching time, t sw which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance speci?ations. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air ?w. a diode, anode to ground, may be placed across q2 and q4 of figure 1. these diodes function as a clamp that catches the negative inductor swing during the dead time between the turn off of the lower mosfets and the turn on of the upper mosfets. the diodes must be a schottky type to prevent the lossy parasitic mosfet body diode from conducting. it is usually acceptable to omit the diodes and let the body diodes of the lower mosfets clamp the negative inductor swing, but ef?iency could drop one or two percent as a result. the diode's rated reverse breakdown voltage must be greater than the maximum input voltage. 1.0 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) ripple current (a peak-peak ) v o / (l x f sw ) single channel 2 channel 3 channel 4 channel figure 12. ripple current vs duty cycle 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) current multiplier single channel 3 channel 4 channel 2 channel figure 13. current multiplier vs duty cycle p upper i o 2 r ds on () v out v in ------------------------------------------------------------ i o v in t sw f sw 2 --------------------------------------------------------- - + = p lower i o 2 r ds on () v in v out () v in -------------------------------------------------------------------------------- - = hip6304
14 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 small outline plastic packages (soic) notes: 1. symbols are defined in the ?o series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 0 12/93 hip6304

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