m5m54r04aj-10,-12 mitsubishi lsis 4194304-bit (1048576-word by 4-bit) cmos static ram mitsubishi electric address inputs 1 notice: this is not a final specification. some parametric limits are subject to change 2001.5.17 ver.f description the m5m54r04aj is a family of 1048576-word by 4-bit static rams, fabricated with the high performance cmos silicon gate process and designed for high speed application. these devices operate on a single 3.3v supply, and are directly ttl compatible. they include a power down feature as well. application high-speed memory units features ?ast access time m5m54r04aj-10 ... 10ns(max) M5M54R04AJ-12 ... 12ns(max) ?ingle +3.3v power supply ?ully static operation : no clocks, no refresh ?ommon data i/o ?asy memory expansion by s ?hree-state outputs : or-tie capability ?e prevents data contention in the i/o bus ?irectly ttl compatible : all inputs and outputs package m5m54r04aj : 32pin 400mil soj outline 32p0k(soj) data inputs/ outputs write control input chip select input output enable input pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 3 a 2 a 1 a 0 dq 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 w a 16 a 10 a 11 oe a 9 a 8 s a 7 a 6 a 5 a 4 dq 2 dq 3 dq 4 a 13 a 14 a 12 18 17 gnd gnd address inputs address inputs address inputs v cc v cc (0v) (0v) (3.3v) (3.3v)
m5m54r04aj-10,-12 mitsubishi electric mitsubishi lsis 4194304-bit (1048576-word by 4-bit) cmos static ram v i = 0 ~ vcc - 2.0 ~ vcc operating temperature v cc v i v o p d t opr t stg v v v mw - 2.0 ~ 4.6 1000 0 ~ 70 - 65 ~ 150 ta=25? 2 icc s w oe h mode non selection stand by absolute maximum ratings parameter supply voltage input voltage output voltage power dissipation storage temperature (bias) symbol unit conditions with respect to gnd ratings dq high-impedance * pulse width 3ns, in case of dc: - 0.5v the operation mode of the m5m54r04aj is determined by a combination of the device control inputs s, w and oe. each mode is summarized in the function table. a write cycle is executed whenever the low level w overlaps with the low level s. the address must be set-up before the write cycle and must be stable during the entire cycle. the data is latched into a cell on the trailing edge of w or s, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. the output enable input oe directly controls the output stage. setting the oe at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. a read cycle is excuted by setting w at a high level and oe at a low level while s are in an active state (s=l). when setting s at high level, the chip is in a non- selectable mode in which both reading and writing are disable. in this mode, the output stage is in a high- impedance state, allowing or-tie with other chips and memory expansion by s. signal-s controls the power-down feature. when s goes high, power dissapation is reduced extremely. the access time from s is equivalent to the address access time. function - 2.0 ~ vcc+0.5 x x dc electrical characteristics ( ta=0 ~ 70 ? , vcc=3.3v 0.3v,unless otherwise noted) v ih v il v oh v v v vcc+0.3 0.8 2.0 2.4 v ol 0.4 i oh = - 4ma symbol parameter max typ limits min condition unit high-level input voltage low-level input voltage high-level output voltage low-level output voltage v i(s) =v ih v i/o = 0 ~ vcc i i i cc1 i cc2 i cc3 ma ma 220 i oz 2 2 ua ua v i(s) =vcc 3 0.2v other inputs v i 0.2v or v i 3 vcc - 0.2v v i(s) =v il other inpus=3v or 0v output-open(duty 100%) address skew = 0ns ac dc 10 input current active supply current stand by current output current in off-state stand by current (mos level) i ol = 8ma v i(s) =v ih other inpus=3v or 0v output-open(duty 100%) address skew = 0ns t stg(bias) storage temperature - 10 ~ 85 function table 90 200 180 10ns cycle v l write active din l x l read active dout h l l active high-impedance h h 12ns cycle 15ns cycle ma 120 ac dc 40 110 90 10ns cycle 12ns cycle 15ns cycle * * * ? ? ? note 1: direction for current flowing into an ic is positive (no mark). +
m5m54r04aj-10,-12 mitsubishi lsis 4194304-bit (1048576-word by 4-bit) cmos static ram mitsubishi electric c i c o input capacitance output capacitance v i =gnd, v i =25mvrms,f=1mhz v o =gnd, v o =25mvrms,f=1mhz 7 8 pf pf capacitance (ta=0~70 ? , vcc=3.3v 0.3v,unless otherwise noted) symbol parameter limit max typ min test condition unit ac electrical characteristics (ta=0~70 ? , vcc=3.3v 0.3v,unless otherwise noted) 3 input pulse levels .................................... v ih =3.0v, v il =0.0v input rise and fall time .................................................... 3ns input timing reference levels ........................ v ih =1.5v, v il =1.5v output timing reference levels ................. v oh =1.5v, v ol =1.5v output loads ........................................................ fig.1,fig.2 (1)measurement condition 5.0v dq 480 w 255 w fig.2 output load for t , t en dis 5pf (including scope and jig) fig.1 output load note 2: c i ,c o are periodically sampled and are not 100% tested. dq rl=50 w vl=1.5v z0=50 w output + +
m5m54r04aj-10,-12 mitsubishi electric mitsubishi lsis 4194304-bit (1048576-word by 4-bit) cmos static ram 4 (2)read cycle (3)write cycle t cw t w (w) ns 10 12 symbol parameter write cycle time write pulse width (oe low) unit limits max min max min ns ns ns ns ns ns ns ns ns ns ns ns ns t w (w) write pulse width(oe high) 10 12 8 10 t su (a) 1 t h (d) t su (d) t su (s) t rec (w) t dis (w) t en (w) t en (oe) t dis (oe) address setup time(w) chip select setup time data setup time data hold time write recovery time output enable time after oe low output disable time after oe high output disable time after w low output enable time after w high t su (a) 2 address setup time(s) 0 0 0 0 6 6 0 0 0 0 0 0 5 6 5 6 0 0 0 0 8 1 1 10 t su (a-wh) address to w high 10 8 m5m54r04aj-10 M5M54R04AJ-12 ns ns ns ns t cr t a (a) t a (oe) t a (s) symbol parameter read cycle time address access time chip select access time output enable access time unit limits max min max min t v (a) data valid time after address change 2 3 ns ns ns ns ns ns ns 5 6 t dis (s) t dis (oe) output disable time after s high output disable time after oe high 5 6 0 0 5 6 0 0 t en (s) t en (oe) output enable time after s low output enable time after oe low 0 0 2 3 10 12 10 12 10 12 t pu power-up time after chip selection t pd power-down time after chip selection 0 0 10 12 m5m54r04aj-10 M5M54R04AJ-12
m5m54r04aj-10,-12 mitsubishi lsis 4194304-bit (1048576-word by 4-bit) cmos static ram mitsubishi electric 5 (4)timing diagrams a 0~19 read cycle 1 t cr ta (a) tv (a) v ih v il tv (a) previous data valid unknown data valid v oh v ol dq 1~4 w=h s=l oe=l note 5. addresses and s valid prior to oe transition low by (ta(a)-ta(oe)), (ta(s)-ta(oe)) read cycle 2 (note 3) s ta (s) w=h oe=l ten (s) t dis (s) unknown v oh v ol dq 1~4 v ih v il data valid t pu i cc 1 i cc 2 t pd 50% 50% (note 4) (note 4) icc t cr read cycle 3 (note 5) oe ta (oe) w=h s=l ten (oe) t dis (oe) unknown data valid v oh v ol dq 1~4 v ih v il (note 4) t cr (note 4) note 3. addresses valid prior to or coincident with s transition low. 4. transition is measured ?00mv from steady state voltage with specified loading in figure 2.
m5m54r04aj-10,-12 mitsubishi electric mitsubishi lsis 4194304-bit (1048576-word by 4-bit) cmos static ram write cycle (w control mode) a 0~19 w dq 1~4 s t cw t dis (oe) ten (oe) trec (w) oe tsu (s) tsu (a-wh) tsu (d) tsu (a) th (d) ten (w) t dis (w) dq 1~4 (note 6) (note 6) data stable t w (w) (output data) (input data) (note 4) (note 4) hi-z v ih v il v ih v il v ih v il v ih v il v ih v il note 6: hatching indicates the state is don't care. 7: when the falling edge of w is simultaneous or prior to the falling edge of s, the output is maintained in the high impedance. 8: t en ,t dis are periodically sampled and are not 100% tested. write cycle(s control) a 0~19 w dq 1~4 s t cw tw (w) trec (w) tsu (s) tsu (d) tsu (a) th (d) ten (s) t dis (w) dq 1~4 data stable (note 6) (note 4) (output data) (input data) (note 7) (note 4) hi-z v ih v il v oh v ol v ih v il v ih v il v ih v il (note 6) 6 v oh v ol
keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibili ty for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mi tsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. mitsubishi electric 7
|
