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april 2003 1 ? 2001 actel corporation v4.0 sx-a family fpgas ? e u leading-edge performance ? 250 mhz system performance 350 mhz internal performance 3.8 ns clock-to-out (pad-to-pad) specifications 12,000 to 108,000 available system gates up to 360 user-programmable i/o pins up to 2,012 dedicated flip-flops 0.22 /0.25 cmos process technology features hot-swap compliant i/os power-up/down friendly (no sequencing required for supply voltages) 66 mhz pci compliant single-chip solution nonvolatile configurable i/o support for 3.3v/5v pci, 5v ttl, 3.3v lvttl, 2.5v lvcmos2 2.5v, 3.3v, and 5v mixed-voltage operation with 5v input tolerance and 5v drive strength devices support multiple temperature grades configurable weak-resistor pull-up or pull-down for outputs at power-up individual output slew rate control up to 100% resource utilization and 100% pin locking deterministic, user-controllable timing unique in-system diagnostic and verification capability with silicon explorer ii boundary scan testing in compliance with ieee standard 1149.1 (jtag) actel?s secure programming technology with fuselock? prevents reverse engineering and design theft sx-a product profile device a54sx08a a54sx16a a54sx32a a54sx72a capacity typical gates system gates 8,000 12,000 16,000 24,000 32,000 48,000 72,000 108,000 logic modules combinatorial cells 768 512 1,452 924 2,880 1,800 6,036 4,024 register cells dedicated flip-flops maximum flip-flops 256 512 528 990 1,080 1,980 2,012 4,024 maximum user i/os 130 180 249 360 global clocks 3333 quadrant clocks 0004 boundary scan testing yes yes yes yes 3.3v/5v pci yes yes yes yes clock-to-out 4.2 ns 4.6 ns 4.7 ns 5.8 ns input set-up (external) 0 ns 0 ns 0 ns 0 ns speed grades ?f, std, ?1, ?2, ?3 ?f, std, ?1, ?2, ?3 ?f, std, ?1, ?2, ?3 ?f, std, ?1, ?2, ?3 temperature grades c, i, a c, i, m, a c, i, m, a c, i, m, a package (by pin count) pqfp tqfp pbga fbga cqfp* 208 100, 144 ? 144 208 100, 144 ? 144, 256 208 100, 144, 176 329 144, 256, 484 208, 256 208 ? ? 256, 484 208, 256 note: for more information about the cqfp package options, refer to the hirel sx-a datasheet at: www.actel.com/documents/hrsxads.pd f
sx-a family fpgas 2v4.0 ordering information plastic device resources user i/os (including clock buffers) device pqfp 208-pin tqfp 100-pin tqfp 144-pin tqfp 176-pin pbga 329-pin fbga 144-pin fbga 256-pin fbga 484-pin a54sx08a 130 81 113 ? ? 111 ?? a54sx16a 175 81 113 ?? 111 180 ? a54sx32a 174 81 113 147 249 111 203 249 a54sx72a 171 ????? 203 360 contact your actel sales representative for product availability. package definitions pqfp = plastic quad flat pack, tqfp = thin quad flat pack, pbga = 1.27mm plastic ball grid array, fbga = 1.0mm fine pitch ball grid array application (temperature range) blank = commercial (0 to +70 c) i = industrial ( ? 40 to +85 c) m = military ( ? 55 to +125 c) a = automotive ( ? 40 to +125 c) package type bg = 1.27mm plastic ball grid array fg = 1.0mm fine pitch ball grid array pq = plastic quad flat pack tq = thin (1.4mm) quad flat pack cq = ceramic quad flat pack* speed grade blank = standard speed ? 1 = approximately 15% faster than standard ? 2 = approximately 25% faster than standard ? 3 = approximately 35% faster than standard ? f = approximately 40% slower than standard part number a54sx08a = 12,000 system gates a54sx16a = 24,000 system gates a54sx32a = 48,000 system gates a54sx72a = 108,000 system gates package lead count a54sx16 pq 208 2 a = 0.22/0.25 cmos technology a *for more information about the cqfp package options, refer to the hirel sx-a datasheet at: www.actel.com/documents/hrsxads.pd f
v4.0 3 sx-a family fpgas product plan speed grade** application ?fstd?1?2?3 c i ? m a a54sx08a device 100-pin thin quad flat pack (tqfp) ????? ???? 144-pin thin quad flat pack (tqfp) ????? ???? 208-pin plastic quad flat pack (pqfp) ????? ???? 144-pin fine pitch ball grid array (fbga) ????? ???? a54sx16a device 100-pin thin quad flat pack (tqfp) ????? ???? 144-pin thin quad flat pack (tqfp) ????? ???? 208-pin plastic quad flat pack (pqfp) ????? ???? 144-pin fine pitch ball grid array (fbga) ????? ???? 256-pin fine pitch ball grid array (fbga) ????? ???? a54sx32a device 100-pin thin quad flat pack (tqfp) ????? ???? 144-pin thin quad flat pack (tqfp) ????? ???? 176-pin thin quad flat pack (tqfp) ????? ??? ? 208-pin plastic quad flat pack (pqfp) ????? ???? 208-pin ceramic quad flat pack (cqfp)* ????? ??? ? 256-pin ceramic quad flat pack (cqfp)* ????? ??? ? 144-pin fine pitch ball grid array (fbga) ????? ???? 256-pin fine pitch ball grid array (fbga) ????? ???? 329-pin plastic ball grid array (pbga) ????? ??? ? 484-pin fine pitch ball grid array (fbga) ????? ??? ? a54sx72a device 208-pin plastic quad flat pack (pqfp) ????? ???? 208-pin ceramic quad flat pack (cqfp)* ????? ??? ? 256-pin ceramic quad flat pack (cqfp)* ????? ??? ? 256-pin fine pitch ball grid array (fbga) ????? ???? 484-pin fine pitch ball grid array (fbga) ????? ???? contact your actel sales representative for product availability. *for more information about the cqfp package options, refer to the hirel sx-a datasheet at: www.actel.com/documents/hrsxads.pd f applications: c = commercial availability: ? = available **speed grade: ?1 = approx. 15% faster than standard i = industrial ?2 = approx. 25% faster than standard m = military ?3 = approx. 35% faster than standard a = automotive ?f = approx. 40% slower than standard ? only std, ?1, ?2 speed grade ? only std, ? 1 speed grade
sx-a family fpgas 4v4.0 general description actel ? s sx-a family of fpgas features a sea-of-modules architecture that delivers high device performance. sx-a devices simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time-to-market for performance-intensive applications. actel ? s sx-a architecture features two types of logic modules, the combinatorial cell (c-cell) and the register cell (r-cell), each optimized for fast and efficient mapping of synthesized logic functions. the routing and interconnect resources are in the metal layers above the logic modules, providing optimal use of silicon. this enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or ? sea-of-modules ? ), which reduces the distance signals have to travel between logic modules. to minimize signal propagation delay, sx-a devices employ both local and general routing resources. the high-speed local routing resources (directconnect and fastconnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. the general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or i/o module. within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (90 percent of connections typically use only three or fewer antifuses). the unique local and general routing structure featured in sx-a devices gives fast and predictable performance, allows 100% pin-locking with full logic utilization, enables concurrent pcb development, reduces design time, and allows designers to achieve performance goals with minimum effort. further complementing sx-a ? s flexible routing structure is a hardwired, constantly loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the i/o cells to achieve fast clock-to-out or fast input set-up times. sx-a devices have easy-to-use i/o cells that do not require hdl instantiation, facilitating design re-use and reducing design and verification time. sx-a family architecture the sx-a family architecture was designed to satisfy performance and integration requirements for production-volume designs in a broad range of applications. programmable interconnect element the sx-a family provides efficient use of silicon by locating the routing interconnect resources between the top two metal layers ( figure 1 ). this completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on sram fpgas and previous generations of antifuse fpgas), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. note: a54sx72a has four layers of metal with the antifuse between metal 3 and metal 4. a54sx08a, a54sx16a, and a54sx32a have three layers of metal with antifuse between metal 2 and metal 3. figure 1 ? sx-a family interconnect elements silicon substrate metal 4 metal 3 metal 2 metal 1 amorphous silicon/ dielectric antifuse tungsten plug via tungsten plug via tungsten plug contact routing tracks
v4.0 5 sx-a family fpgas interconnection between these logic modules is achieved using actel ? s patented metal-to-metal programmable antifuse interconnect elements. the antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. the extremely small size of these interconnect elements gives the sx-a family abundant routing resources and provides excellent protection against design pirating. reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and since sx-a is a nonvolatile, single-chip solution, there is no configuration bitstream to intercept. additionally, the interconnect (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. logic module design the sx-a family architecture is described as a ? sea-of-modules ? architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. actel ? s sx-a family provides two types of logic modules, the register cell (r-cell) and the combinatorial cell (c-cell). the r-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the s0 and s1 lines) control signals ( figure 2 ). the r-cell registers feature programmable clock polarity selectable on a register-by-register basis. this provides additional flexibility while allowing mapping of synthesized functions into the sx-a fpga. the clock source for the r-cell can be chosen from either the hardwired clock, the routed clocks, or internal logic. the c-cell implements a range of combinatorial functions of up to five inputs ( figure 3 on page 6 ). inclusion of the db input and its associated inverter function increases the number of combinatorial functions that can be implemented in a single module from 800 options (as in previous architectures) to more than 4,000 in the sx-a architecture. an example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-or function into a single c-cell. this facilitates construction of 9-bit parity-tree functions with 1.9 ns propagation delays. at the same time, the c-cell structure is extremely synthesis friendly, simplifying the overall design and reducing synthesis time. figure 2 r-cell directconnect input clka, clkb, internal logic hclk cks ckp clr pre y routed data input s0 s1 dq
sx-a family fpgas 6v4.0 chip architecture the sx-a family ? s chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. module organization actel has arranged all c-cell and r-cell logic modules into horizontal banks called clusters. there are two types of clusters: type 1 contains two c-cells and one r-cell, while type 2 contains one c-cell and two r-cells. to increase design efficiency and device performance, actel has further organized these modules into superclusters ( figure 4 on page 7 ). supercluster 1 is a two-wide grouping of type 1 clusters. supercluster 2 is a two-wide group containing one type 1 cluster and one type 2 cluster. sx-a devices feature more supercluster 1 modules than supercluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. routing resources clusters and superclusters can be connected through the use of two innovative local routing resources called fastconnect and directconnect , which enable extremely fast and predictable interconnection of modules within clusters and superclusters ( figure 5 and figure 6 on page 8 ). this routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. directconnect is a horizontal routing resource that provides connections from a c-cell to its neighboring r-cell in a given supercluster. directconnect uses a hardwired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. fastconnect enables horizontal routing between any two logic modules within a given supercluster and vertical routing with the supercluster immediately below it. only one programmable connection is used in a fastconnect path, delivering a maximum pin-to-pin propagation time of 0.3 ns. in addition to directconnect and fastconnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. actel ? s segmented routing structure provides a variety of track lengths for extremely fast routing between superclusters. the exact combination of track lengths and antifuses within each path is chosen by the 100% automatic place-and-route software to minimize signal propagation delays. clock resources actel ? s high-drive routing structure provides three clock networks ( table 1 ). the first clock, called hclk, is hardwired from the hclk buffer to the clock select mux in each r-cell. hclk cannot be connected to combinatorial logic. this provides a fast propagation path for the clock signal, enabling the 3.8 ns clock-to-out (pad-to-pad) performance of the sx-a devices. the hardwired clock is tuned to provide clock skew less than 0.3 ns worst case. if not used, this pin must be set as low or high on the board. it must not be left floating. figure 7 describes the clock circuit used for the constant load hclk. upon power-up of the sx-a device, four clock pulses must be detected on hclk before the clock signal will be propagated to registers in the design. two additional clocks (clka, clkb) are global clocks that can be sourced from external pins or from internal logic signals within the sx-a device. clka and clkb may be connected to sequential cells or to combinational logic. if figure 3 c-cell d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y
v4.0 7 sx-a family fpgas figure 4 cluster organization figure 5 directconnect and fastconnect for type 1 superclusters type 1 supercluster type 2 supercluster cluster 1 cluster 1 cluster 2 cluster 1 r-cell c-cell d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y directconnect input clka, clkb, internal logic hclk cks ckp clr pre y dq routed data input s0 s1 type 1 superclusters directconnect no antifuses 0.1 ns maximum routing delay fastconnect one antifuse 0.3 ns maximum routing delay routing segments typically 2 antifuses max. 5 antifuses
sx-a family fpgas 8v4.0 clka or clkb pins are not used or sourced from signals, then these pins must be set as low or high on the board. they must not be left floating (except in the a54sx72a where these clocks can be configured as regular i/os and can float). figure 8 describes the clka and clkb circuit used in sx-a devices with the exception of a54sx72a. in addition, the a54sx72a device provides four quadrant clocks (qclka, qclkb, qclkc, qclkd ? corresponding to bottom-left, bottom-right, top-left, and top-right locations on the die, respectively), which can be sourced from external pins or from internal logic signals within the device. each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. if qclks are not used as quadrant clocks, they will behave as regular i/os. bidirectional clock buffers are also available on the a54sx72a. the clka, clkb, and qclk circuits for a54sx72a are shown in figure 9 on page 9 . note that bidirectional clock buffers are only available in a54sx72a. for more information, refer to the ? pin description ? section on page 53 . for more information on how to use quadrant clocks in the a54sx72a device, refer to the global clock networks in actel ? s antifuse device s and using a54sx72a and rt54sx72s quadrant clocks application notes. figure 6 directconnect and fastconnect for type 2 superclusters type 2 superclusters routing segments typically 2 antifuses max. 5 antifuses fastconnect one antifuse 0.3 ns maximum routing delay directconnect no antifuses 0.1 ns maximum routing delay table 1 sx-a clock resources a54sx08a a54sx16a a54sx32a a54sx72a routed clocks (clka, clkb) 2222 hardwired clocks (hclk) 1111 quadrant clocks (qclka, qclkb, qclkc, qclkd) 0004 figure 7 sx-a hclk clock pad constant load clock network hclkbuf note: this does not include the clock pad for hirel a54sx72a. figure 8 sx-a routed clock structure clock network from internal logic clkbuf clkbufi clkint clkinti
v4.0 9 sx-a family fpgas other architectural features technology actel ? s sx-a family is implemented on a high-voltage, twin-well cmos process using 0.22 /0.25 design rules. the metal-to-metal antifuse is comprised of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ( ? on ? state) resistance of 25 ? with capacitance of 1.0 ff for low signal impedance. performance the combination of architectural features described above enables sx-a devices to operate with internal clock frequencies of 350 mhz, enabling very fast execution of even complex logic functions. thus, the sx-a family is an optimal platform upon which to integrate the functionality previously contained in multiple cplds. in addition, designs that previously would have required a gate array to meet performance goals can be integrated into an sx-a device with dramatic improvements in cost and time-to-market. using timing-driven place-and-route tools, designers can achieve highly deterministic device performance. user security the actel fuselock advantage ensures that unauthorized users will not be able to read back the contents of an actel antifuse fpga. in addition to the inherent strengths of the architecture, special security fuses that prevent internal probing and overwriting are hidden throughout the fabric of the device. they are located such that they cannot be accessed or bypassed without destroying the rest of the device, making both invasive and more-subtle noninvasive attacks ineffective against actel antifuse fpgas. look for this symbol to ensure your valuable ip is secure. for more information, refer to actel ? s implementation of security in actel antifuse fpgas application note. i/o modules each user i/o on an sx-a device can be configured as an input, an output, a tristate output, or a bidirectional pin. mixed i/o standards can be set for individual pins, though this is only allowed with the same voltage as the input. these i/os, combined with array registers, can achieve clock-to-output-pad timing as fast as 3.8 ns even without the dedicated i/o registers. in most fpgas, i/o cells that have embedded latches and flip-flops require instantiation in hdl code; this is a design complication not encountered in sx-a fpgas. fast pin-to-pin timing ensures that the device is able to interface with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. all unused i/os are configured as tristate outputs by actel ? s designer software, for maximum flexibility when designing new boards or migrating existing designs. sx-a inputs should be driven by high-speed push-pull devices with a low-resistance pull-up device. if the input voltage is greater than v cci and a fast push-pull device is not used, the high-resistance pull-up of the driver and the internal circuitry of the sx-a i/o may create a voltage divider. this voltage divider could pull the input voltage below specification for some devices connected to the driver. a logic '1' may not be correctly presented in this case. for example, if an open figure 9 a54sx72a routed clock and qclock structure clock network from internal logic from internal logic oe qclkbuf qclkbufi qclkint qclkinti qclkbibuf clkbuf clkbufi clkint clkinti clkbibuf ? e u
sx-a family fpgas 10 v4.0 drain driver is used with a pull-up resistor to 5v to provide the logic ? 1 ? input, and v cci is set to 3.3v on the sx-a device, the input signal may be pulled down by the sx-a input. each i/o module has an available power-up resistor of approximately 50k ? that can configure the i/o in a known state during power-up. just slightly before v cca reaches 2.5v, the resistors are disabled, so the i/os will be controlled by user logic. see table 2 and table 3 for more information concerning available i/o features. hot swapping sx-a i/os can be configured to be hot-swappable in compliance with the compact pci (5.0v) specification. however, note that 3.3v pci device is not hot swappable. during power-up/down (or partial up/down), all i/os are tristated. v cca and v cci do not have to be stable during power-up/down. after the sx-a device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. the device ? s output pins are driven to a high impedance state until normal chip operating conditions are reached. table 4 summarizes the v cca voltage at which the i/os behave according to the user ? s design for an sx-a device at room temperature for various ramp-up rates. the data reported assumes a linear ramp-up profile to 2.5v. for more information on power-up and hot-swapping, refer to the application note, actel sx-a and rt54sx-s devices in hot-swap and cold-sparing applications . table 2 i/o features function description input buffer threshold selections 5v pci, ttl 3.3v pci, lvttl 2.5v lvcmos2 flexible output driver 5v: pci, ttl 3.3v: pci, lvttl 2.5v: lvcmos2 output buffer ? hot-swap ? capability (3.3v pci is not hot swappable) i/o on an unpowered device does not sink current can be used for ? cold-sparing ? selectable on an individual i/o basis individually selectable slew rate, high slew or low slew (the default is high slew rate). the slew is only affected on the falling edge of an output. rising edges of outputs are not affected. power-up individually selectable pull-ups and pull-downs during power-up (default is to power-up in tristate) enables deterministic power-up of device v cca and v cci can be powered in any order table 3 i/o characteristics for all i/o configurations hot swappable slew rate control power-up resistor ttl, lvttl, lvcmos2 yes yes. only affects falling edges of outputs pull-up or pull-down 3.3v pci no no. high slew rate only pull-up or pull-down 5v pci yes no. high slew rate only pull-up or pull-down table 4 power-up time at which i/os become active supply ramp rate 0.25v/ s 0.025v/ s 5v/ms 2.5v/ms 0.5v/ms 0.25v/ms 0.1v/ms 0.025v/ms units s s msmsmsmsmsms a54sx08a 10 96 0.34 0.65 2.7 5.4 12.9 50.8 a54sx16a 10 100 0.36 0.62 2.5 4.7 11.0 41.6 a54sx32a 10 100 0.46 0.74 2.8 5.2 12.1 47.2 a54sx72a 10 100 0.41 0.67 2.6 5.0 12.1 47.2
v4.0 11 sx-a family fpgas boundary-scan testing (bst) all sx-a devices are ieee 1149.1 compliant and offer superior diagnostic and testing capabilities by providing boundary scan testing (bst) and probing capabilities. the bst function is controlled through the special jtag pins (tms, tdi, tck, tdo, and trst). the functionality of the jtag pins is defined by two available modes: dedicated and flexible. tms cannot be employed as user i/o in either mode. dedicated mode in dedicated mode, all jtag pins are reserved for bst; designers cannot use them as regular i/os. an internal pull-up resistor is automatically enabled on both tms and tdi pins, and the tms pin will function as defined in the ieee 1149.1 (jtag) specification. to select dedicated mode, users need to reserve the jtag pins in actel ? s designer software. to reserve the jtag pins, users can check the "reserve jtag" box in "device selection wizard" ( figure 10 ). flexible mode in flexible mode, tdi, tck, and tdo may be employed as either user i/os or as jtag input pins. the internal resistors on the tms and tdi pins are not present in flexible jtag mode. to select the flexible mode, users need to uncheck the "reserve jtag" box in "device selection wizard" in actel ? s designer software. in flexible mode, tdi, tck and tdo pins may function as user i/os or bst pins. the functionality is controlled by the bst tap controller. the tap controller receives two control inputs, tms and tck. upon power-up, the tap controller enters the test-logic-reset state. in this state, tdi, tck and tdo function as user i/os. the tdi, tck, and tdo are transformed from user i/os into bst pins when a rising edge on tck is detected while tms is at logic low. to return to test-logic reset state, tms must be high for at least five tck cycles. an external 10k pull-up resistor to v cci should be placed on the tms pin to pull it high by default. table 5 describes the different configuration requirements of bst pins and their functionality in different modes. trst pin the trst pin functions as a dedicated boundary-scan reset pin when the "reserve jtag test reset" option is selected as shown in figure 10 . an internal pull-up resistor is permanently enabled on the trst pin in this mode. actel recommends connecting this pin to ground in normal operation to keep the jtag state controller in the test-logic-reset state. when jtag is being used, it can be left floating or be driven high. when the "reserve jtag test reset" option is not selected, this pin will function as a regular i/o. if unused as an i/o in the design, it will be configured as a tristated output. probing capabilities sx-a devices also provide an internal probing capability that is accessed with the jtag pins. the silicon explorer ii diagnostic hardware is used to control the tdi, tck, tms and tdo pins to select the desired nets for debugging. the user assigns the selected internal nets in actel ? s silicon explorer ii software to the pra/prb output pins for observation. silicon explorer ii automatically places the device into jtag mode. however, probing functionality is only activated when the trst pin is driven high or left floating, allowing the internal pull-up resistor to pull trst high. if the trst pin is held low, the tap controller remains in the test-logic-reset state so no probing can be performed. however, the user must drive the trst pin high or allow the internal pull-up resistor to pull trst high. when selecting the "reserve probe pin" box as shown in figure 10 , direct the layout tool to reserve the pra and prb pins as dedicated outputs for probing. this "reserve" option is merely a guideline. if the designer assigns user i/os to the pra and prb pins and selects the "reserve probe pin" option, designer layout will override the "reserve probe pin" option and place the user i/os on those pins. to allow probing capabilities, the security fuse must not be programmed. programming the security fuse disables the probe circuitry. table 6 summarizes the possible device configurations for probing once the device leaves the "test-logic-reset" jtag state. figure 10 device selection wizard table 5 boundary-scan pin configurations and functions mode designer "reserve jtag" selection tap controller state dedicated (jtag) checked any flexible (user i/o) unchecked test-logic-reset flexible (jtag) unchecked any except test-logic-reset
sx-a family fpgas 12 v4.0 sx-a probe circuit control pins sx-a devices contain internal probing circuitry that provides built-in access to every node in a design, enabling 100% real-time observation and analysis of a device ? s internal logic nodes without design iteration. the probe circuitry is accessed by silicon explorer ii, an easy to use integrated verification and logic analysis tool that can sample data at 100 mhz (asynchronous) or 66 mhz (synchronous). silicon explorer ii attaches to a pc ? s standard com port, turning the pc into a fully functional 18 channel logic analyzer. silicon explorer ii allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. the silicon explorer ii tool uses the boundary-scan ports (tdi, tck, tms, and tdo) to select the desired nets for verification. the selected internal nets are assigned to the pra/prb pins for observation. figure 11 illustrates the interconnection between silicon explorer ii and the fpga to perform in-circuit verification. design considerations avoid using the tdi, tck, tdo, pra, and prb pins as input or bidirectional ports. since these pins are active during probing, critical input signals through these pins are not available. in addition, do not program the security fuse. programming the security fuse disables the probe circuit. actel recommends that you use a 70 ? series termination resistor on every probe connector (tdi, tck, tms, tdo, pra, prb). the 70 ? series termination is used to prevent data transmission corruption during probing and reading back the checksum. table 6 device configuration options for probe capability (trst pin reserved) jtag mode trst 1 security fuse programmed pra, prb 2 tdi, tck, tdo 2 dedicated low no user i/o 3 probing unavailable flexible low no user i/o 3 user i/o 3 dedicated high no probe circuit outputs probe circuit inputs flexible high no probe circuit outputs probe circuit inputs ?? yes probe circuit secured probe circuit secured notes: 1. if the trst pin is not reserved, the device behaves according to trst=high as described in the table. 2. avoid using the tdi, tck, tdo, pra, and prb pins as input or bidirectional ports. since these pins are active during probing, input signals will not pass through these pins and may cause contention. 3. if no user signal is assigned to these pins, they will behave as unused i/os in this mode. unused pins are automatically tris tated by the designer software. figure 11 probe setup silicon explorer ii serial connection 16 additional channels sx-a fpga 70 ? 70 ? 70 ? 70 ? 70 ? 70 ? tdi tck tms tdo pra prb
v4.0 13 sx-a family fpgas development tool support the sx-a family of fpgas is fully supported by both the actel libero ? integrated design environment and the actel designer fpga development software. actel's designer software provides a comprehensive suite of back-end development tools for fpga development. the designer software includes timing-driven place and route, a world-class integrated static timing analyzer and constraints editor, and a design netlist schematic viewer. libero ide provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. libero ide includes synplicity ? synplify for actel, mentor graphics ? viewdraw for actel, actel's own designer software, model technology ? model sim hdl simulator, and synapticad ? waveformer lite ( figure 12 ). figure 12 design flow synthesis timing simulation functional simulation stimulus generation simulator schematic entry synthesis libraries fuse or bitstream layout compile back-annotate netlistviewer smartpower chipedit and chipviewer pinedit timer static timing analyzer and constraints editor i/o assignments design synthesis and optimization power analysis schematic viewer placement editor silicon sculptor (antifuse and flash families) silicon explorer ii (antifuse and flash families) flashpro (flash families) flashpro lite (proasic plus family) bp microsystems programmers cross-probing user testbench actel device design implementation design implementation programming programming system verification system verification design creation/verification design creation/verification hdl editor actgen macro builder optimization and drc timing driven place-and-route libero tm ide project manager
sx-a family fpgas 14 v4.0 2.5v/3.3v/5v operating conditions 3.3v lvttl and 5v ttl electrical specifications absolute maximum ratings 1 symbol parameter limits units v cci dc supply voltage ? 0.3 to +6.0 v v cca dc supply voltage ? 0.3 to +3.0 v v i input voltage ? 0.5 to +5.75 v v o output voltage ? 0.5 to +v cci v t stg storage temperature ? 65 to +150 c note: 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. devices should not be operated outside the recommended operating conditions. recommended operating conditions parameter commercial industrial military units temperature range 1 0 to +70 ? 40 to +85 ? 55 to +125 c 2.5v power supply range 2.25 to 2.75 2.25 to 2.75 2.25 to 2.75 v 3.3v power supply range 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v 5v power supply range 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 v note: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military. symbol commercial industrial parameter min. max. min. max. units v oh v cci = min v i = v ih or v il (i oh = -1ma) 0.9 v cci 0.9 v cci v v cci = min, v cci v i = v ih or v il (i oh = -8ma) 2.4 2.4 v v ol v cci = min, v cci v i = v ih or v il (i ol = 1ma) 0.4 0.4 v v cci = min, v cci v i = v ih or v il (i ol = 12ma) 0.4 0.4 v v il input low voltage 0.8 0.8 v v ih input high voltage 2.0 v cci + 0.5 2.0 v cci + 0.5 v i il / i ih input leakage current, v in = v cci or gnd ? 10 10 ? 10 10 a i oz 3-state output leakage current ? 10 10 ? 10 10 a t r , t f input transition time t r , t f 10 10 ns c io i/o capacitance 10 10 pf i cc standby current 10 20 ma iv curve * can be derived from the ibis model on the web. note: *the ibis model can be found at www.actel.com/support/support/support_ibis.html.
v4.0 15 sx-a family fpgas pci compliance for the sx-a family the sx-a family supports 3.3v and 5v pci and is compliant with the pci local bus specification rev. 2.1. 2.5v lvcmos2 electrical specifications symbol commercial industrial parameter min. max. min. max. units v oh v dd = min, v i = v ih or v il (i oh = -100 a) 2.1 2.1 v v dd = min, v i = v ih or v il (i oh = -1 ma) 2.0 2.0 v v dd = min, v i = v ih or v il (i oh = -2 ma) 1.7 1.7 v v ol v dd = min, v i = v ih or v il (i ol = 100 a) 0.2 0.2 v v dd = min, v i = v ih or v il (i ol = 1ma) 0.4 0.4 v v dd = min, v i = v ih or v il (i ol = 2 ma) 0.7 0.7 v v il input low voltage, v out v vol(max) -0.3 0.7 -0.3 0.7 v v ih input high voltage, v out v voh(min) 1.7 v dd + 0.3 1.7 v dd + 0.3 v i oz 3-state output leakage current, v out = v cci or gnd ? 10 10 ? 10 10 a t r , t f input transition time t r , t f 10 10 ns c io i/o capacitance 10 10 pf i cc standby current 10 20 ma iv curve 1 can be derived from the ibis model on the web. note: 1. the ibis model can be found at www.actel.com/support/support/support_ibis.html.
sx-a family fpgas 16 v4.0 dc specifications (5v pci operation) symbol parameter condition min. max. units v cca supply voltage for array 2.3 2.7 v v cci supply voltage for i/os 4.75 5.25 v v ih input high voltage 2.0 v cci + 0.5 v v il input low voltage ? 0.5 0.8 v i ih input high leakage current 1 v in = 2.7 70 a i il input low leakage current 1 v in = 0.5 ? 70 a v oh output high voltage i out = ? 2 ma 2.4 v v ol output low voltage 2 i out = 3 ma, 6 ma 0.55 v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf notes: 1. input leakage currents include hi-z output leakage for all bidirectional buffers with tristate outputs. 2. signals without pull-up resistors must have 3 ma low output current. signals requiring pull-up must have 6 ma; the latter inc ludes frame#, irdy#, trdy#, devsel#, stop#, serr#, perr#, lock#, and, when used ad[63::32], c/be[7::4]#, par64, req64#, and ack64#. 3. absolute maximum pin capacitance for a pci input is 10 pf (except for clk).
v4.0 17 sx-a family fpgas ac specifications (5v pci operation) symbol parameter condition min. max. units i oh(ac) switching current high 0 < v out 1.4 1 ? 44 ma 1.4 v out < 2.4 1, 2 ( ? 44 + (v out ? 1.4)/0.024) ma 3.1 < v out < v cci 1, 3 equation a on page 18 (test point) v out = 3.1 3 ? 142 ma i ol(ac) switching current low v out 2.2 1 95 ma 2.2 > v out > 0.55 1 (v out /0.023) ma 0.71 > v out > 0 1, 3 equation b on page 18 (test point) v out = 0.71 3 206 ma i cl low clamp current ? 5 < v in ? 1 ? 25 + (v in + 1)/0.015 ma slew r output rise slew rate 0.4v to 2.4v load 4 15v/ns slew f output fall slew rate 2.4v to 0.4v load 4 15v/ns notes: 1. refer to the v/i curves in figure 13 on page 18 . switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. this specification does not apply to clk and rst#, which are system outputs. ? switching current high ? specifications are not relevant to serr#, inta#, intb#, intc#, and intd#, which are open drain outputs. 2. note that this segment of the minimum current curve is drawn from the ac drive point directly to the dc drive point rather th an toward the voltage rail (as is done in the pull-down curve). this difference is intended to allow for an optional n-channel pull-up. 3. maximum current requirements must be met as drivers pull beyond the last step voltage. equations defining these maximums (a a nd b) are provided with the respective diagrams in figure 13 on page 18 . the equation defined maxima should be met by design. in order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rat e at any point within the transition range. the specified load (diagram below) is optional; i.e., the designer may elect to meet this paramete r with an unloaded output per revision 2.0 of the pci local bus specification. however, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal i ntegrity modeling accounts for this. rise slew rate does not apply to open drain outputs. output buffer 1/2 in. max. 50 pf pin
sx-a family fpgas 18 v4.0 figure 13 shows the 5v pci v/i curve and the minimum and maximum pci drive characteristics of the sx-a family. equation a i oh = 11.9 * (v out ? 5.25) * (v out + 2.45) for v cci > v out > 3.1v equation b i ol = 78.5 * v out * (4.4 ? v out ) for 0v < v out < 0.71v dc specifications (3.3v pci operation) figure 13 5v pci v/i curve for sx-a family ?200.0 ?150.0 ?100.0 ?50.0 0.0 50.0 100.0 150.0 200.0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 voltage out (v) current (ma) i oh i ol i oh min spec i oh max spec i ol min spec i ol max spec symbol parameter condition min. max. units v cca supply voltage for array 2.3 2.7 v v cci supply voltage for i/os 3.0 3.6 v v ih input high voltage 0.5v cci v cci + 0.5 v v il input low voltage ? 0.5 0.3v cci v i ipu input pull-up voltage 1 0.7v cci v i il input leakage current 2 0 < v in < v cci ? 10 +10 a v oh output high voltage i out = ? 500 a 0.9v cci v v ol output low voltage i out = 1500 a 0.1v cci v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf notes: 1. this specification should be guaranteed by design. it is the minimum voltage to which pull-up resistors are calculated to pul l a floated network. designers should ensure that the input buffer is conducting minimum current at this input voltage in applications sens itive to static power utilization. 2. input leakage currents include hi-z output leakage for all bidirectional buffers with tristate outputs. 3. absolute maximum pin capacitance for a pci input is 10 pf (except for clk).
v4.0 19 sx-a family fpgas ac specifications (3.3v pci operation) symbol parameter condition min. max. units i oh(ac) switching current high 0 < v out 0.3v cci 1 ? 12v cci ma 0.3v cci v out < 0.9v cci 1 ( ? 17.1(v cci ? v out )) ma 0.7v cci < v out < v cci 1, 2 equation c on page 20 (test point) v out = 0.7v cc 2 ? 32v cci ma i ol(ac) switching current low v cci > v out 0.6v cci 1 16v cci ma 0.6v cci > v out > 0.1v cci 1 (26.7v out )ma 0.18v cci > v out > 0 1, 2 equation d on page 20 (test point) v out = 0.18v cc 2 38v cci ma i cl low clamp current ? 3 < v in ? 1 ? 25 + (v in + 1)/0.015 ma i ch high clamp current v cci + 4 > v in v cci + 1 25 + (v in ? v cci ? 1)/0.015 ma slew r output rise slew rate 0.2v cci - 0.6v cci load 3 14v/ns slew f output fall slew rate 0.6v cci - 0.2v cci load 3 14v/ns notes: 1. refer to the v/i curves in figure 14 on page 20 . switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. this specification does not apply to clk and rst#, which are system outputs. ? switching current high ? specifications are not relevant to serr#, inta#, intb#, intc#, and intd#, which are open drain outputs. 2. maximum current requirements must be met as drivers pull beyond the last step voltage. equations defining these maximums (c a nd d) are provided with the respective diagrams in figure 14 on page 20 . the equation defined maximum should be met by design. in order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rat e at any point within the transition range. the specified load (diagram below) is optional; i.e., the designer may elect to meet this paramete r with an unloaded output per the latest revision of the pci local bus specification. however, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). rise slew rate does not apply to open drain outputs. output buffer 1/2 in. max. 10 pf 1k/25 ? pin 1k/25 ? pin buffer output 10 pf
sx-a family fpgas 20 v4.0 figure 14 shows the 3.3v pci v/i curve and the minimum and maximum pci drive characteristics of the sx-a family. equation c i oh = (98.0/v cci ) * (v out ? v cci ) * (v out + 0.4v cci ) for 0.7 v cci < v out < v cci equation d i ol = (256/v cci ) * v out * (v cci ? v out ) for 0v < v out < 0.18 v cci figure 14 3.3v pci v/i curve for sx-a family ? 150.0 ? 100.0 ? 50.0 0.0 50.0 100.0 150.0 0 0.5 1 1.5 2 2.5 3 3.5 4 voltage out (v) current (ma) i oh i ol i oh min spec i oh max spec i ol min spec i ol max spec
v4.0 21 sx-a family fpgas junction temperature (t j ) the temperature variable in the designer series software refers to the junction temperature, not the ambient temperature. this is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. equation 1, shown below, can be used to calculate junction temperature. junction temperature = ? t + t a (1) where: t a = ambient temperature ? t = temperature gradient between junction (silicon) and ambient ? t = ja * p (2) p = power ja = junction to ambient of package. ja numbers are located in the package thermal characteristics table below. package thermal characteristics the device junction-to-case thermal characteristic is jc , and the junction-to-ambient air characteristic is ja . the thermal characteristics for ja are shown with two different air flow rates. the maximum junction temperature is 150 c. a sample calculation of the absolute maximum power dissipation allowed for a tqfp 176-pin package at commercial temperature and still air is as follows: for power estimator information, please go to http://www.actel.com/products/tools/index.html . package thermal characteristics package type pin count jc ja still air ja 300 ft/min units thin quad flat pack (tqfp) 100 12 37.5 30 c/w thin quad flat pack (tqfp) 144 11 32 24 c/w thin quad flat pack (tqfp) 176 11 28 21 c/w plastic quad flat pack (pqfp) 1 208 8 30 23 c/w plastic quad flat pack (pqfp) with heat spreader 2 208 3.8 20 17 c/w plastic ball grid array (pbga) 329 3 18 13.5 c/w fine pitch ball grid array (fbga) 144 3.8 38.8 26.7 c/w fine pitch ball grid array (fbga) 256 3.3 30 25 c/w fine pitch ball grid array (fbga) 484 3 20 15 c/w 1. the a54sx08a pq208 has no heat spreader. 2. the sx-a pq208 package has a heat spreader for a54sx16a, a54sx32a, and a54sx72a. maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -- 150 c70 c ? 28 c/w ---------------------------------- - 2.86w = = =
sx-a family fpgas 22 v4.0 sx-a timing model* sample path calculations hardwired clock external setup = (t inyh + t ird2 + t sud ) ? t hckh = 0.5 + 0.4+ 0.7 ? 1.1 = 0.5 ns clock-to-out (pad-to-pad) =t hckh + t rco + t rd1 + t dhl = 1.1 + 0.6 + 0.3 + 2.0= 4.0 ns routed clock external setup = (t inyh + t ird2 + t sud ) ? t rckh = 0.5 + 0.4 + 0.7 ? 1.2= 0.4 ns clock-to-out (pad-to-pad) =t rckh + t rco + t rd1 + t dhl = 1.2+ 0.6 + 0.3 + 2.0 = 4.1 ns note: *values shown for a54sx08a, ? 3, worst-case commercial conditions at 3.3v pci with standard place-and-route. input delays internal delays predicted routing delays output delays i/o module t inyh = 0.5 ns t ird2 = 0.4 ns t ird1 = 0.3 ns combinatorial cell i/o module t dhl = 2.0 ns t rd8 = 1.2 ns t rd4 = 0.7 ns t rd1 = 0.3 ns t pd = 0.8 ns i/o module t dhl = 2.0 ns t rd1 = 0.3 ns t rco = 0.6 ns i/o module t inyh = 1.0 ns t enzl = 1.4 ns t sud = 0.7 ns t hd = 0.0 ns t sud = 0.7 ns t hd = 0.0 ns t rckh = 1.2 ns (100% load) dq register cell routed clock t rd1 = 0.3 ns t rco = 0.6 ns t hckh = 1.1 ns dq register cell hard-wired clock i/o module t dhl = 2.0 ns t enzl = 1.4 ns
v4.0 23 sx-a family fpgas output buffer delays ac test loads input buffer delays c-cell delays to ac test loads (shown below) pad d e tribuff in v cc gnd 50% out v ol v oh 1.5v t dlh 50% 1.5v t dhl en v cc gnd 50% out v ol 1.5v t enzl 50% 10% t enlz en v cc gnd 50% out gnd v oh 1.5v t enzh 50% 90% t enhz v cc load 1 (used to measure load 2 (used to measure enable delays) 35 pf to the output v cc gnd 35 pf to the output r to v cc for t pzl r to gnd for t pzh r = 1 k ? propagation delay) under test under test load 3 (used to measure disable delays) v cc gnd 5 pf to the output r to v cc for t plz r to gnd for t phz r = 1 k ? under test pad y inbuf in 3v 0v 1.5v out gnd v cc 50% 1.5v 50% s a b y s, a, or b out gnd v cc 50% t pd out gnd gnd v cc 50% 50% 50% v cc 50% 50% t pd t pd t pd
sx-a family fpgas 24 v4.0 cell timing characteristics timing characteristics timing characteristics for sx-a devices fall into three categories: family-dependent, device-dependent, and design-dependent. the input and output buffer characteristics are common to all sx-a family members. internal routing delays are device-dependent. design dependency means actual delays are not determined until after placement and routing of the user ? s design are complete. delay values may then be determined by using the timer utility or performing simulation with post-layout delays. critical nets and typical nets propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. critical net delays can then be applied to the most timing critical paths. critical nets are determined by net property assignment prior to placement and routing. up to 6 percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical. long tracks some nets in the design use long tracks. long tracks are special routing resources that span multiple rows, columns, or modules. long tracks employ three to five antifuse connections. this increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically, up to 6 percent of nets in a fully utilized device require long tracks. long tracks contribute approximately 4 ns to 8.4 ns delay. this additional delay is represented statistically in higher fanout routing delays. timing derating sx-a devices are manufactured with a cmos process. therefore, device performance varies according to temperature, voltage, and process changes. minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. temperature and voltage derating factors (normalized to worst-case commercial, t j = 70 c, v cca = 2.3v) (positive edge triggered) d clk clr q d clk q clr t hpwh , t wasyn t hd t sud t hp t hpwl , t rco t clr t rpwl t rpwh preset t preset preset flip-flops v cca junction temperature (t j ) ? 55 c ? 40 c0 c25 c70 c85 c 125 c 2.3v 0.75 0.79 0.88 0.89 1.00 1.04 1.16 2.5v 0.70 0.74 0.82 0.83 0.93 0.97 1.08 2.7v 0.66 0.69 0.79 0.79 0.88 0.92 1.02
v4.0 25 sx-a family fpgas a54sx08a timing characteristics (worst-case commercial conditions, v cca = 2.3v , v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units c-cell propagation delays 1 t pd internal array module 0.8 1.0 1.1 1.3 1.8 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.3 0.3 0.3 0.4 0.6 ns t rd1 fo=1 routing delay 0.3 0.3 0.4 0.5 0.6 ns t rd2 fo=2 routing delay 0.4 0.5 0.5 0.6 0.8 ns t rd3 fo=3 routing delay 0.5 0.6 0.7 0.8 1.1 ns t rd4 fo=4 routing delay 0.7 0.8 0.9 1.0 1.4 ns t rd8 fo=8 routing delay 1.2 1.4 1.5 1.8 2.5 ns t rd12 fo=12 routing delay 1.7 2.0 2.2 2.6 3.6 ns r-cell timing t rco sequential clock-to-q 0.6 0.7 0.8 0.9 1.3 ns t clr asynchronous clear-to-q 0.7 0.8 0.9 1.1 1.6 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.1 1.6 ns t sud flip-flop data input set-up 0.7 0.8 0.9 1.1 1.6 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.3 1.5 1.7 2.0 2.8 ns t recasyn asynchronous recovery time 0.3 0.4 0.4 0.5 0.7 ns t hasyn asynchronous hold time 0.3 0.3 0.3 0.4 0.6 ns input module propagation delays t inyh input data pad-to-y high 0.5 0.6 0.7 0.8 1.1 ns t inyl input data pad-to-y low 0.8 1.0 1.0 1.3 1.8 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 0.3 0.3 0.3 0.4 0.6 ns t ird2 fo=2 routing delay 0.4 0.5 0.5 0.6 0.8 ns t ird3 fo=3 routing delay 0.5 0.6 0.7 0.8 1.1 ns t ird4 fo=4 routing delay 0.7 0.8 0.9 1.0 1.4 ns t ird8 fo=8 routing delay 1.2 1.4 1.5 1.8 2.5 ns t ird12 fo=12 routing delay 1.7 2.0 2.2 2.6 3.6 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance.
sx-a family fpgas 26 v4.0 a54sx08a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v, t j = 70c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.1 1.3 1.5 1.8 2.4 ns t hckl input high to low (pad to r-cell input) 1.1 1.2 1.4 1.6 2.2 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 3.0 ns t hcksw maximum skew 0.2 0.2 0.2 0.3 0.4 ns t hp minimum period 2.8 3.2 3.6 4.2 6.0 ns f hmax maximum frequency 350 310 277 238 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.1 1.2 1.3 1.6 2.2 ns t rckl input high to low (light load) (pad to r-cell input) 1.3 1.4 1.6 1.9 2.6 ns t rckh input low to high (50% load) (pad to r-cell input) 1.2 1.4 1.6 1.9 2.6 ns t rckl input high to low (50% load) (pad to r-cell input) 1.4 1.6 1.9 2.2 3.0 ns t rckh input low to high (100% load) (pad to r-cell input) 1.3 1.5 1.7 2.0 2.8 ns t rckl input high to low (100% load) (pad to r-cell input) 1.5 1.7 2.0 2.3 3.1 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.1 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.1 3.0 ns t rcksw maximum skew (light load) 0.3 0.3 0.3 0.3 0.4 ns t rcksw maximum skew (50% load) 0.3 0.3 0.4 0.4 0.7 ns t rcksw maximum skew (100% load) 0.3 0.3 0.4 0.4 0.7 ns
v4.0 27 sx-a family fpgas a54sx08a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.1 1.2 1.4 1.6 2.4 ns t hckl input high to low (pad to r-cell input) 1.0 1.2 1.3 1.5 2.3 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 3.0 ns t hcksw maximum skew 0.2 0.2 0.2 0.3 0.4 ns t hp minimum period 2.8 3.2 3.6 4.2 6.0 ns f hmax maximum frequency 350 310 277 238 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.0 1.2 1.3 1.6 2.2 ns t rckl input high to low (light load) (pad to r-cell input) 1.3 1.4 1.7 2.0 2.8 ns t rckh input low to high (50% load) (pad to r-cell input) 1.1 1.3 1.5 1.8 2.5 ns t rckl input high to low (50% load) (pad to r-cell input) 1.4 1.5 1.9 2.2 3.1 ns t rckh input low to high (100% load) (pad to r-cell input) 1.2 1.4 1.6 1.9 2.6 ns t rckl input high to low (100% load) (pad to r-cell input) 1.5 1.6 2.0 2.3 3.4 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.1 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.1 3.0 ns t rcksw maximum skew (light load) 0.2 0.3 0.3 0.4 0.4 ns t rcksw maximum skew (50% load) 0.3 0.3 0.4 0.4 0.7 ns t rcksw maximum skew (100% load) 0.3 0.3 0.4 0.4 0.7 ns
sx-a family fpgas 28 v4.0 a54sx08a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.0 1.2 1.4 1.5 2.3 ns t hckl input high to low (pad to r-cell input) 1.0 1.1 1.3 1.5 2.2 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 3.0 ns t hcksw maximum skew 0.2 0.2 0.2 0.3 0.4 ns t hp minimum period 2.8 3.2 3.6 4.2 6.0 ns f hmax maximum frequency 350 310 277 238 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.0 1.1 1.2 1.5 2.0 ns t rckl input high to low (light load) (pad to r-cell input) 1.2 1.4 1.6 1.8 2.6 ns t rckh input low to high (50% load) (pad to r-cell input) 1.1 1.3 1.5 1.8 2.5 ns t rckl input high to low (50% load) (pad to r-cell input) 1.3 1.6 1.9 2.1 3.1 ns t rckh input low to high (100% load) (pad to r-cell input) 1.2 1.4 1.6 1.9 2.6 ns t rckl input high to low (100% load) (pad to r-cell input) 1.4 1.7 2.0 2.2 3.2 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.1 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.1 3.0 ns t rcksw maximum skew (light load) 0.2 0.3 0.3 0.4 0.4 ns t rcksw maximum skew (50% load) 0.3 0.3 0.4 0.4 0.7 ns t rcksw maximum skew (100% load) 0.3 0.3 0.4 0.4 0.7 ns
v4.0 29 sx-a family fpgas a54sx08a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 2.5v lvttl output module timing 1 t dlh data-to-pad low to high 3.2 3.8 4.3 5.0 7.0 ns t dhl data-to-pad high to low 2.6 3.0 3.4 4.0 5.5 ns t dhls data-to-pad high to low ? low slew 11.3 13.0 14.8 17.4 24.4 ns t enzl enable-to-pad, z to l 2.4 2.8 3.2 3.7 5.2 ns t enzls data-to-pad, z to l ? low slew 11.8 13.7 15.5 18.2 25.5 ns t enzh enable-to-pad, z to h 3.4 4.0 4.5 5.3 7.5 ns t enlz enable-to-pad, l to z 2.1 2.5 2.8 3.3 4.7 ns t enhz enable-to-pad, h to z 3.4 4.0 4.5 5.3 7.5 ns d tlh delta low to high 0.031 0.037 0.043 0.051 0.071 ns/pf d thl delta high to low 0.017 0.017 0.023 0.023 0.037 ns/pf d thls delta high to low ? low slew 0.057 0.060 0.071 0.086 0.117 ns/pf note: 1. delays based on 35 pf loading.
sx-a family fpgas 30 v4.0 a54sx08a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 3.3v pci output module timing 1 t dlh data-to-pad low to high 2.0 2.3 2.6 3.0 4.3 ns t dhl data-to-pad high to low 2.0 2.3 2.6 3.0 4.3 ns t enzl enable-to-pad, z to l 1.4 1.7 1.9 2.2 3.1 ns t enzh enable-to-pad, z to h 1.4 1.7 1.9 2.2 3.1 ns t enlz enable-to-pad, l to z 2.5 2.8 3.2 3.8 5.3 ns t enhz enable-to-pad, h to z 2.5 2.8 3.2 3.8 5.3 ns d tlh delta low to high 0.025 0.03 0.03 0.04 0.045 ns/pf d thl delta high to low 0.015 0.015 0.015 0.015 0.025 ns/pf 3.3v lvttl output module timing 2 t dlh data-to-pad low to high 2.7 3.2 3.6 4.2 5.9 ns t dhl data-to-pad high to low 2.5 2.8 3.2 3.8 5.3 ns t dhls data-to-pad high to low ? low slew 9.0 10.4 11.8 13.8 19.4 ns t enzl enable-to-pad, z to l 2.2 2.6 2.9 3.4 4.8 ns t enzls enable-to-pad, z to l ? low slew 15.8 18.9 21.3 25.4 34.9 ns t enzh enable-to-pad, z to h 2.9 3.3 3.7 4.4 6.2 ns t enlz enable-to-pad, l to z 2.9 3.3 3.7 4.4 6.2 ns t enhz enable-to-pad, h to z 2.5 2.8 3.2 3.8 5.3 ns d tlh delta low to high 0.025 0.03 0.03 0.04 0.045 ns/pf d thl delta high to low 0.015 0.015 0.015 0.015 0.025 ns/pf d thls delta high to low ? low slew 0.053 0.053 0.067 0.073 0.107 ns/pf notes: 1. delays based on 10 pf loading and 25 ? resistance. 2. delays based on 35 pf loading.
v4.0 31 sx-a family fpgas a54sx08a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 5.0v pci output module timing 1 t dlh data-to-pad low to high 2.1 2.5 2.8 3.3 4.6 ns t dhl data-to-pad high to low 2.7 3.1 3.5 4.2 5.8 ns t dhls data-to-pad high to low ? low slew 7.4 8.5 9.6 11.3 15.9 ns t enzl enable-to-pad, z to l 1.3 1.5 1.7 2.0 2.8 ns t enzls enable-to-pad, z to l ? low slew 3.5 5.1 5.9 6.9 9.7 ns t enzh enable-to-pad, z to h 1.3 1.5 1.7 2.0 2.8 ns t enlz enable-to-pad, l to z 3.0 3.5 3.9 4.6 6.4 ns t enhz enable-to-pad, h to z 3.0 3.5 3.9 4.6 6.4 ns d tlh delta low to high 0.016 0.016 0.02 0.022 0.032 ns/pf d thl delta high to low 0.026 0.03 0.032 0.04 0.052 ns/pf d thls delta high to low ? low slew 0.04 0.052 0.06 0.07 0.096 ns/pf 5.0v ttl output module timing 2 t dlh data-to-pad low to high 1.9 2.2 2.5 3.0 4.2 ns t dhl data-to-pad high to low 2.5 2.9 3.3 3.9 5.4 ns t dhls data-to-pad high to low ? low slew 6.6 7.6 8.6 10.2 14.2 ns t enzl enable-to-pad, z to l 2.1 2.4 2.7 3.2 4.5 ns t enzls enable-to-pad, z to l ? low slew 7.4 8.4 9.5 11.0 15.4 ns t enzh enable-to-pad, z to h 2.3 2.7 3.1 3.6 5.0 ns t enlz enable-to-pad, l to z 3.6 4.2 4.7 5.6 7.8 ns t enhz enable-to-pad, h to z 3.0 3.5 3.9 4.6 6.4 ns d tlh delta low to high 0.014 0.017 0.017 0.023 0.031 ns/pf d thl delta high to low 0.023 0.029 0.031 0.037 0.051 ns/pf d thls delta high to low ? low slew 0.043 0.046 0.057 0.066 0.089 ns/pf notes: 1. delays based on 50 pf loading. 2. delays based on 35 pf loading
sx-a family fpgas 32 v4.0 a54sx16a timing characteristics (worst-case commercial conditions, v cca = 2.3v , v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units c-cell propagation delays 1 t pd internal array module 0.8 1.0 1.1 1.3 1.8 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.3 0.3 0.3 0.4 0.6 ns t rd1 fo=1 routing delay 0.3 0.3 0.4 0.5 0.6 ns t rd2 fo=2 routing delay 0.4 0.5 0.5 0.6 0.8 ns t rd3 fo=3 routing delay 0.5 0.6 0.7 0.8 1.1 ns t rd4 fo=4 routing delay 0.7 0.8 0.9 1.0 1.4 ns t rd8 fo=8 routing delay 1.2 1.4 1.5 1.8 2.5 ns t rd12 fo=12 routing delay 1.7 2.0 2.2 2.6 3.6 ns r-cell timing t rco sequential clock-to-q 0.6 0.7 0.8 0.9 1.3 ns t clr asynchronous clear-to-q 0.7 0.8 0.9 1.1 1.6 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.1 1.6 ns t sud flip-flop data input set-up 0.7 0.8 0.9 1.1 1.6 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.3 1.5 1.7 2.0 2.8 ns t recasyn asynchronous recovery time 0.3 0.4 0.4 0.5 0.7 ns t hasyn asynchronous removal time 0.3 0.3 0.3 0.4 0.6 ns input module propagation delays t inyh input data pad-to-y high 0.5 0.6 0.7 0.8 1.1 ns t inyl input data pad-to-y low 0.8 1.0 1.0 1.3 1.8 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 0.3 0.3 0.3 0.4 0.6 ns t ird2 fo=2 routing delay 0.4 0.5 0.5 0.6 0.8 ns t ird3 fo=3 routing delay 0.5 0.6 0.7 0.8 1.1 ns t ird4 fo=4 routing delay 0.7 0.8 0.9 1.0 1.4 ns t ird8 fo=8 routing delay 1.2 1.4 1.5 0.8 2.5 ns t ird12 fo=12 routing delay 1.7 2.0 2.2 2.6 3.6 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance.
v4.0 33 sx-a family fpgas a54sx16a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.2 1.5 1.6 1.9 2.9 ns t hckl input high to low (pad to r-cell input) 1.1 1.4 1.5 1.8 2.8 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 3.0 ns t hcksw maximum skew 0.1 0.1 0.1 0.1 0.2 ns t hp minimum period 2.7 3.2 3.6 4.2 6.0 ns f hmax maximum frequency 350 310 277 238 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.2 1.3 1.5 1.8 2.5 ns t rckl input high to low (light load) (pad to r-cell input) 1.3 1.4 1.6 1.9 2.7 ns t rckh input low to high (50% load) (pad to r-cell input) 1.5 1.7 2.0 2.3 3.3 ns t rckl input high to low (50% load) (pad to r-cell input) 1.6 1.8 2.1 2.4 3.4 ns t rckh input low to high (100% load) (pad to r-cell input) 1.7 1.9 2.2 2.6 3.6 ns t rckl input high to low (100% load) (pad to r-cell input) 1.8 2.0 2.3 2.7 3.8 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.1 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.1 3.0 ns t rcksw maximum skew (light load) 0.3 0.4 0.4 0.4 0.6 ns t rcksw maximum skew (50% load) 0.5 0.6 0.7 0.8 1.3 ns t rcksw maximum skew (100% load) 0.5 0.6 0.7 0.8 1.3 ns
sx-a family fpgas 34 v4.0 a54sx16a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.2 1.5 1.6 1.9 2.9 ns t hckl input high to low (pad to r-cell input) 1.1 1.4 1.5 1.8 2.8 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 3.0 ns t hcksw maximum skew 0.1 0.1 0.1 0.1 0.2 ns t hp minimum period 2.7 3.2 3.6 4.2 6.0 ns f hmax maximum frequency 350 310 277 238 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.2 1.3 1.5 1.8 2.4 ns t rckl input high to low (light load) (pad to r-cell input) 1.3 1.4 1.7 2.0 2.8 ns t rckh input low to high (50% load) (pad to r-cell input) 1.5 1.7 2.0 2.3 3.3 ns t rckl input high to low (50% load) (pad to r-cell input) 1.6 1.8 2.1 2.4 3.4 ns t rckh input low to high (100% load) (pad to r-cell input) 1.7 1.9 2.2 2.6 3.6 ns t rckl input high to low (100% load) (pad to r-cell input) 1.8 2.0 2.3 2.7 3.8 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.1 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.1 3.0 ns t rcksw maximum skew (light load) 0.3 0.4 0.4 0.4 0.6 ns t rcksw maximum skew (50% load) 0.5 0.6 0.7 0.8 1.3 ns t rcksw maximum skew (100% load) 0.5 0.6 0.7 0.8 1.3 ns
v4.0 35 sx-a family fpgas a54sx16a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.2 1.4 1.6 1.8 2.8 ns t hckl input high to low (pad to r-cell input) 1.1 1.3 1.5 1.7 2.7 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 3.0 ns t hcksw maximum skew 0.1 0.1 0.1 0.1 0.2 ns t hp minimum period 2.7 3.2 3.6 4.2 6.0 ns f hmax maximum frequency 350 310 277 238 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.1 1.2 1.4 1.7 2.3 ns t rckl input high to low (light load) (pad to r-cell input) 1.2 1.4 1.6 1.8 2.6 ns t rckh input low to high (50% load) (pad to r-cell input) 1.4 1.6 1.8 2.2 3.1 ns t rckl input high to low (50% load) (pad to r-cell input) 1.5 1.7 1.9 2.3 3.4 ns t rckh input low to high (100% load) (pad to r-cell input) 1.6 1.9 2.1 2.5 3.5 ns t rckl input high to low (100% load) (pad to r-cell input) 1.7 2.0 2.2 2.6 4.0 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.1 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.1 3.0 ns t rcksw maximum skew (light load) 0.3 0.4 0.4 0.4 0.6 ns t rcksw maximum skew (50% load) 0.5 0.6 0.7 0.8 1.3 ns t rcksw maximum skew (100% load) 0.5 0.6 0.7 0.8 1.3 ns
sx-a family fpgas 36 v4.0 a54sx16a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 2.5v lvttl output module timing 1 t dlh data-to-pad low to high 3.2 3.8 4.3 5.0 7.0 ns t dhl data-to-pad high to low 2.6 3.0 3.4 4.0 5.5 ns t dhls data-to-pad high to low ? low slew 11.3 13.0 14.8 17.4 24.4 ns t enzl enable-to-pad, z to l 2.4 2.8 3.2 3.7 5.2 ns t enzls data-to-pad, z to l ? low slew 11.8 13.7 15.5 18.2 25.5 ns t enzh enable-to-pad, z to h 3.4 4.0 4.5 5.3 7.5 ns t enlz enable-to-pad, l to z 2.1 2.5 2.8 3.3 4.7 ns t enhz enable-to-pad, h to z 3.4 4.0 4.5 5.3 7.5 ns d tlh delta low to high 0.031 0.037 0.043 0.051 0.071 ns/pf d thl delta high to low 0.017 0.017 0.023 0.023 0.037 ns/pf d thls delta high to low ? low slew 0.057 0.060 0.071 0.086 0.117 ns/pf note: 1. delays based on 35 pf loading .
v4.0 37 sx-a family fpgas a54sx16a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 3.3v pci output module timing 1 t dlh data-to-pad low to high 2.0 2.3 2.6 3.0 4.3 ns t dhl data-to-pad high to low 2.0 2.3 2.6 3.0 4.3 ns t enzl enable-to-pad, z to l 1.4 1.7 1.9 2.2 3.1 ns t enzh enable-to-pad, z to h 1.4 1.7 1.9 2.2 3.1 ns t enlz enable-to-pad, l to z 2.5 2.8 3.2 3.8 5.3 ns t enhz enable-to-pad, h to z 2.5 2.8 3.2 3.8 5.3 ns d tlh delta low to high 0.025 0.03 0.03 0.04 0.045 ns/pf d thl delta high to low 0.015 0.015 0.015 0.015 0.025 ns/pf 3.3v lvttl output module timing 2 t dlh data-to-pad low to high 2.7 3.2 3.6 4.2 5.9 ns t dhl data-to-pad high to low 2.5 2.8 3.2 3.8 5.3 ns t dhls data-to-pad high to low ? low slew 9.0 10.4 11.8 13.8 19.4 ns t enzl enable-to-pad, z to l 2.2 2.6 2.9 3.4 4.8 ns t enzls enable-to-pad, z to l ? low slew 15.8 18.9 21.3 25.4 34.9 ns t enzh enable-to-pad, z to h 2.9 3.3 3.7 4.4 6.2 ns t enlz enable-to-pad, l to z 2.9 3.3 3.7 4.4 6.2 ns t enhz enable-to-pad, h to z 2.5 2.8 3.2 3.8 5.3 ns d tlh delta low to high 0.025 0.03 0.03 0.04 0.045 ns/pf d thl delta high to low 0.015 0.015 0.015 0.015 0.025 ns/pf d thls delta high to low ? low slew 0.053 0.053 0.067 0.073 0.107 ns/pf notes: 1. delays based on 10 pf loading and 25 ? resistance. 2. delays based on 35 pf loading.
sx-a family fpgas 38 v4.0 a54sx16a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 5.0v pci output module timing 1 t dlh data-to-pad low to high 2.1 2.5 2.8 3.3 4.6 ns t dhl data-to-pad high to low 2.73 3.1 3.5 4.2 5.8 ns t dhls data-to-pad high to low ? low slew 7.4 8.5 9.6 11.3 15.9 ns t enzl enable-to-pad, z to l 1.3 1.5 1.7 2.0 2.8 ns t enzls enable-to-pad, z to l ? low slew 3.5 5.1 5.9 6.9 9.7 ns t enzh enable-to-pad, z to h 1.3 1.5 1.7 2.0 2.8 ns t enlz enable-to-pad, l to z 3.0 3.5 3.9 4.6 6.4 ns t enhz enable-to-pad, h to z 3.0 3.5 3.9 4.6 6.4 ns d tlh delta low to high 0.016 0.016 0.02 0.022 0.032 ns/pf d thl delta high to low 0.026 0.03 0.032 0.04 0.052 ns/pf d thls delta high to low ? low slew 0.04 0.052 0.06 0.07 0.096 ns/pf 5.0v ttl output module timing 2 t dlh data-to-pad low to high 1.9 2.2 2.5 3.0 4.2 ns t dhl data-to-pad high to low 2.5 2.9 3.3 3.9 5.4 ns t dhls data-to-pad high to low ? low slew 6.6 7.6 8.6 10.2 14.2 ns t enzl enable-to-pad, z to l 2.1 2.4 2.7 3.2 4.5 ns t enzls enable-to-pad, z to l ? low slew 7.4 8.4 9.5 11.0 15.4 ns t enzh enable-to-pad, z to h 2.3 2.7 3.1 3.6 5.0 ns t enlz enable-to-pad, l to z 3.6 4.2 4.7 5.6 7.8 ns t enhz enable-to-pad, h to z 3.0 3.5 3.9 4.6 6.4 ns d tlh delta low to high 0.014 0.017 0.017 0.023 0.031 ns/pf d thl delta high to low 0.023 0.029 0.031 0.037 0.051 ns/pf d thls delta high to low ? low slew 0.043 0.046 0.057 0.066 0.089 ns/pf notes: 1. delays based on 50 pf loading. 2. delays based on 35 pf loading.
v4.0 39 sx-a family fpgas a54sx32a timing characteristics (worst-case commercial conditions, v cca = 2.3v , v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units c-cell propagation delays 1 t pd internal array module 0.8 1.0 1.1 1.3 1.8 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.3 0.3 0.3 0.4 0.6 ns t rd1 fo=1 routing delay 0.3 0.3 0.4 0.5 0.6 ns t rd2 fo=2 routing delay 0.4 0.5 0.5 0.6 0.8 ns t rd3 fo=3 routing delay 0.5 0.6 0.7 0.8 1.1 ns t rd4 fo=4 routing delay 0.7 0.8 0.9 1.0 1.4 ns t rd8 fo=8 routing delay 1.2 1.4 1.5 1.8 2.5 ns t rd12 fo=12 routing delay 1.7 2.0 2.2 2.6 3.6 ns r-cell timing t rco sequential clock-to-q 0.6 0.7 0.8 0.9 1.3 ns t clr asynchronous clear-to-q 0.7 0.8 0.9 1.1 1.6 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.1 1.6 ns t sud flip-flop data input set-up 0.7 0.8 0.9 1.1 1.6 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.3 1.5 1.7 2.0 2.8 ns t recasyn asynchronous recovery time 0.3 0.4 0.4 0.5 0.7 ns t hasyn asynchronous removal time 0.3 0.3 0.3 0.4 0.6 ns input module propagation delays t inyh input data pad-to-y high 0.5 0.6 0.7 0.8 1.1 ns t inyl input data pad-to-y low 0.8 1.0 1.0 1.3 1.8 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 0.3 0.3 0.3 0.4 0.6 ns t ird2 fo=2 routing delay 0.4 0.5 0.5 0.6 0.8 ns t ird3 fo=3 routing delay 0.5 0.6 0.7 0.8 1.1 ns t ird4 fo=4 routing delay 0.7 0.8 0.9 1.0 1.4 ns t ird8 fo=8 routing delay 1.2 1.4 1.5 1.8 2.5 ns t ird12 fo=12 routing delay 1.7 2.0 2.2 2.6 3.6 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance.
sx-a family fpgas 40 v4.0 a54sx32a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.7 2.0 2.3 2.7 4.1 ns t hckl input high to low (pad to r-cell input) 1.5 1.7 1.9 2.3 3.5 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.2 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.2 3.0 ns t hcksw maximum skew 0.3 0.4 0.4 0.5 0.8 ns t hp minimum period 2.7 3.2 3.6 4.4 6.0 ns f hmax maximum frequency 350 310 277 227 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.7 2.0 2.2 2.6 3.7 ns t rckl input high to low (light load) (pad to r-cell input) 2.1 2.4 2.7 3.2 4.5 ns t rckh input low to high (50% load) (pad to r-cell input) 2.1 2.4 2.8 3.2 4.5 ns t rckl input high to low (50% load) (pad to r-cell input) 2.3 2.5 2.9 3.4 5.0 ns t rckh input low to high (100% load) (pad to r-cell input) 2.5 2.9 3.2 3.8 6.4 ns t rckl input high to low (100% load) (pad to r-cell input) 2.5 2.9 3.2 3.8 6.4 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.2 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.2 3.0 ns t rcksw maximum skew (light load) 0.9 1.0 1.1 1.3 2.2 ns t rcksw maximum skew (50% load) 1.2 1.4 1.6 1.9 3.2 ns t rcksw maximum skew (100% load) 1.3 1.5 1.7 2.0 3.4 ns
v4.0 41 sx-a family fpgas a54sx32a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.7 2.0 2.3 2.7 4.1 ns t hckl input high to low (pad to r-cell input) 1.5 1.7 1.9 2.3 3.5 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.2 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.2 3.0 ns t hcksw maximum skew 0.3 0.4 0.4 0.5 0.8 ns t hp minimum period 2.7 3.2 3.6 4.4 6.0 ns f hmax maximum frequency 350 310 277 227 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.7 2.0 2.2 2.6 3.7 ns t rckl input high to low (light load) (pad to r-cell input) 2.1 2.4 2.8 3.3 4.6 ns t rckh input low to high (50% load) (pad to r-cell input) 2.1 2.4 2.8 3.2 4.5 ns t rckl input high to low (50% load) (pad to r-cell input) 2.3 2.5 2.9 3.4 5.0 ns t rckh input low to high (100% load) (pad to r-cell input) 2.5 2.9 3.2 3.8 6.4 ns t rckl input high to low (100% load) (pad to r-cell input) 2.5 2.9 3.2 3.8 6.4 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.2 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.2 3.0 ns t rcksw maximum skew (light load) 0.9 1.0 1.1 1.3 2.2 ns t rcksw maximum skew (50% load) 1.2 1.4 1.6 1.9 3.2 ns t rcksw maximum skew (100% load) 1.3 1.5 1.7 2.0 3.4 ns
sx-a family fpgas 42 v4.0 a54sx32a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.7 1.9 2.3 2.6 4.0 ns t hckl input high to low (pad to r-cell input) 1.5 1.7 1.9 2.2 3.5 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.2 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.2 3.0 ns t hcksw maximum skew 0.3 0.4 0.4 0.5 0.8 ns t hp minimum period 2.7 3.2 3.6 4.4 6.0 ns f hmax maximum frequency 350 310 277 227 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.6 1.9 2.1 2.5 3.5 ns t rckl input high to low (light load) (pad to r-cell input) 2.0 2.4 2.7 3.1 4.4 ns t rckh input low to high (50% load) (pad to r-cell input) 2.0 2.4 2.7 3.1 2.5 ns t rckl input high to low (50% load) (pad to r-cell input) 2.2 2.5 2.8 3.3 5.5 ns t rckh input low to high (100% load) (pad to r-cell input) 2.5 2.9 3.2 3.8 6.4 ns t rckl input high to low (100% load) (pad to r-cell input) 2.5 2.9 3.2 3.8 6.4 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.2 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.2 3.0 ns t rcksw maximum skew (light load) 0.9 1.0 1.1 1.3 2.0 ns t rcksw maximum skew (50% load) 1.2 1.4 1.6 1.9 3.2 ns t rcksw maximum skew (100% load) 1.3 1.5 1.7 2.0 3.4 ns
v4.0 43 sx-a family fpgas a54sx32a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 2.5v lvttl output module timing 1 t dlh data-to-pad low to high 3.2 3.8 4.3 5.0 7.0 ns t dhl data-to-pad high to low 2.6 3.0 3.4 4.0 5.5 ns t dhls data-to-pad high to low ? low slew 11.3 13.0 14.8 17.4 24.4 ns t enzl enable-to-pad, z to l 2.4 2.8 3.2 3.7 5.2 ns t enzls data-to-pad, z to l ? low slew 11.8 13.7 15.5 18.2 25.5 ns t enzh enable-to-pad, z to h 3.4 4.0 4.5 5.3 7.5 ns t enlz enable-to-pad, l to z 2.1 2.5 2.8 3.3 4.7 ns t enhz enable-to-pad, h to z 3.4 4.0 4.5 5.3 7.5 ns d tlh delta low to high 0.031 0.037 0.043 0.051 0.071 ns/pf d thl delta high to low 0.017 0.017 0.023 0.023 0.037 ns/pf d thls delta high to low ? low slew 0.057 0.060 0.071 0.086 0.117 ns/pf note: 1. delays based on 35 pf loading.
sx-a family fpgas 44 v4.0 a54sx32a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 3.3v pci output module timing 1 t dlh data-to-pad low to high 2.0 2.3 2.6 3.0 4.3 ns t dhl data-to-pad high to low 2.0 2.3 2.6 3.0 4.3 ns t enzl enable-to-pad, z to l 1.4 1.7 1.9 2.2 3.1 ns t enzh enable-to-pad, z to h 1.4 1.7 1.9 2.2 3.1 ns t enlz enable-to-pad, l to z 2.5 2.8 3.2 3.8 5.3 ns t enhz enable-to-pad, h to z 2.5 2.8 3.2 3.8 5.3 ns d tlh delta low to high 0.025 0.03 0.03 0.04 0.045 ns/pf d thl delta high to low 0.015 0.015 0.015 0.015 0.025 ns/pf 3.3v lvttl output module timing 2 t dlh data-to-pad low to high 2.7 3.2 3.6 4.2 5.9 ns t dhl data-to-pad high to low 2.5 2.8 3.2 3.8 5.3 ns t dhls data-to-pad high to low ? low slew 9.0 10.4 11.8 13.8 19.4 ns t enzl enable-to-pad, z to l 2.2 2.6 2.9 3.4 4.8 ns t enzls enable-to-pad, z to l ? low slew 15.8 18.9 21.3 25.4 34.9 ns t enzh enable-to-pad, z to h 2.9 3.3 3.7 4.4 6.2 ns t enlz enable-to-pad, l to z 2.9 3.3 3.7 4.4 6.2 ns t enhz enable-to-pad, h to z 2.5 2.8 3.2 3.8 5.3 ns d tlh delta low to high 0.025 0.03 0.03 0.04 0.045 ns/pf d thl delta high to low 0.015 0.015 0.015 0.015 0.025 ns/pf d thls delta high to low ? low slew 0.053 0.053 0.067 0.073 0.107 ns/pf notes: 1. delays based on 10 pf loading and 25 ? resistance. 2. delays based on 35 pf loading.
v4.0 45 sx-a family fpgas a54sx32a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 5.0v pci output module timing 1 t dlh data-to-pad low to high 2.1 2.5 2.8 3.3 4.6 ns t dhl data-to-pad high to low 2.7 3.1 3.5 4.2 5.8 ns t dhls data-to-pad high to low ? low slew 7.4 8.5 9.6 11.3 15.9 ns t enzl enable-to-pad, z to l 1.3 1.5 1.7 2.0 2.8 ns t enzls enable-to-pad, z to l ? low slew 3.5 5.1 5.9 6.9 9.7 ns t enzh enable-to-pad, z to h 1.3 1.5 1.7 2.0 2.8 ns t enlz enable-to-pad, l to z 3.0 3.5 3.9 4.6 6.4 ns t enhz enable-to-pad, h to z 3.0 3.5 3.9 4.6 6.4 ns d tlh delta low to high 0.016 0.016 0.02 0.022 0.032 ns/pf d thl delta high to low 0.026 0.03 0.032 0.04 0.052 ns/pf d thls delta high to low ? low slew 0.04 0.052 0.06 0.07 0.096 ns/pf 5.0v ttl output module timing 2 t dlh data-to-pad low to high 1.9 2.2 2.5 3.0 4.2 ns t dhl data-to-pad high to low 2.5 2.9 3.3 3.9 5.4 ns t dhls data-to-pad high to low ? low slew 6.6 7.6 8.6 10.2 14.2 ns t enzl enable-to-pad, z to l 2.1 2.4 2.7 3.2 4.5 ns t enzls enable-to-pad, z to l ? low slew 7.4 8.4 9.5 11.0 15.4 ns t enzh enable-to-pad, z to h 2.3 2.7 3.1 3.6 5.0 ns t enlz enable-to-pad, l to z 3.6 4.2 4.7 5.6 7.8 ns t enhz enable-to-pad, h to z 3.0 3.5 3.9 4.6 6.4 ns d tlh delta low to high 0.014 0.017 0.017 0.023 0.031 ns/pf d thl delta high to low 0.023 0.029 0.031 0.037 0.051 ns/pf d thls delta high to low ? low slew 0.043 0.046 0.057 0.066 0.089 ns/pf notes: 1. delays based on 50 pf loading. 2. delays based on 35 pf loading.
sx-a family fpgas 46 v4.0 a54sx72a timing characteristics (worst-case commercial conditions, v cca = 2.3v , v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units c-cell propagation delays 1 t pd internal array module 0.8 1.0 1.1 1.3 1.8 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.3 0.3 0.3 0.4 0.6 ns t rd1 fo=1 routing delay 0.3 0.3 0.4 0.5 0.7 ns t rd2 fo=2 routing delay 0.4 0.5 0.6 0.7 1.0 ns t rd3 fo=3 routing delay 0.5 0.7 0.8 0.9 1.3 ns t rd4 fo=4 routing delay 0.7 0.9 1.0 1.1 1.5 ns t rd8 fo=8 routing delay 1.2 1.5 1.7 2.1 2.9 ns t rd12 fo=12 routing delay 1.7 2.2 2.5 3.0 4.2 ns r-cell timing t rco sequential clock-to-q 0.6 0.7 0.8 0.9 1.3 ns t clr asynchronous clear-to-q 0.7 0.8 0.9 1.1 1.6 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.1 1.6 ns t sud flip-flop data input set-up 0.7 0.8 0.9 1.1 1.6 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.3 1.5 1.7 2.0 2.8 ns t recasyn asynchronous recovery time 0.3 0.4 0.4 0.5 0.7 ns t hasyn asynchronous hold time 0.3 0.3 0.3 0.4 0.6 ns input module propagation delays t inyh input data pad-to-y high 0.5 0.6 0.7 0.8 1.1 ns t inyl input data pad-to-y low 0.8 1.0 1.0 1.3 1.8 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 0.3 0.3 0.4 0.5 0.7 ns t ird2 fo=2 routing delay 0.4 0.5 0.6 0.7 1.0 ns t ird3 fo=3 routing delay 0.5 0.7 0.8 0.9 1.3 ns t ird4 fo=4 routing delay 0.7 0.9 1.0 1.1 1.5 ns t ird8 fo=8 routing delay 1.2 1.5 1.7 2.1 2.9 ns t ird12 fo=12 routing delay 1.7 2.2 2.5 3.0 4.2 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance.
v4.0 47 sx-a family fpgas a54sx72a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.3 1.5 1.7 2.1 3.1 ns t hckl input high to low (pad to r-cell input) 1.1 1.3 1.5 1.9 2.9 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.2 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.2 3.0 ns t hcksw maximum skew 0.7 0.8 0.9 1.0 1.6 ns t hp minimum period 2.8 3.2 3.6 4.4 6.0 ns f hmax maximum frequency 350 310 277 227 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 2.3 2.6 2.9 3.5 4.8 ns t rckl input high to low (light load) (pad to r-cell input) 2.6 3.1 3.4 4.0 5.6 ns t rckh input low to high (50% load) (pad to r-cell input) 3.0 3.5 3.9 4.6 6.5 ns t rckl input high to low (50% load) (pad to r-cell input) 3.3 3.8 4.2 4.9 7.1 ns t rckh input low to high (100% load) (pad to r-cell input) 3.7 4.3 4.8 5.7 8.0 ns t rckl input high to low (100% load) (pad to r-cell input) 4.0 4.6 5.1 6.0 8.6 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.2 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.2 3.0 ns t rcksw maximum skew (light load) 1.8 2.1 2.4 2.7 3.8 ns t rcksw maximum skew (50% load) 1.2 1.4 1.6 1.9 3.2 ns t rcksw maximum skew (100% load) 1.4 1.5 1.7 2.0 3.4 ns
sx-a family fpgas 48 v4.0 a54sx72a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.3 1.5 1.7 2.1 3.1 ns t hckl input high to low (pad to r-cell input) 1.1 1.3 1.5 1.9 2.9 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.2 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.2 3.0 ns t hcksw maximum skew 0.7 0.8 0.9 1.0 1.6 ns t hp minimum period 2.8 3.2 3.6 4.4 6.0 ns f hmax maximum frequency 350 310 277 227 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 2.2 2.6 2.9 3.5 4.8 ns t rckl input high to low (light load) (pad to r-cell input) 2.7 3.1 3.5 4.1 5.7 ns t rckh input low to high (50% load) (pad to r-cell input) 3.0 3.5 3.9 4.6 6.5 ns t rckl input high to low (50% load) (pad to r-cell input) 3.3 3.8 4.2 4.9 7.1 ns t rckh input low to high (100% load) (pad to r-cell input) 3.7 4.3 4.8 5.7 8.0 ns t rckl input high to low (100% load) (pad to r-cell input) 4.0 4.6 5.1 6.0 8.6 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.2 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.2 3.0 ns t rcksw maximum skew (light load) 1.8 2.1 2.4 2.7 3.8 ns t rcksw maximum skew (50% load) 1.2 1.4 1.6 1.9 3.2 ns t rcksw maximum skew (100% load) 1.4 1.5 1.7 2.0 3.4 ns
v4.0 49 sx-a family fpgas a54sx72a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckh input low to high (pad to r-cell input) 1.3 1.4 1.7 2.0 3.0 ns t hckl input high to low (pad to r-cell input) 1.1 1.2 1.5 1.8 2.8 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.2 3.0 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.2 3.0 ns t hcksw maximum skew 0.7 0.8 0.9 1.0 1.6 ns t hp minimum period 2.8 3.2 3.6 4.4 6.0 ns f hmax maximum frequency 350 310 277 227 166 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 2.2 2.5 2.8 3.4 4.6 ns t rckl input high to low (light load) (pad to r-cell input) 2.6 3.0 3.4 3.9 5.5 ns t rckh input low to high (50% load) (pad to r-cell input) 3.0 3.5 3.9 4.6 6.5 ns t rckl input high to low (50% load) (pad to r-cell input) 3.3 3.8 4.2 4.9 7.1 ns t rckh input low to high (100% load) (pad to r-cell input) 3.7 4.3 4.8 5.7 8.0 ns t rckl input high to low (100% load) (pad to r-cell input) 4.0 4.6 5.1 6.0 8.6 ns t rpwh min. pulse width high 1.4 1.6 1.8 2.2 3.0 ns t rpwl min. pulse width low 1.4 1.6 1.8 2.2 3.0 ns t rcksw maximum skew (light load) 1.8 2.1 2.4 2.7 3.8 ns t rcksw maximum skew (50% load) 1.4 1.6 1.9 3.2 ns t rcksw maximum skew (100% load) 1.5 1.7 2.0 3.4 ns
sx-a family fpgas 50 v4.0 a54sx72a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 2.3v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 2.5v lvttl output module timing 1 t dlh data-to-pad low to high 3.3 3.9 4.4 5.2 7.2 ns t dhl data-to-pad high to low 2.6 3.0 3.4 4.0 5.5 ns t dhls data-to-pad high to low ? low slew 11.7 13.5 15.3 18.0 25.9 ns t enzl enable-to-pad, z to l 2.4 2.8 3.2 3.7 5.2 ns t enzls data-to-pad, z to l ? low slew 11.8 13.7 15.5 18.2 25.5 ns t enzh enable-to-pad, z to h 3.4 4.0 4.5 5.3 7.5 ns t enlz enable-to-pad, l to z 2.1 2.5 2.8 3.3 4.7 ns t enhz enable-to-pad, h to z 3.4 4.0 4.5 5.3 7.5 ns d tlh delta low to high 0.031 0.037 0.043 0.051 0.071 ns/pf d thl delta high to low 0.017 0.017 0.023 0.023 0.037 ns/pf d thls delta high to low ? low slew 0.057 0.060 0.071 0.086 0.117 ns/pf note: 1. delays based on 35 pf loading.
v4.0 51 sx-a family fpgas a54sx72a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 3.3v pci output module timing 1 t dlh data-to-pad low to high 2.0 2.3 2.6 3.0 4.3 ns t dhl data-to-pad high to low 2.0 2.3 2.6 3.0 4.3 ns t enzl enable-to-pad, z to l 1.4 1.7 1.9 2.2 3.1 ns t enzh enable-to-pad, z to h 1.4 1.7 1.9 2.2 3.1 ns t enlz enable-to-pad, l to z 2.5 2.8 3.2 3.8 5.3 ns t enhz enable-to-pad, h to z 2.5 2.8 3.2 3.8 5.3 ns d tlh delta low to high 0.025 0.03 0.03 0.04 0.045 ns/pf d thl delta high to low 0.015 0.015 0.015 0.015 0.025 ns/pf 3.3v lvttl output module timing 2 t dlh data-to-pad low to high 2.7 3.2 3.6 4.2 5.9 ns t dhl data-to-pad high to low 2.5 2.8 3.2 3.8 5.3 ns t dhls data-to-pad high to low ? low slew 9.0 10.4 11.8 13.8 19.4 ns t enzl enable-to-pad, z to l 2.2 2.6 2.9 3.4 4.8 ns t enzls enable-to-pad, z to l ? low slew 15.8 18.9 21.3 25.4 34.9 ns t enzh enable-to-pad, z to h 2.9 3.3 3.7 4.4 6.2 ns t enlz enable-to-pad, l to z 2.9 3.3 3.7 4.4 6.2 ns t enhz enable-to-pad, h to z 2.5 2.8 3.2 3.8 5.3 ns d tlh delta low to high 0.025 0.03 0.03 0.04 0.045 ns/pf d thl delta high to low 0.015 0.015 0.015 0.015 0.025 ns/pf d thls delta high to low ? low slew 0.053 0.053 0.067 0.073 0.107 ns/pf notes: 1. delays based on 10 pf loading and 25 ? resistance. 2. delays based on 35 pf loading.
sx-a family fpgas 52 v4.0 a54sx72a timing characteristics (continued) (worst-case commercial conditions v cca = 2.3v, v cci = 4.75v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units 5.0v pci output module timing 1 t dlh data-to-pad low to high 2.1 2.5 2.8 3.3 4.6 ns t dhl data-to-pad high to low 2.7 3.1 3.5 4.2 5.8 ns t dhls data-to-pad high to low ? low slew 7.4 8.5 9.6 11.3 15.9 ns t enzl enable-to-pad, z to l 1.3 1.5 1.7 2.0 2.8 ns t enzls enable-to-pad, z to l ? low slew 3.5 5.1 5.9 6.9 9.7 ns t enzh enable-to-pad, z to h 1.3 1.5 1.7 2.0 2.8 ns t enlz enable-to-pad, l to z 3.0 3.5 3.9 4.6 6.4 ns t enhz enable-to-pad, h to z 3.0 3.5 3.9 4.6 6.4 ns d tlh delta low to high 0.016 0.016 0.02 0.022 0.032 ns/pf d thl delta high to low 0.026 0.03 0.032 0.04 0.052 ns/pf d thls delta high to low ? low slew 0.04 0.052 0.06 0.07 0.096 ns/pf 5.0v ttl output module timing 2 t dlh data-to-pad low to high 1.9 2.2 2.5 3.0 4.2 ns t dhl data-to-pad high to low 2.5 2.9 3.3 3.9 5.4 ns t dhls data-to-pad high to low ? low slew 6.6 7.6 8.6 10.2 14.2 ns t enzl enable-to-pad, z to l 2.1 2.4 2.7 3.2 4.5 ns t enzls enable-to-pad, z to l ? low slew 7.4 8.4 9.5 11.0 15.4 ns t enzh enable-to-pad, z to h 2.3 2.7 3.1 3.6 5.0 ns t enlz enable-to-pad, l to z 3.6 4.2 4.7 5.6 7.8 ns t enhz enable-to-pad, h to z 3.0 3.5 3.9 4.6 6.4 ns d tlh delta low to high 0.014 0.017 0.017 0.023 0.031 ns/pf d thl delta high to low 0.023 0.029 0.031 0.037 0.051 ns/pf d thls delta high to low ? low slew 0.043 0.046 0.057 0.066 0.089 ns/pf notes: 1. delays based on 50 pf loading. 2. delays based on 35 pf loading.
v4.0 53 sx-a family fpgas pin description clka/b clock a and b these pins are clock inputs for clock distribution networks. input levels are compatible with standard ttl, lvttl, 3.3v pci or 5v pci specifications. the clock input is buffered prior to clocking the r-cells. if not used, this pin must be set low or high on the board except a54sx72a. in a54sx72a these clocks can be configured as user i/o. qclka/b/c/d, quadrant clock a, b, c, and d i/o these four pins are the quadrant clock inputs and are only for a54sx72a with a, b, c, and d corresponding to bottom-left, bottom-right, top-left, and top-right quadrants, respectively. they are clock inputs for clock distribution networks. input levels are compatible with standard ttl, lvttl, 3.3v pci or 5v pci specifications. each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. the clock input is buffered prior to clocking the r-cells. if not used as a clock it will behave as a regular i/o. gnd ground low supply voltage. hclk dedicated (hardwired) array clock this pin is the clock input for sequential modules. input levels are compatible with standard ttl, lvttl, 3.3v pci or 5v pci specifications. this input is directly wired to each r-cell and offers clock speeds independent of the number of r-cells being driven. if not used, this pin must be set low or high on the board. it must not be left floating. i/o input/output the i/o pin functions as an input, output, tristate, or bidirectional buffer. based on certain configurations, input and output levels are compatible with standard ttl, lvttl, 3.3v pci or 5v pci specifications. unused i/o pins are automatically tristated by the designer series software. nc no connection this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. the only exception is for the a54sx32a fg-484, where the nc pins must be left floating. pra, i/o probe a/b prb, i/o the probe pin is used to output data from any user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. the probe pin can be used as a user-defined i/o when verification has been completed. the pin ? s probe capabilities can be permanently disabled to protect programmed design confidentiality. tck, i/o test clock test clock input for diagnostic probe and device programming. in flexible mode, tck becomes active when the tms pin is set low (refer to table 5 on page 11 ). this pin functions as an i/o when the boundary scan state machine reaches the ? logic reset ? state. tdi, i/o test data input serial input for boundary scan testing and diagnostic probe. in flexible mode, tdi is active when the tms pin is set low (refer to table 5 on page 11 ). this pin functions as an i/o when the boundary scan state machine reaches the ? logic reset ? state. tdo, i/o test data output serial output for boundary scan testing. in flexible mode, tdo is active when the tms pin is set low (refer to table 5 on page 11 ). this pin functions as an i/o when the boundary scan state machine reaches the "logic reset" state. when silicon explorer ii is being used, tdo will act as an output when the "checksum" command is run. it will return to user io when "checksum" is complete. tms test mode select the tms pin controls the use of the ieee 1149.1 boundary scan pins (tck, tdi, tdo, trst). in flexible mode when the tms pin is set low, the tck, tdi, and tdo pins are boundary scan pins (refer to table 5 on page 11 ). once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the ? logic reset ? state. at this point, the boundary scan pins will be released and will function as regular i/o pins. the ? logic reset ? state is reached 5 tck cycles after the tms pin is set high. in dedicated test mode, tms functions as specified in the ieee 1149.1 specifications. trst, i/o boundary scan reset pin once it is configured as the jtag reset pin, the trst pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. the trst pin is equipped with an internal pull-up resistor. this pin functions as an i/o when the ? reserve jtag reset pin ? is not selected in designer. v cci supply voltage supply voltage for i/os. see ? recommended operating conditions ? table on page 14 . all v cci power pins in the device should be connected. v cca supply voltage supply voltage for array. see ? recommended operating conditions ? table on page 14 . all v cca power pins in the device should be connected.
54 v4.0 package pin assignments 208-pin pqfp (top view) 208-pin pqfp 1 208
v4.0 55 208-pin pqfp pin number a54sx08a function a54sx16a function a54sx32a function a54sx72a function 1gndgndgndgnd 2 tdi, i/o tdi, i/o tdi, i/o tdi, i/o 3 i/o i/o i/o i/o 4 nc i/o i/o i/o 5 i/o i/o i/o i/o 6 nc i/o i/o i/o 7 i/o i/o i/o i/o 8 i/o i/o i/o i/o 9 i/o i/o i/o i/o 10 i/o i/o i/o i/o 11 tms tms tms tms 12 v cci v cci v cci v cci 13 i/o i/o i/o i/o 14 nc i/o i/o i/o 15 i/o i/o i/o i/o 16 i/o i/o i/o i/o 17 nc i/o i/o i/o 18 i/o i/o i/o gnd 19 i/o i/o i/o v cca 20 nc i/o i/o i/o 21 i/o i/o i/o i/o 22 i/o i/o i/o i/o 23 nc i/o i/o i/o 24 i/o i/o i/o i/o 25 nc nc nc i/o 26 gndgndgndgnd 27 v cca v cca v cca v cca 28 gndgndgndgnd 29 i/o i/o i/o i/o 30 trst, i/o trst, i/o trst, i/o trst, i/o 31 nc i/o i/o i/o 32 i/o i/o i/o i/o 33 i/o i/o i/o i/o 34 i/o i/o i/o i/o 35 nc i/o i/o i/o 36 i/o i/o i/o i/o 37 i/o i/o i/o i/o 38 i/o i/o i/o i/o 39 nc i/o i/o i/o 40 v cci v cci v cci v cci 41 v cca v cca v cca v cca 42 i/o i/o i/o i/o 43 i/o i/o i/o i/o 44 i/o i/o i/o i/o 45 i/o i/o i/o i/o 46 i/o i/o i/o i/o
56 v4.0 47 i/o i/o i/o i/o 48 nc i/o i/o i/o 49 i/o i/o i/o i/o 50 nc i/o i/o i/o 51 i/o i/o i/o i/o 52 gndgndgndgnd 53 i/o i/o i/o i/o 54 i/o i/o i/o i/o 55 i/o i/o i/o i/o 56 i/o i/o i/o i/o 57 i/o i/o i/o i/o 58 i/o i/o i/o i/o 59 i/o i/o i/o i/o 60 v cci v cci v cci v cci 61 nc i/o i/o i/o 62 i/o i/o i/o i/o 63 i/o i/o i/o i/o 64 nc i/o i/o i/o 65 i/o i/o nc i/o 66 i/o i/o i/o i/o 67 nc i/o i/o i/o 68 i/o i/o i/o i/o 69 i/o i/o i/o i/o 70 nc i/o i/o i/o 71 i/o i/o i/o i/o 72 i/o i/o i/o i/o 73 nc i/o i/o i/o 74 i/o i/o i/o qclka 75 nc i/o i/o i/o 76 prb, i/o prb, i/o prb, i/o prb,i/o 77 gndgndgndgnd 78 v cca v cca v cca v cca 79 gndgndgndgnd 80 nc nc nc nc 81 i/o i/o i/o i/o 82 hclk hclk hclk hclk 83 i/o i/o i/o v cci 84 i/o i/o i/o qclkb 85 nc i/o i/o i/o 86 i/o i/o i/o i/o 87 i/o i/o i/o i/o 88 nc i/o i/o i/o 89 i/o i/o i/o i/o 90 i/o i/o i/o i/o 91 nc i/o i/o i/o 92 i/o i/o i/o i/o 208-pin pqfp (continued) pin number a54sx08a function a54sx16a function a54sx32a function a54sx72a function
v4.0 57 93 i/o i/o i/o i/o 94 nc i/o i/o i/o 95 i/o i/o i/o i/o 96 i/o i/o i/o i/o 97 nc i/o i/o i/o 98 v cci v cci v cci v cci 99 i/o i/o i/o i/o 100 i/o i/o i/o i/o 101 i/o i/o i/o i/o 102 i/o i/o i/o i/o 103 tdo, i/o tdo, i/o tdo, i/o tdo, i/o 104 i/o i/o i/o i/o 105 gnd gnd gnd gnd 106 nc i/o i/o i/o 107 i/o i/o i/o i/o 108 nc i/o i/o i/o 109 i/o i/o i/o i/o 110 i/o i/o i/o i/o 111 i/o i/o i/o i/o 112 i/o i/o i/o i/o 113 i/o i/o i/o i/o 114 v cca v cca v cca v cca 115 v cci v cci v cci v cci 116 nc i/o i/o gnd 117 i/o i/o i/o v cca 118 i/o i/o i/o i/o 119 nc i/o i/o i/o 120 i/o i/o i/o i/o 121 i/o i/o i/o i/o 122 nc i/o i/o i/o 123 i/o i/o i/o i/o 124 i/o i/o i/o i/o 125 nc i/o i/o i/o 126 i/o i/o i/o i/o 127 i/o i/o i/o i/o 128 i/o i/o i/o i/o 129 gnd gnd gnd gnd 130 v cca v cca v cca v cca 131 gnd gnd gnd gnd 132ncncnci/o 133 i/o i/o i/o i/o 134 i/o i/o i/o i/o 135 nc i/o i/o i/o 136 i/o i/o i/o i/o 137 i/o i/o i/o i/o 138 nc i/o i/o i/o 208-pin pqfp (continued) pin number a54sx08a function a54sx16a function a54sx32a function a54sx72a function
58 v4.0 139 i/o i/o i/o i/o 140 i/o i/o i/o i/o 141 nc i/o i/o i/o 142 i/o i/o i/o i/o 143 nc i/o i/o i/o 144 i/o i/o i/o i/o 145 v cca v cca v cca v cca 146 gnd gnd gnd gnd 147 i/o i/o i/o i/o 148 v cci v cci v cci v cci 149 i/o i/o i/o i/o 150 i/o i/o i/o i/o 151 i/o i/o i/o i/o 152 i/o i/o i/o i/o 153 i/o i/o i/o i/o 154 i/o i/o i/o i/o 155 nc i/o i/o i/o 156 nc i/o i/o i/o 157 gnd gnd gnd gnd 158 i/o i/o i/o i/o 159 i/o i/o i/o i/o 160 i/o i/o i/o i/o 161 i/o i/o i/o i/o 162 i/o i/o i/o i/o 163 i/o i/o i/o i/o 164 v cci v cci v cci v cci 165 i/o i/o i/o i/o 166 i/o i/o i/o i/o 167 nc i/o i/o i/o 168 i/o i/o i/o i/o 169 i/o i/o i/o i/o 170 nc i/o i/o i/o 171 i/o i/o i/o i/o 172 i/o i/o i/o i/o 173 nc i/o i/o i/o 174 i/o i/o i/o i/o 175 i/o i/o i/o i/o 176 nc i/o i/o i/o 177 i/o i/o i/o i/o 178 i/o i/o i/o qclkd 179 i/o i/o i/o i/o 180 clka clka clka clka 181 clkb clkb clkb clkb 182ncncncnc 183 gnd gnd gnd gnd 184 v cca v cca v cca v cca 208-pin pqfp (continued) pin number a54sx08a function a54sx16a function a54sx32a function a54sx72a function
v4.0 59 185 gnd gnd gnd gnd 186 pra, i/o pra, i/o pra, i/o pra, i/o 187 i/o i/o i/o v cci 188 i/o i/o i/o i/o 189 nc i/o i/o i/o 190 i/o i/o i/o qclkc 191 i/o i/o i/o i/o 192 nc i/o i/o i/o 193 i/o i/o i/o i/o 194 i/o i/o i/o i/o 195 nc i/o i/o i/o 196 i/o i/o i/o i/o 197 i/o i/o i/o i/o 198 nc i/o i/o i/o 199 i/o i/o i/o i/o 200 i/o i/o i/o i/o 201 v cci v cci v cci v cci 202 nc i/o i/o i/o 203 nc i/o i/o i/o 204 i/o i/o i/o i/o 205 nc i/o i/o i/o 206 i/o i/o i/o i/o 207 i/o i/o i/o i/o 208 tck, i/o tck, i/o tck, i/o tck, i/o 208-pin pqfp (continued) pin number a54sx08a function a54sx16a function a54sx32a function a54sx72a function
60 v4.0 package pin assignments (continued) 100-pin tqfp (top view) 1 100-pin tqfp 100
v4.0 61 100-tqfp pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function 1 gnd gnd gnd 51 gnd gnd gnd 2 tdi, i/o tdi, i/o tdi, i/o 52 i/o i/o i/o 3 i/o i/o i/o 53 i/o i/o i/o 4 i/o i/o i/o 54 i/o i/o i/o 5 i/o i/o i/o 55 i/o i/o i/o 6 i/o i/o i/o 56 i/o i/o i/o 7 tms tms tms 57 v cca v cca v cca 8v cci v cci v cci 58 v cci v cci v cci 9 gnd gnd gnd 59 i/o i/o i/o 10 i/o i/o i/o 60 i/o i/o i/o 11 i/o i/o i/o 61 i/o i/o i/o 12 i/o i/o i/o 62 i/o i/o i/o 13 i/o i/o i/o 63 i/o i/o i/o 14 i/o i/o i/o 64 i/o i/o i/o 15 i/o i/o i/o 65 i/o i/o i/o 16 trst, i/o trst, i/o trst, i/o 66 i/o i/o i/o 17 i/o i/o i/o 67 v cca v cca v cca 18 i/o i/o i/o 68 gnd gnd gnd 19 i/o i/o i/o 69 gnd gnd gnd 20 v cci v cci v cci 70 i/o i/o i/o 21 i/o i/o i/o 71 i/o i/o i/o 22 i/o i/o i/o 72 i/o i/o i/o 23 i/o i/o i/o 73 i/o i/o i/o 24 i/o i/o i/o 74 i/o i/o i/o 25 i/o i/o i/o 75 i/o i/o i/o 26 i/o i/o i/o 76 i/o i/o i/o 27 i/o i/o i/o 77 i/o i/o i/o 28 i/o i/o i/o 78 i/o i/o i/o 29 i/o i/o i/o 79 i/o i/o i/o 30 i/o i/o i/o 80 i/o i/o i/o 31 i/o i/o i/o 81 i/o i/o i/o 32 i/o i/o i/o 82 v cci v cci v cci 33 i/o i/o i/o 83 i/o i/o i/o 34 prb, i/o prb, i/o prb, i/o 84 i/o i/o i/o 35 v cca v cca v cca 85 i/o i/o i/o 36 gnd gnd gnd 86 i/o i/o i/o 37 nc nc nc 87 clka clka clka 38 i/o i/o i/o 88 clkb clkb clkb 39 hclk hclk hclk 89 nc nc nc 40 i/o i/o i/o 90 v cca v cca v cca 41 i/o i/o i/o 91 gnd gnd gnd 42 i/o i/o i/o 92 pra, i/o pra, i/o pra, i/o 43 i/o i/o i/o 93 i/o i/o i/o 44 v cci v cci v cci 94 i/o i/o i/o 45 i/o i/o i/o 95 i/o i/o i/o 46 i/o i/o i/o 96 i/o i/o i/o 47 i/o i/o i/o 97 i/o i/o i/o 48 i/o i/o i/o 98 i/o i/o i/o 49 tdo, i/o tdo, i/o tdo, i/o 99 i/o i/o i/o 50 i/o i/o i/o 100 tck, i/o tck, i/o tck, i/o
62 v4.0 package pin assignments (continued) 144-pin tqfp (top view) 1 144 144-pin tqfp
v4.0 63 144-pin tqfp pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function 1 gnd gnd gnd 39 i/o i/o i/o 2 tdi, i/o tdi, i/o tdi, i/o 40 i/o i/o i/o 3 i/o i/o i/o 41 i/o i/o i/o 4 i/o i/o i/o 42 i/o i/o i/o 5 i/o i/o i/o 43 i/o i/o i/o 6 i/o i/o i/o 44 v cci v cci v cci 7 i/o i/o i/o 45 i/o i/o i/o 8 i/o i/o i/o 46 i/o i/o i/o 9 tms tms tms 47 i/o i/o i/o 10 v cci v cci v cci 48 i/o i/o i/o 11 gnd gnd gnd 49 i/o i/o i/o 12 i/o i/o i/o 50 i/o i/o i/o 13 i/o i/o i/o 51 i/o i/o i/o 14 i/o i/o i/o 52 i/o i/o i/o 15 i/o i/o i/o 53 i/o i/o i/o 16 i/o i/o i/o 54 prb, i/o prb, i/o prb, i/o 17 i/o i/o i/o 55 i/o i/o i/o 18 i/o i/o i/o 56 v cca v cca v cca 19 nc nc nc 57 gnd gnd gnd 20 v cca v cca v cca 58 nc nc nc 21 i/o i/o i/o 59 i/o i/o i/o 22 trst, i/o trst, i/o trst, i/o 60 hclk hclk hclk 23 i/o i/o i/o 61 i/o i/o i/o 24 i/o i/o i/o 62 i/o i/o i/o 25 i/o i/o i/o 63 i/o i/o i/o 26 i/o i/o i/o 64 i/o i/o i/o 27 i/o i/o i/o 65 i/o i/o i/o 28 gnd gnd gnd 66 i/o i/o i/o 29 v cci v cci v cci 67 i/o i/o i/o 30 v cca v cca v cca 68 v cci v cci v cci 31 i/o i/o i/o 69 i/o i/o i/o 32 i/o i/o i/o 70 i/o i/o i/o 33 i/o i/o i/o 71 tdo, i/o tdo, i/o tdo, i/o 34 i/o i/o i/o 72 i/o i/o i/o 35 i/o i/o i/o 73 gnd gnd gnd 36 gnd gnd gnd 74 i/o i/o i/o 37 i/o i/o i/o 75 i/o i/o i/o 38 i/o i/o i/o 76 i/o i/o i/o
64 v4.0 77 i/o i/o i/o 111 i/o i/o i/o 78 i/o i/o i/o 112 i/o i/o i/o 79 v cca v cca v cca 113 i/o i/o i/o 80 v cci v cci v cci 114 i/o i/o i/o 81 gnd gnd gnd 115 v cci v cci v cci 82 i/o i/o i/o 116 i/o i/o i/o 83 i/o i/o i/o 117 i/o i/o i/o 84 i/o i/o i/o 118 i/o i/o i/o 85 i/o i/o i/o 119 i/o i/o i/o 86 i/o i/o i/o 120 i/o i/o i/o 87 i/o i/o i/o 121 i/o i/o i/o 88 i/o i/o i/o 122 i/o i/o i/o 89 v cca v cca v cca 123 i/o i/o i/o 90 nc nc nc 124 i/o i/o i/o 91 i/o i/o i/o 125 clka clka clka 92 i/o i/o i/o 126 clkb clkb clkb 93 i/o i/o i/o 127 nc nc nc 94 i/o i/o i/o 128 gnd gnd gnd 95 i/o i/o i/o 129 v cca v cca v cca 96 i/o i/o i/o 130 i/o i/o i/o 97 i/o i/o i/o 131 pra, i/o pra, i/o pra, i/o 98 v cca v cca v cca 132 i/o i/o i/o 99 gnd gnd gnd 133 i/o i/o i/o 100 i/o i/o i/o 134 i/o i/o i/o 101 gnd gnd gnd 135 i/o i/o i/o 102 v cci v cci v cci 136 i/o i/o i/o 103 i/o i/o i/o 137 i/o i/o i/o 104 i/o i/o i/o 138 i/o i/o i/o 105 i/o i/o i/o 139 i/o i/o i/o 106 i/o i/o i/o 140 v cci v cci v cci 107 i/o i/o i/o 141 i/o i/o i/o 108 i/o i/o i/o 142 i/o i/o i/o 109 gnd gnd gnd 143 i/o i/o i/o 110 i/o i/o i/o 144 tck, i/o tck, i/o tck, i/o 144-pin tqfp (continued) pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function
v4.0 65 package pin assignments (continued) 176-pin tqfp (top view) 176-pin tqfp 176 1
66 v4.0 176-pin tqfp pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function 1 gnd 46 i/o 91 i/o 136 i/o 2 tdi, i/o 47 i/o 92 i/o 137 i/o 3 i/o 48 i/o 93 i/o 138 i/o 4 i/o 49 i/o 94 i/o 139 i/o 5 i/o 50 i/o 95 i/o 140 v cci 6 i/o 51 i/o 96 i/o 141 i/o 7i/o 52v cci 97 i/o 142 i/o 8 i/o 53 i/o 98 v cca 143 i/o 9 i/o 54 i/o 99 v cci 144 i/o 10 tms 55 i/o 100 i/o 145 i/o 11 v cci 56 i/o 101 i/o 146 i/o 12 i/o 57 i/o 102 i/o 147 i/o 13 i/o 58 i/o 103 i/o 148 i/o 14 i/o 59 i/o 104 i/o 149 i/o 15 i/o 60 i/o 105 i/o 150 i/o 16 i/o 61 i/o 106 i/o 151 i/o 17 i/o 62 i/o 107 i/o 152 clka 18 i/o 63 i/o 108 gnd 153 clkb 19 i/o 64 prb, i/o 109 v cca 154 nc 20 i/o 65 gnd 110 gnd 155 gnd 21 gnd 66 v cca 111 i/o 156 v cca 22 v cca 67 nc 112 i/o 157 pra, i/o 23 gnd 68 i/o 113 i/o 158 i/o 24 i/o 69 hclk 114 i/o 159 i/o 25 trst, i/o 70 i/o 115 i/o 160 i/o 26 i/o 71 i/o 116 i/o 161 i/o 27 i/o 72 i/o 117 i/o 162 i/o 28 i/o 73 i/o 118 i/o 163 i/o 29 i/o 74 i/o 119 i/o 164 i/o 30 i/o 75 i/o 120 i/o 165 i/o 31 i/o 76 i/o 121 i/o 166 i/o 32 v cci 77 i/o 122 v cca 167 i/o 33 v cca 78 i/o 123 gnd 168 i/o 34 i/o 79 i/o 124 v cci 169 v cci 35 i/o 80 i/o 125 i/o 170 i/o 36 i/o 81 i/o 126 i/o 171 i/o 37 i/o 82 v cci 127 i/o 172 i/o 38 i/o 83 i/o 128 i/o 173 i/o 39 i/o 84 i/o 129 i/o 174 i/o 40 i/o 85 i/o 130 i/o 175 i/o 41 i/o 86 i/o 131 i/o 176 tck, i/o 42 i/o 87 tdo, i/o 132 i/o 43 i/o 88 i/o 133 gnd 44 gnd 89 gnd 134 i/o 45 i/o 90 i/o 135 i/o
v4.0 67 package pin assignments (continued) 329-pin pbga (top view) 23 22 21 20 19 18 17 16 15 14 10 11 12 13 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac
68 v4.0 329-pin pbga pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function a1 gnd aa23 v cci ac22 v cci c21 v cci a2 gnd ab1 i/o ac23 gnd c22 gnd a3 v cci ab2 gnd b1 v cci c23 nc a4 nc ab3 i/o b2 gnd d1 i/o a5 i/o ab4 i/o b3 i/o d2 i/o a6 i/o ab5 i/o b4 i/o d3 i/o a7 v cci ab6 i/o b5 i/o d4 tck, i/o a8 nc ab7 i/o b6 i/o d5 i/o a9 i/o ab8 i/o b7 i/o d6 i/o a10 i/o ab9 i/o b8 i/o d7 i/o a11 i/o ab10 i/o b9 i/o d8 i/o a12 i/o ab11 prb, i/o b10 i/o d9 i/o a13 clkb ab12 i/o b11 i/o d10 i/o a14 i/o ab13 hclk b12 pra, i/o d11 v cca a15 i/o ab14 i/o b13 clka d12 nc a16 i/o ab15 i/o b14 i/o d13 i/o a17 i/o ab16 i/o b15 i/o d14 i/o a18 i/o ab17 i/o b16 i/o d15 i/o a19 i/o ab18 i/o b17 i/o d16 i/o a20 i/o ab19 i/o b18 i/o d17 i/o a21 nc ab20 i/o b19 i/o d18 i/o a22 v cci ab21 i/o b20 i/o d19 i/o a23 gnd ab22 gnd b21 i/o d20 i/o aa1 v cci ab23 i/o b22 gnd d21 i/o aa2 i/o ac1 gnd b23 v cci d22 i/o aa3 gnd ac2 v cci c1 nc d23 i/o aa4 i/o ac3 nc c2 tdi, i/o e1 v cci aa5 i/o ac4 i/o c3 gnd e2 i/o aa6 i/o ac5 i/o c4 i/o e3 i/o aa7 i/o ac6 i/o c5 i/o e4 i/o aa8 i/o ac7 i/o c6 i/o e20 i/o aa9 i/o ac8 i/o c7 i/o e21 i/o aa10 i/o ac9 v cci c8 i/o e22 i/o aa11 i/o ac10 i/o c9 i/o e23 i/o aa12 i/o ac11 i/o c10 i/o f1 i/o aa13 i/o ac12 i/o c11 i/o f2 tms aa14 i/o ac13 i/o c12 i/o f3 i/o aa15 i/o ac14 i/o c13 i/o f4 i/o aa16 i/o ac15 nc c14 i/o f20 i/o aa17 i/o ac16 i/o c15 i/o f21 i/o aa18 i/o ac17 i/o c16 i/o f22 i/o aa19 i/o ac18 i/o c17 i/o f23 i/o aa20 tdo, i/o ac19 i/o c18 i/o g1 i/o aa21 v cci ac20 i/o c19 i/o g2 i/o aa22 i/o ac21 nc c20 i/o g3 i/o
v4.0 69 g4 i/o l20 nc r1 i/o y4 gnd g20 i/o l21 i/o r2 i/o y5 i/o g21 i/o l22 i/o r3 i/o y6 i/o g22 i/o l23 nc r4 i/o y7 i/o g23 gnd m1 i/o r20 i/o y8 i/o h1 i/o m2 i/o r21 i/o y9 i/o h2 i/o m3 i/o r22 i/o y10 i/o h3 i/o m4 v cca r23 i/o y11 i/o h4 i/o m10 gnd t1 i/o y12 v cca h20 v cca m11 gnd t2 i/o y13 nc h21 i/o m12 gnd t3 i/o y14 i/o h22 i/o m13 gnd t4 i/o y15 i/o h23 i/o m14 gnd t20 i/o y16 i/o j1 nc m20 v cca t21 i/o y17 i/o j2 i/o m21 i/o t22 i/o y18 i/o j3 i/o m22 i/o t23 i/o y19 i/o j4 i/o m23 v cci u1 i/o y20 gnd j20 i/o n1 i/o u2 i/o y21 i/o j21 i/o n2 trst, i/o u3 v cca y22 i/o j22 i/o n3 i/o u4 i/o y23 i/o j23 i/o n4 i/o u20 i/o k1 i/o n10 gnd u21 v cca k2 i/o n11 gnd u22 i/o k3 i/o n12 gnd u23 i/o k4 i/o n13 gnd v1 v cci k10 gnd n14 gnd v2 i/o k11 gnd n20 nc v3 i/o k12 gnd n21 i/o v4 i/o k13 gnd n22 i/o v20 i/o k14 gnd n23 i/o v21 i/o k20 i/o p1 i/o v22 i/o k21 i/o p2 i/o v23 i/o k22 i/o p3 i/o w1 i/o k23 i/o p4 i/o w2 i/o l1 i/o p10 gnd w3 i/o l2 i/o p11 gnd w4 i/o l3 i/o p12 gnd w20 i/o l4 nc p13 gnd w21 i/o l10 gnd p14 gnd w22 i/o l11 gnd p20 i/o w23 nc l12 gnd p21 i/o y1 nc l13 gnd p22 i/o y2 i/o l14 gnd p23 i/o y3 i/o 329-pin pbga (continued) pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function pin number a54sx32a function
70 v4.0 package pin assignments (continued) 144-pin fbga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m
v4.0 71 144-pin fbga pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function a1 i/o i/o i/o d3 tdi, i/o tdi, i/o tdi, i/o a2 i/o i/o i/o d4 i/o i/o i/o a3 i/o i/o i/o d5 i/o i/o i/o a4 i/o i/o i/o d6 i/o i/o i/o a5 v cca v cca v cca d7 i/o i/o i/o a6 gnd gnd gnd d8 i/o i/o i/o a7 clka clka clka d9 i/o i/o i/o a8 i/o i/o i/o d10 i/o i/o i/o a9 i/o i/o i/o d11 i/o i/o i/o a10 i/o i/o i/o d12 i/o i/o i/o a11 i/o i/o i/o e1 i/o i/o i/o a12 i/o i/o i/o e2 i/o i/o i/o b1 i/o i/o i/o e3 i/o i/o i/o b2 gnd gnd gnd e4 i/o i/o i/o b3 i/o i/o i/o e5 tms tms tms b4 i/o i/o i/o e6 v cci v cci v cci b5 i/o i/o i/o e7 v cci v cci v cci b6 i/o i/o i/o e8 v cci v cci v cci b7 clkb clkb clkb e9 v cca v cca v cca b8 i/o i/o i/o e10 i/o i/o i/o b9 i/o i/o i/o e11 gnd gnd gnd b10 i/o i/o i/o e12 i/o i/o i/o b11 gnd gnd gnd f1 i/o i/o i/o b12 i/o i/o i/o f2 i/o i/o i/o c1 i/o i/o i/o f3 nc nc nc c2 i/o i/o i/o f4 i/o i/o i/o c3 tck, i/o tck, i/o tck, i/o f5 gnd gnd gnd c4 i/o i/o i/o f6 gnd gnd gnd c5 i/o i/o i/o f7 gnd gnd gnd c6 pra, i/o pra, i/o pra, i/o f8 v cci v cci v cci c7 i/o i/o i/o f9 i/o i/o i/o c8 i/o i/o i/o f10 gnd gnd gnd c9 i/o i/o i/o f11 i/o i/o i/o c10 i/o i/o i/o f12 i/o i/o i/o c11 i/o i/o i/o g1 i/o i/o i/o c12 i/o i/o i/o g2 gnd gnd gnd d1 i/o i/o i/o g3 i/o i/o i/o d2 v cci v cci v cci g4 i/o i/o i/o
72 v4.0 g5 gnd gnd gnd k3 i/o i/o i/o g6 gnd gnd gnd k4 i/o i/o i/o g7 gnd gnd gnd k5 i/o i/o i/o g8 v cci v cci v cci k6 i/o i/o i/o g9 i/o i/o i/o k7 gnd gnd gnd g10 i/o i/o i/o k8 i/o i/o i/o g11 i/o i/o i/o k9 i/o i/o i/o g12 i/o i/o i/o k10 gnd gnd gnd h1 trst, i/o trst, i/o trst, i/o k11 i/o i/o i/o h2 i/o i/o i/o k12 i/o i/o i/o h3 i/o i/o i/o l1 gnd gnd gnd h4 i/o i/o i/o l2 i/o i/o i/o h5 v cca v cca v cca l3 i/o i/o i/o h6 v cca v cca v cca l4 i/o i/o i/o h7 v cci v cci v cci l5 i/o i/o i/o h8 v cci v cci v cci l6 i/o i/o i/o h9 v cca v cca v cca l7 hclk hclk hclk h10 i/o i/o i/o l8 i/o i/o i/o h11 i/o i/o i/o l9 i/o i/o i/o h12 nc nc nc l10 i/o i/o i/o j1 i/o i/o i/o l11 i/o i/o i/o j2 i/o i/o i/o l12 i/o i/o i/o j3 i/o i/o i/o m1 i/o i/o i/o j4 i/o i/o i/o m2 i/o i/o i/o j5 i/o i/o i/o m3 i/o i/o i/o j6 prb, i/o prb, i/o prb, i/o m4 i/o i/o i/o j7 i/o i/o i/o m5 i/o i/o i/o j8 i/o i/o i/o m6 i/o i/o i/o j9 i/o i/o i/o m7 v cca v cca v cca j10 i/o i/o i/o m8 i/o i/o i/o j11 i/o i/o i/o m9 i/o i/o i/o j12 v cca v cca v cca m10 i/o i/o i/o k1 i/o i/o i/o m11 tdo, i/o tdo, i/o tdo, i/o k2 i/o i/o i/o m12 i/o i/o i/o 144-pin fbga (continued) pin number a54sx08a function a54sx16a function a54sx32a function pin number a54sx08a function a54sx16a function a54sx32a function
v4.0 73 package pin assignments (continued) 256-pin fbga (top view) 1 3 5 7911 13 15 246 8 10 12 14 16 c e g j l n r d f h k m p t b a
74 v4.0 256-pin fbga pin number a54sx16a function a54sx32a function a54sx72a function pin number a54sx16a function a54sx32a function a54sx72a function a1 gnd gnd gnd c14 i/o i/o i/o a2 tck, i/o tck, i/o tck, i/o c15 i/o i/o i/o a3 i/o i/o i/o c16 i/o i/o i/o a4 i/o i/o i/o d1 i/o i/o i/o a5 i/o i/o i/o d2 i/o i/o i/o a6 i/o i/o i/o d3 i/o i/o i/o a7 i/o i/o i/o d4 i/o i/o i/o a8 i/o i/o i/o d5 i/o i/o i/o a9 clkb clkb clkb d6 i/o i/o i/o a10 i/o i/o i/o d7 i/o i/o i/o a11 i/o i/o i/o d8 pra, i/o pra, i/o pra, i/o a12 nc i/o i/o d9 i/o i/o qclkd a13 i/o i/o i/o d10 i/o i/o i/o a14 i/o i/o i/o d11 nc i/o i/o a15 gnd gnd gnd d12 i/o i/o i/o a16 gnd gnd gnd d13 i/o i/o i/o b1 i/o i/o i/o d14 i/o i/o i/o b2 gnd gnd gnd d15 i/o i/o i/o b3 i/o i/o i/o d16 i/o i/o i/o b4 i/o i/o i/o e1 i/o i/o i/o b5 i/o i/o i/o e2 i/o i/o i/o b6 nc i/o i/o e3 i/o i/o i/o b7 i/o i/o i/o e4 i/o i/o i/o b8 v cca v cca v cca e5 i/o i/o i/o b9 i/o i/o i/o e6 i/o i/o i/o b10 i/o i/o i/o e7 i/o i/o qclkc b11 nc i/o i/o e8 i/o i/o i/o b12 i/o i/o i/o e9 i/o i/o i/o b13 i/o i/o i/o e10 i/o i/o i/o b14 i/o i/o i/o e11 i/o i/o i/o b15 gnd gnd gnd e12 i/o i/o i/o b16 i/o i/o i/o e13 nc i/o i/o c1 i/o i/o i/o e14 i/o i/o i/o c2 tdi, i/o tdi, i/o tdi, i/o e15 i/o i/o i/o c3 gnd gnd gnd e16 i/o i/o i/o c4 i/o i/o i/o f1 i/o i/o i/o c5 nc i/o i/o f2 i/o i/o i/o c6 i/o i/o i/o f3 i/o i/o i/o c7 i/o i/o i/o f4 tms tms tms c8 i/o i/o i/o f5 i/o i/o i/o c9 clka clka clka f6 i/o i/o i/o c10 i/o i/o i/o f7 v cci v cci v cci c11 i/o i/o i/o f8 v cci v cci v cci c12 i/o i/o i/o f9 v cci v cci v cci c13 i/o i/o i/o f10 v cci v cci v cci
v4.0 75 f11 i/o i/o i/o j8 gnd gnd gnd f12 vcca vcca vcca j9 gnd gnd gnd f13 i/o i/o i/o j10 gnd gnd gnd f14 i/o i/o i/o j11 v cci v cci v cci f15 i/o i/o i/o j12 i/o i/o i/o f16 i/o i/o i/o j13 i/o i/o i/o g1 nc i/o i/o j14 i/o i/o i/o g2 i/o i/o i/o j15 i/o i/o i/o g3 nc i/o i/o j16 i/o i/o i/o g4 i/o i/o i/o k1 i/o i/o i/o g5 i/o i/o i/o k2 i/o i/o i/o g6 v cci v cci v cci k3 nc i/o i/o g7 gnd gnd gnd k4 v cca v cca v cca g8 gnd gnd gnd k5 i/o i/o i/o g9 gnd gnd gnd k6 v cci v cci v cci g10 gnd gnd gnd k7 gnd gnd gnd g11 v cci v cci v cci k8 gnd gnd gnd g12 i/o i/o i/o k9 gnd gnd gnd g13 gnd gnd gnd k10 gnd gnd gnd g14 nc i/o i/o k11 v cci v cci v cci g15 v cca v cca v cca k12 i/o i/o i/o g16 i/o i/o i/o k13 i/o i/o i/o h1 i/o i/o i/o k14 i/o i/o i/o h2 i/o i/o i/o k15 nc i/o i/o h3 v cca v cca v cca k16 i/o i/o i/o h4 trst, i/o trst, i/o trst, i/o l1 i/o i/o i/o h5 i/o i/o i/o l2 i/o i/o i/o h6 v cci v cci v cci l3 i/o i/o i/o h7 gnd gnd gnd l4 i/o i/o i/o h8 gnd gnd gnd l5 i/o i/o i/o h9 gnd gnd gnd l6 i/o i/o i/o h10 gnd gnd gnd l7 v cci v cci v cci h11 v cci v cci v cci l8 v cci v cci v cci h12 i/o i/o i/o l9 v cci v cci v cci h13 i/o i/o i/o l10 v cci v cci v cci h14 i/o i/o i/o l11 i/o i/o i/o h15 i/o i/o i/o l12 i/o i/o i/o h16 nc i/o i/o l13 i/o i/o i/o j1 nc i/o i/o l14 i/o i/o i/o j2 nc i/o i/o l15 i/o i/o i/o j3 nc i/o i/o l16 nc i/o i/o j4 i/o i/o i/o m1 i/o i/o i/o j5 i/o i/o i/o m2 i/o i/o i/o j6 v cci v cci v cci m3 i/o i/o i/o j7 gnd gnd gnd m4 i/o i/o i/o 256-pin fbga (continued) pin number a54sx16a function a54sx32a function a54sx72a function pin number a54sx16a function a54sx32a function a54sx72a function
76 v4.0 m5 i/o i/o i/o p11 i/o i/o i/o m6 i/o i/o i/o p12 i/o i/o i/o m7 i/o i/o qclka p13 v cca v cca v cca m8 prb, i/o prb, i/o prb, i/o p14 i/o i/o i/o m9 i/o i/o i/o p15 i/o i/o i/o m10 i/o i/o i/o p16 i/o i/o i/o m11 i/o i/o i/o r1 i/o i/o i/o m12 nc i/o i/o r2 gnd gnd gnd m13 i/o i/o i/o r3 i/o i/o i/o m14 nc i/o i/o r4 nc i/o i/o m15 i/o i/o i/o r5 i/o i/o i/o m16 i/o i/o i/o r6 i/o i/o i/o n1 i/o i/o i/o r7 i/o i/o i/o n2 i/o i/o i/o r8 i/o i/o i/o n3 i/o i/o i/o r9 hclk hclk hclk n4 i/o i/o i/o r10 i/o i/o qclkb n5 i/o i/o i/o r11 i/o i/o i/o n6 i/o i/o i/o r12 i/o i/o i/o n7 i/o i/o i/o r13 i/o i/o i/o n8 i/o i/o i/o r14 i/o i/o i/o n9 i/o i/o i/o r15 gnd gnd gnd n10 i/o i/o i/o r16 gnd gnd gnd n11 i/o i/o i/o t1 gnd gnd gnd n12 i/o i/o i/o t2 i/o i/o i/o n13 i/o i/o i/o t3 i/o i/o i/o n14 i/o i/o i/o t4 nc i/o i/o n15 i/o i/o i/o t5 i/o i/o i/o n16 i/o i/o i/o t6 i/o i/o i/o p1 i/o i/o i/o t7 i/o i/o i/o p2 gnd gnd gnd t8 i/o i/o i/o p3 i/o i/o i/o t9 v cca v cca v cca p4 i/o i/o i/o t10 i/o i/o i/o p5 nc i/o i/o t11 i/o i/o i/o p6 i/o i/o i/o t12 nc i/o i/o p7 i/o i/o i/o t13 i/o i/o i/o p8 i/o i/o i/o t14 i/o i/o i/o p9 i/o i/o i/o t15 tdo, i/o tdo, i/o tdo, i/o p10 nc i/o i/o t16 gnd gnd gnd 256-pin fbga (continued) pin number a54sx16a function a54sx32a function a54sx72a function pin number a54sx16a function a54sx32a function a54sx72a function
v4.0 77 package pin assignments (continued) 484-pin fbga (top view) 1 2 3 4 5 6 7 8 9 10 11121314 15161718 19 20212223 242526 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
78 v4.0 484-pin fbga pin number a54sx32a function a54sx72a function pin number a54sx32a function a54sx72a function pin number a54sx32a function a54sx72a function a1 nc* nc ab11 i/o i/o ad5 i/o i/o a2 nc* nc ab12 prb, i/o prb, i/o ad6 i/o i/o a3 nc* i/o ab13 v cca v cca ad7 i/o i/o a4 nc* i/o ab14 i/o i/o ad8 i/o i/o a5 nc* i/o ab15 i/o i/o ad9 v cci v cci a6 i/o i/o ab16 i/o i/o ad10 i/o i/o a7 i/o i/o ab17 i/o i/o ad11 i/o i/o a8 i/o i/o ab18 i/o i/o ad12 i/o i/o a9 i/o i/o ab19 i/o i/o ad13 v cci v cci a10 i/o i/o ab20 tdo, i/o tdo, i/o ad14 i/o i/o a11 nc* i/o ab21 gnd gnd ad15 i/o i/o a12 nc* i/o ab22 nc* i/o ad16 i/o i/o a13 i/o i/o ab23 i/o i/o ad17 v cci v cci a14 nc* nc ab24 i/o i/o ad18 i/o i/o a15 nc* i/o ab25 nc* i/o ad19 i/o i/o a16 nc* i/o ab26 nc* i/o ad20 i/o i/o a17 i/o i/o ac1 i/o i/o ad21 i/o i/o a18 i/o i/o ac2 i/o i/o ad22 i/o i/o a19 i/o i/o ac3 i/o i/o ad23 v cci v cci a20 i/o i/o ac4 nc* i/o ad24 nc* i/o a21 nc* i/o ac5 v cci v cci ad25 nc* i/o a22 nc* i/o ac6 i/o i/o ad26 nc* i/o a23 nc* i/o ac7 v cci v cci ae1 nc* nc a24 nc* i/o ac8 i/o i/o ae2 i/o i/o a25 nc* nc ac9 i/o i/o ae3 nc* i/o a26 nc* nc ac10 i/o i/o ae4 nc* i/o aa1 nc* i/o ac11 i/o i/o ae5 nc* i/o aa2 nc* i/o ac12 i/o qclka ae6 nc* i/o aa3 v cca v cca ac13 i/o i/o ae7 i/o i/o aa4 i/o i/o ac14 i/o i/o ae8 i/o i/o aa5 i/o i/o ac15 i/o i/o ae9 i/o i/o aa22 i/o i/o ac16 i/o i/o ae10 i/o i/o aa23 i/o i/o ac17 i/o i/o ae11 nc* i/o aa24 i/o i/o ac18 i/o i/o ae12 i/o i/o aa25 nc* i/o ac19 i/o i/o ae13 i/o i/o aa26 nc* i/o ac20 v cci v cci ae14 i/o i/o ab1 nc* nc ac21 i/o i/o ae15 nc* i/o ab2 v cci v cci ac22 i/o i/o ae16 nc* i/o ab3 i/o i/o ac23 nc* i/o ae17 i/o i/o ab4 i/o i/o ac24 i/o i/o ae18 i/o i/o ab5 nc* i/o ac25 nc* i/o ae19 i/o i/o ab6 i/o i/o ac26 nc* i/o ae20 i/o i/o ab7 i/o i/o ad1 i/o i/o ae21 nc* i/o ab8 i/o i/o ad2 i/o i/o ae22 nc* i/o ab9 i/o i/o ad3 gnd gnd ae23 nc* i/o ab10 i/o i/o ad4 i/o i/o ae24 nc* i/o note: *these pins must be left floating on the a54sx32a device.
v4.0 79 ae25 nc* nc b19 i/o i/o d13 i/o i/o ae26 nc* nc b20 i/o i/o d14 i/o i/o af1 nc* nc b21 nc* i/o d15 i/o i/o af2 nc* nc b22 nc* i/o d16 i/o i/o af3 nc i/o b23 nc* i/o d17 i/o i/o af4 nc* i/o b24 nc* i/o d18 i/o i/o af5 nc* i/o b25 i/o i/o d19 i/o i/o af6 nc* i/o b26 nc* nc d20 i/o i/o af7 i/o i/o c1 nc* i/o d21 v cci v cci af8 i/o i/o c2 nc* i/o d22 gnd gnd af9 i/o i/o c3 nc* i/o d23 i/o i/o af10 i/o i/o c4 nc* i/o d24 i/o i/o af11 nc* i/o c5 i/o i/o d25 nc* i/o af12 nc* nc c6 v cci v cci d26 nc* i/o af13 hclk hclk c7 i/o i/o e1 nc* i/o af14 i/o qclkb c8 i/o i/o e2 nc* i/o af15 nc* i/o c9 v cci v cci e3 i/o i/o af16 nc* i/o c10 i/o i/o e4 i/o i/o af17 i/o i/o c11 i/o i/o e5 gnd gnd af18 i/o i/o c12 i/o i/o e6 tdi, io tdi, io af19 i/o i/o c13 pra, i/o pra, i/o e7 i/o i/o af20 nc* i/o c14 i/o i/o e8 i/o i/o af21 nc* i/o c15 i/o qclkd e9 i/o i/o af22 nc* i/o c16 i/o i/o e10 i/o i/o af23 nc* i/o c17 i/o i/o e11 i/o i/o af24 nc* i/o c18 i/o i/o e12 i/o i/o af25 nc* nc c19 i/o i/o e13 v cca v cca af26 nc* nc c20 v cci v cci e14 clkb clkb b1 nc* nc c21 i/o i/o e15 i/o i/o b2 nc* nc c22 i/o i/o e16 i/o i/o b3 nc* i/o c23 i/o i/o e17 i/o i/o b4 nc* i/o c24 i/o i/o e18 i/o i/o b5 nc* i/o c25 nc* i/o e19 i/o i/o b6 i/o i/o c26 nc* i/o e20 i/o i/o b7 i/o i/o d1 nc* i/o e21 i/o i/o b8 i/o i/o d2 tms tms e22 i/o i/o b9 i/o i/o d3 i/o i/o e23 i/o i/o b10 i/o i/o d4 v cci v cci e24 i/o i/o b11 nc* i/o d5 nc* i/o e25 v cci v cci b12 nc* i/o d6 tck, i/o tck, i/o e26 gnd gnd b13 v cci v cci d7 i/o i/o f1 v cci v cci b14 clka clka d8 i/o i/o f2 nc* i/o b15 nc* i/o d9 i/o i/o f3 nc* i/o b16 nc* i/o d10 i/o i/o f4 i/o i/o b17 i/o i/o d11 i/o i/o f5 i/o i/o b18 v cci v cci d12 i/o qclkc f22 i/o i/o 484-pin fbga (continued) pin number a54sx32a function a54sx72a function pin number a54sx32a function a54sx72a function pin number a54sx32a function a54sx72a function note: *these pins must be left floating on the a54sx32a device.
80 v4.0 f23 i/o i/o k17 gnd gnd n5 i/o i/o f24 i/o i/o k22 i/o i/o n10 gnd gnd f25 i/o i/o k23 i/o i/o n11 gnd gnd f26 nc* i/o k24 nc* nc n12 gnd gnd g1 nc* i/o k25 nc* i/o n13 gnd gnd g2 nc* i/o k26 nc* i/o n14 gnd gnd g3 nc* i/o l1 nc* i/o n15 gnd gnd g4 i/o i/o l2 nc* i/o n16 gnd gnd g5 i/o i/o l3 i/o i/o n17 gnd gnd g22 i/o i/o l4 i/o i/o n22 v cca v cca g23 v cca v cca l5 i/o i/o n23 i/o i/o g24 i/o i/o l10 gnd gnd n24 i/o i/o g25 nc* i/o l11 gnd gnd n25 i/o i/o g26 nc* i/o l12 gnd gnd n26 nc* nc h1 nc* i/o l13 gnd gnd p1 nc* i/o h2 nc* i/o l14 gnd gnd p2 nc* i/o h3 i/o i/o l15 gnd gnd p3 i/o i/o h4 i/o i/o l16 gnd gnd p4 i/o i/o h5 i/o i/o l17 gnd gnd p5 v cca v cca h22 i/o i/o l22 i/o i/o p10 gnd gnd h23 i/o i/o l23 i/o i/o p11 gnd gnd h24 i/o i/o l24 i/o i/o p12 gnd gnd h25 nc* i/o l25 i/o i/o p13 gnd gnd h26 nc* i/o l26 i/o i/o p14 gnd gnd j1 nc* i/o m1 nc* nc p15 gnd gnd j2 nc* i/o m2 i/o i/o p16 gnd gnd j3 i/o i/o m3 i/o i/o p17 gnd gnd j4 i/o i/o m4 i/o i/o p22 i/o i/o j5 i/o i/o m5 i/o i/o p23 i/o i/o j22 i/o i/o m10 gnd gnd p24 v cci v cci j23 i/o i/o m11 gnd gnd p25 i/o i/o j24 i/o i/o m12 gnd gnd p26 i/o i/o j25 v cci v cci m13 gnd gnd r1 nc* i/o j26 nc* i/o m14 gnd gnd r2 nc* i/o k1 i/o i/o m15 gnd gnd r3 i/o i/o k2 v cci v cci m16 gnd gnd r4 i/o i/o k3 i/o i/o m17 gnd gnd r5 trst, i/o trst, i/o k4 i/o i/o m22 i/o i/o r10 gnd gnd k5 v cca v cca m23 i/o i/o r11 gnd gnd k10 gnd gnd m24 i/o i/o r12 gnd gnd k11 gnd gnd m25 nc* i/o r13 gnd gnd k12 gnd gnd m26 nc* i/o r14 gnd gnd k13 gnd gnd n1 i/o i/o r15 gnd gnd k14 gnd gnd n2 v cci v cci r16 gnd gnd k15 gnd gnd n3 i/o i/o r17 gnd gnd k16 gnd gnd n4 i/o i/o r22 i/o i/o 484-pin fbga (continued) pin number a54sx32a function a54sx72a function pin number a54sx32a function a54sx72a function pin number a54sx32a function a54sx72a function note: *these pins must be left floating on the a54sx32a device.
v4.0 81 r23 i/o i/o u3 i/o i/o v25 nc* i/o r24 i/o i/o u4 i/o i/o v26 nc* i/o r25 nc* i/o u5 i/o i/o w1 i/o i/o r26 nc* i/o u10 gnd gnd w2 i/o i/o t1 nc* i/o u11 gnd gnd w3 i/o i/o t2 nc* i/o u12 gnd gnd w4 i/o i/o t3 i/o i/o u13 gnd gnd w5 i/o i/o t4 i/o i/o u14 gnd gnd w22 i/o i/o t5 i/o i/o u15 gnd gnd w23 v cca v cca t10 gnd gnd u16 gnd gnd w24 i/o i/o t11 gnd gnd u17 gnd gnd w25 nc* i/o t12 gnd gnd u22 i/o i/o w26 nc* i/o t13 gnd gnd u23 i/o i/o y1 nc* i/o t14 gnd gnd u24 i/o i/o y2 nc* i/o t15 gnd gnd u25 v cci v cci y3 i/o i/o t16 gnd gnd u26 i/o i/o y4 i/o i/o t17 gnd gnd v1 nc* i/o y5 nc* i/o t22 i/o i/o v2 nc* i/o y22 i/o i/o t23 i/o i/o v3 i/o i/o y23 i/o i/o t24 i/o i/o v4 i/o i/o y24 v cci v cci t25 nc* i/o v5 i/o i/o y25 i/o i/o t26 nc* i/o v22 v cca v cca y26 i/o i/o u1 i/o i/o v23 i/o i/o u2 v cci v cci v24 i/o i/o 484-pin fbga (continued) pin number a54sx32a function a54sx72a function pin number a54sx32a function a54sx72a function pin number a54sx32a function a54sx72a function note: *these pins must be left floating on the a54sx32a device.
82 v4.0 list of changes the following table lists critical changes that were made in the current version of the document. data sheet categories in order to provide the latest information to designers, some data sheets are published before data has been fully characterized. these data sheets are marked as ? advanced ? or preliminary ? data sheets. the definition of these categories are as follows: advanced the data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. previous version changes in current version (v3.0) page v4.0 the ? sx-a product profile ? table on page 1 was updated. page 1 the ? ordering information ? section on page 2 was updated. page 2 the ? product plan ? section on page 3 was updated. page 3 figure 1 on page 4 was updated. page 4 the ? ? clock resources ? section on page 6 ? was updated page 6 the ? sx-a clock resources ? table on page 8 is new. page 8 the ? user security ? section on page 9 is new. page 9 the ? i/o modules ? section on page 9 was updated. page 9 the ? i/o features ? table on page 10 was updated. page 10 the ? i/o characteristics for all i/o configurations ? table on page 10 is new. page 10 the ? power-up time at which i/os become active ? table on page 10 is new page 10 figure 10 on page 11 is new. page 11 the ? boundary-scan pin configurations and functions ? table on page 11 is new. page 11 the ? device configuration options for probe capability (trst pin reserved) ? table on page 12 is new. page 12 the ? sx-a probe circuit control pins ? section on page 12 was updated. page 12 the ? design considerations ? section on page 12 was updated. page 12 figure 11 on page 12 was updated. page 12 the ? development tool support ? section on page 13 was updated. page 13 figure 12 on page 13 is new. page 13 the ? absolute maximum ratings1 ? table on page 14 was updated. page 14 the ? recommended operating conditions ? table on page 14 was updated. page 14 the ? 3.3v lvttl and 5v ttl electrical specifications ? table on page 14 was updated. page 14 the ? 2.5v lvcmos2 electrical specifications ? table on page 15 was updated. page 15 the sx-a timing model* and sample path calculations equations were updated. page 22 the ? pin description ? section on page 53 was updated. page 53 v2.0.1 the section, ? development tool support ? section on page 13 has been updated. page 10 the section, ? i/o modules ? section on page 9 , and the table, i/o features, table 2 on page 10 have been updated. page 9 the ? sx-a timing model* ? section on page 22 and several timing tables on pages 22-49 have new timing numbers. pages 19, 22-49
actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. http://www.actel.com actel corporation 955 east arques avenue sunnyvale, california 94086 usa tel: (408) 739-1010 fax: (408) 739-1540 actel europe ltd. dunlop house, riverside way camberley, surrey gu15 3yl united kingdom tel: +44 (0)1276 401450 fax: +44 (0)1276 401490 actel japan exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan tel: +81 03-3445-7671 fax: +81 03-3445-7668 actel hong kong 39th floor one pacific place 88 queensway admiralty, hong kong tel: 852-22735712 5172147-6/4.03 preliminary the data sheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. unmarked (production) the data sheet contains information that is considered to be final.

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