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acpl-061l, acpl-064l, acpl-m61l, acpl-w61l, acpl-k64l ultra low power 10 mbd digital cmos optocouplers data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the avago ultra low power acpl-x6xl digital optocouplers combine an algaas light emitting diode (led) and an integrated high gain photodetector. the optocoupler consumes extremely low power, at maximum 1.3ma i dd2 current per channel across temperature. with a forward led current as low as 1.6 ma most microprocessors can directly drive the led. an internal faraday shield provides a guaranteed common mode transient immunity speci?cation of 20 kv/ s. maximum ac and dc circuit isolation is achieved while maintaining ttl/cmos compatibility. the optocouplers cmos outputs are slew-rate controlled and is designed to allow the rise and fall time to be con- trolled over a wide load capacitance range. the acpl-x6xl series operates from both 3.3 v and 5 v supply voltages with guaranteed ac and dc performance from C40c to +105c. these low-power optocouplers are suitable for high speed logic interface applications. functional diagrams features ultra-low i dd current: 1.3 ma/channel maximum low input current: 1.6 ma built-in slew-rate controlled outputs 20 kv/ s minimum common mode rejection (cmr) at v cm = 1000 v high speed: 10 mbd minimum guaranteed ac and dc performance over wide temperature: C40c to +105c wide package selection: so-5, so-8, stretched so-6 and stretched so-8 safety approval C ul 1577 recognized C 3750 vrms for 1 minute for acpl-061l/064l/m61l and 5000 vrms* for 1 minute for acpl-w61l/k64l C csa approval C iec/en/din en 60747-5-5 approval for reinforced insulation (approved for acpl-m61l, pending approval for acpl-064l/w61l/k64l/061l) rohs compliant applications communication interfaces: rs485, canbus and i 2 c microprocessor system interfaces digital isolation for a/d and d/a convertors lead (pb) free rohs 6 fully compliant r o h s 6 f u lly co m p l ia n t optio n s a v ai l a bl e ; -xxxe de n otes a l ead -f ree product 2 3 anode cathode v dd vo nc 4 1 7 6 5 8 gnd nc nc shield acpl-061l^ 2 3 6 4 1 5 nc* anode cathode v dd gnd vo shield acpl-k64l acpl-m61l 1 3 6 4 5 anode cathode v dd gnd vo truth table (positive logic) led output on l off h * pin 7 of the acpl-061l is not connected a 0.1 f bypass capacitor must be connected betwee n pins v dd and gnd. ^ advanced information, may subject to changes. preliminary information 4 1 v dd vo 1 anode1 cathode1 vo 2 gnd cathode2 anode2 shield 3 2 5 8 6 7 acpl-064l acpl-w61l 4 1 v dd vo 1 anode1 cathode1 vo 2 gnd cathode2 anode2 shield 3 2 5 8 6 7
2 ordering information the acpl-061l, acpl-064l and acpl-m61l are ul recognized with an isolation voltage of 3750 v rms for 1 minute per ul1577. the acpl-w61l and acpl-k64l are ul recognized with an isolation voltage of 5000 v rms for 1 minute per ul1577. all devices are rohs compliant. part number option package surface mount tape & reel ul 5000 v rms / 1 minute rating iec/en/ din en 60747-5-5 quantity rohs compliant acpl-061l ^ -000e so-8 x 100 per tube -500e x x 1500 per reel -560e x x x 1500 per reel acpl-064l -000e so-8 x 100 per tube -500e x x 1500 per reel -560e x x x 1500 per reel acpl-m61l -000e so-5 x 100 per tube -500e x x 1500 per reel -560e x x x 1500 per reel acpl-w61l -000e stretched s06 x x 100 per tube -500e x x x 1000 per reel -560e xxxx 1000 per reel acpl-k64l -000e stretched s08 x x 80 per tube -500e x x x 1000 per reel -560e xxxx 1000 per reel to form an ordering part number, choose a part number from the part number column and combine it with the desired option from the option column. example 1: the part number acpl-m61l-560e describes an optocoupler with a surface mount so-5 package; delivered in tape and reel with 1500 parts per reel; with iec/en/din en 60747-5-5 safety approval; and full rohs compliance. option datasheets are available. contact your avago sales representative or authorized distributor for information. ^ advanced information, may subject to changes.
3 package outline drawings acpl-061l and acpl-064l so-8 package xxxv yww 8765 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * total package length (inclusive of mold ?ash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation acpl-m61l so-5 package mxxx xxx 7.0 0.2 (0.276 0.008) 2.5 0.1 (0.098 0.004) 0.102 0.102 (0.004 0.004) 4.4 0.1 (0.173 0.004) 1.27 (0.050) bsc 0.216 0.038 (0.0085 0.0015) 0.71 (0.028) min 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) dimensions in millimeters (inches) * maximum mold ?ash on each side is 0.15 mm (0.006) note: floating lead protrusion is 0.15 mm (6 mils) max. 7 max. max. lead coplanarity = 0.102 (0.004)
4 acpl-w61l stretched so-6 package acpl-k63l stretched so-8 package 4.580 0.180 45 0.381 0.127 (0.015 0.005) 1.27 (0.050) bsg 0.20 0.10 (0.008 0.004) 0.45 (0.018) 0.750 0.250 (0.0295 0.010) 11.50 0.250 (0.453 0.010) 6.807 0.268 dimensions in millimeters (inches). lead coplanarity = 0.1 mm (0.004 inches). 7 12.65 (0.498) land pattern recommendation 3.180 0.127 (0.125 0.005) 1.590 0.127 (0.063 0.005) 7 1.91 (0.075) 3 2 1 4 5 6 0.76 (0.030) +0.254 0 +0.010 - 0.000 +0.127 0 +0.005 - 0.000 ) ( ) ( 4 0.381 0.13 (0.015 0.005) 1.270 (0.050) bsg dimensions in millimeters (inches). lead coplanarity = 0.1 mm (0.004 inches). 12.650 (0.5) 7 1.905 (0.1) 3 2 1 5 6 7 8 45 0.200 0.100 (0.008 0.004) 0.450 (0.018) 0.750 0.250 (0.0295 0.010) 11.5 0.250 (0.453 0.010) 6.807 0.127 (0.268 0.005) 7 3.180 0.127 (0.125 0.005) 1.590 0.127 (0.063 0.005) 5.850 0.230 +0.25 0 +0.010 - 0.000 ) ( land pattern recommendation
5 re?ow soldering pro?le the recommended re?ow soldering conditions are per jedec standard j-std-020 (latest revision). non-halide ?ux should be used. regulatory information the acpl-061l, acpl-064l, acpl-m61l, acpl-w61l and acpl-k64l are pending approval by the following organizations: iec/en/din en 60747-5-5 (option 060 only) ul approval under ul 1577 component recognition program up to v iso = 3750 v rms for the acpl-m61l/061l/064l and v iso = 5000 v rms for the acpl-w61l/k64l, file e55361. csa approval under csa component acceptance notice #5, file ca 88324. insulation and safety related speci?cations parameter symbol acpl-061l acpl-064l acpl-m61l acpl-w61l acpl-k64l units conditions minimum external air gap (external clearance) l(101) 4.9 5 8 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (external creepage) l(102) 4.8 5 8 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 0.08 0.08 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti 175 175 175 v din iec 112/vde 0303 part 1 isolation group iiia iiia iiia material group (din vde 0110, 1/89, table 1)
6 iec/en/din en 60747-5-5 insulation characteristics* (option 060) description symbol characteristic unit acpl-061l^/ acpl- 064l/ acpl- m61l acpl-w61l/ acpl- k64l installation classi?cation per din vde 0110/39, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 600 v rms for rated mains voltage 100 v rms i C iv i C iii i C ii i C iv i C iv i C iii i C iii climatic classi?cation 55/105/21 55/105/21 pollution degree (din vde 0110/39) 2 2 maximum working insulation voltage v iorm 560 1140 v peak input to output test voltage, method b* v iorm x 1.875=v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1063 2137 v peak input to output test voltage, method a* v iorm x 1.6=v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc v pr 896 1824 v peak highest allowable overvoltage (transient overvoltage t ini = 60 sec) v iotm 6000 8000 v peak safety-limiting values C maximum values allowed in the event of a failure. case temperature input current** output power** t s i s, input p s, output 150 150 600 175 230 600 c ma mw insulation resistance at t s , v io = 500 v r s >10 9 >10 9 * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulation s section, (iec/en/ din en 60747-5-5) for a detailed description of method a and method b partial discharge test pro?les. ** refer to the following ?gure for dependence of p s and i s on ambient temperature. absolute maximum ratings parameter symbol min max units condition storage temperature t s -55 125 c operating temperature t a -40 105 c reverse input voltage v r 5v supply voltage v dd 6.5 v average forward input current i f C8 ma peak forward input current (i f at 1 s pulse width, <10% duty cycle) i f(tran) C1 a 1 s pulse width, <300 pulses per second 80 ma 1 s pulse width, <10% duty cycle output current i o 10 ma output voltage v o C0.5 v dd +0.5 v input power dissipation p i 14 mw output power dissipation p o 20 mw lead solder temperature t ls 260c for 10 sec., 1.6 mm below seating plane solder re?ow temperature pro?le see package outline drawings section
7 recommended operating conditions parameter symbol min max units operating temperature t a - 40 105 c input current, low level i fl 0 250 a input current, high level i fh 1.6 6.0 ma power supply voltage v dd 2.7 5.5 v forward input voltage v f (off) 0.8 v logic low input voltage v il 0 0.8 v electrical speci?cations (dc) over the recommended temperature (t a = C40c to +105c) and supply voltage (2.7 v v dd 5.5 v). all typical speci?- cations are at v dd = 5 v and t a = 25c. parameter symbol min typ max units test conditions input forward voltage v f 0.95 1.3 1.7 v i f = 2 ma input reverse breakdown voltage bv r 35 vi r = 10 a logic high output voltage v oh v dd - 0.1 v dd vi f = 0 ma, v i = 0 v (r t = 1.68 k ) or (r t = 870 ), i o = -20 a figure 11 v dd - 1.0 v dd vi f = 0 ma, v i = 0 v (r t = 1.68 k ) or (r t = 870 ), i o = -3.2 ma figure 11 logic low output voltage v ol 0.03 0.1 v i f = 2 ma, v i = 5 v (r t = 1.68 k ) or v i = 3.3v (r t = 870 ), i o = 20 a figure 11 0.18 0.4 v i f = 2 ma, v i = 5 v (r t = 1.68 k ) or v i = 3.3v (r t = 870 ), i o = 3.2 ma figure 11 input threshold current i th 0.7 1.3 ma logic low output supply current i ddl 0.8 1.3 ma logic high output supply current i ddh 0.8 1.3 ma input capacitance c in 60 pf f = 1 mhz, v f = 0 v input diode temperature coe?cient v f / t a -1.6 mv/c i f = 2 ma
8 switching speci?cations (ac) over the recommended temperature (t a = C40c to +105c) and supply voltage (2.7 v v dd 5.5 v). all typical speci- ?cations are at v dd = 5 v, t a = 25c. parameter symbol min typ max units test conditions propagation delay time to logic low output [1] t phl 46 80 ns i f = 2 ma, v i = 5 v, r t = 1.68 k , c l = 15 pf, cmos signal levels. i f = 2 ma, v i = 3.3 v, r t = 870 , c l = 15 pf, cmos signal levels. figure 11 propagation delay time to logic high output [1] t plh 40 80 ns pulse width t pw 100 ns pulse width distortion [2] pwd 6 30 ns propagation delay skew [3] t psk 30 ns output rise time (10% C 90%) t r 12 ns i f = 2 ma, v i = 5 v, r t = 1.68 k , c l = 15 pf, cmos signal levels. figure 11 10 ns i f = 2 ma, v i = 3.3 v, r t = 870 , c l = 15 pf, cmos signal levels. figure 11 output fall time (90% - 10%) t f 12 ns i f = 2 ma, v i = 5 v, r t = 1.68 k , c l = 15 pf, cmos signal levels. figure 11 10 ns i f = 2 ma, v i = 3.3 v, r t = 870 , c l = 15 pf, cmos signal levels. figure 11 static common mode transient immunity at logic high output [4] | cm h | 20 35 kv/ sv cm = 1000 v, t a = 25c, i f = 0 ma, v i = 0 v (r t =1.68 k ) or (r t = 870 ), c l = 15 pf, cmos signal levels. figure 11 static common mode transient immunity at logic low output [5] | cm l | 20 35 kv/ sv cm = 1000 v, t a = 25c, v i = 5 v (r t = 1.68 k ) or v i = 3.3 v (r t = 870 ), i f = 2 ma, c l = 15 pf, cmos signal levels. figure 11 dynamic common mode transient immunity [6] cmr d 35 kv/ sv cm = 1000 v, t a = 25c, i f = 2 ma, v i = 5 v (r t = 1.68 k ) or v i = 3.3 v (r t = 870 ), 10mbd datarate, the absolute increase of pwd < 10ns figure 11
9 package characteristics all typicals are at t a = 25c. parameter symbol part number min typ max units test conditions input-output insulation v iso acpl-061l^ acpl-064l acpl-m61l 3750 v rms rh < 50% for 1 min. t a = 25c acpl-w61l acpl-k64l 5000 input-output resistance r i-o 10 12 v i-o = 500 v input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 25c ^ advanced information, may subject to changes. notes: 1. t phl propagation delay is measured from the 50% (v in or i f ) on the rising edge of the input pulse to the 50% v dd of the falling edge of the v o signal. t plh propagation delay is measured from the 50% (v in or i f ) on the falling edge of the input pulse to the 50% level of the rising edge of the v o signal. 2. pwd is de?ned as |t phl - t plh |. 3. t psk is equal to the magnitude of the worst case di?erence in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 4. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. 6. cm d is the maximum tolerable rate of the common mode voltage dur ing data transmission to assure that the absolute increase of the pwd is less than 10 ns.
10 figure 1. typical input diode forward current characteristic. figure 2. typical input threshold current versus temperature. figure 3. typical logic high output supply current versus temperature. figure 4. typical logic low output supply current versus temperature. figure 5. typical switching speed versus pulse input with a 5 v supply voltage. figure 6. typical switching speed versus pulse input current with a 3.3 v supply voltage. 0 0.2 0.4 0.6 0.8 1 -40 -20 0 20 40 60 80 100 120 t a - temperature - c i th - input threshold current - ma 3.3v 5v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -40 0 40 80 120 t a - temperature - c i ddh - logic high output supply current - ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -40 0 40 80 120 t a - temperature - c i ddl - logic low output supply current - ma -10 0 10 20 30 40 50 60 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i f - pulse input current - ma t p - propagation delay; pwd-pulse width distortion - ns t phl _5.0v t plh _5.0v pwd_5.0v -10 0 10 20 30 40 50 60 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i f - pulse input current -ma t p - propagation delay; pwd-pulse width distortion - ns 3.3v 5v 3.3v 5v t phl _3.3v t plh _3.3v pwd_3.3v 0.01 0.1 1 10 1.1 1.2 1.3 1.4 1.5 v f - forward voltage - v i f - forward current - ma i f v f t a = 25c
11 figure 7. typical v f versus temperature. supply bypassing, led bias resistors and pc board layout the acpl-x6xl optocouplers are extremely easy to use and feature high speed, push-pull cmos outputs. pull-up resistors are not required. the external components required for proper operation are the input limiting resistors and the output bypass capacitor. capacitor values should be 0.1 f. for each capacitor, the total lead length connecting the capacitor to the v dd and gnd pins should not exceed 20 mm. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -40 -20 0 20 40 60 80 100 t a - temperature - c v f - forward voltage - v figure 8. recommended printed circuit board layout and input current limiting resistor selection. for acpl-m61l/w61l: v dd = 3.3 v: r 1 = 510 1%, r 2 = 360 1% v dd = 5.0 v: r 1 = 1000 1%, r 2 = 680 1% r t = r 1 + r 2 r 1 /r 2 1.5 c = 0.1 f 5 4 6 3 1 xxx yww i f gnd 1 v o v dd c gnd 2 v i r 1 r 2 5 3 4 2 7 6 8 1 xxx yww i f gnd 1 v o v dd c gnd 2 v i r 1 r 2 acpl-m61l acpl-w61l acpl-064l/k64l acpl-061l 5 4 6 3 2 1 xxx yww i f gnd 1 v o v dd c gnd 2 v i r 1 r 2 5 3 4 2 7 6 8 1 xxx yww i f gnd 1 v o1 v dd c gnd 2 v i r 1 r 2 i f gnd 2 v i r 1 r 2 v o2 for acpl-061l/064l/k64l: v dd = 3.3 v: r 1 = 430 1%, r 2 = 430 1% v dd = 5.0 v: r 1 = 845 1%, r 2 = 845 1% r t = r 1 + r 2 r 1 /r 2 1
12 figure 10. parallel data transmission example figure 9. propagation delay skew waveform propagation delay is a ?gure of merit which describes how quickly a logic signal propagates through a system. the propagation delay from low-to-high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high-to-low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high-to-low (see figure 9). pulse-width distortion (pwd) results when t plh and t phl di?er in value. pwd is de?ned as the di?erence between t plh and t phl. pwd determines the maximum data rate of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, a pwd of 20-30% of the minimum pulse width is tolerable; the exact ?gure depends on the particular application (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important parameter to consider in parallel data applications where synchroni- zation of signals on parallel data lines is a concern. if the parallel data is being sent through a group of opto- couplers, di?erences in propagation delays will cause the data to arrive at the outputs of the optocouplers at di?erent times. if this di?erence in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. propagation delay skew is de?ned as the di?erence between the minimum and maximum propagation delays, either t plh or t phl , for any given group of opto- couplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). as shown in figure 10, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the di?erence between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. the ?gure shows data and clock signals at the inputs and outputs of the optocou- plers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. figure 10 shows that there will be uncertainty in both the data and the clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the t psk speci?ed optocouplers o?er the advantages of guaranteed speci?cations for propagation delays, pulse- width distortion and propagation delay skew over the recommended temperature, and power supply ranges. 50% 50% t psk v i v o v i v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t psk t psk propagation delay, pulse-width distortion and propagation delay skew
13 optocoupler cmr performance the principal protection against common mode noise, comes from the fundamental isolation properties of the optocoupler, and this in turn is directly related to the input-output leakage capacitance of the optocoupler. to provide maximum protection to circuitry connected to the input or output of the optocoupler the leakage capac- itance is minimized by having large separation distances at all points in the optocoupler construction, including the led/photodiode interface. in addition to the optocouplers basic physical construc- tion, additional circuit design steps mitigate the e?ects of common mode noise. the most important of these is the faraday shield on the photodetector stage. a faraday shield is e?ective in optocouplers because the internal modulation frequency (light) is many orders of magnitude higher than the common mode noise frequency. improving cmr performance at the application level in an end application it desirable that the optocouplers common mode isolation be as close as possible to that indicated in the data sheet speci?cations. the ?rst step in meeting this goal is to ensure maximum separation between pcb interconnects on either side of the opto- coupler is maintained and that pcb tracks beneath the optocoupler are avoided. it is inevitable that a certain amount of cmr noise will be coupled into the inputs and this can potentially result in false-triggering of the input. this problem is frequently observed in devices with input high input impedance. in some cases this can cause momentary missing pulses and may even cause input circuitry to latch-up in some alternate technologies. the acpl-x6xl optocoupler family does not have an input latch-up issue. even at very high cmr levels such as those experienced in end equipment level tests (for example iec61000-4-4) the acpl-x6xl series is immune to latch-up because of the simple diode structure of the led. in some cases achieving the rated data sheet cmr per- formance level is not possible in an application. this is often because of the practical need to actually connect the isolator input to the output of a dynamically changing signal rather than tying the input statically to v dd or gnd. a data sheet cmr specmanship issue is often seen with alternative technology isolators that are based on ac encoding techniques. to address the need to de?ne achievable end application performance on data sheets, the acpl-x6xl optocouplers include an additional typical performance speci?cation for dynamic cmr in the electrical parameter table. the dynamic cmr speci?cation indicates the typical achiev- able cmr performance as the input is being toggled on or o? during a cmr transient. the logic output the acpl-x6xl optocouplers is mainly controlled by led current level, and since the led current features very fast rise and fall times, dynamic noise immunity is essentially the same as static noise immunity. despite their immunity to input latch-up and the excellent dynamic cmr immunity, acpl-x6xl opto- coupler devices are still potentially vulnerable to miss- operation caused by the led being turned either on or o? during a cmr disturbance. if the led status could be ensured by design, the overall application level cmr performance would be that of the photodetector. to bene?t from the inherently high cmr capabilities of the acpl-x6xl family, some simple steps about operating the led at the application level should be taken. in particular, ensure that the led stays either on or o? during a cmr transient. some common design techniques to accomplish this are: keep the led on: i) overdrive the led with a higher than required forward current. keep the led o?: i) reverse bias the led during the o? state. ii) minimize the o?-state impedance across the anode and cathode of the led during the o? state. all these methods allow the full cmr capability of the acpl-x6xl family to be achieved, but they do have practical implementation issues or require a compromise on power consumption. there is, however, an e?ective method to meet the goal of maintaining the led status during a cmr event with no other design compromises other than adding a single resistor. this cmr optimization takes advantage of the di?erential connection to the led. by ensuring the common mode impedances at both the cathode and anode of the led are equal, the cmr transient on the led is e?ectively canceled. as shown in figure 11, this is easily achieved by using two, instead of one, input bias resistors.
14 split led bias resistor for optimum cmr figure 11 shows the recommended drive circuit for the acpl-x6xl that gives optimum common-mode rejection. the two current setting resistors balance the common mode impedances at the leds anode and cathode. common-mode transients can capacitively couple from the led anode (or cathode) to the output-side ground causing current to be shunted away from the led (which is not wanted when the led should be on) or conversely cause current to be injected into the led (which is not wanted when the led should be o? ). figure 12 shows the parasitic capacitances (c la and c lc ) between the leds anode and cathode, and output ground. also shown in figure 12 on the input side is an ac-equivalent circuit. table 1 shows the directions of i lp and i ln depend on the polarity of the common-mode transient. for transients occurring when the led is on, common-mode rejection (cm l , since the output is at "low" state) depends on led current (i f ). for conditions where i f is close to the switching threshold (i th ), cm l also depends on the extent to which i lp and i ln balance each other. in other words, any condition where a common-mode transient causes a momentary decrease in i f (i.e. when dv cm /dt > 0 and |i fp | > |i fn |, referring to table 1). will cause a common-mode failure for transients which are fast enough. likewise for a common-mode transient that occurs when the led is o? (i.e. cm h , since the output is at "high" state), if an imbalance between i lp and i ln results in a transient i f equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below 2 v, which constitutes a cm h failure. the resistors recommended in figure 11 include both the output impedance of the logic driver circuit and the external limiting resistor. the balanced i led -setting resistors help equalize the common mode voltage change at the anode and cathode. this reduces i led changes caused by transient coupling through the parasitic capaci- tors c la and c lc shown in figure 12. for acpl-m61l/w61l: v dd2 = 3.3 v: r 1 = 510 1%, r 2 = 360 1% v dd2 = 5.0 v: r 1 = 1000 1%, r 2 = 680 1% r t = r 1 + r 2 r 1 /r 2 1.5 v dd gnd 2 v dd2 0.1 f gnd 1 r 2 r 1 shield v o 74ls04 or any totem-pole output logic gate figure 11. recommended high-cmr drive circuit for the acpl-x6xl. for acpl-061l/064l/k64l: v dd = 3.3 v: r 1 = 430 1%, r 2 = 430 1% v dd = 5.0 v: r 1 = 845 1%, r 2 = 845 1% r t = r 1 + r 2 r 1 /r 2 1
15 figure 12. ac equivalent circuit of acpl-x6xl. gnd 2 v o v dd2 0.1 f r 1 shield r 2 i ln i lp c lc c la table 1. common mode pulse polarity and led current transients if dv cm /dt is: then i lp ?ows: and i ln ?ows: if |i lp | < |i ln | led current i f is momentarily: if |i lp | > |i ln | led current i f is momentarily: positive (> 0) away from the led anode through c la away from the led cathode through c lc increased decreased negative (< 0) toward the led anode through c la toward the led cathode through c lc decreased increased for acpl-061l/064l/k64l: v dd = 3.3 v: r 1 = 430 1%, r 2 = 430 1% v dd = 5.0 v: r 1 = 845 1%, r 2 = 845 1% r t = r 1 + r 2 r 1 /r 2 1 for acpl-m61l/w61l: v dd2 = 3.3 v: r 1 = 510 1%, r 2 = 360 1% v dd2 = 5.0 v: r 1 = 1000 1%, r 2 = 680 1% r t = r 1 + r 2 r 1 /r 2 1.5
16 glitch free power-up and power-down feature. upon powering-up or powering-down of the optocoupler, glitches produced in the output are undesirable. glitches can lead to false data in the optocoupler application. acpl-x6xl has a feature that holds the output in a known state until v dd is at a safe level. figure 13 and 14 show typical output waveforms during power-up and power- down process. slew-rate controlled outputs feature typically, the output slew rate (rise and fall time) will vary with the output load, as more time is needed to charge up the higher load. the propagation delay and the pwd will increase with the load capacitance. this will be an issue especially in parallel communication because di?erent communication line will have di?erent load capacitances. however, avagos new optocoupler acpl-x6xl has built in slew-rate controlled feature, to ensure that the output rise and fall time remain stable across wide load capacitance. figure 15 shows the rise time and fall time for acpl-x6xl at 3.3v and 5v. 500 s v dd2 =1 v ( t yp) v dd2 h igh i mpedence h igh i mpedence i. led is off ou t pu t figure 13. v dd ramp when led is o?. h igh i mpedence 500 s v dd2 =1 v ( t yp) ii. led is on v dd2 ou t pu t v dd2 = 2v ( t yp) discharge de l ay, depending on t he power supp l y s l ew ra t e h igh i mpedence figure 14. v dd ramp when led is on. figure 15. rise and fall time of acpl-x6xl across wide load capacitance rise time (v dd = 5.0v) 0 5 10 15 20 25 30 -40 -20 0 20 40 60 80 100 temperature (c) rise time (ns) 10pf 15pf 22pf 33pf 47pf 100pf 0 5 10 15 20 25 -40 -20 0 20 40 60 80 100 temperature (c) fall time (ns) fall time (v dd = 5.0v) 10pf 15pf 22pf 33pf 47pf 100pf rise time (v dd = 3.3v) 0 5 10 15 20 25 -40 -20 0 20 40 60 80 100 temperature (c) rise time (ns) 10pf 15pf 22pf 33pf 47pf 100pf fall time (v dd = 3.3v) 0 5 10 15 20 25 -40 -20 0 20 40 60 80 100 temperature (c) rise time (ns) 10pf 15pf 22pf 33pf 47pf 100pf
v dd2 = 5 v, i f = 2 ma 0 10 20 30 40 50 60 -40 -20 0 20 40 60 80 100 temp ( c) t p or pwd (ns) t phl t plh t phl t plh pwd v dd2 = 3.3 v, i f = 2 ma 0 10 20 30 40 50 60 -40 -20 0 20 40 60 80 100 temp ( c) t p or pwd (ns) t phl t plh t phl t plh pwd with peaking no peaking with peaking no peaking for product i nf or m atio n a n d a co m plete list o f distri b utors, please go to our we b site: www.avagotech.com a v ago, a v ago tech n ologies, the a logo a n d r 2 coupler? are trade m arks o f a v ago tech n ologies i n the u n ited states a n d other cou n tries. data su b ject to cha n ge. cop y right ? 2005 - 2010 a v ago tech n ologies. all rights reser v ed. av02 - 2150en - april 8, 2010 speed improvement a peaking capacitor can be placed across the input current limit resistor (figure 11) to achieve enhanced speed per- formance. the value of the peaking cap is dependent to the rise and fall time of the input signal and supply voltages and led input driving current (i f ). figure 12 shows signi?cant improvement of propagation delay and pulse with distortion with added peak capacitor at driving current of 2ma and 3.3v/5v power supply. figure 16. connection of peaking capacitor (cpeak) in parallel of the input limiting resistor (r 1 ) to improve speed performance (i) v dd2 = 5v, cpeak = 47pf, r 1 = 845 (ii) v dd2 = 3.3v, cpeak = 47pf, r 1 = 430 figure 17. improvement of tp and pwd with added 47pf peaking capacitor in parallel of input limiting resistor. gnd 2 v dd2 0.1f gnd 1 r 1 shield v in + ? c peak v o r 2

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