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scd7000a rev c features full militarized pmc-sierra rm7000a microprocessor dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance 225, 300, 350 mhz operating frequency consult factory for latest speeds mips iv superset instruction set architecture high performance interface (rm52xx compatible) 800 mb per second peak throughput 100 mhz max. freq., multiplexed address/data supports 1/2 clock multipliers (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9) ieee 1149.1 jtag (tap) boundary scan integrated primary and secondary caches - all are 4-way set associat ive with 32 byte line size 16kb instruction 16kb data: non-blocking and write-back or write-through 256kb on-chip secondary: unified, non-blocking, block writeback mips iv instruction set data prefetch instruction allows the processor to overlap cache miss latency and instruction execution floating point combined multiply-add instruction increases performance in signal processing and graphics applications conditional moves reduce branch frequency index address modes (register + register) embedded supply de-coupling capacitors and additional pll filter components integrated memory management unit (act52xx compatible) fully associative joint tlb (shared by i and d translations) 48 dual entries map 96 pages 4 entry dtlb and 4 entry itlb variable page size (4kb to 16mb in 4x increments) embedded application enhancements specialized dsp intege r multiply-accumulate instruction, (mad/madu) and three-operand multiply instruction (mul/u) per line cache locking in primaries and secondary bypass secondary cache option i&d test/break-point (watch) registers for emulation & debug performance counter for system and software tuning & debug ten fully prioritized vectored interrupts - 6 external, 2 internal, 2 software fast hit-writeback-invalidate and hit-invalidate cache operations for efficient cache management high-performance floating point unit - 700m flops maximum single cycle repeat rate for common single-precision operations and some double-precision operations single cycle repeat rate for single-precision combined multiply-add operations two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations fully static cmos design with dynamic power down logic standby reduced power mode with wait instruction 3 watts typical @ 1.8v int., 3.3v i/o, 300mhz 208-lead cqfp, cavity-up package (f17) 208-lead cqfp, inverted footprint (f24), with the same pin rotation as the commercial pmc-sierra rm5261a act 7000asc standard products october 9, 2009 64-bit superscaler microprocessor www.aeroflex.com/avionics
2 scd7000a rev c 9/9/09 aeroflex plainview block diagram pad buffer address buffer a/d bus pad bus m-pipe bus dva d bus f-pipe bus itag dtlb dtag itlb set b secondary tags set a secondary tags set c secondary tags set d secondary tags 4 - way set associative primary data cache on - chip 256k byte secondary cache, 4 - way set associative 4 - way set associative primary instruction cache store buffer write buffer read buffer prefetch buffer instruction dispatch unit m pipe register f pipe register floating - point control floating-point load / align floating-point register file packer / unpacker comparator floating-point multadd, add, sub, cvt, div, sqrt multiplier array iva program counter itlb virtuals branch pc adder pc incrementer system / memory control joint tlb co-processor 0 int mult. div. madd pll/clocks fa bus integer control load aligner integer register file m pipe f pipe dtlb virtuals adder stain/sh shifter adder logicals logicals
3 scd7000a rev c 9/9/09 aeroflex plainview description the act 7000asc is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. it has two high performance 64-bit integer units as well as a high throughput, fully pipelined 64-bit floating point unit. to keep its multiple execution un its running efficiently, the act 7000asc integrates not only 16kb 4-way set associative instruction and da ta caches but backs them up with an integrated 256kb 4-way set associative secondary as well. for maximum efficiency, the data and secondary caches are writeback and nonblocking. a rm52xx family compatible, operating system friendly memory management unit with a 64/48-entry fully associative tlb and a high-performance 64-bit system interface supporting hardware prioritized and vect ored interrupts round out the main features of the processor. the act-7000asc is ideally suited for high end embedded control applications such as: avionics upgrades, unmanned aerial/land/underwater vehicle guidance systems, flight computers, digital mapping systems and smart munitions. the multiply-a ccumulate operation is the core primitive of almost all signal processing algorithms allowing the act-7000asc to eliminate the need for a separate dsp engine in ma ny embedded applications. hardware overview the act 7000asc offers a high-level of integration targeted at high-performance embedded applications. the key elements of the act 70 00asc are briefly described below. cpu registers like all mips isa processors, the act 7000asc cpu has a simple, clean user visible state consisting of 32 general purpose registers, or gpr?s, two special purpose registers for integer multiplic ation and division, and a program counter; there are no condition code bits. figure 1 shows the user visible state. superscalar dispatch the act 7000asc has an efficient symmetric superscalar dispatch unit which a llows it to issue up to two instructions per cycle. for purp oses of instruction issue, the act 7000asc defines four classes of instructions: integer, load/store, branches, and floating-point. there are two logical pipelines, the function , or f, pipeline and the memory , or m, pipeline. note however that the m pipe can execute integer as well as memory type instructions. figure 2 is a simplification of the pipeline section and illustrates the basics of th e instruction is sue mechanism. table 1 ? instruction issue rules f pipe m pipe one of: one of: integer, branch, floating-point, integer mul, div integer, load/store general purpose registers 63 0 multiply/divide registers 063 0 r1 hi r2 63 0 ?lo ? ? program counter ?63 0 r29 pc r30 r31 figure 1 ? cp0 registers
4 scd7000a rev c 9/9/09 aeroflex plainview figure 2 is a simplification of the pipeline section and illustrates the basics of the instruction issue mechanism. the figure illustrates that one f pipe instruction and one m pipe instruction can be issu ed concurrently but that two m pipe or two f pipe instructions cannot be issued. table 2 specifies more completely th e instructions within each class. . the symmetric superscal ar capability of the act 7000asc, in combination w ith its low latency integer execution units and high-throughput fully pipelined floating-point execution un it, provides unparalleled price/performance in comput ational intensive embedded applications. pipeline the logical length of both the f and m pipelines is five stages with state committing in the register write, or w, pipe stage. the physical length of the floating-point execution pipeline is actually seven stages but this is completely transparent to the user. figure 3 shows instruction execution within the act 7000asc when inst ructions are issuing simultaneously down both pipe lines. as illustrated in the figure, up to ten instructions can be executing simultaneously. this figure presents a somewhat simplistic figure 2 ? instruction issue paradigm fp f pipe f pipe ibus m pipe ibus fp m pipe integer f pipe integer m pipe dispatch unit instruction cache table 2 ? dual issue instruction classes integer load/store floating-point branch add, sub, or, xor, shift, etc. lw, sw, ld, sd, ldc1, sdc1, mov, movc, fmov, etc. fadd, fsub, fmult, fmadd, fdiv, fcmp, fsqrt, etc. beq, bne, bczt, bczf, j, etc. i0 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i1 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i2 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i3 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i4 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i5 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i6 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i7 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i8 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w i9 1l 2l 1r 2r 1a 2a 1d 2d 1w 2w one cycle 1i-1r: 2i: 2r: 1a: 1a: 1a-2a: 2a: 2a-2d: 1d: 2w: instruction cache access instruction virtual to physical address translation register file read, bypass calculation, instruction decode, branch address calculation issue or slip decision, branch decision data virtual address calculation integer add, logical, shift store align data cache access and load align data virtual to physical address translation register file write figure 3 ? pipeline
5 scd7000a rev c 9/9/09 aeroflex plainview view of the processors operation however since the out-of-order completion of load s, stores, and long latency floating-point operations can result in there being even more instructions in pro cess than what is shown. note that instruction depend encies, resource conflicts, and branches result in some of the instruction slots being occupied by nops. integer unit like the act 52xx family, the act 7000asc implements the mips iv inst ruction set architecture, and is therefore fully upward comp atible with applications that run on processors such as the r4650 and r4700 that implement the earlier generatio n mips iii instruction set architecture. additionally, the act 7000asc includes two implementation specific in structions not found in the baseline mips iv isa, but that are useful in the embedded market place. described in de tail in a later section of this datasheet, these instructions are integer multiply-accumulate and thr ee-operand integer multiply. the act 7000asc integer unit includes thirty-two general purpose 64-bit registers, the hi/lo result registers for the two-pipeline operan d integer multiply/divide operations, and the program counter, or pc. there are two separate execution units, one of which can execute function, or f, type instruc tions and one which can execute memory, or m, type inst ructions. see above for a description of the instruction types and the issue rules. as a special case, intege r multiply/divide instructions as well as their corresponding mfhi and mflo instructions can only be executed in the f t ype execution unit. within each execution unit the operational characteristics are the same as on previous mips design s with single cycle alu operations (add, sub, logical, shift), one cycle load delay, and an autonomous multiply/divide unit. register file the act 7000asc has thirty-two general purpose registers with register loca tion (r0) hard wired to zero value. these registers are used for scalar integer operations and address calculation. in orde r to service the two integer execution units, the register file has four read ports and two write ports and is fully bypa ssed both within and between the two execution units to mi nimize operation latency in the pipeline. alu the act 7000asc has two complete integer alu?s each consisting of an integer adder/subtractor, a logic unit, and a shifter. table 3 shows th e functions performed by the alu?s for each execution unit. each of these units is optimized to perform all operat ions in a single processor cycle. integer multiply/divide the act 7000asc has a single dedicated integer multiply/divide unit optimized for high-speed multiply and multiply-accumulate operatio ns. the multiply/divide unit resides in the f type execution unit. table 4 shows the performance of the multiply/div ide unit on each operation. the baseline mips iv isa specif ies that the results of a multiply or divide operation be placed in the hi and lo registers. these values can then be transferred to the general purpose register file using the move-from-hi and move-from-lo (mfhi/mflo) instructions. in addition to the baselin e mips iv integer multiply instructions, the act 7000a sc also implements the 3-operand multiply instructio n, mul. this instruction specifies that the multiply resu lt go directly to the integer register file rather than the lo register. the portion of the multiply that would have norma lly gone into the hi register is discarded. for applications where it is known that the upper half of the multiply resu lt is not required, using the mul instruction eliminates the necessity of executing an explicit mflo instruction. also included in the act 7000asc are the multiply-add instructions m ad/madu. this instruction multiplies two operands and ad ds the resulting product to the current contents of the hi and lo registers. the multiply-accumulate operatio n is the core primitive of almost all signal processing algorithms allowing the act 7000asc to eliminate the need for a separate dsp engine in many embedded applications. table 3 ? alu operations unit f pipe m pipe adder add, sub add, sub, data address add logic logic, moves, zero shifts (nop) logic, moves, zero shifts (nop) shifter non zero shift non zero shift, store align table 4 ? integer multiply / divide operations opcode operand size latency repeat rate stall cycles mult/u, mad/u 16 bit430 32 bit540 mul 16 bit 4 3 2 32 bit543 dmult, dmultu any980 div, divd any 36 36 0 ddiv, ddivu any 68 68 0
6 scd7000a rev c 9/9/09 aeroflex plainview by pipelining the multiply- accumulate function and dynamically determining the size of the input operands, the act 7000asc is able to ma ximize throughput while still using an area efficient implementation. floating-point coprocessor the act 7000asc incorporates a high-performance fully pipe-lined floating-poin t coprocessor which includes a floating-point register f ile and autonomous execution units for multiply/ add/convert and divide/square root. the floating-point coprocessor is a tightly coupled co-execution unit, decoding and executing instructions in parallel with, and in the case of floating-point loads and stores, in cooperation with th e m pipe of the integer unit. as described earlier, the superscalar capabilities of the act 7000asc allow floa ting-point computation instructions to issue concurrent ly with integer instructions. floating-point unit the act 7000asc floatin g-point execution unit supports single and double precision arithmetic, as specified in the ieee stan dard 754. the execution unit is broken into a separate divide/square root unit and a pipelined multiply/add unit. ov erlap of divide/square root and multiply/add is supported. the act 7000asc main tains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. precise exceptions are extremely important in object-oriented programming environments and highly desirable for debugging in any environment. the floating-point unit?s operation set includes floating-point add, subtract , multiply, multiply-add, divide, square root, reciprocal, recipr ocal square root, conditional moves, conversion between fixed-point and floating-point format, conversion between floating-point formats, and floating-point compare. table 5 gives the latencies of the floating-point instructions in internal processor cycles. floating-point general register file the floating-point general register file, fgr, is made up of thirty-two 64-bit registers. with the floating-point load and store double instructions, ldc1 and sdc1, the floating-point unit can take advantage of the 64-bit wide data cache and issue a floating-point coprocessor load or store double-word instruction in every cycle. the floating-point control re gister file contains two registers; one for determining configuration and revision information for the coproce ssor and one for control and status information. these registers are primarily used for diagnostic software, exception handling, state saving and restoring, and control of rounding modes. to support superscalar operations, the fgr has four read ports and two write ports, and is fully bypassed to minimize operation latency in the pipeline. three of the read ports and one write port are used to support the combined multiply-add instruction while the fourth read and second write port allows a concurrent floating-point load or store and conditional moves. system control coprocessor (cp0) the system control coprocessor (cp0) in the mips architecture is responsible for the virtual memory sub-system, the exception control system, and the diagnostics capability of the processor. in the mips architecture, the system contro l coprocessor (and thus the kernel software) is implemen tation dependent. for memory management, the act 7000asc cp0 is logically identical to that of the rm5200 fam ily and r5000. for interrupt exceptions and diagnostics, the act 7000asc is a superset of the rm5200 family and r5000 implementing additional features describe d later in the sections on interrupts, the test/bre akpoint facility, and the performance counter facility. table 5 ? floating point latencies and repeat rates operation latency single/double repeat rate single/double fadd 4 1 fsub 4 1 fmult 4/5 1/2 fmadd 4/5 1/2 fmsub 4/5 1/2 fdiv 21/36 19/34 fsqrt 21/36 19/34 frecip 21/36 19/34 frsqrt 38/68 36/66 fcvt.s.d 4 1 fcvt.s.w 6 3 fcvt.s.l 6 3 fcvt.d.s 4 1 fcvt.d.w 4 1 fcvt.d.l 4 1 fcvt.w.s 4 1 fcvt.w.d 4 1 fcvt.l.s 4 1 fcvt.l.d 4 1 fcmp 1 1 fmov, fmovc 1 1 fabs, fneg 1 1
7 scd7000a rev c 9/9/09 aeroflex plainview the memory management unit controls the virtual memory system page mapping. it consists of an instruction address translation buffer, or itlb, a data address translation buffer, or dtlb, a joint tlb, or jtlb, and coprocessor registers used by the virtual memory mapping sub-system. system control coprocessor registers the act 7000asc incorporat es all system control coprocessor (cp0) registers internally. these registers provide the path through which the virtual memory system?s page mapping is examined and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). in addition, the act 7000asc includes registers to implement a real -time cycle counting facility, to aid in cache and system diag nostics, and to assist in data error detection. to support the non-blocking caches and enhanced interrupt handling capabilitie s of the act 7000asc, both the data and control register spaces of cp0 are supported by the act 7000asc. in the data re gister space, that is the space accessed using the mfc0 and mtc0 instructions, the act 7000asc supports the same registers as found in the rm5200, r4000 and r5000 families. in the control space, that is the space accessed by the previously unused ctc0 and cfc0 instructions, the act 7000asc supports five new registers. the first three of these new 32-bit registers support the enhanced interrupt handling capabilities and are the interrupt control, interrupt priority level lo (ipllo), and interrupt priority level hi (iplhi) registers. these registers are described further in the section on interrupt handling. the other two registers, imprecise error 1 and imprecise error 2 , have been added to help diagnose bus errors which occur on non-blocking memory references. figure 4 shows the cp0 registers. virtual to physical address mapping the act 7000asc provides three modes of virtual addressing: ? user mode ? supervisor mode ? kernel mode this mechanism is availabl e to system software to provide a secure environment for user processes. bits in the cp0 status register determine which virtual addressing mode is used. in the user mode, the act 7000asc provides a single, uniform virtual address space of 256gb (2gb in 32-bit mode). when operating in the kernel mode, four distinct virtual address spaces, totalling 1024 gb (4gb in 32-bit mode), are simultaneously available an d are differentiated by the high-order bits of the virtual address. the act 7000asc processor also supports a supervisor mode in which the virtual address space is 256.5gb (2.5gb in 32-bit mode), divided into three regions based on the high-order bits of the virtual address. figure 5 shows the address space layout for 32-bit operation. info 7* index 0* random 1* wired 6* prid 15* lladdr 17* taglo 28* taghi 29* epc 14* ecc 26* status 12* context 4* count 9* badvaddr 8* compare 11* cause 13* watch1 18* watch2 19* errorepc 30* config 16* perf counter 25* perf ctr cntrl 22* watch mask 24* iplhi 19* ipllo 18* intcontrol 20* imp error 1 26* imp error 2 27* pagemask 5* entryhi 10* entrylo1 3* entrylo0 2* tlb (entries protected from tlbwr) used for memory management * registered number used for exception processing control space registers xcontext 20* cacheerr 27* 47 0 figure 4 ? cp0 registers
8 scd7000a rev c 9/9/09 aeroflex plainview when the act 7000asc is configured for 64-bit addressing, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout. joint tlb for fast virtual-to-physical address translation, the act 7000asc uses a large, fully associative tlb that maps virtual pages to their corresponding physical addresses. as indicated by its name, the joint tlb (jtlb) is used for both instruction and data translations. the jtlb is organized as pairs of even/o dd entries, and maps a virtual address and address space iden tifier into the large, 64gb physical address space. by default, the jtlb is configured as 48 pairs of even/odd entries. the 64 even/odd entry optional configuration is set at boot time. two mechanisms are provided to assist in controlling the amount of mapped space, and the replacement characteristics of various memory regions. first, the page size can be configured, on a per-entry basis, to use page sizes in the range of 4kb to 16mb (in 4x multiples). a cp0 register, pagemask, is loaded with the desired page size of a mapping, and that si ze is stored into the tlb along with the virtual address when a new entry is written. thus, operating systems can create special purpose maps; for example, a typical frame buffer can be memory mapped using only one tlb entry. the second mechanism controls the replacement algorithm when a tlb miss occurs. the act 7000asc provides a random replacement algorithm to select a tlb entry to be written with a new mapping; however, the processor also provides a mechanism whereby a system specific number of mappings ca n be locked into the tlb, thereby avoiding random repl acement. this mechanism allows the operating system to guarantee that certain pages are always mapped for performance reasons and for deadlock avoidance. this me chanism also facilitates the design of real-time system s by allowing deterministic access to critical software. the jtlb also contains information that controls the cache coherency protocol for each page. specifically, each page has attribute bits to de termine whether the coherency algorithm is: uncached, write -back, write-through with write-allocate, write-thr ough without write-allocate, write-back with secondary bypa ss. note that both of the write-through protocols bypass the secondary cache since it does not support writes of less than a complete cache line. these protocols are used for both code and data on the act 7000asc with data using write-back or write-through depending on the application. the write-through modes support the same efficient frame buffer handling as the rm5200 family, r4700 and r5000. instruction tlb the act 7000asc uses a 4-entry instruction tlb (itlb) to minimize contention for the jtlb, to eliminate the critical path of translating through a large associative array, and to save power. each itlb entry maps a 4kb page. the itlb improves performance by allowing instruction address tr anslation to occur in parallel with data address translation. when a mi ss occurs on an instruction address translation by the itlb, the least-recently used itlb entry is filled from the jtlb. the operation of the itlb is completely transparent to the user. data tlb the act 7000asc uses a 4-entry data tlb (dtlb) for the same reasons cited above for the itlb. each dtlb entry maps a 4kb page. the dtlb improves performance by allowing data address tran slation to occur in parallel with instruction address transl ation. when a miss occurs on a data address translation by the dtlb, the dtlb is filled from the jtlb. the dtlb ref ill is pseudo-lru: the least recently used entry of the least recently used pair of entries is filled. the operation of the dtlb is completely transparent to the user. cache memory in order to keep the ac t 7000asc?s superscalar pipeline full and operating efficiently, the act 7000asc has integrated primary instru ction and data caches with single cycle access as well as a large unified secondary figure 5 ? kernel mode virtual addressing (32-bit mode) 0xffffffff kernel virtual address space (kseg3) mapped, 0.5gb 0xe0000000 0xdfffffff supervisor virtual address space (ksseg) mapped, 0.5gb 0xc0000000 0xbfffffff uncached kernel physical address space (kseg1) unmapped, 0.5gb 0xa0000000 0x9fffffff cached kernel physical address space (kseg0) unmapped, 0.5gb 0x80000000 0x7fffffff user virtual address space (kuseg) mapped, 2.0gb 0x00000000
9 scd7000a rev c 9/9/09 aeroflex plainview cache with a three cycle miss penalty from the primaries. each primary cache has a 64-bit read path, a 128-bit write path, and both caches can be accessed simultaneously. the primary caches provide the in teger and floating-point units with an aggregate band-width of 3.6 gb per second at an internal clock frequency of 22 5 mhz. during an instruction or data primary cache ref ill, the secondary cache can provide a 64-bit datum every cycle following the initial three cycle latency for a peak bandwidth of 2.4 gb per second. instruction cache the act 7000asc has an integrated 16kb, four-way set associative instructio n cache and, even though instruction address tr anslation is done in parallel with the cache access, the combination of 4-way set associativity and 16kb size results in a cach e which is virtually indexed and physically tagged. since the effective physical index eliminates the potential for virt ual aliases in the cache, it is possible that some operating system code can be simplified as compared with the rm5200 family, r5000 and r4000 class processors. the data array portion of the instruction cache is 64 bits wide and protected by word pa rity while the tag array holds a 24-bit physical address, 14 housekeeping bits, a valid bit, and a single bit of parity protection. by accessing 64 bits per cy cle, the instruction cache is able to supply two instructions per cycle to the superscalar dispatch unit. for signal processing, graphics, and other numerical code sequences wher e a floating-point load or store and a floating-point comp utation instruction are being issued together in a loop, the entire bandwidth available from the instruction cache will be consumed by instruction issue. for typical integer co de mixes, where instruction dependencies and other resource constraints restrict the achievable parallelism, the extra instruction cache bandwidth is used to fetch both the taken and non-taken branch paths to minimize the overall penalty for branches. a 32-byte (eight instruction) line size is used to maximize the communication efficiency between the instruction cache and the secondary cache, or memory system. the act 7000asc is the first mips risc microprocessor to support cache locking on a per line basis. the contents of each line of the cache can be locked by setting a bit in the tag. locking the line prevents its contents from being overwritten by a subsequent cache miss. refill will occur only in to unlocked cache lines. this mechanism allows the program mer to lock critical code into the cache thereby guaran teeing deterministic behavior for the locked code sequence. data cache the act 7000asc has an integrated 16kb, four-way set associative data cache, and even though data address translation is done in paralle l with the cache access, the combination of 4-way set associativity and 16kb size results in a cache which is physically indexed and physically tagged. since th e effective physical index eliminates the potential for vi rtual aliases in the cache, it is possible that some operating system code can be simplified compared to the rm5200 family, r5000 and r4000 class processors. the data cache is non-blocking; that is, a miss in the data cache will not ne cessarily stall the processor pipeline. as long as no inst ruction is encountered which is dependent on the data reference which caused the miss, the pipeline will continue to adva nce. once there are two cache misses outstanding, the proces sor will stall if it encounters another load or store instruction. a 32-byte (eight word) line size is used to maximize the communication efficiency between the data cache and the secondary cache or memory system. the data array portion of the data cache is 64 bits wide and protected by byte pa rity while the tag array holds a 24-bit physical address, 3 housekeeping bits, a two bit cache state field, and has two bits of parity protection. the normal write policy is write-bac k, which means that a store to a cache line does not immediately cause memory to be updated. this increases syst em performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. softwa re can, however, select write-through on a per-page basis when appropriate, such as for frame buffers. cache pr otocols supported for the data cache are: 1. uncached. reads to addresses in a memory area identified as uncached will not access the cache. writes to such addresses will be written directly to main memory withou t updating the cache. 2. write-back. loads and instruction fetches will first search the cache, reading the next memory hierarchy level only if the desired data is not cache resident. on data store operations, the cache is first searched to determine if the target address is cache resident. if it is resident, the cache contents will be updated, and the cache line marked fo r later write-back. if the cache lookup misses, the target line is first brought into the cache and then the write is performed as above. 3. write-through with write allocate. loads and instruction fetches will first search the cache, reading from memory only if the de sired data is not cache resident; write-through data is never cached in the secondary cache. on data store operations, the cache is first searched to determ ine if the target address is cache resident. if it is resident, the primary cache contents will be updated an d main memory will also be written leaving the write-back bit of the cache line unchanged; no writes will occur into the secondary. if the cache lookup misses, the target line is first brought into the cache and then the write is performed as above. 4. write-through without write allocate. loads and instruction fetches will first search the cache, reading from memory only if the de sired data is not cache resident; write-through data is never cached in the secondary. on data store operations, the cache is first searched to determine if the target address is cache resident. if it is resident, the cache contents will be updated and main memory will also be written
10 scd7000a rev c 9/9/09 aeroflex plainview leaving the write-back bit of the cache line unchanged; no writes will occur into the secondary. if the cache lookup misses, then only main memory is written. 5. write-back with secondary bypass. loads and instruction fetches first search the primary cache, reading from memory only if the desired data is not resident; the secondary is not searched. on data store operations, the primary cach e is first searched to determine if the target address is resident. if it is resident, the cache contents are updated, and the cache line marked for la ter write-back. if the cache lookup misses, the target line is first brought into the cache and then the write is performed as above. associated with the data ca che is the store buffer. when the act 7000asc executes a store instruction, this single-entry buffer gets written with the store data while the tag comparison is performed. if the tag matches, then the data is written into the data ca che in the next cycle that the data cache is not accessed (the next non-load cycle). the store buffer allows the act 7000asc to execute a store every processor cycle and to perform back-to-back stores without penalty. in the ev ent of a store immediately followed by a load to the same address, a combined merge and cache write will occur such that no penalty is incurred. secondary cache the act 7000asc has an integrated 256kb, four-way set associative, block write-back secondary cache. the secondary has the same line size as the primaries, 32 bytes, is logically 64-bits wide matc hing the system interface and primary widths, and is protected with doubleword parity. the secondary tag array holds a 20-bit physical address, 2 housekeeping bits, a three bit cache state field, and two parity bits. by integrating a secondary cache, the act 7000asc is able to dramatically decrease the latency of a primary cache miss without dramatically in creasing the number of pins and the amount of power required by the processor. from a technology point of view, in tegrating a secondary cache maximally leverages cmos semiconductor technology by using silicon to build the structures that are most amenable to silicon technology; silicon is being used to build very dense, low power memory arra ys rather than large power hungry i/o buffers. further benefits of an integr ated secondary are flexibility in the cache organization and management policies that are not practical with an exte rnal cache. two previously mentioned examples are th e 4-way associativity and write-back cache protocol. a third management policy fo r which integration affords flexibility is cache hierarch y management. with multiple levels of cache, it is nece ssary to specify a policy for dealing with cases where two ca che lines at level n of the hierarchy would, if possible, be sharing an entry in level n+1 of the hierarchy. the policy followed by the act 7000asc is motivated by the desire to get maximum cache utility and results in the act 7000asc allowing entries in the primaries which do not necessarily have a corresponding entry in the s econdary; the act 7000asc does not force the primaries to be a subset of the secondary. for example, if primary cache line a is being filled and a cache line already exists in the secondary for primary cache line b at the location where primary a?s line would reside then that secondary entry wi ll be replaced by an entry corresponding to primary cache line a and no action will occur in the primary for cach e line b. this operation will create the aforementioned s cenario where the primary cache line which initially ha d a corresponding secondary entry will no longer have such an entry. such a primary line is called an orphan. in genera l, cache lines at level n+1 of the hierarchy are called pa rents of level n?s children. another act 7000asc cache management optimization occurs for the ca se of a secondary cache line replacement where the secondary line is dirty and has a corresponding dirty line in the pr imary. in this case, since it is permissible to leave the dirty line in the primary, it is not necessary to write the se condary line back to main memory. taking this scenario one step further, a final optimization occurs when the aforementioned dirty primary line is replaced by another line and must be written back, in this case, it will be written directly to memory bypassing the secondary cache. secondary caching protocols unlike the primary data cache, the secondary cache supports only uncached and block write-back. as noted earlier, cache lines mana ged with either of the write-through protocols will not be placed in the secondary cache. a new caching attribut e, write-back with secondary bypass, allows the secondary to be bypassed entirely. when this attribute is selected, the secondarywill not be filled on load misses and will not be written on dirty write-backs from the primary. table 6 ? cache attributes attribute instruction data secondary size 16kb 16kb 256kb associativity 4-way 4-way 4-way replacement algorithm. cyclic cyclic cyclic line size 32 byte 32 byte 32 byte
11 scd7000a rev c 9/9/09 aeroflex plainview cache locking the act 7000asc allows critical code or data fragments to be locked into the primary and secondary caches. the user has complete control over what locking is performed with cache line gran ularity. for instruction and data fragments in the primarie s, locking is accomplished by setting either or both of the cac he lock enable bits in the cp0 ecc register, specifying the set via a field in the cp0 ecc register, and then executing either a load instruction or a fill_i cache operation for data or instructions respectively. only two sets ar e lockable within each cache: set a and set b. locking within the secondary works identically to the primaries us ing a separate secondary lock enable bit and the same set se lection field. as with the primaries, only two sets are lo ckable: sets a and b. table 7 summarizes the cache locking capabilities. cache management to improve the performance of critical data movement operations in the embedded environment, the act 7000asc significantly improves the speed of operation of certain critical cache management operations as compared with the r5 000 and r4000 families. in particular, the speed of the hit-write-back-invalidate and hit-invalidate cache operations has been improved in some cases by an order of magnitude over that of the earlier families. table 8 compares the act 7000asc with the r4000 and r5000 processors. for the hit-dirty case of h it-writeback-invalidate, if the writeback buffer is full from some previous cache eviction then n is the number of cycles required to empty the write-back buffer. if the buffer is empty then n is zero. the penalty value is the number of processor cycles beyond the one cycle required to issue the instruction that is required to implement the operation. primary write buffer writes to secondary cache or external memory, whether cache miss write-backs or stores to uncached or write-through addresses, use the integrated primary write buffer. the write buffer holds up to four 64-bit address and data pairs. the entire buffer is used for a data cache write-back and allows the proc essor to proceed in parallel with memory update. for uncached and write-through stores, the write buffer signif icantly increases performance by decoupling the sysad bus tr ansfers from the instruction execution stream. system interface the act 7000asc provides a high-performance 64-bit system interface which is compatible with the rm5200 family and r5000. unlike the r4000 and r5000 family processors which provide only an integral multiplication index vaddr 11..0 vaddr 11..0 paddr 15..0 ta g paddr 35..12 paddr 35..12 paddr 35..16 write policy n.a. write-back, write- through block write-back, bypass read policy n.a. non-blocking (2 outstanding) non-blocking (data only, 2 outstanding) read order critical word first critic al word first critical word first write order na sequential sequential miss restart following: complete line first double (if waiting for data) n.a. parity per word per byte per doubleword table 6 ? cache attributes (cont) attribute instruction data secondary table 7 ? cache locking control cache lock enable set select activate primary i ecc[27] ecc[28]= 0 a ecc[28]= 1 b fill_i primary d ecc[26] ecc[28]= 0 a ecc[28]= 1 b load/store secondary ecc[25] ecc[28]= 0 a ecc[28]= 1 b fill_i or load/store table 8 ? penalty cycle operation condition penalty act 7000asc r4000/r5000 hit-writeback- invalidate miss 0 7 hit-clean 3 12 hit-dirty 3+n 14+n hit-invalidate miss 0 7 hit 2 9
12 scd7000a rev c 9/9/09 aeroflex plainview factor between sysclock an d the pipeline clock, the act 7000asc also allows half-integral multipliers, thereby providing greater gr anularity in the designers choice of pipeline and syst em interface frequencies. the interface consists of a 64-bit address/data bus with 8 check bits and a 9-bit comman d bus. in addition, there are six handshake signals and six interrupt inputs. the interface has a simple timing sp ecification and is capable of transferring data between the processor and memory at a peak rate of 600 mb/sec with a 75 mhz sysclock. figure 6 shows a typical embedded system using the act 7000asc. this example shows a system with a bank of drams, and an interface asic which provides dram control as well as an i/o port. system address/data bus the 64-bit system address da ta (sysad) bus is used to transfer addresses and data between the act 7000asc and the rest of the system. it is protected with an 8-bit parity check bus, sysadc. the system interface is co nfigurable to allow easy interfacing to memory an d i/o systems of varying frequencies. the data rate and the bus frequency at which the act 7000asc transmits da ta to the system interface are programmable via boot ti me mode control bits. also, the rate at which the proce ssor receives data is fully controlled by the external de vice. therefore, either a low cost interface requiring no read or write buffering or a faster, high-performance in terface can be designed to communicate with the act 7000asc. again, the system designer has the flex ibility to make these price/performance trade-offs. system command bus the act 7000asc interface has a 9-bit system command (syscmd) bus. the command bus indicates whether the sysad bus carries an address or data. if the sysad bus carries an address, then the syscmd bus also indicates what type of trans action is to take place (for example, a read or write). if the sysad bus carries data, then the syscmd bus also gi ves information about the data (for example, this is the last data word transmitted, or the data contains an error). the syscmd bus is bidirectional to support both processor requests and external requests to the act 7000asc. processor requests are initiated by the act 7000asc and responded to by an external device. external requests are issued by an external device and require the act 7000asc to respond. the act 7000asc supports one to eight byte and 32-byte block transfers on the sysad bus. in the case of a sub-double-word transfer, the 3 low-order address bits give the byte address of the transfer, and the syscmd bus indicates the number of bytes being transferred. handshake signals there are six handshake signals on the system interface. two of these, rdrdy* and wrrdy *, are used by an external device to indicate to the act 7000asc whether it can accept a new read or write transaction. the act 7000asc samples these signals before deasserting the address on read and write requests. extrqst* and release* are used to transfer control of the sysad and syscmd buses from the processor to an external device. when an exte rnal device needs to control the interface, it asserts extrqst *. the act 7000asc responds by asserting release* to release the system interface to slave state. validout* and validin* are used by the act 7000asc and the external device respectively to indicate that there is a valid command or data on the sysad and syscmd buses. the act 7000asc asserts validout* when it is driving these bu ses with a valid command or data, and the external device drives validin* when it has control of the buses and is driving a valid command or data. system interface operation the act 7000asc can issue read and write requests to an external device, while an external device can issue null and write requests to the act 7000asc. for processor reads, the act 7000asc asserts validout* and simultaneously drives the address and read command on the sysad and syscmd buses. if the system interface has rdrdy* asserted, then the processor tristates its drivers and releases the syst em interface to slave state by asserting release *. the external device can then begin sending data to the act 7000asc. pci bus xx control dram latch 72 72 72 25 sysad bus syscmd memory i/o controller flash / address boot rom act 7000asc 8 figure 6 ? typical embedded system block diagram
13 scd7000a rev c 9/9/09 aeroflex plainview figure 7 shows a processor block read request and the external agent read respon se for a system with a transaction. the read latency is 4 cycles (validout* to validin *), and the response data pattern is ddxxdd. figure 8 shows a processor block write where the processor was programmed with write-back data rate boot code 2, or ddxxd-dxx. data prefetch the act 7000asc supports the mips iv integer data prefetch (pref) and floating-point data prefetch (prefx) instructions. these instructio ns are used by the compiler or by an assembly language programmer when it is known or suspected that an upcoming da ta reference is going to miss in the cache. by appropriately placing a prefetch instruction, the memory late ncy can be hidden under the execution of other instructions. if the execution of a prefetch instruction would cause a memory management or address error exception the prefetch is treated as a nop. the ?hint? field of the data prefetch instruction is used to specify the action taken by the instruction. the instruction can operate normally (that is, fetching data as if for a load operation) or it can allocate and fill a cache line with zeroes on a primary data cache miss. enhanced write modes the act 7000asc implemen ts two enhancements to the original r4000 write mechanism: write reissue and pipeline writes. in write reissu e mode, a write rate of one write every two bus cycles can be achieved. a write issues if wrrdy* is asserted two cycles earlier and is still asserted during the issue cycle. if it is not still asserted then the last write will reissue. pi pe-lined writes have the same two bus cycle write repeat rate, but can issue one additional write following the deassertion of wrrdy *. external requests the act 7000asc can respond to certain requests issued by an external device . these requests take one of two forms: write requests an d null requests. an external device executes a write request when it wishes to update one of the processors writable resources such as the internal interrupt register. a null reque st is executed when the external device wishes the processor to reassert ownership of the processor external inte rface. typically a null request will be executed after an external device, that has acquired control of the processor interface via extrqst *, has completed an independent tr ansaction between itself and system memory in a system where memory is connected directly to the sysad bus. norm ally this transaction would be a dma read or write from the i/o system. test / breakpoint registers to increase both observability and controllability of the processor thereby easing hardware and software debugging, a pair of test/break-point, or watch, registers, watch1 and watch2, have been added to the act 7000asc. each watch register can be separately enabled to watch for a load ad dress, a store address, or an instruction address. all address comparisons are done on physical addresses. an associated register, watch mask, has also been added so that either or both of the watch registers can compare against an address range rather than a specific address. the range granularity is limited to a power of two. when enabled, a match of e ither watch register results in an exception. if the watch is enabled for a load or store address then the exception is the watch exception as defined for the r4000 with cause exception code twenty-three. if the watch is enabled for instruction addresses then a newly defined instruction watch exception is taken and the cause code is sixteen. the watch register which caused the exception is indicated by cause bits 25..24. table 9 summarizes a watch operation. table 9 ? watch control register register bit field/function 63 62 61 60:36 35:2 1:0 watch1, 2 store load instr 0 addr 0 31:2 1 0 watch mask mask mask watch 2 mask watch 1 data0 ndata data1 ndata addr read sysad syscmd validout* validin* rdrdy* wrrdy* release* sysclock data2 data3 ndata neod figure 7 ? processor block read
14 scd7000a rev c 9/9/09 aeroflex plainview performance counters like the test/break-point capability desc ribed above, the performance counter feature has been added to improve the observability and controllability of the processor thereby easing system debug and, especially in the case of the performance counters, easing system tuning. the performance counter feat ure is implemented using two new cp0 registers, perfcount and perfcontrol. the perfcount register is a 32-bit writable counter which causes an interrupt when bit 31 is set. the perfcontrol register is a 32-bit register containing a five bit field which selects one of twenty-two event types as well as a handful of bits which control the ov erall counting function. note that only one event type can be counted at a time and that counting can occur for user code, kernel code, or both. the event types and control bits are listed in table 10. the performance counter inte rrupt will only occur when interrupts are enabled in the status register, ie=1, and interrupt mask bit 13 (im[1 3]) of the coprocessor 0 interrupt control register is not set. since the performance counter can be set up to count table 10 ? performance counter control perfcontrol field description 4..0 event type 00: clock cycles 01: total instructions issued 02: floating-point instructions issued 03: integer instructions issued 04: load instructions issued 05: store instructions issued 06: dual issued pairs 07: branch prefetches 08: external cache misses 09: stall cycles 0a: secondary cache misses 0b: instruction cache misses 0c: data cache misses 0d: data tlb misses 0e: instruction tlb misses 0f: joint tlb instruction misses 10: joint tlb data misses 11: branches taken 4.0 con?t 12: branches issued 13: secondary cache writebacks 14: primary cache writebacks 15: dcache miss stall cycles (cycles where both cache miss tokens taken and a third address is requested) 16: cache misses 17: fp possible exception cycles 18: slip cycles due to multiplier busy 19: coprocessor 0 slip cycles 1a: slip cycles due to pending non-blockingloads 1b: write buffer full stall cycles 1c: cache instruction stall cycles 1d: multiplier stall cycles 1e: stall cycles due to pending non-blocking loads - stall start of exception 7..5 reserved (must be zero) 8 count in kernel mode 0: disable 1: enable 9 count in user mode 0: disable 1: enable 10 count enable 0: disable 1: enable 31..11 reserved (must be zero) table 10 ? performance counter control (cont) perfcontrol field description data0 data1 addr sysad syscmd validout* validin* rdrdy* wrrdy* release* sysclock data2 data3 ndata ndata write ndata neod ndata figure 8 ? processor block write
15 scd7000a rev c 9/9/09 aeroflex plainview clock cycles, it can be used as either a) a second timer or b) a watchdog interrupt. a watchdog interrupt can be used as an aid in debugging system or software ?hangs.? typically the software is setup to period ically update the count so that no interrupt will occur. when a hang occurs the interrupt ultimately triggers thereby br eaking free from the hang-up. interrupt handling in order to provide better real time interrupt handling, the act 7000asc provides an extended set of hardware interrupts each of which can be separately prioritized and separately vectored. as described above, the performance counter is also a hardware inte rrupt source, ip[13] . also, whereas the r4000 and r5000 family processors map the timer interrupt onto ip[7] , the act 7000asc provides a separate interrupt, ip[12] , for this purpose. all of these interrupts, ip[13..0] , the performance counter, and the timer, have corresponding interrupt mask bits, im[13..0], and interrupt pe nding bits, ip[13..0], in the status, interrupt control, an d cause registers. the bit assignments for the interrupt control and cause registers are shown in table 11 and table 12 below. the status register has not changed from the rm5200 family and r5000, and is not shown. the iv bit in the cause register is the global enable bit for the enhanced interrupt features. if this bit is clear then interrupt operation is compa tible with the rm5200 family and r5000. although not related to the interrupt mechanism, note that the w1 and w2 bits indicate which watch register caused a particular watch exception. in the interrupt control re gister, the interrupt vector spacing is controlled by the spacing field as described below. the interrupt mask field (im[15..8]) contains the interrupt mask for interrupt s eight through thirteen. im[15..14] are reserved for future use. the timer enable ( te ) bit is used to gate the timer interrupt to the cause register. if te is set to 0, the timer interrupt is not gated to ip12 . if te is set to 1, the timer interrupt is gated to ip12 . the setting for mode bit 11 is used to determine if the timer interrupt replaces the external interrupt ( int5* ) as an input to ip7 in the cause register. if mode bit 11 is set to 0, the timer interrupt is gated to ip7 . if mode bit 11 is set to 1, external int5* is gated to ip7 . in order to utilize both the external interrupt ( int5* ) and the internal timer interrupt , mode bit 11 must be set to 1, and te must be set to 1. in this case, the timer interrupt will utilize ip12 , and int5* will utilize ip7 . please also reference the logic diagram for interrupt signals in the rm7000 user manual. priority of the interrupts is set via two new coprocessor 0 registers called interrupt priority level lo, ipllo, and interrupt priority level hi, iplhi. these two registers contain a four-bit field corresponding to each interru pt thereby allowing each interrupt to be programmed w ith a priority level from 0 to 13 inclusive. the priorities can be set in any manner including having all the priorities set exactly the same. priority 0 is the highest level and priority 15 the lowest. the format of the priority level registers is shown in table 13 and table 14 below. the priority level registers are located in the coprocessor 0 control register space. for further details about the control space see the section describing coprocessor 0. in addition to programmab le priority levels, the act 7000asc also permits th e spacing between interrupt vectors to be programmed. for example, the minimum spacing between two adjacent vectors is 0x20 while the maximum is 0x200. this pr ogrammability allows the user to either set up the vectors as jumps to the actual interrupt routines or, if interrupt latenc y is paramount, to include the entire interrupt routine at the ve ctor. table 15 illustrates the complete set of vector spacin g selections along with the coding as required in the interrupt control register bits 4:0. in general, the active interr upt priority combined with the spacing setting generates a vector offset which is then added to the interrupt base addr ess of 0x200 to generate the interrupt exception offset. this offset is then added to the exception base to produce the final interrupt vector address. standby mode the act 7000asc provides a means to reduce the amount of power consumed by the internal core when the cpu would not otherwise be performing any useful operations. this state is known as standby mode. executing the wait instruc tion enables interrupts and enters standby mode. when the wait instruction completes the w pipe stage, if the sysad bus is currently idle, the internal processor cl ocks will stop thereby freezing the pipeline. the phas e lock loop, or pll, internal timer/ counter, and the ?w ake up? input pins: ip[5:0] *, nmi *, extreq *, reset *, and coldreset* continue to operate in their normal fashion. if the sysa d bus is not idle when the wait instruction completes the w pipe stage, then the wait is treated as a nop. once the processor is in standby, any interrupt, includ ing the internally generated timer interrupt, will cause the pr ocessor to exit standby and resume operation where it left off. the wait instruction is typically inserted in the id le loop of the operating system or real time executive. table 15 ? interrupt vector spacing icr[4..0] spacing 0x0 0x000 0x1 0x020 0x2 0x040 0x4 0x080 0x8 0x100 0x10 0x200 others reserved
16 scd7000a rev c 9/9/09 aeroflex plainview jtag interface the act 7000asc interface supports jtag boundary scan in conformance with ieee 11 49.1. the jtag interface is especially helpful for checking the integr ity of the processor?s pin connections. boot-time options fundamental operational modes for the pr ocessor are initialized by the boot-time mode contro l interface. the boot-time mode control interface is a serial interface operating at a very low frequency (sysclock divided by 256). the low frequency operation allows the initializatio n information to be kept in a low cost eprom; alternatively the twenty or so bits could be generated by the system interface asic. immediately after the vccok signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all the fundamental operational modes. modeclock runs continuously from the assertion of vcco k. boot-time modes the boot-time serial mode stream is defined in table 16. bit 0 is the bit presen ted to the processor when vccok is deasserted; bit 255 is the last. table 11 ? cause register 31 30 29,28 27 26 25 24 23..8 7 6..2 0,1 bd 0 ce 0 w2 w1 iv ip[15..0] 0 exc 0 table 12 ? interupt control register 31..16 15..8 7 6..5 4..00 0 im[15..8] te 0 spacing table 13 ? ipllo register 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0 ipl7 iipl6 ipl5 ipl4 ipl3 ipl2 ipl1 ipl0 table 14 ? iplhi register 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0 0 0 ipl13 ipl12 ipl11 ipl10 ipl9 ipl8
17 scd7000a rev c 9/9/09 aeroflex plainview table 16 ? boot time mode stream mode bit description 0 reserved: must be zero 4..1 write-back data rate 0: dddd 1: ddxddx 2: ddxxddxx 3: dxdxdxdx 4: ddxxxddxxx 5 ddxxxxddxxxx 6: dxxdxxdxxdxx 7: ddxxxxxxddxxxxxx 8: dxxxdxxxdxxxdxxx 9-15:reserved 7..5 sysclock to pclock multiplier mode bit 20 = 0 / mode bit 20 = 1 0: multiply by 2/x 1: multiply by 3/x 2: multiply by 4/x 3: multiply by 5/2.5 4: multiply by 6/x 5: multiply by 7/3.5 6: multiply by 8/x 7: multiply by 9/4.5 8 specifies byte ordering. logically ored with bigendian input signal. 0: little endian 1: big endian 10..9 non-block write control 00: r4000 compatible non-block writes 01: reserved 10..9 con?t 10: pipelined non-block writes 11: non-block write re-issue 11 timer interrupt enable/disable 0: internal timer interrupt gated to ip[7] 1: external int5* gated to ip[7] 12 reserved: must be zero 14..13 output driver strength - 100% = fastest 00: 67% strength 01: 50% strength 10: 100% strength 11: 83% strength 15 reserved must be zero 17..16 system configuration identifiers- software visible in processor config[21..20] register 19..18 reserved: must be zero 20 pclock to sysclock multipliers. 0: integer multipliers (2,3,4,5,6,7,8,9) 1: half integer mult ipliers (2.5,3.5,4.5) 23..21 reserved: must be zero 24 jtlb size. 0: 48 dual-entry 1: 64 dual-entry 25 on-chip secondary cache control. 0: disable 1: enable 255..26 reserved: must be zero table 16 ? boot time mode stream (cont) mode bit description
18 scd7000a rev c 9/9/09 aeroflex plainview pll analog power filtering the act 7000asc includes extra p ll analog power fiiltering circuitry designed to pr ovide low noise, temperature stable filtering for the vccp and vssp signal s. the included circuitry co nsists of several passive components located at the closest po ssible point to the rm7000a die and is configured as shown in figure 9. additional board level ppl f iltering is also required. the recommen ded configuration is shown in figure 10. 64 65 .01 f 1000 pf 5 5 rm7000a die vccp vssp 10 f .1 f 5 5 64 65 vccp vssp 1000 pf vccint vssint figure 10 ? recommended boar d level pll filter circuit figure 9 ? act 7000asc including pll filter circuit for the act 7000asc
19 scd7000a rev c 9/9/09 aeroflex plainview absolute maximum rating 1 symbol parameter limits units v term terminal voltage with respect to v ss -0.5 2 to +3.9 v t c case operating temperature -55 to +125 c t stg storage temperature -65 to +150 c i in dc input current 20 3 ma i out dc output current 4 20 ma note 1: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a st ress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note 2: v in minimum = -2.0v for pulse width less than 15ns. v in should not exceed 3.9 volts. note 3: when v in < 0v or v in > v cc io note 4: not more than one output should be shorted at a ti me. duration of the short should not exceed 30 seconds. recommended operating conditions cpu speed temperature vss vssint vccio vccp 225 - 350mhz -55c to +125c (t c ) 0v 1.8v 50mv 3.3v 150mv 1.8v 150mv note: v cc i/o should not exceed vccint by greater than 2.0v during the power-up sequence. note: applying a logic high state to any i/o pin before vccint becomes stable is not recommended. note: as specified in ieee 1149.1 (jtag), the jtms pin must be he ld low during reset to avoid entering jtag test mode. refer to the rm7000 family users manual, appendix e. dc electrical characteristics parameter minimum maximum conditions v ol -0.2v|i out | = 100a v oh v cc io - 0.2v - v ol -0.4v|i out | = 2ma v oh 2.4v - v il -0.3v 0.8 v ih 2.0v v cc io + 0.3v i in - - 15a 15a v in =0 v in =v cc io c in -10pf c out -10pf
20 scd7000a rev c 9/9/09 aeroflex plainview power consumption parameter condition cpu clock speed 225 mhz 300 mhz 350 mhz max 2 max 2 max 2 vccint power (mwatts) standby - 865 865 925 active maximum with no ffu operation 2 2350 2750 3550 maximum worst case instruction mix 2500 3000 4000 notes 1. worst case supply voltage (maximum v cc i nt ) with worst case temperature (maximum tcase). 2. dhrystone 2.1 instruction mix. 3. i/o supply power is applicat ion dependent, but typically <20% of v cc i nt . ac electrical characteri stics ? clock parameters parameter symbol test condition cpu clock speed units 225mhz 300mhz 350mhz minmaxminmaxminmax sysclock high t schigh transition < 5ns 3 - 3 - 3 - ns sysclock low t sclow transition < 5ns 3 - 3 - 3 - ns sysclock frequency 25 75 25 75 25 70 mhz sysclock period t scp -40-40-40ns clock jitter for sysclock t jitterin - 200 - 150 - 150 ps sysclock rise time t scrise -2-2-2ns sysclock fall time t scfall -2-2-2ns modeclock period t modeckp - 256 - 256 - 256 t scp jtag clock period t jtagckp -4-4-4 t scp note: operation of the act 7000asc is only guaranteed with the phase lock loop enabled.
21 scd7000a rev c 9/9/09 aeroflex plainview system interface parameters parameter 1 sym test conditions 225mhz 300mhz 350mhz units m i n m a x m i n m a x m i n m a x data output 2,3 t do mode 14...13 = 10 (fastest) 1.04.51.04.51.04.5 ns mode 14...13 = 01 (slowest) 1.05.51.05.51.05.5 ns data setup 4 t ds t rise = see above table 2.5-2.5-2.5- ns data hold 4 t dh t fall = see above table 1.0-1.0-1.0- ns notes: 1. timings are measured from 1.5v of the clock to 1.5v of the signal. 2. capacitive load for all output timings is 50pf. 3. data output timing applies to all signal pins whether tristate i/o or output only. 4. setup and hold parameters apply to all signal pins whether tristate i/o or input only. boot-time interface parameters parameter symbol test conditions min max units mode data setup t ds - 4- sysclock cycles mode data hold t dh - 0- sysclock timing input timing output timing t jitterin t scrise t scfall sysclock t scp data sysclock data t dh t ds data sysclock data data t do t do min clock timing system interface timing (sysad, syscmd, validin*, validout*, etc.)
22 scd7000a rev c 9/9/09 aeroflex plainview pin descriptions the following is a list of control, data, clock, interrupt, and miscellaneous pins of the act 7000asc. pin name type description system interface: extrqst* input external request signals that the system interface is submitting an external request. release* output re lease interface signals that the processor is releasing the system interface to slave state rdrdy* input read ready signals that an external agent can now accept a processor read. wrrdy* input write ready signals that an external agent can now accept a processor write request. validin* input valid input signals that an external agent is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. validout* output valid output signals that the processor is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. sysad(63:0) input/ output system address/data bus a 64-bit address and data bus for communication between the processor and an external agent. sysadc(7:0) input/ output system address/data check bus an 8-bit bus containing parity check bits for the sysad bus during data cycles. syscmd(8:0) input/ output system command/data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. syscmdp input/ output system command/data identifier bus parity for the rm7000a, unused on input and zero on output. clock/control interface: sysclock input system clock master clock input used as the system interface reference clock. all output timings are relative to this input clock. pipeline operation frequency is derived by multiplying this clock up by the factor selected during bo ot initialization vccp input vcc for pll quiet vccint for the internal phase locked loop. must be connected to vccint. see figure 10 for additiona l ppl filtering information. vssp input vss for pll quiet vss for the internal phase locked loop. must be connected to vss. see figure 10 for additiona l ppl filtering information. interrupt interface int*(5:0) input interrupt six general processor interrupts, bit-wise ored with bits 5:0 of the interrupt register. nmi* input non-maskable interrupt non-maskable interrupt, ored with bit 15 of the interrupt register (bit 6 in r5000 compatibility mode).
23 scd7000a rev c 9/9/09 aeroflex plainview for additional detail informatio n regarding the operation of the pmc-sierra see the latest pmc-sierra datasheet for the rm7000a 64-bit superscalar microprocessor with on-c hip secondary cache (doc. # pmc-2002227), issue no. 5: august, 2002 jtag interface: jtdi input jtag data in jtag serial data in. jtck input jtag clock input jtag serial clock input. jtdo output jtag data out jtag serial data out. jtms input jtag command jtag command signal, signals that the incoming serial data is command data. initializatio n interface: bigendian input big endian / little endian control allows the system to change the processor addressing mode without rewriting the mode rom. vccok input vcc is ok when asserted, this signal indicates to the act-7000asc that the v cc i nt power supply has been above the recommended value for more th an 100 milliseconds and will remain stable. th e assertion of vccok initiates the reading of the boot-time mode control serial stream. coldreset* input cold reset this signal must be asserted for a power on reset or a cold reset. coldreset must be de-asserted synchronously with sysclock. reset* input reset this signal must be asserted for any reset sequence. it may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. reset must be de-asserted synchronously with sysclock. modeclock output boot mode clock serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. modein input boot mode data in serial boot-mode data input. pin descriptions (cont) the following is a list of control, data, clock, interrupt, and miscellaneous pins of the act 7000asc. pin name type description
24 scd7000a rev c 9/9/09 aeroflex plainview 1.131 (28.727) sq 1.109 (28.169) sq 1.009 (25.63) .9998 (25.37) 51 spaces at .0197 (51 spaces at .50) .0236 (.51) .0158 (.49) 52 1 208 156 157 105 104 53 pin 1 chamfer detail "a" 05 1.331 (33.807) 1.269 (32.233) .005 (.127) .008 (.202) .055 (1.397) ref .055 (1.397) .045 (1.143) .115 (2.921) max .960 (24.384) sq ref .130 (3.302) max .010r ref .010r ref .010 (.253) .007 (.178) .015 (.381) .009 (.229) .090 (2.286) ref package information ? "f17" ? cqfp 208 leads detail "a" .050 (1.27) .030 (.762) units: inches (millimeters) lid 1.131 (28.727) sq 1.109 (28.169) sq 1.009 (25.63) .9998 (25.37) 51 spaces at .0197 (51 spaces at .50) .0236 (.51) .0158 (.49) 157 208 1 53 52 104 105 156 pin 1 chamfer detail "a" 05 1.331 (33.807) 1.291 (32.791) .005 (.127) .008 (.202) .139 (3.531) max .024 (.610) .010 (.253) .115 (2.921) max .012r ref .012r ref .010 (.253) .007 (.178) package information ? "f24" ? inverted cqfp 208 leads detail "a" .060 (1.524) .040 (1.016) units: inches (millimeters) .055 (1.397) ref .055 (1.397) .045 (1.143) .960 (24.384) ref lid note: pin rotation is opposite of pmc-sierra pquad due to cavity-up construction. note: pin rotation is identical to pmc-sie rra pquad due to cavity-down construction.
25 scd7000a rev c 9/9/09 aeroflex plainview act 7000asc microprocessor cqfp pinouts ? "f17" & "f24" pin # function pin # function pin # function pin # function 1 vccio 53 nc 105 vccio 157 nc 2 nc 54 nc 106 nmi* 158 nc 3 nc 55 nc 107 extrqst* 159 nc 4 vccio 56 vccio 108 reset* 160 nc 5 vss 57 vss 109 coldreset* 161 vccio 6 sysad4 58 modein 110 vccok 162 vss 7 sysad36 59 rdrdy* 111 bigendian 163 sysad28 8 sysad5 60 wrrdy* 112 vccio 164 sysad60 9 sysad37 61 validin* 113 vss 165 sysad29 10 vccint 62 validout* 114 sysad16 166 sysad61 11 vss 63 release* 115 sysad48 167 vccint 12 sysad6 64 vccp 116 vccint 168 vss 13 sysad38 65 vssp 117 vss 169 sysad30 14 vccio 66 sysclock 118 sysad17 170 sysad62 15 vss 67 vccint 119 sysad49 171 vccio 16 sysad7 68 vss 120 sysad18 172 vss 17 sysad39 69 vccio 121 sysad50 173 sysad31 18 sysad8 70 vss 122 vccio 174 sysad63 19 sysad40 71 vccint 123 vss 175 sysadc2 20 vccint 72 vss 124 sysad19 176 sysadc6 21 vss 73 syscmd0 125 sysad51 177 vccint 22 sysad9 74 syscmd1 126 vccint 178 vss 23 sysad41 75 syscmd2 127 vss 179 sysadc3 24 vccio 76 syscmd3 128 sysad20 180 sysadc7 25 vss 77 vccio 129 sysad52 181 vccio 26 sysad10 78 vss 130 sysad21 182 vss 27 sysad42 79 syscmd4 131 sysad53 183 sysadc0 28 sysad11 80 syscmd5 132 vccio 184 sysadc4 29 sysad43 81 vccio 133 vss 185 vccint 30 vccint 82 vss 134 sysad22 186 vss 31 vss 83 syscmd6 135 sysad54 187 sysadc1 32 sysad12 84 syscmd7 136 vccint 188 sysadc5 33 sysad44 85 syscmd8 137 vss 189 sysad0 34 vccio 86 syscmdp 138 sysad23 190 sysad32 35 vss 87 vccint 139 sysad55 191 vccio 36 sysad13 88 vss 140 sysad24 192 vss 37 sysad45 89 vccint 141 sysad56 193 sysad1 38 sysad14 90 vss 142 vccio 194 sysad33 39 sysad46 91 vccio 143 vss 195 vccint 40 vccint 92 vss 144 sysad25 196 vss 41 vss 93 int0* 145 sysad57 197 sysad2 42 sysad15 94 int1* 146 vccint 198 sysad34 43 sysad47 95 int2* 147 vss 199 sysad3 44 vccio 96 int3* 148 sysad26 200 sysad35 45 vss 97 int4* 149 sysad58 201 vccio 46 modeclock 98 int5* 150 sysad27 202 vss 47 jtdo 99 vccio 151 sysad59 203 nc 48 jtdi 100 vss 152 vccio 204 nc 49 jtck 101 nc 153 vss 205 nc 50 jtms 102 nc 154 nc 206 nc 51 vccio 103 nc 155 nc 207 vccio 52 vss 104 nc 156 vss 208 vss
26 plainview, new york toll free: 800-the-1553 fax: 516-694-6715 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com scd7000a rev c 10/9/09 plainview, new york toll free: 800-the-1553 fax: 516-694-6715 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 aeroflex microelectronic solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. all parameters must be validated for each customer's application by engineering. no liability is assumed as a result of use of this product. no patent licenses are implied. all trademarks are acknowledged. parent company aeroflex, inc. 2003. our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused export control: export warning: this product is controlled for expor t under the international traffic in arms regulations (itar). a license from the u.s. department of state is required prior to the export of this product from the united states. aeroflex?s military and space pr oducts are controlled for export under the international traffic in arms regulations (itar) and may not be sold or proposed or offered for sale to certain countries. (see itar 126.1 for complete information.) the qed logo and riscmark are trademarks of pmc-sierra, inc. mips is a registered trademark of mips technologies, inc. a ll other trademarks are the respective property of the trademark hol ders. sample ordering information part number screening speed (mhz) package act-7000asc-300f17i industrial temperature 300 208 lead cqfp act-7000asc-300f17c commercial temperature 300 act-7000asc-300f17t milit ary temperature 300 act-7000asc-300f17m m ilitary screening 300 part number breakdown act? 7000a sc ? 225 f17 m aeroflex-plainview base processor type 225 = 225mhz 300 = 300mhz 350 = 350mhz 400 = 400mhz (future option) cache style package type & size c = commercial temp, 0c to +70c i = industrial temp, -40c to +85c t = military temp, -55c to +125c m = military temp, -55c to +125c, screened * q = mil-prf-38534 compliant/smd if applicable screening * screened to the individual test methods of mil-std-883 sc = secondary cache maximum pipeline freq. surface mount package f17 = 1.120" sq 208 lead cqfp f24 = 1.120" sq inverted 208 lead cqfp aeroflex-plainview base processor type 225 = 225mhz 300 = 300mhz 350 = 350mhz 400 = 400mhz (future option) cache style package type & size c = commercial temp, 0c to +70c i = industrial temp, -40c to +85c t = military temp, -55c to +125c m = military temp, -55c to +125c, screened * q = mil-prf-38534 compliant/smd if applicable screening * screened to the individual test methods of mil-std-883 maximum pipeline freq. surface mount package f17 = 1.120" sq 208 lead cqfp f24 = 1.120" sq inverted 208 lead cqfp

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