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dual 256-position i 2 c digital potentiometer preliminary technical data ad5243/ad5248 fea t ures 2-channel, 256 -position end-to-end r e s istance 2.5 k?, 10 k?, 50 k?, 1 00 k? compact msop-10 ( 3 mm 4. 9 mm) package full re ad/write of wiper register power-on preset to midscale extra package address decod e pins ad 0 and ad 1(a d 5248 ) single supply +2.7 v to +5.5 v low temperature coefficient 3 5 ppm/c low power, i dd = 5 a wide operatin g temperature C40c to + 125 c evaluation board available a pplic a t io ns mechanical pot e ntiometer replacement in ne w designs transducer adj u stment of pre ssure, tempera t ure, position, chemical, and optical sensors rf amplifier bi asing automotive e l ectronics adjustment gain control and offset a d just ment gener a l ov er view the ad5243 & ad5248 p r o v ide a co m p ac t 3x4.9mm p a cka g e d s o l u tio n f o r d u a l 256 p o si tio n ad j u s t m e n t a p p l ica t ion s . th es e d e v i ce s p e rf o r m th e sa m e e l ectr o n i c a d j u s t m e n t fun c ti o n a s a 3- t e r m inal m e c h anical p o t e n t iomet e r (ad5243) o r a 2-t e r m inal va r i a b le r e sis t o r (ad5248). a v aila b l e in f o ur dif f er en t end-t o - end r e sis t an ce val u es (2.5k, 10k, 50k, 100k ) th es e lo w t e m p era t ur e co ef f i cien t de vice s a r e ide a l fo r hig h acc u rac y a nd st abi l it y v a r i abl e re s i st anc e a d ju st me n t s . t h e w i p e r s e t t i n g s a r e co n t r o lla b le th r o ugh th e i 2 c com p a t i b le dig i t a l in t e r f ace . the ad5248 has ext r a p a c k a g e addres s deco de p i ns ad0 & ad1 al lo win g m u l t i p le p a r t s t o s h a r e th e s a me i 2 c 2- wir e b u s o n a pcb . the r e sis t an ce b e tw e e n t h e wi p e r a n d ei t h er e n d p o in t o f t h e f i xe d re s i stor v a r i e s l i ne arly w i t h re sp e c t to t h e dig i t a l c o de tra n sf e r r e d i n t o th e rd a c la t c h 1 . o p era t ing f r o m a 2.7 t o 5.5 v o l t p o w e r s u p p l y a nd co n s u m in g l e ss t h an 5 a a l l o w s for u s age i n p o r t abl e b a t t e r y op e r a t e d ap p l i c at i o n s . a l l p a r t s a r e gua r a n t e e d t o op e r a t e o v er t h e exten d e d a u t o m o t i v e t e m p era t ur e ra n g e o f -40c t o +125c. func ti onal bl oc k di a g rams i 2 c in t e rface wi p e r regi st e r 1 a1 w1 b1 v dd sda sc l gnd a2 w2 wi p e r regi st e r 2 b2 f i g u re 1. a d 52 43 b1 rda c re g i st e r 1 addres s decode se r i al in pu t r e gi st er 8 v dd gnd sda scl ad 0 ad 1 w1 w2 b2 2 rdac regi s t er 2 f i g u re 2. a d 52 48 note: the terms di gital potentiometer , vr , and rdac are use d inte rchange a bl y. purc hase of l i c e nse d i 2 c c o mp on ent s of a n al og devi c e s o r on e of i t s sub l i c ensed associated c o mpani e s conv eys a license f o r the purcha ser un d e r the philips i 2 c paten t rig h ts to use th ese co mpon en ts in an i 2 c system , provi d ed th at the system co n f o r ms to th e i 2 c stan d a r d s p ecificatio n as d e fin e d by p h ilips. in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . rev. pre5/12/03
ad5243/ad5248 preliminary technical data table of contents e l e c t r ical c h a r ac t e r i s t ics2.5 k? v e rsio n ................................... 3 e l ec tr ical c h a r ac t e r i s t ics10 k?, 50 k?, 100 k? v e rsio n s ....... 4 t i min g cha r ac ter i s t ics2.5 k? , 10 k?, 50 k?, 100 k? v e rsio n s ............................................................................................................. 5 ab s o l u t e m a x i m u m r a t i n g s 1 .......................................................... 5 t y p i cal p e r f o r ma n c e c h a r ac t e r i s t ics ............................................. 6 t e st cir c ui t s ....................................................................................... 7 i 2 c i n ter f ace ....................................................................................... 8 o p era t ion ......................................................................................... 10 p r og ra mmin g t h e v a r i a b le resis t o r ......................................... 10 p r og ra mmin g t h e p o t e n t iom e ter di vider ............................... 11 i 2 c c o m p a t i b le 2-w i r e s e r i al bus ............................................ 11 l e ve l s h if t i n g fo r b i dir e c t io nal i n t e r f ace . ............................... 12 es d p r o t e c t i on ........................................................................... 12 t e r m inal v o l t a g e o p era t in g r a n g e .......................................... 12 p o w e r - u p s e q u en c e ................................................................... 13 l a yo u t and p o wer s u p pl y b y p a s s in g . ...................................... 13 p i n c o nf igura t io n an d f u n c t i on d e s c r i p t ion s ........................... 14 p i n c o nf igura t io n ...................................................................... 14 p i n f u n c t i on d e s c r i p t io n s ........................................................ 14 o u t l in e dim e n s io n s ....................................................................... 15 or der i n g g u ide . ......................................................................... 15 es d c a u t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 revisi on h i s t or y rev i s i o n 0: i n i t ial v e r s i o n rev. pr e 5/12/03 | page 2 of 16
preliminary technical data ad5243/ad5248 electrical characteristics2.5 k? version (v dd = 5 v 10 %, o r 3 v 10%; v a = +v dd ; v b = 0 v ; C40c < t a < +125c; unles s o t h e r w is e n o ted . ) ta ble 1. p a r a m e t e r s y m b o l c o n d i t i o n s m i n typ 1 m a x u n i t dc charac teri sticsrheos t at mode resistor differential nonlin earit y 2 r - d n l r wb , v a = no con n ect C1.8 0.2 +1.8 lsb resistor integral nonlinearity 2 r - i n l r wb , v a = no con n ect C5 0.75 +5 lsb nominal resi sto r t o lerance 3 ? r ab t a = 25c C30 +30 % resistance tem p erature coefficient ?r ab /?t v ab = v dd , wiper = no con n ect 35 ppm/c wiper resistanc e r w 5 0 1 2 0 ? dc charac teri sticspote ntiometer divid e r mode (specifications a pply to all vrs) resolution n 8 b i t s differential non l inearity 4 d n l C 1 . 5 0 . 1 + 1 . 5 l s b integral nonlinearity 4 i n l C 1 . 5 0 . 6 + 1 . 5 l s b voltage divider temperature coefficient ?v w /?t code = 0x80 15 ppm/c full-scale error v wfs e code = 0xff C6 C2.5 0 lsb zero-scale err o r v wzs e code = 0x00 0 +2 +6 lsb resistor termi n a l s voltage range 5 v a,b,w g n d v dd v capacitance 6 a, b c a,b f = 1 mhz, measured to gnd, code = 0x80 4 5 p f capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 6 0 p f shutdown supply current 7 i dd_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd / 2 1 n a digital inpu ts and outpu t s input logic hig h v ih 2 . 4 v input logic low v il 0 . 8 v input logic hig h v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 p f power suppli e s power supply range v dd ran g e 2 . 7 5 . 5 v supply current i dd v ih = 5 v or v il = 0 v 3 5 a power dissi pati on 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0.2 mw power supply s e nsitivity pss ?v dd = +5 v 10%, code = mids cale 0 . 0 2 0 . 0 5 % / % dynamic ch aracteris t ics 6, 9 bandwidth C3db b w _ 5 k r ab = 2.5 k?, co de = 0x80 2.4 mhz t o tal harmonic distortion t h d w v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise v o ltage density e n_wb r wb = 2.5 k?, rs = 0 4.5 nv/hz rev. pr e 5/12/03 | page 3 of 16
ad5243/ad5248 preliminary technical data electrical characteristics10 k?, 50 k?, 100 k? versions (v dd = 5 v 10 %, o r 3 v 10%; v a = v dd ; v b = 0 v ; C40c < t a < +125c; unles s o t h e r w is e n o ted . ) ta ble 2. p a r a m e t e r s y m b o l c o n d i t i o n s m i n typ 1 m a x u n i t dc charac teri sticsrheos t at mode resistor differential nonlin earit y 2 r - d n l r wb , v a = no con n ect C1 0.1 +1 lsb resistor integral nonlinearity 2 r - i n l r wb , v a = no con n ect C2 0.25 +2 lsb nominal resi sto r t o lerance 3 ? r ab t a = 25c C30 +30 % resistance tem p erature coefficient ?r ab /?t v ab = v dd , wiper = no connect 3 5 p p m / c wiper resistanc e r w v dd = 5 v 50 120 ? dc charac teri sticspote ntiometer divid e r mode (specifications a pply to all vrs) resolution n 8 b i t s differential non l inearity 4 d n l C 1 0 . 1 + 1 l s b integral nonlinearity 4 i n l C 1 0 . 3 + 1 l s b voltage divider temperature coefficient ?v w /?t code = 0x80 15 ppm/c full-scale error v wfs e code = 0xff C3 C1 0 lsb zero-scale err o r v wzs e code = 0x00 0 1 3 lsb resistor termi n als voltage range 5 v a,b,w g n d v dd v capacitance 6 a, b c a,b f = 1 mhz, measured to gnd, code = 0x80 4 5 p f capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 6 0 p f shutdown supply current 7 i dd_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd / 2 1 n a digital inpu ts and outpu t s input logic hig h v ih 2 . 4 v input logic low v il 0 . 8 v input logic hig h v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 p f power suppli e s power supply range v dd ran g e 2 . 7 5 . 5 v supply current i dd v ih = 5 v or v il = 0 v 3 5 a power dissi pati on 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0 . 2 m w power supply s e nsitivity pss ?v dd = +5 v 10%, code = mids cale 0 . 0 2 0 . 0 5 % / % dynamic ch aracteris t ics 6, 9 bandwidth C3db b w r ab = 10 k?/50 k?/100 k?, code = 0x80 6 0 0 / 1 0 0 / 4 0 k h z t o tal harmonic distortion t h d w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0 . 0 5 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise v o ltage density e n_wb r wb = 5 k?, rs = 0 9 nv/hz rev. pr e 5/12/03 | page 4 of 16
preliminary technical data ad5243/ad5248 timing characteristics2.5 k?, 10 k?, 50 k?, 100 k? versions (v dd = +5v 1 0 % , o r +3v 10% ; v a = v dd ; v b = 0 v ; C40c < t a < +125c; unles s o t h e r w is e n o ted . ) ta ble 3. p a r a m e t e r s y m b o l c o n d i t i o n s m i n typ 1 max unit i 2 c inte rface timing c harac teris t ics 6, 10 (spe cifications apply to all parts) scl clock frequ ency f scl 4 0 0 k h z t bu f bus free ti me between stop and start t 1 1 . 3 s t hd;sta hold time (repeated sta r t) t 2 after this period, the first clock p u lse is generated. 0 . 6 s t low low period of scl clock t 3 1 . 3 s t high high period of scl clock t 4 0 . 6 5 0 s t su ;st a se tup tim e for repeated start condition t 5 0 . 6 s t hd;dat data hold time t 6 0 . 9 s t su ;dat data setu p time t 7 1 0 0 n s t f fall time of both sda and sc l signals t 8 3 0 0 n s t r rise time of both sda and sc l signals t 9 3 0 0 n s t su ;st o set u p tim e for stop condition t 10 0 . 6 s notes 1 typical s p ecif ications repres ent avera g e read ings at + 25c and v dd = 5 v. 2 r e si st o r po si t i on n o n l i n ea ri t y error r - in l i s t h e devi a t i o n f r om an ideal val u e meas ured betw een the maximum re si s t a n ce a n d t h e m i n im um resi st a n ce wi per posi t i on s. r - d n l m e a s ure s t h e rela t i ve st ep ch a n ge from i d ea l bet w een succ essi ve t a p posi t i on s . pa rt s a r e gua ra n t eed m o n o t o n i c. 3 v ab = v dd , w i p e r ( v w ) = no co nne ct. 4 inl and dnl are m e as ured at v w with the rda c c o nf igured a s a p o tentiometer d i vid e r s imil ar to a vol t age output d/a converter. va = v dd a n d v b = 0 v. dnl s p ecif ication l i mits of 1 l s b maximum ar e guarante e d m o no to nic o p e r ating co nd itio ns . 5 res i s t or terminal s a , b, w have no l imitations on pol a ri ty with res p ect to eac h other. 6 gua r a n t eed by des i gn a n d n o t subj ect t o pro d uct i on t e st . 7 mea s ure d a t t h e a t e rm i n a l . th e a t e r m i n a l i s open ci rcui t e d i n sh ut d o wn m o de. 8 p diss i s ca lcula t e d fr om (i dd v dd ). cmo s l o gi c leve l i n put s resu lt in minimum power d i ss ipation. 9 al l d y namic characteris t ics use v dd = 5 v. 10 see timing d iagrams for l o cations of meas ured val u es . absolute maximum ratings 1 (t a = +25c, unles s o t h e r w is e no t e d . ) ta ble 4. p a r a m e t e r v a l u e v dd to gnd C0.3 v to +7 v v a , v b , v w to g n d v dd i max 1 2 0 m a digital inputs and output vo ltage to gnd 0 v to +7 v operating tem p erature range C40c to +125c maximum junction temperature (t jma x ) 1 5 0 c storage temperature C65c to +150c lead temperature (soldering, 10 sec) 300c t h ermal resista n ce 2 ja : msop-10 230c/w notes 1 maximum terminal curr ent is b o unde d by the maximum current handling of the s w itches , maxi m um power d i ss ip ation of the package, and maximum appl ied vol t age acros s any two of the a , b, and w terminal s at a given resi st a n ce. 2 pa cka g e pow e r di ssi pa t i on = (t jm ax C t a )/ ja . s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . rev. pr e 5/12/03 | page 5 of 16
ad5243/ad5248 preliminary technical data typical perf orm ance cha r acte ristics rev. pr e 5/12/03 | page 6 of 16
preliminary technical data ad5243/ad5248 test circuits f i gur e 3 t o f i gur e 11 il l u s t ra t e t h e t e s t cir c ui ts t h a t def i n e t h e t e st con d i t io ns us e d in t h e p r o d uc t sp e c if ic a t i o n t a b l es. v ms a w b dut v + = v dd 1lsb = v + / 2 n v+ f i gure 3. t e s t ci r c u i t for p o tent io me ter d i v i de r n o n lin ea ri t y e r r o r (inl, dnl) no connect i w v ms a w b dut f i gure 4. t e s t ci r c u i t for r e s i s t or p o s i t i on n o n lin ea rit y e rror (r heo s ta t o p er a t ion; r - inl, r - dnl) v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 ? v ms2 ]/ i w a w b dut f i gure 5. t e s t ci r c u i t for wipe r r e s i s t an c e ? v ? v ? v ? v ms % dd % pss (% / %) = v+ = v dd 10% psrr (db) = 20 log ms dd ( ) v dd v a v ms a w b v+ f i g u re 6. t e s t ci r c u i t f o r p o we r su p p ly s e ns it iv it y ( p ss, ps sr ) op279 w 5v b v out offset gnd offset bias a dut v in f i gure 7. t e s t ci r c u i t for in ve r t ing g a in b a v in op279 w 5v v out offset gnd offset bias dut f i gure 8. t e s t ci r c u i t for n o n i n v e r ting g a in +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in f i gure 9. t e s t ci r c u i t for g a in v s . f r equ e nc y w b v ss to v dd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v f i gu r e 1 0 . t e st ci r c u i t fo r i n cr em en ta l on re si sta n c e w b v cm i cm a nc gnd nc v ss v dd dut nc = no connect f i gure 11. t e s t c i rc uit for co m m o n -mode l e ak age cu rre nt rev. pr e 5/12/03 | page 7 of 16
ad5243/ad5248 preliminary technical data i 2 c interface ta ble 5 . writ e mo de ad5243 s 0 1 0 1 1 1 1 w a a 0 sd x x x x x x a d7 d6 d 5 d 4 d 3 d 2 d1 d0 a p slave address byte instruction byte data byte ad5248 s 0 1 0 1 1 a d 1 a d 0 w a a 0 sd x x x x x x a d7 d6 d 5 d 4 d 3 d 2 d 1 d0 a p slave address byte instruction byte data byte ta ble 6. r e a d mo de ad5243 s 0 1 0 1 1 1 1 r a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p slave address byte data byte ad5248 s 0 1 0 1 1 a d 1 a d 0 r a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p slave address byte data byte s = s t a r t c o n d i t io n p = s t o p c o n d i t io n a = a c k n o w le dge x = d o n t c a r e w = w r i t e r = re ad a0 = rd a c sub addr es s s e le c t b i t s d = sh u t do w n co nne c t s wi p e r to b ter m ina l and o p e n cir c ui ts a t e r m i n a l . i t do es n o t cha n ge con t e n ts o f wi p e r re g i ste r . d7, d6, d5, d4, d3, d2, d1, d0 = d a t a bi ts rev. pr e 5/12/03 | page 8 of 16
preliminary technical data ad5243/ad5248 t 1 t 3 t 4 t 2 t 7 t 8 t 9 ps p s t 10 t 5 t 9 t 8 scl sd a t 2 t 6 f i g u re 12. i 2 c inter f a c e d e ta il ed ti mi ng di a g r a m sc l fr a m e 1 fr a m e 2 st a r t by m a st er a ck b y a d 5243 sl a v e a ddre ss byt e s t op by m a st er i n st r uct i o n byt e sd a 0 1 0 1 1 1 1 r/ w a0 sd x x x x x 1 9 1 9 d7 d6 d5 d4 d3 d2 d1 d0 a ck b y a d 5243 fr a m e 3 da t a byt e 1 9 a ck b y a d 5243 x f i g u re 13. w r it ing t o t h e r d a c r e g i s t e r C a d 5 2 4 3 sc l fr a m e 1 fr a m e 2 st a r t by m a st er a ck b y a d 5248 sl a v e a ddre ss byt e s t op by m a st er i n st r uct i o n byt e sd a 0 1 0 1 1 ad 1 ad 0 r/ w a0 sd x x x x x 1 9 1 9 d7 d6 d5 d4 d3 d2 d1 d0 a ck b y a d 5248 fr a m e 3 da t a byt e 1 9 a ck b y a d 5248 x f i g u re 14. w r it ing t o t h e r d a c r e g i s t e r C a d 5 2 4 8 no a c k by m a st er sc l sd a 0 1 0 1 1 1 1 r/ w d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 fr a m e 1 fr a m e 2 st a r t by m a st er ac k b y a d 5 243 sl a v e a ddre ss byt e rda c r e g i st er s t op b y m a st er f i g u re 15. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de C a d 52 4 3 no a c k by m a st er sc l sd a 0 1 0 1 1 ad 1 ad 0 r/ w d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 fr a m e 1 fr a m e 2 st a r t by m a st er ac k b y a d 5 248 sl a v e a ddre ss byt e rda c r e g i st er s t op b y m a st er f i g u re 16 r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de C a d 52 4 8 rev. pr e 5/12/03 page 9 of 16
ad5243/ad5248 preliminary technical data ope ration the ad5243/48 is a 256-p o si tion di g i tal l y co n t rol l ed va r i a b le re s i stor ( v r ) d e v i c e . an in t e r n al p o w e r - o n p r es et places t h e wi p e r a t mids cale d u r i n g p o w e r - on, w h ich sim p l i f i es t h e f a u l t condi t i on r e co v e r y at p o w e r- u p . programming te variable resi stor r h eos t at ope r ation the n o minal r e sis t a n ce o f the rd a c be tw e e n t e r m inals a and b is a v a i la b l e in 5 k?, 10 k?, 50 k?, a nd 100 k? . th e f i nal tw o o r t h r e e dig i ts of t h e p a r t n u m b er det e r m i n e t h e n o minal r e sis t a n c e val u e , e . g., 10 k? = 10 ; 50 k? = 50. the n o minal re s i st anc e ( r ab ) o f th e vr has 2 56 co n t ac t p o in ts acces s e d b y t h e w i p e r t e r m i n al , pl us t h e b ter m inal co n t ac t. the 8- b i t da t a in t h e rd a c l a tc h is deco ded t o s e lec t on e o f the 256 p o s s i b le s e t t i n gs. a ssu me a 10 k? p a r t is us e d , t h e w i p e r s f i rst co nne c t io n s t a r ts a t t h e b t e r m i n al fo r da t a 0x0 0 . sin c e t h er e is a 60 ? wi p e r con t ac t r e sis t a n ce , suc h co nn ec tion yie l ds a mini m u m o f 60 ? r e sist a n ce b e tw e e n ter m ina l s w an d b . t h e s e con d co n n e c t i o n is t h e f i rst t a p p o in t, w h ich c o r r esp o n d s t o 99 ? (r wb = r ab /256 + r w = 39 ? + 60 ?) f o r da ta 0x01. the thir d conn e c tio n is the n e xt ta p p o in t, r e p r es en tin g 138 ? (2 39 ? + 60 ?) f o r da ta 0x0 2 , a n d s o o n . e a c h ls b da ta val u e in cr e a s e m o v e s t h e w i p e r u p t h e r e sis t o r ladder un t i l t h e l a s t t a p p o in t is r e ac hed a t 9961 ? (r ab C 1 ls b + r w ). f i gur e 17 s h o w s a sim p lif i e d di ag ra m o f t h e e q u i valen t rd a c c i r c ui t w h er e t h e l a st re s i stor st r i ng w i l l not b e a c c e ss e d ; t h e r e f ore, t h e r e is 1 l s b les s o f th e n o minal r e sis t a n ce a t f u l l s c ale in addi tion t o t h e wi p e r r e sist an ce. b rdac latch and decoder w a r s r s r s r s sd bit d7 d6 d4 d5 d2 d3 d1 d0 f i g u re 17. a d 5 2 4 3 / 48 eq uiv a lent r d a c circuit t h e g e n e ral eq ua ti o n d e t e rm in in g th e d i g i tall y p r ogra m m e d o u t p u t r e s i s t a n ce bet w een w a n d b i s w ab wb r r d d r + = 256 ) ( ( 1 ) w h er e d is the decimal e q ui val e n t o f the b i na r y co de lo aded in t h e 8- b i t r d a c r e g i s t er , r ab is t h e e n d- to -e n d resist a n ce, an d r w is th e wi p e r r e sis t a n c e co n t r i b u t e d b y th e on r e sis t an ce o f th e in t e rn al swi t c h . i n s u mma r y , if r ab = 10 k? a n d t h e a t e r m ina l is o p en c i rc u i te d, t h e f o l l ow i n g output r e s i st an c e r wb will be set f o r th e indic a te d r d a c la tch co des. ta ble 7. co des an d co r r e spo n di ng r wb res i st ance d (dec.) r wb (?) output state 255 9,961 full scale (r ab C 1 lsb + r w ) 1 2 8 5 , 0 6 0 m i d s c a l e 1 9 9 1 l s b 0 60 zero scale (wiper contact resistance) n o t e tha t in t h e zer o -s cale con d i t io n a f i ni t e wi p e r r e sis t a n c e of 60 ? is p r es en t. c a r e s h o u ld b e t a k e n t o li mi t t h e c u r r en t f l o w b e tw e e n w and b in t h is st a t e to a max i m u m p u ls e c u r r en t o f n o m o r e tha n 2 0 ma. o t her w is e , deg r ada t ion or p o s s i b le des t r u c t io n o f th e in t e r n al s w i t c h co n t ac t can o c c u r . si mi l a r to t h e me ch ani c a l p o te n t i o me te r , t h e re s i st a n c e of t h e rd a c bet w een th e wi per w a n d t e rm i n al a als o p r od uces a d i g i t a l l y c o nt r o l l e d c o mp l e m e nt a r y r e s i s t a n c e r wa . w h en t h es e t e r m ina l s a r e us e d , t h e b t e r m in a l ca n b e op e n e d . s e t t in g t h e r e sis t a n c e val u e fo r r wa st a r ts a t a max i m u m va lue o f r e sist a n ce a n d de cr e a s e s as t h e da t a lo ade d in t h e la t c h i n cr e a s e s in va l u e . the ge n e ra l e q u a t i o n fo r t h is o p era t io n is w ab wa r r d d r + ? = 256 256 ) ( (2) fo r r ab = 10 k? a n d t h e b t e r m inal o p en c i r c ui ted , the f o l l ow i n g output re s i st anc e r wa wi l l b e s e t fo r t h e indic a te d rd a c l a t c h co des. ta ble 8. co des an d co r r e spo n di ng r wa resist ance d (dec.) r wa (?) output state 2 5 5 9 9 f u l l s c a l e 1 2 8 5 , 0 6 0 m i d s c a l e 1 9 , 9 6 1 1 l s b 0 1 0 , 0 6 0 z e r o s c a l e t y p i cal de vice to device ma t c hin g is p r o c es s lo t dep e n d en t and ma y va r y b y u p t o 30%. si n c e t h e r e sis t an c e e l e m e n t is p r o c es s e d in thin f i lm t e chn o log y , th e c h a n g e in r ab wi t h t e m p era t ur e has a v e r y lo w 45 p p m/ c t e m p er a t ur e co ef f i cien t. rev. pr e 5/12/03 | page 10 of 16
preliminary technical data ad5243/ad5248 programm ing t h e po tent iomet e r divi der voltage o u tp ut ope r ation h e i g i t a l p o te n t i o e te r e a s i ly ge ne r a te s a volt age i v i e r a t i p e r to b a n i p e r to a prop or t i ona l to t h e i n put volt age a t a t o b n l i e t h e p o la r i ty o v dd t o d hic h u s t e p o s i t i ve vol t ag e ac ro ss a b a an b c a n e a t e i t h e r po l a ri t y ig n o r i n g t h e e e c t o t h e i p e r r e sist a n ce o r a p p r o i a t ion co nne c t in g t h e a t e r ina l t o 5 v a n t h e b ter ina l t o g r o u n p r o uces a n ou t p u t v o l t a g e a t the i p e r t o b star tin g a t v u p t o b les s than 5 v a c h b o v o l t a g e is e u a l t o th e v o l t a g e a p p l ie acr o s s t e r inal ab ivie y t h e 25 p o si t i o n s o t h e p o t e n t io e t e r ivier h e ge n e ral e u a t i o n e i nin g t h e output vo lt ag e at v i th r e sp e c t t o g r o u n o r a n y vali in p u t v o l t a g e a p plie t o t e r ina l s a an b is b a w v d v d d v ? + = b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = i 2 c compatible 2-wire serial bus the 2- wir e i 2 c s e r i a l bu s proto c o l op e r a t e s a s f o l l ow s : 1. the mas t er ini t i a t e s da t a t r an sfer b y es t a b l is hing a st a r t co ndi t ion, w h ich is w h e n a h i g h -t o-lo w t r a n s i t i o n o n t h e s d a line o c c u rs while scl is hig h (s ee f i gur e 1 3 ). th e fol l o w in g b y t e i s t h e sla ve addr es s b y t e , w h ich co n s is ts o f t h e sla ve addr ess fol l o w e d b y a n r/ w bit ( t h i s bit de te r m i n e s w h e t he r da t a w i l l b e re a d f r om or w r i t te n to t h e sla ve de v i ce ). th e ad524 3 has a f i xe d sla v e addr es s b y t e w h er eas t h e ad5248 has tw o co nf igura b le addr es s b i ts ad0 and ad1 (s ee t a b l e 5). the s l a v e w h os e addr es s co r r esp o n d s t o t h e t r an smi t t e d addr es s r e s p onds b y p u l l in g t h e s d a l i n e lo w d u r i n g t h e nin t h clo c k p u ls e (t his is t e r m e d t h e ack n o w le d g e b i t). a t th i s s t a g e , all o t h e r devi ce s o n t h e b u s r e m a in idle wh ile t h e s e l e c t e d d e v i c e w a i t s for da t a to b e w r it te n to or re a d f r om i t s s e r i a l r e g i s t er . i f t h e r/ w b i t is hig h , t h e mas t er wi l l r e ad f r o m t h e sla ve de v i ce . on t h e o t h e r hand , if t h e r/ w bit i s lo w , t h e mast er wi l l wr i t e t o t h e s l a ve de vi ce . 2. i n t h e wr i t e m o de , t h e s e con d b y t e is t h e in s t r u c t io n b y t e . the f i rst b i t (m s b ) o f t h e inst r u c t io n b y t e is t h e rd a c sub addr es s s e le c t b i t. a log i c lo w wil l s e le c t c h a n nel-1 an d a log i c hig h wil l s e le c t c h a n ne l-2. the s e cond ms b , s d , is a s h u t do wn b i t. a log i c hig h ca us es an o p e n cir c ui t a t t e r m i n al a w h i l e sh or t i n g t h e wi p e r t o t e r m in a l b . this o p er a t io n y i e l ds a l m o st 0 ? in rh e o st a t m o de o r 0 v in p o te n t io m e ter mo de. i t is im p o r t an t t o n o t e t h a t t h e s h u t do wn o p er a t ion do es n o t dis t ur b t h e co n t en ts o f t h e r e g i st er . w h e n b r o u g h t o u t o f sh u t dow n , t h e pr e v iou s s e t t i n g wi l l b e a p pl ie d to t h e r d a c . a l s o , d u r i n g s h u t d o w n , n e w s e t t i n g s c a n b e p r og ra mm e d . w h en t h e p a r t is r e t u r n e d f r o m s h u t do wn, t h e co r r es p o n d i n g vr s e t t i n g w i l l b e a p plie d t o t h e r d a c . the r e ma i n der o f t h e b i ts i n t h e in s t r u c t io n b y t e a r e don t ca r e s(s e e t a b l e 5). a f te r a c k n ow l e dg i n g t h e i n st r u c t i o n b y te, t h e l a st b y te i n w r i t e m o d e i s t h e da ta b y t e . d a ta i s tra n s m i t t e d o v e r th e s e r i al b u s in s e u en ces o f nin e clo c k p u ls es (eig h t da ta b i ts f o l l owe d by an a c k n ow l e d g e bit ) . t h e t r ans i t i on s on t h e s d a line m u s t o c c u r d u r i n g the lo w p e r i o d o f scl an d r e ma in sta b le d u r i n g th e hig h p e r i o d o f scl (s e e t a b l e 5). 3. i n t h e r e a d m o de , th e da ta b y t e f o llo w s i m m e dia t e l y a f t e r t h e ack n o w le dg m e n t o f t h e s l a ve addr es s b y te . d a t a is t r a n smi t t e d o v er t h e s e r i al b u s in s e u e n ces o f nin e c l o c k p u ls es(a s l ig h t dif f er en ce wi t h t h e wr i t e m o de , w h er e t h er e a r e eig h t da t a b i ts fol l o w e d b y a n ack n o w le dge b i t). s i m i la r l y , th e tra n s i ti o n s o n t h e s d a lin e m u s t occur d u ri n g th e l o w pe ri od o f s c l a n d r e m a in s t a b l e d u ri n g th e hig h p e r i o d o f scl (s ee f i gur e 15 an d f i g u re 1 6 ) . n o t e t h a t t h e cha nne l o f in t e r e s t is t h e on e t h a t i s p r e v io us l y s e le c t e d i n t h e w r i t e m o de . i n t h e cas e w h er e us ers n e e d t o r e ad t h e r d a c va l u es o f b o t h channe ls, t h e y n e e d t o p r og ra m t h e f i rs t cha n n e l in t h e w r i t e m o de an d th en c h a n g e t o th e r e ad m o d e t o r e a d th e f i r s t ch a n n e l v a lu e. a f te r t h a t , t h e y ne e d to ch ange b a c k to t h e w r i t e m o de wi t h t h e s e co nd cha n nel s e le c t e d an d r e a d t h e s e con d c h ann e l val u e in t h e read m o de a g a i n. i t is n o t n e ce s s a r y fo r users t o is s u e t h e f r a m e 3 da t a b y t e in t h e wr i t e mo de fo r s u bs e uen t r e adb a ck o p er a t ion. u s ers s h o u ld r e f e r t o f i gur e 15 f o r th e p r ogra m m i n g f o r m a t . rev. pr e 5/12/03 | page 11 of 16
ad5243/ad5248 preliminary technical data 4. af t e r al l da ta b i ts ha v e be en r e ad o r wr i t t e n, a s t o p co ndi t ion is est a b l ish e d b y t h e mast er . a s t op co n d i t ion is def i n e d as a lo w-to -hig h t r a n s i t i o n o n t h e sd a l i ne w h i l e scl is hig h . i n wr i t e mo de , t h e mas t er wi l l p u l l t h e sd a lin e hig h d u r i n g t h e t e n t h clo c k p u ls e t o est a b l ish a st op co ndi t ion (s ee f i gur e 13) i n r e ad m o de , t h e mas t er wil l is s u e a n o a c k n o w le dge fo r t h e nin t h clo c k p u ls e (i .e ., t h e s d a li ne r e ma i n s hig h ). the mas t er wi l l t h en b r in g t h e s d a line lo w be fo r e th e t e n t h c l o c k p u ls e w h ic h g o es hig h t o es ta b l ish a s t o p co n d i t ion (s ee f i gur e 15 and f i gur e 16). a r e p e a t e d wr i t e f u n c t i on g i v e s t h e us er f l exi b i l i t y t o u p da te t h e rd a c o u t p u t a n u m b er o f tim e s a f t e r addr es sing a n d in s t r u c t in g t h e p a r t o n l y o n ce . f o r exa m ple , a f t e r t h e r d a c has ack n o w le dge d i t s sl a v e ad dr ess a n d inst r u c t io n b y tes in t h e wr i t e mo de , t h e rd a c o u t p ut w i l l u p da t e o n e a ch s u cces s i ve b y t e . i f dif f er en t in s t r u c t io n s a r e n e e d e d , t h e w r i t e/r e ad mo de has to st a r t a g ai n w i t h a ne w sla v e addr ess, inst r u c t io n, a n d da t a b y t e . s i mi la rl y , a r e p e a t e d r e ad f u n c tion o f th e rd a c is als o al lo w e d . multiple dev i ces on one bu s(applies only to ad5248) f i gur e 18 s h o w s f o ur ad5248 devices o n t h e s a m e s e r i al b u s. e a ch has a dif f er en t s l a v e addr e s s since t h e s t a t es o f t h eir a d 0 a n d a d 1 p i n s ar e dif f er en t. thi s al lo ws e a ch de vice on t h e b u s to b e w r it te n to or re a d f r om i n de p e nde n t l y . t h e ma st e r de v i c e o u t p ut b u s li n e dr i v ers a r e o p en-dra i n p u l l -dow n s in a f u l l y i 2 c co m p a t i b le in t e r f ace . s d a s c l a d 5 2 4 8 a d 1 a d 0 m a s t e r s d a s c l r p r p + 5 v s d a s c l a d 5 2 4 8 a d 1 a d 0 s d a s c l a d 5 2 4 8 a d 1 a d 0 s d a s c l a d 5 2 4 8 a d 1 a d 0 + 5 d v + 5 v + 5 v f i g u re 18. m u lt ip le a d 52 48 d e v i ces on o n e i 2 c b u s level shif ting for bi directio nal interface w h i l e m o s t legac y sys t em s ma y b e o p era t e d a t on e v o l t a g e , a n e w co m p o n en t m a y b e o p ti mized a t a n o t h e r . w h e n t w o sys t em s o p era t e t h e s a me sig n al a t t w o dif f er en t v o l t a g es, p r o p e r le v e l shif t i ng is n e e d e d . f o r in st a n c e , o n e can us e a 3.3 v e 2 pro m to i n te r f a c e w i t h a 5 v di g i t a l p o te n t i o me te r . a l e v e l shif t i ng s c h e m e is n e e d e d t o en a b le a b i dir e c t iona l co m m un ica t i o n so th a t t h e set t in g o f th e di gi ta l po t e n t i o m e t e r ca n b e sto r e d to a n d r e t r ie ve d f r o m t h e e 2 p r o m . f i gur e 19 show s o n e of t h e i m pl e m e n t a t i ons . m 1 an d m 2 c a n b e a n y n-c h ann e l sig n al fet s , o r if v dd fal l s be lo w 2.5 v , lo w thr e s h old fet s s u c h as t h e fd v301n . e 2 pr o m a d 52 43 sd a 1 scl 1 d g r p r p 3.3v 5v s m1 scl 2 sd a 2 r p r p g s m2 v dd1 = 3.3v v dd2 = 5v d f i gure 19. l e vel s h if ting for o p e r at ion at d i ffe r e nt p o te ntials esd protection a l l dig i t a l in pu t s a r e p r o t e c te d wi t h a s e r i es in pu t r e sisto r a n d p a ralle l z e n e r e s d s t r u ct ur es sh o w n in f i gur e 20 a n d f i gur e 21. this a p plies t o t h e dig i t a l in p u t p i n s sd a, scl, a n d a d 0. logic 340 ? terminal voltage operating ra nge the ad5243/48 v dd a n d g n d p o w e r su p p ly def i n e s t h e b o u n d a r y c o nd it i o ns for prop e r 3 - te r m i n a l d i g i t a l p o t e n t iom e t e r op era t ion. s u p p ly sig n als p r es en t o n t e r m inals a, b , a n d w tha t ex ceed v dd o r g n d wil l be c l am p e d b y the i n t e rn al f o r w a r d b i ased d i od es (see f i gur e 22). a v d d b w v ss f i g u re 22. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and v ss rev. pr e 5/12/03 | page 12 of 16
preliminary technical data ad5243/ad5248 power-up sequence sin c e t h e es d pr o t e c t i o n di o d e s limi t t h e v o l t age co m p l i an ce a t t e r m ina l s a, b , a n d w (s e e f i gu r e 22), i t is im p o r t a n t t o p o w e r v dd /gnd bef o r e a p p l yin g an y vol t a g e t o t e r m inals a, b , a n d w ; o t h e r w is e , t h e dio d e wi l l b e fo r w a r d b i as e d s u ch t h a t v dd wi l l b e p o w e r e d uni n t e n t io nal l y an d ma y a f fe c t t h e r e s t o f t h e us er s cir c ui t. t h e id e a l p o w e r - u p s e q u en c e is in t h e fol l o w in g o r der : gnd , v dd , d i g i t a l i n p u t s , a n d t h e n v a/ b / w . t h e r e l a t i ve ord e r of po w e ri n g v a , v b , v w , a n d t h e di g i t a l i n p u ts is no t im p o r t a n t as l o ng a s t h e y are p o we re d af te r v dd /gnd . layout and power supply b y passing i t is a go o d p r ac t i ce t o em plo y co m p ac t, mi nim u m le ad len g t h la yo u t desig n . th e le ads t o th e in p u ts sh o u ld be as dir e c t as pos s i b le wi th a m i n i m u m co n d uct o r le n g th . g r o u n d p a th s s h o u ld ha v e lo w r e sis t a n ce an d l o w ind u c t an ce . s i mil a rl y , i t is al s o a g o o d p r ac tice t o b y p a s s t h e p o w e r s u p p lies wi t h q u ali t y ca p a ci t o rs f o r o p tim u m sta b ili t y . s u p p l y leads t o th e de vice s h o u l d b e b y p a s s e d wi th dis c o r c h i p cer a mic c a p a ci t o rs o f 0.01 f t o 0.1 f . l o w es r 1 f t o 10 f ta n t al um o r e l ec tr ol ytic ca p a ci t o rs sh o u ld als o be a p p l ied a t t h e su p p lies t o mini mi ze an y t r a n sien t dist ur b a n c e an d lo w f r e q uen c y r i p p le (s ee f i gur e 23). n o t e tha t t h e dig i tal g r o u nd sho u ld als o be j o i n e d re motely to t h e an a l o g g r ou nd a t one p o i n t to mi ni m i z e th e gr o u n d bo un ce . a d 52 43 v dd c1 c3 gnd 10 f 0.1 f + v dd f i g u r e 2 3 . p o w e r su pp l y by pa s s i n g rev. pr e 5/12/03 | page 13 of 16
ad5243/ad5248 preliminary technical data pin conf iguration and fu nction descriptions pin c o nfig uratio n b1 w 1 a1 b2 w2 v dd scl sda 8 7 6 5 4 3 2 1 9 10 gn d a2 f i gur e 2 4 . - ad52 43 p i n co nfi g ur a t i o n b1 w 1 ad 0 b 2 w2 v dd scl sda 8 7 6 5 4 3 2 1 9 10 gn d ad1 f i gure 25. C ad 5243 pin configur ation pin func ti on descrip t io ns ta ble 9. p i n n a m e d e s c r i p t i o n 1 b 1 b1 t e r m i n a l . 2 a 1 a1 t e r m i n a l . 3 w 2 w2 t e r m i n a l . 4 g n d digital g r o u n d . 5 v dd positive power s u pply. 6 scl serial clock input. positive edg e triggered. 7 sda serial data inpu t/ output. 8 a 2 a2 t e r m i n a l . 9 b 2 b2 t e r m i n a l . 1 0 w 2 w2 t e r m i n a l . table 10. p i n n a m e d e s c r i p t i o n 1 b 1 b1 t e r m i n a l . 2 a d 0 programmable address bit 0 for multiple package decoding. 3 w 2 w2 t e r m i n a l 4 g n d digital g r o u n d . 5 v dd positive power s u pply.. 6 scl serial clock input. positive edg e triggered. 7 sda serial data inpu t/ output. 8 a d 1 programmable address bit 1 for multiple package decoding. 9 b 2 b2 t e r m i n a l . 1 0 w 1 w1 t e r m i n a l . rev. pr e 5/12/03 | page 14 of 16
preliminary technical data ad5243/ad5248 outline dimensions 0.23 0.20 0.17 0.80 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bs c 3.00 bsc 3 .00 bs c 4.90 bsc pin 1 compliant to jedec standards mo-187ba coplanarit y 0.10 f i g u re 26. 1 0 -l e a d m i n i s m al l o u t l i n e p a ck ag e [m sop] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s ordering guide m o d e l r ab (?) temperature package descri ption package option branding ad5243brm2.5- r2 2.5k C40c to +125c msop-10 rm-10 d0l ad5243brm2.5- rl7 2.5k C40c to +125c msop-10 rm-10 d0l ad5243brm10- r2 10k C40c to +125c msop-10 rm-10 d0m ad5243brm10- rl7 10k C40c to +125c msop-10 rm-10 d0m ad5243brm50- r2 50k C40c to +125c msop-10 rm-10 d0n ad5243brm50- rl7 50k C40c to +125c msop-10 rm-10 d0n ad5243brm100 -r2 100k C40c to +125c msop-10 rm-10 d0p ad5243brm100 -rl7 100k C40c to +125c msop-10 rm-10 d0p ad5243eval see note 1 evaluation boar d m o d e l r ab (?) temperature package descri ption package option branding ad5248brm2.5- r2 2.5k C40c to +125c msop-10 rm-10 d1f ad5248brm2.5- rl7 2.5k C40c to +125c msop-10 rm-10 d1f ad5248brm10- r2 10k C40c to +125c msop-10 rm-10 d1g ad5248brm10- rl7 10k C40c to +125c msop-10 rm-10 d1g ad5248brm50- r2 50k C40c to +125c msop-10 rm-10 d1h ad5248brm50- rl7 50k C40c to +125c msop-10 rm-10 d1h ad5248brm100 -r2 100k C40c to +125c msop-10 rm-10 d1j ad5248brm100 -rl7 100k C40c to +125c msop-10 rm-10 d1j ad5248eval see note 1 evaluation boar d 1 th e evaluat i on board is s h ippe d with the 10 k ? r ab re si st or opt i on ; h o w e ver, t h e boa r d i s com p a t i b le wi t h a ll a v a i l a b le r e si st or va lu e opt i on s. the ad5243/48 co n t a i n s 2532 t r a n sis t o r s. die size: 30.7 mil 7 6 .8 mil = 2,358 s q . mil . esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. rev. pr e 5/12/03 | page 15 of 16
ad5243/ad5248 preliminary technical data notes rev. pr e 5/12/03 | page 16 of 16

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