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cmos, 170 mhz, triple, 10-bit high speed video dac adv7123-ep rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features 170 msps throughput rate triple, 10-bit digital-to-analog converters (dacs) sfdr ?70 db at f clk = 50 mhz; f out = 1 mhz ?53 db at f clk = 140 mhz; f out = 40 mhz rs-343a-/rs-170-compatible output complementary outputs dac output current range: 2.0 ma to 26.5 ma ttl-compatible inputs internal reference: 1.235 v single-supply 3.3 v operation 48-lead lfcsp package low power dissipation: 30 mw minimum at 3 v low power standby mode: 6 mw typical at 3 v supports defense and aerospace applications (aqec standard) military temperature range: ?55c to +105c controlled manufacturing baseline one assembly/test site one fabrication site enhanced product change notification qualification data available on request applications digital video systems high resolution color graphics digital radio modulation image processing instrumentation video signal reconstruction functional block diagram 10 10 10 10 10 10 data register dac dac blank sync r9 to r0 g9 to g0 b9 to b0 psave clock dac adv7123-ep data register data register blank and sync logic power-down mode voltage reference circuit ior ior iog iog iob v ref r set v aa comp gnd iob 09200-001 figure 1. general description the adv7123-ep is a triple, high speed digital-to-analog converter (dac) on a single monolithic chip. it consists of three high speed, 10-bit video dacs with complementary outputs, a standard ttl input interface, and a high impedance, analog output current source. the adv7123-ep has three separate 10-bit-wide input ports. a single 3.3 v power supply and clock are the only components required to make the part functional. the adv7123-ep has additional video control signals: composite sync and blank . the adv7123-ep also has a power save mode. the adv7123-ep is fabricated in a 5 v cmos process. its monolithic cmos construction ensures greater functionality with lower power dissipation. the adv7123-ep is available in a 48-lead lfcsp package. full details about this enhanced product are available in the adv7123 data sheet, which should be consulted in conjunction with this data sheet. product highlights 1. guaranteed monotonic to 10 bits. 2. compatible with a wide variety of high resolution color graphics systems, including rs-343a and rs-170.
adv7123-ep rev. 0 | page 2 of 1 2 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dynamic specifications ............................................................... 4 ? timing specifications ...................................................................5 ? absolute maximum ratings ............................................................7 ? esd caution...................................................................................7 ? pin configuration and function descriptions ..............................8 ? outline dimensions ....................................................................... 10 ? ordering guide .......................................................................... 10 ? revision history 7/10revision 0: initial version
adv7123-ep rev. 0 | page 3 of 12 specifications v aa = 3.0 v to 3.6 v, v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 1 unless otherwise noted; t j max = 110c. table 1. parameter 2 min typ max unit test conditions/comments 1 static performance resolution (each dac) 10 bits r set = 680 integral nonlinearity (bsl) ?1 +0.5 +1 lsb r set = 680 differential nonlinearity ?1 +0.25 +1 lsb r set = 680 digital and control inputs input high voltage, v ih 2.0 v input low voltage, v il 0.8 v input current, i in ?1 +1 a v in = 0.0 v or v dd psave pull-up current 20 a input capacitance, c in 10 pf analog outputs output current 2.0 26.5 ma green dac, sync = high 2.0 18.5 ma rgb dac, sync = low dac-to-dac matching 1.0 % output compliance range, v oc 0 1.4 v output impedance, r out 70 k output capacitance, c out 10 pf offset error 0 0 % fsr tested with dac output = 0 v gain error 3 0 % fsr fsr = 17.62 ma voltage reference, external reference range, v ref 1.12 1.235 1.35 v voltage reference, internal voltage reference, v ref 1.235 v power dissipation digital supply current 4 2.2 5.0 ma f clk = 50 mhz 6.5 12.0 ma f clk = 140 mhz 7.5 13.5 ma f clk = 170 mhz analog supply current 67 72 ma r set = 560 8 ma r set = 4933 standby supply current 2.1 5.0 ma psave = low, digital and control inputs at v dd power supply rejection ratio 0.1 0.5 %/% 1 temperature range t min to t max : ?55c to +105c. 2 these maximum/minimum specifications are guaranteed by characterization over the 3.0 v to 3.6 v range. 3 gain error = {(measured (fsc)/ideal (fsc) ? 1) 100}, where ideal (fsc) = v ref /r set k (0x3ffh) and k = 7.9896. 4 digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 v and v dd .
adv7123-ep rev. 0 | page 4 of 12 dynamic specifications v aa = 3.0 v to 3.6 v, v ref = 1.235 v, r set = 680 , c l = 10 pf. all specifications are at t a = 25c, unless otherwise noted; t j max = 110c. table 2. parameter 1 min typ max unit ac linearity spurious-free dynamic range to nyquist 2 single-ended output f clk = 50 mhz; f out = 1.00 mhz 67 dbc f clk = 50 mhz; f out = 2.51 mhz 67 dbc f clk = 50 mhz; f out = 5.04 mhz 63 dbc f clk = 50 mhz; f out = 20.2 mhz 55 dbc f clk = 100 mhz; f out = 2.51 mhz 62 dbc f clk = 100 mhz; f out = 5.04 mhz 60 dbc f clk = 100 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 40.4 mhz 48 dbc f clk = 140 mhz; f out = 2.51 mhz 57 dbc f clk = 140 mhz; f out = 5.04 mhz 58 dbc f clk = 140 mhz; f out = 20.2 mhz 52 dbc f clk = 140 mhz; f out = 40.4 mhz 41 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz 70 dbc f clk = 50 mhz; f out = 2.51 mhz 70 dbc f clk = 50 mhz; f out = 5.04 mhz 65 dbc f clk = 50 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 2.51 mhz 67 dbc f clk = 100 mhz; f out = 5.04 mhz 63 dbc f clk = 100 mhz; f out = 20.2 mhz 58 dbc f clk = 100 mhz; f out = 40.4 mhz 52 dbc f clk = 140 mhz; f out = 2.51 mhz 62 dbc f clk = 140 mhz; f out = 5.04 mhz 61 dbc f clk = 140 mhz; f out = 20.2 mhz 55 dbc f clk = 140 mhz; f out = 40.4 mhz 53 dbc spurious-free dynamic range within a window single-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 77 dbc f clk = 50 mhz; f out = 5.04 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.04 mhz; 4 mhz span 64 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 74 dbc f clk = 50 mhz; f out = 5.00 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.00 mhz; 4 mhz span 60 dbc total harmonic distortion f clk = 50 mhz; f out = 1.00 mhz t a = 25c 66 dbc t min to t max 65 dbc f clk = 50 mhz; f out = 2.00 mhz 64 dbc f clk = 100 mhz; f out = 2.00 mhz 64 dbc f clk = 140 mhz; f out = 2.00 mhz 55 dbc
adv7123-ep rev. 0 | page 5 of 12 parameter 1 min typ max unit dac performance glitch impulse 10 pv-sec dac-to-dac crosstalk 3 23 db data feedthrough 4 , 5 22 db clock feedthrough 4 , 5 33 db 1 these maximum/minimum specifications are guaranteed by characterization over the 3.0 v to 3.6 v range. 2 the adv7123-ep exhibits high pe rformance when operating with an internal voltage reference, v ref . 3 dac-to-dac crosstalk is measured by holding one dac high whil e the other two dacs are making low-to-high and high-to-low trans itions. 4 clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. glitch impulse inclu des clock and data feedthrough. 5 ttl input values are 0 v to 3 v, with input rise/fall times of 3 ns, measured at the 10% and 90% points. timing reference poin ts are 50% for inputs and outputs. timing specifications v aa = 3.0 v to 3.6 v, v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 1 unless otherwise noted; t j max = 110c. table 3. parameter 2 , 3 symbol min typ max unit test conditions/comments analog outputs analog output delay t 6 7.5 ns analog output rise/fall time 4 t 7 1.0 ns analog output transition time 5 t 8 15 ns analog output skew 6 t 9 1 2 ns clock control clock frequency 7 f clk 170 mhz data and control setup t 1 0.68 ns data and control hold t 2 2.9 ns clock period t 3 5.88 ns clock pulse width high 6 t 4 2.6 ns f clk_max = 170 mhz clock pulse width low 6 t 5 2.6 ns f clk_max = 170 mhz pipeline delay 6 t pd 1.0 1.0 1.0 clock cycles psave up time 6 t 10 4 10 ns 1 temperature range t min to t max : ?55c to +105c. 2 these maximum/minimum specifications are guaranteed by characterization over the 3.0 v to 3.6 v range. 3 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ). 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a fu ll-scale transition. 5 measured from the 50% point of full-scale transition to within 2% of the final output value. 6 guaranteed by characterization. 7 f clk maximum specification prod uction tested at 125 mhz.
adv7123-ep rev. 0 | page 6 of 12 t 3 t 1 t 4 t 8 t 2 t 6 t 7 t 5 clock digital inputs (r9 to r0, g9 to g0, b9 to b0, sync, blank) analog inputs (ior, ior, iog, iog, iob, iob) notes 1. output delay ( t 6 ) measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 2. output rise/fall time ( t 7 ) measured between the 10% and 90% points of full-scale transition. 3. transition time ( t 8 ) measured from the 50% point of full-scale transition to within 2% of the fin a l output value. 09200-002 figure 2. timing diagram
adv7123-ep rev. 0 | page 7 of 12 absolute maximum ratings table 4. parameter rating v aa to gnd 7 v voltage on any digital pin gnd ? 0.5 v to v aa + 0.5 v ambient operating temperature (t a ) ?55c to +105c storage temperature (t s ) ?65c to +150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec) 300c vapor phase soldering (1 minute) 220c i out to gnd 1 0 v to v aa stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 analog output short circuit to any power supply or common gnd can be of an indefinite duration.
adv7123-ep rev. 0 | page 8 of 12 pin configuration and fu nction descriptions v aa b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 clock r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 psave r set g0 g1 g2 g3 g4 g5 g6 g7 g8 g9 comp v aa v aa iob gnd gnd v ref iob iog iog ior ior blank notes 1. the exposed paddle on the underside of the package must be soldered to the ground plane to increase the reliability of the solder joints and to maximize the thermal capability of the package. sync adv7123-ep top view (not to scale) 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 35 36 34 33 32 31 30 29 28 27 26 25 pin 1 indicator 09200-003 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 to 10, 14 to 23, 39 to 48 g0 to g9, b0 to b9, r0 to r9 red, green, and blue pixel data inputs (ttl compatible). pixel data is latched on the rising edge of clock. r0, g0, and b0 are the least significant data bits. unused pixel data inputs should be connected to either the regular printed circuit board (pcb) power or ground plane. 11 blank composite blank control input (ttl compatible). a logi c 0 on this control input drives the analog outputs ior, iob, and iogto the blanking level. the blank signal is latched on the rising edge of clock. when blank is a logic 0, the r0 to r9, g0 to g9, and b0 to b9 pixel inputs are ignored. 12 sync composite sync control input (ttl compatible). a logic 0 on the sync input switches off a 40 ire current source. the sync current is internally connected to the iog analog output. sync does not override any other control or data input; therefore, it should only be asserted during the blanking interval. sync is latched on the rising edge of clock. if sync information is not required on the green channel, the sync input should be tied to logic 0. 13, 29, 30 v aa analog power supply (3.3 v 10%). all v aa pins on the adv7123-ep must be connected. 24 clock clock input (ttl compatible). the rising edge of clock latches the r0 to r9, g0 to g9, b0 to b9, sync , and blank pixel and control inputs. typically, the clock input is the pixel clock rate of the video system. clock should be driven by a dedicated ttl buffer. 25, 26 gnd ground. the gnd pins must be connected. 27, 31, 33 iob , iog , ior differential red, green, and blue current outputs (high impedance curren t sources). these rgb video outputs are specified to directly drive rs-343a and rs-170 video levels into a doubly terminated 75 coaxial cable. if the complementary outputs are not required , these outputs should be tied to ground. 28, 32, 34 iob, iog, ior red, green, and blue current outputs (high impedance current sources). these rgb video outputs are specified to directly drive rs-343a and rs-170 video levels into a doubly terminated 75 coaxia l cable. all three current outputs should have similar output loads whether or not they are all being used. 35 comp compensation pin for the internal reference amplifier. a 0.1 f ceramic capacitor must be connected between comp and v aa . 36 v ref voltage reference input for dacs or voltage reference output (1.235 v). the v ref pin is normally terminated to v aa through a 0.1 f capacitor. however, the adv7123-ep can be overdriven by an external 1.23 v reference ( ad1580 ), if required.
adv7123-ep rev. 0 | page 9 of 12 pin no. mnemonic description 37 r set a resistor (r set ) connected between this pin and gnd controls the magnitude of the full-scale video signal. note that the ire relationships are maintained, regardless of the full-sc ale output current. for nominal video levels into a doubly terminated 75 load, r set = 530 . the relationship between r set and the full-scale output current on iog (assuming i sync is connected to iog) is given by r set () = 11,445 v ref (v)/ iog (ma) the relationship between r set and the full-scale output current on ior, iog, and iob is given by iog (ma) = 11,445 v ref (v)/ r set () ( sync being asserted) ior, iob (ma) = 7989.6 v ref (v)/ r set () the equation for iog is the same as that for ior and iob when sync is not being used, that is, sync is tied permanently low. 38 psave power save control pin. reduced power consumption is available on the adv7123-ep when this pin is active. ep exposed pad the exposed paddle on the underside of the package must be soldered to the ground plane to increase the reliability of the solder joints and to max imize the thermal capability of the package.
adv7123-ep rev. 0 | page 10 of 1 2 outline dimensions 112408-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-wkkd. 1 0.50 bsc bottom view top view pin 1 indicator 7.00 bsc sq 48 13 24 25 36 37 12 exposed pad p i n 1 i n d i c a t o r 4.25 4.10 sq 3.95 0.45 0.40 0.35 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.25 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18 figure 4. 48-lead lead frame chip scale package [lfcsp_wq] 7 mm 7 mm body, very very thin quad (cp-48-5) dimensions shown in millimeters ordering guide model 1 temperature range speed option pa ckage description package option ADV7123SCP170EP-RL ?55c to +105c 170 mhz 48-lead lfcsp_wq cp-48-5 1 available in 3.3 v version only.
adv7123-ep rev. 0 | page 11 of 1 2 notes
adv7123-ep rev. 0 | page 12 of 12 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09200-0-7/10(0)

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