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rev.3.00 jan 13, 2006 page 1 of 29 hm64ylb36512 series 16m synchronous late write fast static ram (512-kword 36-bit) rej03c0270-0300 rev.3.00 jan.13.2006 description the hm64ylb36512 is a synchronous fast static ram organized as 512-kword 36-bit. it has realized high speed access time by employing the most advanced cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. it is packaged in standard 119-bump bga. note: all power supply and ground pins must be connected for proper operation of the device. features ? 2.5 v 5% operation and 1.5 v (v ddq ) ? 16m bit density ? byte write control (4 byte write selects, one for each 9-bit) ? optional 18 configuration ? hstl compatible i/o ? programmable impedance output drivers ? asynchronous g output control ? asynchronous sleep mode ? fc-bga 119pin package with sram jedec standard pinout ? limited set of boundary scan jtag ieee 1149.1 compatible ? mode selectable among late write, associative late write (late select) and register-latch ? late select mode: ? synchronous register to register operation ? late sas select, selects which half of 72-bit core data to return on reads ? sas serves as way select ? differential hstl clock inputs ? late write mode: ? synchronous register to register operation ? differential hstl clock inputs ? register-latch mode: ? synchronous register to latch operation ? differential pseudo-hstl clock inputs
hm64ylb36512 series rev.3.00 jan 13, 2006 page 2 of 29 ordering information type no. organization modes access time cycle time package hm64ylb36512bp-28 512k 36 late select mode late write mode 1.6 ns 2.8 ns late select mode late write mode 1.6 ns 3.3 ns HM64YLB36512BP-33 512k 36 register-latch mode 5.5 ns 6.5 ns 119-bump 1.27 mm 14 mm 22 mm bga prbg0119db-a (bp-119e) note: hm: hitachi memory prefix, 64: external cache sram, y: v dd = 2.5 v, l: dual mode sram, b: v ddq = 1.5 v pin arrangement 1 2 3 4 5 6 7 a v ddq sa14 sa13 nc sa6 sa7 v ddq b nc sa15 sa12 nc sa5 sa9 nc c nc sa16 sa11 v dd sa4 sa8 nc d dqc7 dqc8 v ss zq v ss dqb8 dqb7 e dqc5 dqc6 v ss ss v ss dqb6 dqb5 f v ddq dqc4 v ss g v ss dqb4 v ddq g dqc3 dqc2 swec nc sweb dqb2 dqb3 h dqc1 dqc0 v ss nc v ss dqb0 dqb1 j v ddq v dd v ref v dd v ref v dd v ddq k dqd1 dqd0 v ss k v ss dqa0 dqa1 l dqd3 dqd2 swed k swea dqa2 dqa3 m v ddq dqd4 v ss swe v ss dqa4 v ddq n dqd5 dqd6 v ss sa17 v ss dqa6 dqa5 p dqd7 dqd8 v ss sas/sa0 v ss dqa8 dqa7 r nc sa10 m1 v dd m2 sa1 nc t nc nc sa18 sa3 sa2 nc zz u v ddq tms tdi tck tdo nc v ddq (top view) note: 4p pin is sas in both the late select mode and the late write mode, or is sa0 in the register-latch mode.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 3 of 29 block diagram (late select mode) read add. reg. write add. reg. (way0) 256k 36 memory array (way1) 256k 36 memory array read add. reg. write add. reg. ss reg. swe reg. output reg. din reg. sa1 to sa18 sas swe ss 1 0 k 1 0 1 0 output reg. sa1 to sa18 compare swex 1st reg. swex (x: a to d) swex 2nd reg. byte write control 1 0 way select output enable dqxn (x: a to d, n: 0 to 8) 1 0 match0 match1 impedance control zq g block diagram (late write mode) read add. reg. write add. reg. (way0) 512k 36 memory array ss reg. swe reg. output reg. din reg. sas sa1 to sa18 swe ss 1 0 k 1 0 sa1 to sa18 sas compare swex 1st reg. swex (x: a to d) swex 2nd reg. byte write control output enable dqxn (x: a to d, n: 0 to 8) match0 impedance control zq g
hm64ylb36512 series rev.3.00 jan 13, 2006 page 4 of 29 block diagram (register-latch mode) read add. reg. write add. reg. (way0) 512k 36 memory array ss reg. swe reg. output latch din reg. sa0 to sa18 swe ss 1 0 k 1 0 sa0 to sa18 compare swex 1st reg. swex (x: a to d) swex 2nd reg. byte write control output enable dqxn (x: a to d, n: 0 to 8) match0 impedance control zq g
hm64ylb36512 series rev.3.00 jan 13, 2006 page 5 of 29 pin descriptions name i/o type descriptions notes v dd supply core power supply v ss supply ground v ddq supply output power supply v ref supply input reference, provides input reference voltage k input clock input, active high k input clock input, active low ss input synchronous chip select swe input synchronous write enable san input synchronous address input n: 1 to 18 (late select mode) (late write mode) n: 0 to 18 (register-latch mode) sas input late select: synchronous way select late write: synchronous address input sa0 in the register-latch mode swex input synchronous byte write enables x: a to d g input asynchronous output enable zz input power down mode select zq input output impedance control 1 dqxn i/o synchronous data input/output x: a to d n: 0 to 8 m1, m2 input output protocol mode select tms input boundary scan test mode select tck input boundary scan test clock tdi input boundary scan test data input tdo output boundary scan test data output nc ? no connection m1 m2 protocol notes v ss v ss synchronous register to register operation (late select mode) 2 v ss v dd synchronous register to register operation (late write mode) 3 v dd v ss synchronous register to latch operation (register-latch mode) 2 notes: 1. zq is to be connected to v ss via a resistance rq where 175 ? rq 300 ? . if zq = v ddq or open, output buffer impedance will be maximum. 2. mode control pins m1 and m2 are used to select different read protocols. these mode control input pins are set at power-up and will not change the states during the sram operates. late select mode: single clock, late sas select, pipelined read protocol late write mode: single clock, pipelined read protocol register-latch mode: single differential clock register-latch mode protocol 3. mode control pin m2 can be set to v ddq instead of v dd .
hm64ylb36512 series rev.3.00 jan 13, 2006 page 6 of 29 truth table late select mode late write mode register-latch mode zz ss ss ss ss g g g g swe swe swe swe swea swea swea swea sweb sweb sweb sweb swec swec swec swec swed swed swed swed k k k k k operation dq (n) dq (n+1) dq (n) dq (n+1) h sleep mode high-z high-z high-z high-z l h l-h h-l dead (not selected) high-z high-z l h h dead (dummy read) high-z high-z high-z l l l h l-h h-l read d out (a, b, c, d) 0 to 8 d out (a, b, c, d) 0 to 8 l l l l l l l l-h h-l write a, b, c, d byte high-z d in (a, b, c, d) 0 to 8 high-z d in (a, b, c, d) 0 to 8 l l l h l l l l-h h-l write b, c, d byte high-z d in (b, c, d) 0 to 8 high-z d in (b, c, d) 0 to 8 l l l l h l l l-h h-l write a, c, d byte high-z d in (a, c, d) 0 to 8 high-z d in (a, c, d) 0 to 8 l l l l l h l l-h h-l write a, b, d byte high-z d in (a, b, d) 0 to 8 high-z d in (a, b, d) 0 to 8 l l l l l l h l-h h-l write a, b, c byte high-z d in (a, b, c) 0 to 8 high-z d in (a, b, c) 0 to 8 l l l h h l l l-h h-l write c, d byte high-z d in (c, d) 0 to 8 high-z d in (c, d) 0 to 8 l l l l h h l l-h h-l write a, d byte high-z d in (a, d) 0 to 8 high-z d in (a, d) 0 to 8 l l l l l h h l-h h-l write a, b byte high-z d in (a, b) 0 to 8 high-z d in (a, b) 0 to 8 l l l h l l h l-h h-l write b, c byte high-z d in (b, c) 0 to 8 high-z d in (b, c) 0 to 8 l l l h h h l l-h h-l write d byte high-z d in (d) 0 to 8 high-z d in (d) 0 to 8 l l l h h l h l-h h-l write c byte high-z d in (c) 0 to 8 high-z d in (c) 0 to 8 l l l h l h h l-h h-l write b byte high-z d in (b) 0 to 8 high-z d in (b) 0 to 8 l l l l h h h l-h h-l write a byte high-z d in (a) 0 to 8 high-z d in (a) 0 to 8 notes: 1. h: v ih , l: v il , : v ih or v il 2. swe , ss , swea to swed , sa and sas are sampled at the rising edge of k clock.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 7 of 29 programmable impedance output drivers output buffer impedance can be programmed by terminating the zq pin to v ss through a precision resistor (rq). the value of rq is five times the output impedance desired. the allowable value of rq to guarantee impedance matching with a tolerance of 15% is 250 ? . if the status of zq pin is open, output impedance is maximum value. maximum impedance also occurs with zq connected to v ddq . the impedance update of the output driver occurs when the sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high-z, therefore will trigger an update. at power up, the output buffer is in high-z. it will take 4,096 cycles for the impedance to be completely updated. absolute maximum ratings parameter symbol rating unit notes input voltage on any pin v in ? 0.5 to v ddq + 0.5 v 1, 4 core supply voltage v dd ? 0.5 to +3.13 v 1 output supply voltage v ddq ? 0.5 to +2.1 v 1, 4 operating temperature t opr 0 to +85 c storage temperature t stg ? 55 to +125 c output short-circuit current i out 25 ma latch up current i li 200 ma package junction to top thermal resistance j-top 6.5 c/w 5 package junction to board thermal resistance j-board 12 c/w 5 notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher voltages than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then v in . remember, according to the absolute maximum ratings table, v ddq is not to exceed 2.1 v, whatever the instantaneous value of v ddq . 5. see figure below. j-top thermocouple thermo grease water cold plate sram teflon block jedec/2s2p bga thermal board thermocouple thermo grease water cold plate sram teflon block jedec/2s2p bga thermal board j-board water water
hm64ylb36512 series rev.3.00 jan 13, 2006 page 8 of 29 note: the following dc and ac specifications shown in the tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. recommended dc operating conditions (ta = 0 to +85 c) late select mode late write mode register-latch mode parameter symbol min typ max min typ max unit notes power supply voltage: core v dd 2.38 2.50 2.63 2.38 2.50 2.63 v power supply voltage: i/o v ddq 1.40 1.50 1.60 1.40 1.50 1.60 v input reference voltage: i/o v ref 0.60 0.75 0.90 0.70 0.75 0.80 v 1 input high voltage v ih v ref + 0.10 ? v ddq + 0.30 v ref + 0.15 ? v ddq + 0.50 v 4 input low voltage v il ? 0.30 ? v ref ? 0.10 ? 0.50 ? v ref ? 0.15 v 4 clock differential voltage v dif 0.10 ? v ddq + 0.30 0.10 ? v ddq + 0.30 v 2, 3 clock common mode voltage v cm 0.60 ? 0.90 0.90 ? 1.30 v 3 notes: 1. peak to peak ac component superimposed on v ref may not exceed 5% of v ref . 2. minimum differential input voltage required for differential input clock operation. 3. see figure below. 4. v ref = 0.75 v (typ). differential voltage / common mode voltage v dif v cm v ddq v ss
hm64ylb36512 series rev.3.00 jan 13, 2006 page 9 of 29 dc characteristics (ta = 0 to +85 c, v dd = 2.5 v 5%) late select mode late write mode register-latch mode parameter symbol min max min max unit notes input leakage current i li ? 2 ? 2 a 1 output leakage current i lo ? 5 ? 5 a 2 standby current i sbzz ? 150 ? 150 ma 3 v dd operating current, excluding output drivers i dd ? 450 ? 350 ma 4 quiescent active power supply current i dd2 ? 200 ? 200 ma 5 maximum power dissipation, including output drivers p ? 2.3 ? 2.3 w 6 parameter symbol min typ max unit notes output low voltage v ol v ss ? v ss + 0.4 v 7 v oh1 v ddq ? 0.4 ? v ddq v 8 output high voltage v oh2 1.3 ? v ddq v 12 zq pin connect resistance rq ? 250 ? ? output ?low? current i ol (v ddq /2) / {(rq/5) ? 15%} (v ddq /2) / {(rq/5) + 15%} ma 9, 11 output ?high? current i oh (v ddq /2) / {(rq/5) + 15%} (v ddq /2) / {(rq/5) ? 15%} ma 10, 11 notes: 1. 0 v in v ddq for all input pins (except v ref , zq, m1, m2 pin) 2. 0 v out v ddq , dq in high-z 3. all inputs (except clock) are held at either v ih or v il , zz is held at v ih , i out = 0 ma. specification is guaranteed at +75 c junction temperature. 4. i out = 0 ma, read 50% / write 50%, v dd = v dd max, frequency = min. cycle 5. i out = 0 ma, read 50% / write 50%, v dd = v dd max, frequency = 3 mhz 6. output drives a 12 pf load and switches every cycle. this parameter should be used by the sram designer to determine electrical and package requirements for the sram device. 7. rq = 250 ? , i ol = 6.8 ma 8. rq = 250 ? , i oh = ? 6.8 ma 9. measured at v ol = 1/2 v ddq 10. measured at v oh = 1/2 v ddq 11. the total external capacitance of zq pin must be less than 7.5 pf. 12. rq = 250 ? , i oh = ? 100 a
hm64ylb36512 series rev.3.00 jan 13, 2006 page 10 of 29 ac characteristics (ta = 0 to +85 c, v dd = 2.5 v 5%) late select mode, late write mode hm64ylb36512bp -28 -33 parameter symbol min max min max unit notes ck clock cycle time t khkh 2.8 ? 3.3 ? ns ck clock high width t khkl 1.2 ? 1.3 ? ns ck clock low width t klkh 1.2 ? 1.3 ? ns address setup time t avkh 0.3 ? 0.3 ? ns 2 data setup time t dvkh 0.3 ? 0.3 ? ns 2 address hold time t khax 0.6 ? 0.6 ? ns data hold time t khdx 0.6 ? 0.6 ? ns clock high to output valid t khqv ? 1.6 ? 1.6 ns 1 clock high to output hold t khqx 0.65 ? 0.65 ? ns 1, 6 clock high to output low-z ( ss control) t khqx2 0.65 ? 0.65 ? ns 1, 4, 6 clock high to output high-z t khqz 0.65 2.0 0.65 2.0 ns 1, 3, 6 output enable low to output low-z t glqx 0.1 ? 0.1 ? ns 1, 4, 6 output enable low to output valid t glqv ? 2.0 ? 2.0 ns 1, 4 output enable high to output high-z t ghqz ? 2.0 ? 2.0 ns 1, 3 sleep mode recovery time t zzr 20.0 ? 20.0 ? ns 5 sleep mode enable time t zze ? 15.0 ? 15.0 ns 1, 3, 5 register-latch mode hm64ylb36512bp -33 parameter symbol min max unit notes ck clock cycle time t khkh 6.5 ? ns ck clock high width t khkl 1.2 ? ns ck clock low width t klkh 1.2 ? ns address setup time t avkh 0.4 ? ns 2 data setup time t dvkh 0.4 ? ns 2 address hold time t khax 1.0 ? ns data hold time t khdx 1.0 ? ns clock high to output valid t khqv 1.7 5.5 ns 1 clock low to output valid t klqv 0.5 2.3 ns clock low to output hold t klqx 0.5 ? ns clock low to output low-z ( ss control) t klqx2 0.5 ? ns 1, 4, 6 clock high to output high-z t khqz 0.5 2.3 ns 1, 3, 6 output enable low to output low-z t glqx 0.1 ? ns 1, 4, 6 output enable low to output valid t glqv ? 2.3 ns 1, 4 output enable high to output high-z t ghqz ? 2.3 ns 1, 3 sleep mode recovery time t zzr 20.0 ? ns 5 sleep mode enable time t zze ? 15.0 ns 1, 3, 5 notes: 1. see figure in ?ac test conditions?. 2. parameters may be guaranteed by design, i.e., without tester guardband. 3. transitions are measured 50 mv of output high impedance from output low impedance. 4. transitions are measured 50 mv from steady state voltage. 5. when zz is switching, clock input k must be at the same logic level for the reliable operation. 6. minimum value is verified by design and tested without guardband.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 11 of 29 timing waveforms (late select mode) read cycle-1 k, k q0 q1 q 2 ss swe swex dq a2 a3 a4 a1 sa t avkh t khax t avkh t khax t avkh t khax t khqx t khqv a10 a20 a30 a00 sas t khkh t khkl t klkh read cycle-2 ( ss controlled) t khkh t khkl t klkh a3 a4 a1 sa t khax t avkh t khax swex ss swe t avkh t khax dq q0 q1 q3 t khqz t khqx2 sas a30 a10 t avkh t khax k, k notes: g , zz = v il , x: a to d
hm64ylb36512 series rev.3.00 jan 13, 2006 page 12 of 29 read cycle-3 ( g controlled) q0 q1 q3 a2 a3 a4 a1 sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g t ghqz t glqx t glqv a10 a20 a30 a00 sas t khkh t khkl t klkh k, k read operation (late select mode) during read cycle, n-1 bits of address (sa) are registered during the first rising clock edge. the nth bit of address (sas) is registered one clock edge later (the second edge). the setup time requirements for all address bits are the same. sas is used as the nth bit of address on both read and write. the internal array is read between this first edge and second edge, and data is captured in the output register at the second clock edge. this requires the nth address bit (sas) to be used as the mux select before the output register. alternatively, the nth address bit can be registered, and used as the mux select during the data drive cycle. in that case, the output drive should still have a monotonic edge transition (no glitches due to logic switch).
hm64ylb36512 series rev.3.00 jan 13, 2006 page 13 of 29 write cycle a2 a3 a4 a1 k, k sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g d1 d2 d3 d0 t avkh t khax t dvkh t khdx a20 a30 a40 a10 sas t avkh t khax t khkh t khkl t klkh notes: zz = v il , x: a to d write operation (late write and late select mode) during writes, the write data follows the write address by one cycle. all n bits of address are presented during the same cycle. any subsequent read to this address should get the latest data. because in the actual implementation the data will be written into the sram array only after the next write address is received, a one-entry buffer is needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of the same address.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 14 of 29 read-write cycle k, k t khkh t khkl t klkh a6 a7 a3 a4 a1 sa t avkh t khax ss t avkh t khax swe t avkh t khax swex t avkh t khax q0 q1 d3 q4 d6 g t khqv t khqx t ghqz t dvkh t khdx t glqv t glqx t khqz dq a60 a30 a40 a10 sas t avkh t khax read read ( g control) read write dead ( ss control) write notes: zz = v il , x: a to d zz control k, k t khkh t khkl t klkh sa a1 t avkh t khax ss t avkh t khax swex swe t avkh t khax q1 t zzr dq t zze zz sleep active sleep off sleep active sas a10 t avkh t khax notes: g = v il , x: a to d when zz is switching, clock input k must be at the same logic level for the reliable operation.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 15 of 29 timing waveforms (late write mode) read cycle-1 k, k q1 q2 ss swe swex dq a2 a3 a4 a1 sa t avkh t khax t avkh t khax t avkh t khax t khqx t khqv t khkh t khkl t klkh read cycle-2 ( ss controlled) k, k a3 a4 a1 sa t avkh t khax t avkh t khax swex ss swe t avkh t khax dq q0 q1 q3 t khqz t khqx2 t khkh t khkl t klkh
hm64ylb36512 series rev.3.00 jan 13, 2006 page 16 of 29 read cycle-3 ( g controlled) q0 q1 q3 a2 a3 a4 a1 sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g t ghqz t glqx t glqv k, k t khkh t khkl t klkh read operation (late write mode) during read cycle, the address is registered during the first rising clock edge, the internal array is read between this first edge and second edge, and data is captured in the output register.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 17 of 29 write cycle a2 a3 a4 a1 k, k sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g d1 d2 d3 d0 t avkh t khax t dvkh t khdx t khkh t khkl t klkh notes: zz = v il , x: a to d write operation (late write and late select mode) during write cycle, the write data follows the write address by one cycle. all n bits of address are presented during the same cycle. any subsequent read to this address should get the latest data. because in the actual implementation the data will be written into the sram array only after the next write address is received, a one-entry buffer is needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of the same address.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 18 of 29 read-write cycle k, k t khkh t khkl t klkh a6 a7 a3 a4 a1 sa t avkh t khax ss t avkh t khax swe t avkh t khax swex t avkh t khax q0 q1 d3 q4 d6 g t khqv t khqx t ghqz t dvkh t khdx t glqv t glqx t khqz dq read read ( g control) read write dead ( ss control) write notes: zz = v il , x: a to d zz control k, k t khkh t khkl t klkh sa a1 t avkh t khax ss t avkh t khax swex swe t avkh t khax q1 t zzr dq t zze zz sleep active sleep off sleep active notes: g = v il , x: a to d when zz is switching, clock input k must be at the same logic level for the reliable operation.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 19 of 29 timing waveforms (register-latch mode) read cycle-1 k, k q0 q2 q3 ss swe swex dq a2 a3 a4 a1 sa t avkh t avkh t avkh t klqv t klqx t khkh t khkl t klkh q1 t khqv t khax t khax khax t note: zz = v il read cycle-2 ( ss controlled) t khkh t khkl t klkh a3 a4 a1 sa t khax t avkh t avkh t khax swex ss swe t avkh t khax dq q0 q1 q3 t khqz t khqv t klqx2 k, k note: zz = v il
hm64ylb36512 series rev.3.00 jan 13, 2006 page 20 of 29 read cycle-3 ( g controlled) q0 q1 q2 q3 a2 a3 a4 a1 sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g t ghqz t glqx t glqv t khkh t khkl t klkh k, k note: zz = v il write cycle a2 a3 a4 a1 k, k sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g d1 d2 d3 d0 t avkh t khax t dvkh t khdx t khkh t khkl t klkh note: zz = v il
hm64ylb36512 series rev.3.00 jan 13, 2006 page 21 of 29 read-write cycle-1 k, k t khkh t khkl t klkh a6 a7 a3 a4 a1 sa t avkh t khax ss t avkh t khax swe t avkh t khax swex t avkh t khax q0 q1 d3 q4 d6 g t klqx t klqv t ghqz t dvkh t khdx t glqv t glqx t khqz dq read read read write dead ( ss control) write t khqv q2 a2 note: zz = v il read-write cycle-2 k, k t khkh t khkl t klkh a6 a7 a3 a4 a1 sa t avkh t khax ss t avkh t khax swe t avkh t khax swex t avkh t khax q0 q1 d3 q4 d6 g t klqx t klqv t khqz t dvkh t khdx t klqv dq read read read write dead ( ss control) write t khqv q2 low fixed a2 a5 t khqz note: g , zz = v il during this period dq pins are in the output state so that the input signal of opposite phase to the outputs must not be applied.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 22 of 29 zz control k, k t khkh t khkl t klkh sa a1 t avkh t khax ss t avkh t khax swex swe t avkh t khax q1 t zzr dq t zze zz sleep active sleep off sleep active
hm64ylb36512 series rev.3.00 jan 13, 2006 page 23 of 29 input capacitance (v dd = 2.5 v, v ddq = 1.5 v, ta = +25 c, f = 1 mhz) parameter symbol min max unit pin name notes input capacitance c in ? 4 pf san, sas, ss , swe , swex 1, 3 clock input capacitance c clk ? 5 pf k, k 1, 2, 3 i/o capacitance c io ? 5 pf dqxn 1, 3 notes: 1. this parameter is sampled and not 100% tested. 2. exclude g 3. connect pins to gnd, except v dd , v ddq , and the measured pin. ac test conditions conditions parameter symbol late select mode late write mode register-latch mode unit note input and output timing reference levels v ref 0.75 0.75 v input signal amplitude v il , v ih 0.25 to 1.25 0.25 to 1.25 v input rise / fall time tr, tf 0.5 (10% to 90%) 0.5 (10% to 90%) ns clock input timing reference level differential cross point differential cross point v dif to clock 0.75 0.75 v v cm to clock 0.75 1.10 v output loading conditions see figure below see figure below note: parameters are tested with rq = 250 ? and v ddq = 1.5 v. output loading conditions 50 ? 16.7 ? 16.7 ? 50 ? 5 pf dq 50 ? 16.7 ? 50 ? 5 pf 0.75 v 0.75 v 0.75 v
hm64ylb36512 series rev.3.00 jan 13, 2006 page 24 of 29 boundary scan test access port operations overview in order to perform the interconnect testing of the modules that include this sram, the serial boundary scan test access port (tap) is designed to operate in a manner consistent with ieee standard 1149.1 - 1990. but does not implement all of the functions required for 1149.1 compliance. the hm64ylb series contains a tap controller. instruction register, boundary scans register, bypass register and id register. test access port pins symbol i/o name tck test clock tms test mode select tdi test data in tdo test data out note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. to disable the tap, tck must be connected to v ss . tdo should be left unconnected. to test boundary scan, the zz pin needs to be kept below v ref ? 0.4 v. tap dc operating characteristics (ta = 0 to +85 c) parameter symbol min max notes boundary scan input high voltage v ih 1.4 v 3.6 v boundary scan input low voltage v il ? 0.3 v 0.8 v boundary scan input leakage current i li ? 10 a +10 a 1 boundary scan output low voltage v ol ? 0.2 v 2 boundary scan output high voltage v oh 2.1 v ? 3 boundary scan output leakage current i lo ? 5 a +5 a 4 notes: 1. 0 v in 3.6 v for all logic input pins 2. i ol = 2 ma at v dd = 2.5 v. 3. i oh = ? 2 ma at v dd = 2.5 v. 4. 0 v out v dd , tdo in high-z
hm64ylb36512 series rev.3.00 jan 13, 2006 page 25 of 29 tap ac operating characteristics (ta = 0 to +85 c) parameter symbol min max unit note test clock cycle time t thth 67 ? ns test clock high pulse width t thtl 30 ? ns test clock low pulse width t tlth 30 ? ns test mode select setup t mvth 10 ? ns test mode select hold t thmx 10 ? ns capture setup t cs 10 ? ns 1 capture hold t ch 10 ? ns 1 tdi valid to tck high t dvth 10 ? ns tck high to tdi don?t care t thdx 10 ? ns tck low to tdo unknown t tlqx 0 ? ns tck low to tdo valid t tlqv ? 20 ns note: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture. tap ac test conditions (v dd = 2.5 v) temperature 0 c ta +85 c input timing measurement reference level 1.1 v input pulse levels 0 to 2.5 v input rise/fall time 1.5 ns typical (10% to 90%) output timing measurement reference level 1.25 v test load termination supply voltage (v t ) 1.25 v output load see figure below boundary scan ac test load dut tdo z 0 = 50 ? 50 ? v t
hm64ylb36512 series rev.3.00 jan 13, 2006 page 26 of 29 tap controller timing diagram tck tms tdi tdo ram address t thth t thtl t mvth t thmx t dvth t thdx t tlqv t tlqx t cs t ch t tlth test access port registers register name length symbol note instruction register 3 bits ir [2:0] bypass register 1 bit bp id register 32 bits id [31:0] boundary scan register 70 bits bs [70:1] tap controller instruction set ir2 ir1 ir0 instruction operation 0 0 0 sample-z tristate all data drivers and capture the pad value 0 0 1 idcode 0 1 0 sample-z tristate all data drivers and capture the pad value 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 private do not use. they are reserved for vendor use only 1 1 1 bypass note: this device does not perform extest, intest or the preload portion of the preload command in ieee 1149.1.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 27 of 29 boundary scan order (hm64ylb36512) bit # bump id signal name bit # bump id signal name 1 5r m2 36 3b sa12 2 4p sas/sa0 37 2b sa15 3 4t sa3 38 3a sa13 4 6r sa1 39 3c sa11 5 5t sa2 40 2c sa16 6 7t zz 41 2a sa14 7 6p dqa8 42 2d dqc8 8 7p dqa7 43 1d dqc7 9 6n dqa6 44 2e dqc6 10 7n dqa5 45 1e dqc5 11 6m dqa4 46 2f dqc4 12 6l dqa2 47 2g dqc2 13 7l dqa3 48 1g dqc3 14 6k dqa0 49 2h dqc0 15 7k dqa1 50 1h dqc1 16 5l swea 51 3g swec 17 4l k 52 4d zq 18 4k k 53 4e ss 19 4f g 54 4g nc 20 5g sweb 55 4h nc 21 7h dqb1 56 4m swe 22 6h dqb0 57 3l swed 23 7g dqb3 58 1k dqd1 24 6g dqb2 59 2k dqd0 25 6f dqb4 60 1l dqd3 26 7e dqb5 61 2l dqd2 27 6e dqb6 62 2m dqd4 28 7d dqb7 63 1n dqd5 29 6d dqb8 64 2n dqd6 30 6a sa7 65 1p dqd7 31 6c sa8 66 2p dqd8 32 5c sa4 67 3t sa18 33 5a sa6 68 2r sa10 34 6b sa9 69 4n sa17 35 5b sa5 70 3r m1 notes: 1. bit#1 is the first scan bit to exit the chip. 2. bit#2 is sas in both the late select mode and the late write mode, or is sa0 in the register-latch mode. 3. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a ?place holder?. place holder registers are internally connected to v ss . 4. in boundary scan mode, differential input k and k are referenced to each other and must be at the opposite logic levels for the reliable operation. 5. zz must remain v il during boundary scan. 6. in boundary scan mode, zq must be driven to v ddq or v ss supply rail to ensure consistent results. 7. m1 and m2 must be driven to v dd , v ddq or v ss supply rail to ensure consistent results.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 28 of 29 id register part revision number (31:28) device density and configuration (27:18) vendor definition (17:12) vendor jedec code (11:1) start bit (0) hm64ylb36512 0000 0011100100 xxxxxx 00000000111 1 tap controller state diagram 1 111 0 0 00 00 0 0 0 1 11 11 0 1 11 1 10 10 0 0 0 0 1 test-logic- reset run-test/ idle select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select- ir-scan note: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck.
hm64ylb36512 series rev.3.00 jan 13, 2006 page 29 of 29 package dimensions hm64ylb36512bp series (prbg0119db-a / previous code: bp-119e) 2.02 1.80 mass[typ.] 1.1g bp-119e renesas code jeita package code previous code 0.20 0.35 y 1 w v 0.30 22.00 2.24 0.77 0.69 0.61 0.94 0.88 0.82 1.27 0.20 14.00 y x b a reference symbol dimension in millimeters min nom max a 1 e z e z d s e s d e d p-bga119-14x22-1.27 prbg0119db-a 1 1 a s s y v s y 1 234567 b c d e f g h j k l m n p r t u s b b a s a a a 0.15 () 18.04 11.08 e e 0.15 b m m 4 d e
revision history hm64ylb36512 series data sheet description rev. date page summary 0.0 may. 6, 2002 ? initial issue 0.1 aug. 30, 2002 5 18 truth table deletion of notes3 input capacitance addition of notes3 1.0 feb. 7, 2003 6 change of programmable impedance output drivers 2.00 jul. 19, 2005 ? ? 1 2 2 4 5 6 7 8 9 10 19-22 23 27 29 change format issued by renesas technology corp. the former HM64YLB36512BP-33 and the former hm64ylb36514bp-6h are integrated into the new HM64YLB36512BP-33 change of features, adding register-latch mode ordering information addition of modes addition of renesas package codes pin arrangement 4p: sas to sas/sa0 addition of note addition of block diagram in register-latch mode pin descriptions change of san, sas notes, adding register-latch mode addition of m1, m2 protocol in register-latch mode change of notes2, adding register-latch mode truth table: addition of dq (n), dq (n+1) in register-latch mode change of programmable impedance output drivers recommended dc operating conditions addition of the values in register-latch mode dc characteristics: addition of the values in register-latch mode ac characteristics: addition of the table in register-latch mode addition of timing waveforms in register-latch mode ac test conditions: addition of the values in register-latch mode boundary scan order bit#2: sas to sas/sa0 notes2-6 to notes3-7 addition of notes2 package dimensions addition of renesas package codes changed to renesas formats 3.00 jan. 13, 2006 9 dc characteristics: v oh to v oh1 , addition of v oh2
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