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| hys72t64000hr?[3/?/5]?a hys72t1280x0hr?[3/?/5]?a hys72t256xx0hr?[3/?/5]?a 240-pin registered ddr2 sdram modules ddr2 sdram rdimm sdram rohs compliant data sheet, rev. 1.30, mar. 2006 memory products cover page
edition 2006-03 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2006. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. imprint template: mp_a4_s_rev321 / 3 / 2005-10-05 hys72t64000hr?[3/?/5]?a , hys72t1280x0hr?[3/?/5]?a, hys72t256xx0hr?[3/?/5]?a revision history: 2006-03, rev. 1.30 previous version: 2005-08, rev. 1.20 page subjects (major cha nges since last revision) 7 added product types hys72t256040hr?[3s/3.7]?a 37 , 38 added i dd values for hys72t256040hr?[3s/3.7]?a 50 , 58 added spd codes for hys72t256040hr?[3s/3.7]?a 75 added package outline for hys72t256040hr?[3s/3.7]?a we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send us your proposal (including a reference to this document) to: techdoc.mp@infineon.com revision history data sheet 4 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin configuration and block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 speed grades definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.2 on die termination (odt) cu rrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6 product type nomenclature (ddr2 drams and dimms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table of contents data sheet 5 rev. 1.30, 2006-03 09122003-awkk-ztpq 240-pin registered ddr2 sdram modules ddr2 sdram hys72t64000hr?[3/?/5]?a hys72t1280x0hr?[3/?/5]?a hys72t256xx0hr?[3/?/5]?a 1overview this chapter gives an overview of the 240-pin regi stered ddr2 sdram modules product family and describes its main characteristics. 1.1 features ? 240-pin pc2-5300, pc2-4200 and pc2-3200 ddr2 sdram memory modules for pc, workstation and server main memory applications ? one rank 64m x 72, 128m x 72 ,and two ranks 128m 72, 256m 72, and four ranks 256m 72 module organization and 64m 4, 64m 8, 128m 4 chip organization ? 512 mbyte, 1 gbyte and 2 gbyte modules built with 512-mbit ddr2 sdrams in p-tfbga-60 chipsize packages. ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? all speed grades faster than ddr2-400 comply with ddr2?400 timing specifications. ? programmable cas latencies (3, 4 & 5), burst length (4 & 8) and burst type ? auto refresh (cbr) and self refresh ? all inputs and outputs sstl_18 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? rdimm dimensions (nominal): 30,00 mm high, 133.35 mm wide ? based on standard reference layouts raw card ?f?, ?g?, ?h?, ?j? and ?n? ? rohs compliant products 1) performance tables ? table 1 ?performance table for pc2?5300? on page 5 ? table 2 ?performance table for pc2?4200? on page 6 ? table 3 ?performance table for pc2-3200? on page 6 1) rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2 002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercury, lead, cadmiu m, hexavalent chromium, po lybrominated biphenyls and polybrominated biphenyl ethers. table 1 performance table for pc2?5300 product type speed code ?3 ?3s unit speed grade pc2?5300 4?4?4 pc2?5300 5?5?5 ? max. clock frequency @cl5 f ck5 333 333 mhz @cl4 f ck4 333 266 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 12 15 ns min. row precharge time t rp 12 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 57 60 ns hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules overviewfeatures data sheet 6 rev. 1.30, 2006-03 09122003-awkk-ztpq table 2 performance table for pc2?4200 product type speed code ?3.7 unit speed grade pc2?4200 4?4?4 ? max. clock frequency @cl5 f ck5 266 mhz @cl4 f ck4 266 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 45 ns min. row cycle time t rc 60 ns table 3 performance table for pc2-3200 product type speed code ?5 unit speed grade pc2-3200 3?3?3 ? max. clock frequency @cl5 f ck5 200 mhz @cl4 f ck4 200 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 40 ns min. row cycle time t rc 55 ns data sheet 7 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules overviewdescription 1.2 description the infineon hys72t[64/128/256]xx0hr?[3/3s/3.7 /5]?a module family are registered dimm modules ?rdimms? with 30,0 mm height based on ddr2 technology. dimms are ava ilable as ecc modules in 64m x 72 (512 mbyte), 128m x 72 (1 gbyte) and 256m x 72 (2 gbyte) or ganization and density, intended for mounting into 240-pin connector sockets. the memory array is designed with 512-mbit double-d ata-rate-two (ddr2) sync hronous drams. all control and address signals are re-driven on the dimm using regi ster devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed wit h configuration data and the second 128 bytes are available to the customer. table 4 ordering information for rohs compliant products product type 1) 1) all part numbers end with a place code, designating the silicon die revision. example: hys72t64000hr?5?a, indicating rev. ?a? dies are used for ddr2 sdram components. for a ll infineon ddr2 module and component nomenclature see chapter 6 of this data sheet. compliance code 2) 2) the compliance code is printed on the module label and describes the speed grade, for example ?pc2?4200r?444?11? f0?, where 4200r means registered dimm modules with 4.26 gb/sec module bandwidth and ?444-11? means column address strobe (cas) latency = 4, row co lumn delay (rcd) latency = 4 and row precharge (rp) latency = 4 using the latest jedec spd revision 1.1 and produced on the raw card ?f? description sdram technology pc2-5300 hys72t64000hr?3?a 512 mb 1r 8 pc2?5300r?444?12?f0 1 rank, ecc 512 mbit ( 8) hys72t128000hr?3?a 1 gb 1r 4 pc2?5300r?444?12?h0 1 rank, ecc 512 mbit ( 4) hys72t128020hr?3?a 1 gb 2r 8 pc2?5300r?444?12?g0 2 ranks, ecc 512 mbit ( 8) hys72t256220hr?3?a 2 gb 2r 4 pc2?5300r?444?12?j1 2 ranks, ecc 512 mbit ( 4) hys72t64000hr?3s?a 512 mb 1r 8 pc2?5300r?555?12?f0 1 rank, ecc 512 mbit ( 8) hys72t128000hr?3s?a 1 gb 1r 4 pc2?5300r?555?12?h0 1 rank, ecc 512 mbit ( 4) hys72t128020hr?3s?a 1 gb 2r 8 pc2?5300r?555?12?g0 2 ranks, ecc 512 mbit ( 8) hys72t256220hr?3s?a 2 gb 2r 4 pc2?5300r?555?12?j1 2 ranks, ecc 512 mbit ( 4) hys72t256040hr?3s?a 2 gb 2r 4 pc2?5300r?555?12?n0 2 ranks, ecc 512 mbit ( 8) pc2?4200 hys72t64000hr?3.7?a 512 mb 1r 8 pc2?4200r?444?12?f0 1 rank, ecc 512 mbit ( 8) hys72t128000hr?3.7?a 1 gb 1r 4 pc2?4200r?444?12?h0 1 rank, ecc 512 mbit ( 4) hys72t128020hr?3.7?a 1 gb 2r 4 pc2?4200r?444?12?g0 2 ranks, ecc 512 mbit ( 8) hys72t256220hr?3.7?a 2 gb 2r 4 pc2?4200r?444?12?j1 2 ranks, ecc 512 mbit ( 4) hys72t256040hr?3.7?a 2 gb 2r 4 pc2?4200r?444?12?n0 2 ranks, ecc 512 mbit ( 8) pc2-3200 hys72t64000hr?5?a 512 mb 1r 8 pc2?3200r?333?12?f0 1 rank, ecc 512 mbit ( 8) hys72t128000hr?5?a 1 gb 1r 4 pc2?3200r?333?12?h0 1 rank, ecc 512 mbit ( 4) hys72t128020hr?5?a 1 gb 2r 8 pc2?3200r?333?12?g0 2 ranks, ecc 512 mbit ( 8) hys72t256220hr?5?a 2 gb 2r 4 pc2?3200r?333?12?j1 2 ranks, ecc 512 mbit ( 4) hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules overviewdescription data sheet 8 rev. 1.30, 2006-03 09122003-awkk-ztpq table 5 address format dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/columns bits raw card 512 mb 64m 72 1 ecc 9 14/2/10 f 1gb 128m 72 1 ecc 18 14/2/11 g 1 gb 128m 72 2 ecc 18 14/2/10 h 2gb 256m 72 2 ecc 36 14/2/11 j 2gb 256m 72 4 ecc 36 14/2/11 n table 6 components on modules 1) 1) for a detailed description of all available functions of the dram components on these mo dules see the component data sheet. product type 2) 2) green product dram components 2) dram density dram organization hys72t64000hr hyb18t512800af 512 mbit 64m 8 hys72t128000hr hyb18t512400af 512 mbit 128m 4 hys72t128020hr hyb18t512800af 512 mbit 64m 8 hys72t256020hr hyb18t512400af 512 mbit 128m 4 hys72t256220hr hyb18t512400af 512 mbit 128m 4 hys72t256040hr hyb18t512800af 512 mbit 64m 8 data sheet 9 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams 2 pin configuration and block diagrams 2.1 pin configuration the pin configuration of the registered ddr2 sdram dimm is listed by function in table 7 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 8 and table 9 respectively. the pin numbering is depicted in figure 1 . table 7 pin configuration of rdimm pin or ball no. name pin type buffer type function clock signals 185 ck0 i sstl clock signal ck0, complementary clock signal ck0 the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and the falling edge of ck . a delay locked loop (dll) circuit is driven from the clock inputs and output timing fo r read operations is synchronized to the input clock. 186 ck0 isstl 52 cke0 i sstl clock enables 1:0 activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke0 initiates the power down mo de or the self refresh mode. note: 2-ranks module 171 cke1 i sstl nc nc ? not connected note: 1-rank module control signals 193 s0 isstl chip select rank 1:0 enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s0 ; rank 1 is selected by s1 . the input signals also disable all outputs (except cke and odt) of the register(s) on the dimm when both inputs are high. when s is high, all register outputs (except ck, odt and chip select) remain in the previous state. note: 2-ranks module 76 s1 isstl nc nc ? not connected note: 1-rank module 192 ras isstl row address strobe (ras), co lumn address strobe (cas), write enable (we) when sampled at the cross point of the rising edge of ck, and falling edge of ck , ras , cas and we define the operation to be executed by the sdram. 74 cas isstl 73 we isstl hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data sheet 10 rev. 1.30, 2006-03 09122003-awkk-ztpq 18 reset icmos register reset the reset pin is connected to the rst pin on the register and to the oe pin on the pll. when low, all register outputs will be driven low and the pll clocks to the drams and the register(s) will be set to low-level. the pl l will remain synchronized with the input clock. address signals 71 ba0 i sstl bank address bus 1:0 selects internal sdram memory bank 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc i sstl not connected less than 1gb ddr2 sdrams 188 a0 i sstl address bus 12:0, address signal 10/autoprecharge during a bank activate command cycle, defines the row address when sampled at the cro sspoint of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba[ 1 :0] defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba[ 1 :0] to control which bank(s) to precharge. if ap is high, all ban ks will be precharged regardless of the state of ba[ 1 :0] inputs. if ap is low, then ba[ 1 :0] are used to define which bank to precharge. 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl 70 a10 i sstl ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 note: modules based on 4, 8 nc nc ? not connected note: modules based on 16 174 a14 i sstl address signal 14 note: 2 gbit based module nc nc ? not connected note: 1 gbit based module or smaller table 7 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function data sheet 11 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data signals 3 dq0 i/o sstl data bus 63:0 data input/ output pins 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl 159 dq31 i/o sstl 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl table 7 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data sheet 12 rev. 1.30, 2006-03 09122003-awkk-ztpq 206 dq39 i/o sstl data bus 63:0 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl 98 dq48 i/o sstl 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl check bits 42 cb0 i/o sstl check bits 7:0 check bit input / output pins note: nc on non-ecc module 43 cb1 i/o sstl 48 cb2 i/o sstl 49 cb3 i/o sstl 161 cb4 i/o sstl 162 cb5 i/o sstl 167 cb6 i/o sstl 168 cb7 i/o sstl table 7 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function data sheet 13 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data strobe bus 7dqs0i/osstl data strobes 17:0 the data strobes, associated with one data byte, sourced with data transfers. in write mode, the da ta strobe is sourced by the controller and is centered in the data window. in read mode the data strobe is sourced by the ddr2 sdram and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crossp oint of respective dqs and dqs. if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to v ss through a 20 ohm to 10 kohm resistor and ddr2 sdram mode registers programmed appropriately. note: see block diagram for corresponding dq signals 6dqs0 i/o sstl 16 dqs1 i/o sstl 15 dqs1 i/o sstl 28 dqs2 i/o sstl 27 dqs2 i/o sstl 37 dqs3 i/o sstl 36 dqs3 i/o sstl 84 dqs4 i/o sstl 83 dqs4 i/o sstl 93 dqs5 i/o sstl 92 dqs5 i/o sstl 105 dqs6 i/o sstl 104 dqs6 i/o sstl 114 dqs7 i/o sstl 113 dqs7 i/o sstl 46 dqs8 i/o sstl 45 dqs8 i/o sstl 126 dqs9 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 135 dqs10 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 147 dqs11 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 156 dqs12 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 203 dqs13 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms table 7 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data sheet 14 rev. 1.30, 2006-03 09122003-awkk-ztpq 212 dqs14 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 224 dqs15 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 233 dqs16 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 165 dqs17 i/o sstl not connected note: 8 based dimms only nc nc ? not connected note: 4 based dimms 125 dqs9 i/o sstl data strobes 17:9 note: 4 based module 134 dqs10 i/o sstl 146 dqs11 i/o sstl 155 dqs12 i/o sstl 202 dqs13 i/o sstl 211 dqs14 i/o sstl 223 dqs15 i/o sstl 232 dqs16 i/o sstl 164 dqs17 i/o sstl 125 dm0 i sstl data masks 7:0 the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. note: 8 based module 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl table 7 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function data sheet 15 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams eeprom 120 scl i cmos serial bus clock this signal is used to clock data into and out of the spd eeprom. 119 sda i/o od serial bus data this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected from sda to v ddspd on the motherboard to act as a pull-up. 239 sa0 i cmos serial address select bus 2:0 these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range 240 sa1 i cmos 101 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage reference voltage for the sstl-18 inputs. 238 v ddspd pwr ? eeprom power supply serial eeprom positive power suppl y, wired to a separated power pin at the connector which suppor ts from 1.7 volt to 3.6 volt. 51, 56, 62, 72, 75, 78, 170, 175,, 181, 191, 194 v ddq pwr ? i/o driver power supply power and ground for the ddr sdram 53, 59, 64, 67, 69, 172, 178, 184,, 187, 189, 197 v dd pwr ? power supply power and ground for the ddr sdram 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 v ss gnd ? ground plane power and ground for the ddr sdram table 7 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data sheet 16 rev. 1.30, 2006-03 09122003-awkk-ztpq other pins 19, 55, 68, 102, 137, 138, 173, 220, 221 nc nc ? not connected pins not connected on infineon rdimm?s 195 odt0 i sstl on-die termination control 1:0 asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram mode register. note: 2-ranks module 77 odt1 i sstl nc nc ? note: 1-rank modules table 8 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 9 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nu not usable nc not connected table 7 pin configuration of rdimm (cont?d) pin or ball no. name pin type buffer type function data sheet 17 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams figure 1 pin configuration for rdimm (240 pins) - 0 0 4 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 2 % & $ 1 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 $ 1 3 6 3 3 . # 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 $ 1 6 3 3 $ 1 3 2 % 3 % 4 6 3 3 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 # " 6 3 3 $ 1 3 # " 6 3 3 # + % . # " ! 6 $ $ 1 ! ! 6 $ $ 1 6 $ $ 6 3 3 . # ! ! 0 6 $ $ 1 # ! 3 . # 3 6 $ $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 6 3 3 $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 3 # , 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $ 1 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 # " $ 1 3 6 3 3 # " 6 $ $ 1 6 $ $ . # ! 6 $ $ ! ! 6 3 3 6 $ $ 6 $ $ " ! 7 % 6 $ $ 1 . # / $ 4 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 $ 1 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 3 ! 6 3 3 $ 1 3 $ 1 6 3 3 $ 1 $ 1 3 6 3 3 $ 1 3 $ ! 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 . # 6 3 3 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 $ - $ 1 3 6 3 3 . # $ 1 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 # " $ - $ 1 3 6 3 3 # " 6 $ $ 1 6 $ $ . # ! ! 6 $ $ ! ! 6 $ $ # + ! " ! 2 ! 3 6 $ $ 1 . # ! 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 . # 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 6 $ $ 3 0 $ 3 ! 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $ 1 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 # " 6 3 3 . # $ 1 3 # " 6 3 3 . # # + % . # 6 $ $ 1 ! ! 6 $ $ 1 ! # + 6 $ $ 6 $ $ 6 $ $ 1 3 / $ 4 6 $ $ $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 $ 1 $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ - $ 1 3 6 3 3 $ 1 $ 1 6 3 3 . # $ 1 3 $ 1 6 3 3 3 ! & 2 / . 4 3 ) $ % " ! # + 3 ) $ % hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data sheet 18 rev. 1.30, 2006-03 09122003-awkk-ztpq 2.2 block diagram figure 2 block diagram raw card f rdimm (x72, 1 rank, x8) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. s0 connects to dcs and v dd connects to csr on the register. - 0 " 4 $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 # " # " # " # " # " # " # " # " $ 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + # + 2 % 3 % 4 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r 2 3 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 % ' ) 3 4 % 2 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 / $ 4 # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % / $ 4 0 # + 0 # + 2 % 3 % 4 data sheet 19 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams figure 3 block diagram raw card g rdimm (x72, 2 ranks, x8) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. rs0 and rs1 alternate between the back and front sides of the dimm. - 0 " 4 $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 # " # " # " # " # " # " # " # " $ $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 2 % ' ) 3 4 % 2 2 3 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 # + % 2 / $ 4 2 / $ 4 # 3 3 $ 2 ! - s $ $ # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % # + % / $ 4 / $ 4 0 # + 0 # + 2 % 3 % 4 2 3 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ 1 3 $ 1 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 3 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + # + 2 % 3 % 4 # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ # 3 $ 1 3 $ 1 3 $ - 2 $ 1 3 . 5 2 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data sheet 20 rev. 1.30, 2006-03 09122003-awkk-ztpq figure 4 block diagram raw card h rdimm (x72, 1 rank, x4) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. s0 connects to dcs of register1 and csr of register2. 3. csr of register1 and dcs of register2 connects to v dd . 4. reset , pck7 and pck7 connect to both registers. - 0 " 4 $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 # " # " # " # " 6 3 3 $ 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + # + 2 % 3 % 4 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r 2 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 % ' ) 3 4 % 2 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 / $ 4 # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % / $ 4 0 # + 0 # + 2 % 3 % 4 # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - $ 1 3 $ 1 3 # " # " # " # " 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 6 3 3 # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - $ $ $ # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - # 3 $ 1 3 $ 1 3 ) / ) / ) / ) / $ - $ $ $ $ $ $ 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 data sheet 21 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams figure 5 block diagram raw card l rdimm (x72, 2ranks, x4) note: 1. unless otherwise noted, resistors are 22 ? 5% 2. rs0 and rs1 alternate between the bottom and surface sides of the dimm. 3. s0 connects to dcs and s1 connects to csr on a pair of registers. s1 connects to dcs and s0 connects to csr on another pair of registers. 4. reset , pck7 and pck7 connect to all registers. - 0 " 4 2 3 6 3 3 2 3 $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 # " # " # " # " $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ $ $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 # " # " # " # " 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r # + # + 2 % 3 % 4 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 % ' ) 3 4 % 2 2 3 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 # + % 2 / $ 4 2 / $ 4 # 3 3 $ 2 ! - s $ $ # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % # + % / $ 4 / $ 4 0 # + 0 # + 2 % 3 % 4 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams data sheet 22 rev. 1.30, 2006-03 09122003-awkk-ztpq figure 6 block diagram raw card j rdimm (x72, 2ranks, x4) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. rs0 and rs1 alternate between the bottom and surface sides of the dimm. 3. s0 connects to dcs and s1 connects to csr on a pair of registers. s1 connects to dcs and s0 connects to csr on another pair of registers. 4. reset , pck7 and pck7 connect to all registers. - 0 " 4 2 3 6 3 3 2 3 $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 # " # " # " # " $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ 1 3 $ 1 3 $ - # 3 ) / ) / ) / ) / $ $ $ $ $ $ $ $ $ $ $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ $ $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 3 $ 1 3 # " # " # " # " 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r # + # + 2 % 3 % 4 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 % ' ) 3 4 % 2 2 3 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 # + % 2 / $ 4 2 / $ 4 # 3 3 $ 2 ! - s $ $ # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % # + % / $ 4 / $ 4 0 # + 0 # + 2 % 3 % 4 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ data sheet 23 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules pin configuration and block diagrams figure 7 block diagram raw card n rdimm (x72, 4ranks, x8) notes 1. unless otherwise noted, resistors are 22 ? 5% 2. s0 and s2 connects to dcs0 , s1 and s3 to dcs1 on a register a. s1 and s3 connects to dcs and s0 and s2 connects to csr on another pair of register. 3. s2 and s3 have required pull up resistors (100k ?), not indicated here. 4. a13-an have optional pull down resistors (100k ? ), not indicated here. 5. reset, pck7 and pck7 connect to all registers. other signals connect to two of four registers. - 0 " 4 0 , , / % 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + 0 # + # + 3 $ 2 ! - s $ $ # + 3 $ 2 ! - s $ $ # + 2 e g i s t e r # + 2 e g i s t e r # + # + 2 % 3 % 4 3 # , 3 $ ! 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 $ ! ! ! ! 7 0 2 % ' ) 3 4 % 2 2 3 2 3 2 " ! 2 " ! n 2 ! 2 ! n 2 2 ! 3 2 # ! 3 2 7 % 2 # + % 2 # + % 2 / $ 4 2 / $ 4 # 3 3 $ 2 ! - s $ $ 2 3 # 3 3 $ 2 ! - s $ $ # 3 3 $ 2 ! - s $ $ 2 3 # 3 3 $ 2 ! - s $ $ " ! " ! n 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ / $ 4 3 $ 2 ! - s $ $ 3 3 " ! " ! n ! ! n 2 ! 3 # ! 3 7 % # + % # + % / $ 4 / $ 4 0 # + 0 # + 2 % 3 % 4 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 2 e g i s t e r ! # # 0 ! 2 ? ) . 0 0 / 1 % 2 2 2 e g i s t e r " # # 0 ! 2 ? ) . 0 0 / 1 % 2 2 2 e g i s t e r ! # # 0 ! 2 ? ) . 0 0 / 1 % 2 2 2 e g i s t e r ! # # 0 ! 2 ? ) . 0 0 / 1 % 2 2 6 3 3 6 $ $ 6 3 3 6 $ $ 6 $ $ 6 $ $ 6 $ $ 6 $ $ % r r ? / u t 6 3 3 0 ! 2 ? ) . $ $ $ $ $ 1 3 $ 1 3 $ 1 $ - $ $ $ $ $ $ 1 3 $ 1 3 # " $ - $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - # 3 $ 1 3 $ 1 3 ) / $ - $ 1 3 $ 1 3 $ 1 $ - $ 1 3 $ 1 3 $ 1 $ - $ 1 3 $ 1 3 $ 1 $ - $ 1 3 $ 1 3 $ 1 $ - $ 1 3 $ 1 3 $ 1 $ - $ 1 3 $ 1 3 $ 1 $ - $ 1 3 $ 1 3 $ 1 $ - 2 3 2 3 2 3 2 3 hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 24 rev. 1.30, 2006-03 09122003-awkk-ztpq 3 electrical characteristics 3.1 absolute maximum ratings caution is needed not to exceed abolute maxi mum ratings of the dram device listed in table 10 at any time. 3.2 dc operating conditions table 10 absolute maximum ratings symbol parameter rating unit notes v dd voltage on v dd pin relative to v ss ?1.0 to +2.3 v 1)2) 1) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional o peration of the device at these or any ot her conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 to +2.3 v 2)3) v ddl voltage on v ddl pin relative to v ss ?0.5 to +2.3 v 2)3) v in , v out voltage on any pin relative to v ss ?0.5 to +2.3 v 2) t stg storage temperature ?55 to +100 c 2)3) 3) storage temperature is the case surface te mperature on the center/top side of the dram. table 11 dram component operating temperature range symbol parameter rating unit notes t oper operating temperature 0 to 95 c 1)2)3) 1) operating temperature is the case surface tem perature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dram specification will be supported. during operation, the dram case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) self-refresh period is hard-coded in th e chip and therefore it is imperative t hat the system ensures the dram is below 85 c case temperature before in itiating self-refresh operation. table 12 operating conditions parameter symbol values unit notes min. max. dimm module operating temperature range (ambient) t opr 0+55 c dram component case temperature range t case 0+95 c 1)2)3)4) 1) dram component case temperature is the surface temperat ure in the center on the to p side of any of the drams. 2) within the dram component case temperature range all dram specificat ion will be supported. 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. 4) self-refresh period is hard-coded in the drams and therefore it is imperative that the syst em ensures the dram is below 85 c case temperature before in itiating self-refresh operation. storage temperature t stg ?50 +100 c barometric pressure (operating & storage) pbar +69 +105 kpa 5) 5) up to 3000 m operating humidity (relative) h opr 10 90 % data sheet 25 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics 3.3 ac characteristics 3.3.1 speed grades definitions table 13 supply voltage levels and dc operating conditions parameter symbol values unit notes min. typ. max. device supply voltage v dd 1.7 1.8 1.9 v output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih(dc) v ref +0.125 ? v ddq +0.3 v dc input logic low v il (dc ) ? 0.30 ? v ref ?0.125 v in / output leakage current i l ? 5 ? 5 a 3) 3) input voltage for any connec tor pin under test of 0 v v in v ddq + 0.3 v; all other pins at 0 v. current is per pin table 14 speed grade definition speed bins for ddr2?667 speed grade ddr2?667c ddr2?667d unit notes ifx sort name ?3 ?3s cas-rcd-rp latencies 4?4?4 5?5?5 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) only. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the cross point when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 383.758ns 1)2)3)4) @ cl = 5 t ck 3838ns 1)2)3)4) row active time t ras 45 70000 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 57 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12 ? 15 ? ns 1)2)3)4) row precharge time t rp 12 ? 15 ? ns 1)2)3)4) hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 26 rev. 1.30, 2006-03 09122003-awkk-ztpq table 15 speed grade definition speed bins for ddr2?533c speed grade ddr2?533c unit note ifx sort name ?3.7 cas-rcd-rp latencies 4?4?4 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) only. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the cross point when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 3.75 8 ns 1)2)3)4) row active time t ras 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4) table 16 speed grade definition speed bins for ddr2?400b speed grade ddr2?400b unit note ifx sort name ?5 cas-rcd-rp latencies 3?3?3 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) only. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the cross point when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 58 ns 1)2)3)4) @ cl = 5 t ck 58 ns 1)2)3)4) row active time t ras 40 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 55 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4) data sheet 27 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics 3.3.2 ac timing parameters table 17 timing parameter by speed grade - ddr2?667 parameter symbol ddr2?667 unit notes 1)2)3)4)5) 6)7) min. max. dq output access time from ck / ck t ac ?450 + 450 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?ns dq and dm input hold time (differential data strobe) t dh (base) 175 ?? ps dq and dm input hold time (single ended data strobe) t dh1 (base) ?? ? ps dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?400 +400 ps dqs input low (high) pu lse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dq s & associated dq signals) t dqsq ?240ps write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup ti me (differential data strobe) t ds (base) 100 ? ps dq and dm input setup time (single ended data strobe) t ds1 (base) ?? ? ps dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) data-out high-impedance time from ck / ck t hz ? t ac.max ps address and control input hold time t ih (base) 275 ? ps address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 200 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 28 rev. 1.30, 2006-03 09122003-awkk-ztpq data output hold time from dqs t qh t hpq ? t qhs ? data hold skew factor t qhs ?340ps average periodic refresh interval t refi ?7.8 s 8) ?3.9 s 9) auto-refresh to ac tive/auto-refresh command period t rfc 105 ? ns precharge-all (4 banks) command period t rp t rp ?ns read preamble t rpre 0.9 1.1 t ck read postamble t rpst 0.40 0.60 t ck active bank a to active bank b command period t rrd 7.5 ? ns 10 ? ns internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.35 x t ck ? t ck write postamble t wpst 0.40 0.60 t ck write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck t ck internal write to read command delay t wtr 7.5 ? ns exit power down to any valid command (other than nop or deselect) t xard 2? t ck exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? t ck exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) for details and notes see the relevant infineon component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 4)5)6)7) 3) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) 0 c t case 85 c 9) 85 c < t case 95 c table 17 timing parameter by speed grade - ddr2?667 (cont?d) parameter symbol ddr2?667 unit notes 1)2)3)4)5) 6)7) min. max. data sheet 29 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics table 18 timing parameter by speed grade - ddr2-533 parameter symbol ddr2?533 unit notes 1)2)3)4) 5)6)7) min. max. dq output access time from ck / ck t ac ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge wr ite recovery + precharge time t dal wr + t rp ? t ck minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns dq and dm input hold time (differential data strobe) t dh (base) 225 ?? ps dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setu p time (differential data strobe) t ds (base) 100 ? ps dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) data-out high-impedance time from ck / ck t hz ? t ac.max ps address and control input hold time t ih (base) 375 ? ps address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 250 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ? hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 30 rev. 1.30, 2006-03 09122003-awkk-ztpq data hold skew factor t qhs ? 400 ps average periodic refresh interval t refi ?7.8 s 8) ?3.9 s 9) auto-refresh to ac tive/auto-refresh command period t rfc 105 ? ns precharge-all (4 banks) command period t rp t rp ?ns read preamble t rpre 0.9 1.1 t ck read postamble t rpst 0.40 0.60 t ck active bank a to active bank b command period t rrd 7.5 ? ns 10 ? ns internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 x t ck ? t ck write postamble t wpst 0.40 0.60 t ck write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck t ck internal write to read command delay t wtr 7.5 ? ns exit power down to any valid command (other than nop or deselect) t xard 2? t ck exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) for details and notes see the relevant infineon component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 4)5)6)7) 3) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) 0 c t case 85 c 9) 85 c < t case 95 c table 18 timing parameter by speed grade - ddr2-533 (cont?d) parameter symbol ddr2?533 unit notes 1)2)3)4) 5)6)7) min. max. data sheet 31 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics table 19 timing parameter by speed grade - ddr2-400 parameter symbol ddr2?400 unit notes 1)2)3)4) 5)6)7) min. max. dq output access time from ck / ck t ac ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge wr ite recovery + precharge time t dal wr + t rp ? t ck minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns dq and dm input hold time (differential data strobe) t dh (base) 275 ?? ps dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 350 ps write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setu p time (differential data strobe) t ds (base) 150 ? ps dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) data-out high-impedance time from ck / ck t hz ? t ac.max ps address and control input hold time t ih (base) 475 ? ps address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 350 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ? hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 32 rev. 1.30, 2006-03 09122003-awkk-ztpq data hold skew factor t qhs ? 450 ps average periodic refresh interval t refi ?7.8 s 8) ?3.9 s 9) auto-refresh to ac tive/auto-refresh command period t rfc 105 ? ns precharge-all (4 banks) command period t rp t rp ?ns read preamble t rpre 0.9 1.1 t ck read postamble t rpst 0.40 0.60 t ck active bank a to active bank b command period t rrd 7.5 ? ns 10 ? ns internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 x t ck ? t ck write postamble t wpst 0.40 0.60 t ck write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck t ck internal write to read command delay t wtr 10 ? ns exit power down to any valid command (other than nop or deselect) t xard 2? t ck exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) for details and notes see the relevant infineon component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 4)5)6)7) 3) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential st robe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs/dqs , rdqs/rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) 0 c t case 85 c 9) 85 c < t case 95 c table 19 timing parameter by speed grade - ddr2-400 parameter symbol ddr2?400 unit notes 1)2)3)4) 5)6)7) min. max. data sheet 33 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics 3.3.3 odt ac electri cal characteristics table 20 odt ac characteristics and operating conditions for ddr2-667 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max +0.7ns ns 1) 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max +1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max +0.6ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mo de entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck table 21 odt ac characteristics and operating conditions for ddr2-533 and ddr2-400 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mo de entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 34 rev. 1.30, 2006-03 09122003-awkk-ztpq 3.4 i dd specifications and conditions table 22 i dd measurement conditions 1)2)3)4)5)6)7)8) parameter symbol operating current 0 one bank active - precharge; t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , t rcd = t rcd.min , al = 0, cl = cl .min ; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 precharge standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are switching, data bus in puts are switching i dd2n precharge power-down current other control and address inputs are stable, data bus in puts are floating . i dd2p precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are stable, data bus inputs are floating. i dd2q active power-down current all banks open; t ck = t ck.min , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to low (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ck.min , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power-down exit); i dd3p(1) active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.max ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w burst refresh current t ck = t ck.min ., refresh command every t rfc = t rfc.min interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ck.min , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d data sheet 35 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are fl oating. reset is low. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) idd specifications are tested after the device is properly initialized and idd pa rameter are specified with odt disabled. 3) definitions for i dd see table 23 4) i dd1 , i dd4r and i dd7 current measurements are defined with the outputs disabled ( i out = 0 ma). to achieve this on module level the output buffers can be disabl ed using an emrs(1) (extended mode register command) by setting a12 bit to high. 5) for two rank modules: for all active current measur ements the other rank is in precharge power-down mode i dd2p 6) reset signal is high fo r all currents, except for i dd6 (self refresh) 7) all current measurements includes register and pll current consumption 8) for details and notes see the relevant infineon component data sheet table 23 definitions for i dd parameter description low v in v il(ac).max , high is defined as v in v ih(ac).min stable inputs are stable at a high or low level floating inputs are v ref = v ddq /2 switching inputs are changing between high and low every other clock (once per 2 cycles) for address and control signals, and inputs changing between high and low every othe r data transfer (once per cycle) for dq signals no t including mask or strobes. table 22 i dd measurement conditions (cont?d) 1)2)3)4)5)6)7)8) parameter symbol hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 36 rev. 1.30, 2006-03 09122003-awkk-ztpq i dd specifications ? table 24 ? i dd specification for hys72t[64/128/256]xxxhr?3?a? on page 36 ? table 25 ? i dd specification for hys2t[64/128/256]xxxhr?3s?a? on page 37 ? table 26 ? i dd specification for hys72t[64/128/256]xxxhr?3.7?a? on page 38 ? table 27 ? i dd specification for hys72t[64/128/256]xxxhr?5?a? on page 39 table 24 i dd specification for hys72t[64/128/256]xxxhr?3?a product type hys72t64000hr?3?a hys72t128000hr?3?a hys72t128020hr?3?a hys72t256220hr?3?a units notes 1) 1) module i dd is calculated on the basis of component i dd and includes currents of registers and pll. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 512 mb 1 gb 1 gb 2 gb 72 72 72 72 1 rank 1 rank 2 ranks 2 ranks ?3 ?3 ?3 ?3 i dd0 1060 1950 1110 2040 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 1200 2220 1240 2310 ma 2) i dd2p 430 685 480 780 ma 3) 3) both ranks are in the same i dd current mode i dd2n 840 1500 1290 2400 ma 3) i dd2q 750 1320 1110 2040 ma 3) i dd3p_0 (fast) 560 940 730 1280 ma 3) i dd3p_1 (slow) 440 700 490 810 ma 3) i dd3n 840 1500 1290 2400 ma 3) i dd4r 1560 2940 1600 3030 ma 2) i dd4w 1650 3120 1690 3210 ma 2) i dd5b 1650 3120 1690 3210 ma 2) i dd5d 440 700 490 810 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c i dd6 45 90 90 180 ma 3)4) i dd7 1780 3390 1830 3480 ma 2) data sheet 37 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics table 25 i dd specification for hys2t[64/128/256]xxxhr?3s?a product type hys72t64000hr?3s?a hys72t128000hr?3s?a hys72t128020hr?3s?a hys72t256220hr?3s?a hys72t256040hr?3s?a units notes 1) 1) module i dd is calculated on the basis of component i dd and includes currents of registers and pll. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 512 mb 1 gb 1 gb 2 gb 2 gb 72 72 72 72 72 1 rank 1 rank 2 ranks 2 ranks 4 ranks ?3s ?3s ?3s ?3s ?3s i dd0 1020 1870 1070 1960 1160 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 1150 2130 1200 2220 1290 ma 2) i dd2p 430 685 480 780 570 ma 3) 3) both ranks are in the same i dd current mode i dd2n 840 1500 1290 2400 2190 ma 3) i dd2q 750 1320 1110 2040 1830 ma 3) i dd3p_0 (fast) 560 940 730 1280 1070 ma 3) i dd3p_1 (slow) 440 700 490 810 600 ma 3) i dd3n 840 1500 1290 2400 2190 ma 3) i dd4r 1560 2940 1600 3030 1690 ma 2) i dd4w 1650 3120 1690 3210 1780 ma 2) i dd5b 1650 3120 1690 3210 1780 ma 2) i dd5d 440 700 490 810 600 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c i dd6 45 90 90 180 180 ma 3)4) i dd7 1710 3240 1750 3330 1840 ma 2) hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 38 rev. 1.30, 2006-03 09122003-awkk-ztpq table 26 i dd specification for hys72t[64/128/256]xxxhr?3.7?a product type hys72t64000hr?3.7?a hys72t128000hr?3.7?a hys72t128020hr?3.7?a hys72t256220hr?3.7?a hys72t256040hr?3.7?a units notes 1) 1) module i dd is calculated on the basis of component i dd and includes currents of registers and pll. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 512 mb 1 gb 1 gb 2 gb 2 gb 72 72 72 72 72 1 rank 1 rank 2 ranks 2 ranks 4 ranks ?3.7 ?3.7 ?3.7 ?3.7 ?3.7 i dd0 920 1670 950 1740 1020 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 1010 1850 1040 1920 1110 ma 2) i dd2p 370 572 400 640 470 ma 3) 3) both ranks are in the same i dd current mode i dd2n 690 1220 1050 1940 1770 ma 3) i dd2q 600 1040 870 1580 1410 ma 3) i dd3p_0 (fast) 470 790 620 1080 910 ma 3) i dd3p_1 (slow) 380 590 420 680 510 ma 3) i dd3n 690 1220 1050 1940 1770 ma 3) i dd4r 1140 2120 1180 2190 1250 ma 2) i dd4w 1190 2210 1220 2280 1290 ma 2) i dd5b 1500 2840 1540 2910 1610 ma 2) i dd5d 380 610 440 720 550 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c i dd6 36 72 72 144 144 ma 3)4) i dd7 1590 3030 1630 3100 1700 ma 2) data sheet 39 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics table 27 i dd specification for hys72t[64/128/256]xxxhr?5?a product type hys72t64000hr?5?a hys72t128000hr?5?a hys72t128020hr?5?a hys72t256220hr?5?a units notes 1) 1) module i dd is calculated on the basis of component i dd and includes currents of registers and pll. odt disabled. i dd1, i dd4r, and i dd7, are defined with the outputs disabled. organization 512 mb 1 gb 1 gb 2 gb 72 72 72 72 1 rank 1 rank 2 ranks 2 ranks ?5 ?5 ?5 ?5 i dd0 770 1400 810 1470 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 820 1490 850 1560 ma 2) i dd2p 310 477 350 550 ma 3) 3) both ranks are in the same i dd current mode i dd2n 560 980 850 1560 ma 3) i dd2q 500 860 730 1310 ma 3) i dd3p_0 (fast) 390 640 510 870 ma 3) i dd3p_1 (slow) 320 500 370 590 ma 3) i dd3n 590 1040 910 1670 ma 3) i dd4r 910 1670 940 1740 ma 2) i dd4w 950 1760 990 1830 ma 2) i dd5b 1360 2570 1390 2640 ma 2) i dd5d 330 510 380 620 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c i dd6 36 72 72 144 ma 3)4) i dd7 1450 2750 1480 2820 ma 2) hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics data sheet 40 rev. 1.30, 2006-03 09122003-awkk-ztpq 3.4.1 i dd test conditions for testing the i dd parameters, the following timing parameters are used: table 28 i dd measurement test conditions for ddr2?667 parameter symbol ?3 ?3s unit ddr2?667c ddr2?667d cas latency cl (idd) 45 t ck clock cycle time t ck(idd) 33.75ns active to read or write delay t rcd(idd) 12 15 ns active to active / auto -refresh command period t rc(idd) 57 60 ns active bank a to active bank b command delay 8 1) 1) 4 & 8 (1 kb page size) t rrd(idd) 7.5 7.5 ns 16 2) 2) 16 (2 kb page size), not on 256m components t rrd(idd) 10 10 ns active to precharge command t ras.min(idd) 45 45 ns t ras.max(idd) 70000 70000 ns precharge command period t rp(idd) 12 15 ns auto-refresh to active / auto-refresh command period t rfc(idd) 105 105 ns average periodic refresh interval t refi 7.8 7.8 s table 29 i dd measurement test condition s for ddr2?400 and ddr2?533 parameter symbol ?3.7 ?5 unit ddr2?533c ddr2?400b cas latency c l (idd) 43 t ck clock cycle time t ck(idd) 3.75 5 ns active to read or write delay t rcd(idd) 15 15 ns active to active / auto -refresh command period t rc(idd) 60 55 ns active bank a to active bank b command delay 8 1) 1) 4 & 8 (1 kb page size) t rrd(idd) 7.5 7.5 ns 16 2) 2) 16 (2 kb page size), not on 256m components t rrd(idd) 10 10 ns active to precharge command t ras.min(idd) 45 40 ns t ras.max(idd) 70000 70000 ns precharge command period t rp(idd) 15 15 ns auto-refresh to active / auto-refresh command period t rfc(idd) 105 105 ns average periodic refresh interval t refi 7.8 7.8 s data sheet 41 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules electrical characteristics 3.4.2 on die termina tion (odt) current the odt function adds addi tional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a[6,2] in the emrs(1) a ?weak? or ?strong? termination can be selected. the current consumption for any terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a odt is enabled during a given period of time. table 30 odt current per terminated pin parameter symbol min. typ. m ax. unit emrs(1) state enabled odt current per dq odt is high; data bus inputs are floating i odto 5 6 7.5 ma/dq a6 = 0, a2 = 1 2.5 3 3.75 ma/dq a6 = 1, a2 = 0 7.5 9 11.25 ma/dq a6 = 1, a2 = 1 active odt current per dq odt is high; worst case of data bus inputs are stable or switching. i odtt 10 12 15 ma/dq a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 15 18 22.5 ma/dq a6 = 1, a2 = 0 hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 42 rev. 1.2, 2005-08 09122003-awkk-ztpq 4spdcodes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect . all values with xx in the table are module specific byte s which are defined during production. list of spd code tables ? table 31 ?spd codes for hys64t[64/128/256]xx0hr?3?a? on page 42 ? table 32 ?spd codes for hys72t[64/128]0x0hr?3s?a? on page 46 ? table 33 ?spd codes for hys72t256xx0hr?3s?a? on page 50 ? table 34 ?spd codes for hys72t[64/128]0x0hr?3.7?a? on page 54 ? table 35 ?spd codes for hys 72t256xx0hr?3.7?a? on page 58 ? table 36 ?spd codes for hys72t[64/128]0x0hr?5?a? on page 62 ? table 37 ?spd codes for hys72t256xx0hr?5?a? on page 66 table 31 spd codes for hys64t[64/128/256]xx0hr?3?a product type hys72t64000hr?3?a hys72t128000hr?3?a hys72t128020hr?3?a hys72t256220hr?3?a organization 512mb 1gb 1gb 2gb 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2?5300r? 444 pc2?5300r? 444 pc2?5300r? 444 pc2?5300r? 444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd byte s in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 4 number of column addresses 0a 0b 0a 0b 5 dimm rank and stacking information 60 60 61 61 6 data width 48 48 48 48 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 45 11 error correction support (non-ecc, ecc) 02 02 02 02 12 refresh rate and type 82 82 82 82 13 primary sdram width 08 04 08 04 data sheet 43 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 14 error checking sdram width 08 04 08 04 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 01 01 01 01 21 dimm attributes 04 05 05 07 22 component attributes 03 03 03 03 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 30 24 t ac sdram @ cl max -1 [ns] 45 45 45 45 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 30 30 30 30 28 t rrd.min [ns] 1e 1e 1e 1e 29 t rcd.min [ns] 30 30 30 30 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 80 01 80 01 32 t as.min and t cs.min [ns] 20 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 27 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 17 17 17 17 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 39 39 39 39 table 31 spd codes for hys64t[64/128/256]xx0hr?3?a (cont?d) product type hys72t64000hr?3?a hys72t128000hr?3?a hys72t128020hr?3?a hys72t256220hr?3?a organization 512mb 1gb 1gb 2gb 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2?5300r? 444 pc2?5300r? 444 pc2?5300r? 444 pc2?5300r? 444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 44 rev. 1.2, 2005-08 09122003-awkk-ztpq 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 18 18 18 18 45 t qhs.max [ns] 22 22 22 22 46 pll relock time 0f 0f 0f 0f 47 t case.max delta / ? t 4r4w delta53535353 48 psi(t-a) dram 78 78 78 78 49 ? t 0 (dt0) 4f4f4f4f 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 2e 2e 2e 2e 51 ? t 2p (dt2p) 26 26 26 26 52 ? t 3n (dt3n) 26 26 26 26 53 ? t 3p.fast (dt3p fast) 2b2b2b2b 54 ? t 3p.slow (dt3p slow) 1b1b1b1b 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 4a 4a 4a 4a 56 ? t 5b (dt5b) 20 20 20 20 57 ? t 7 (dt7) 23232323 58psi(ca) pll c4c4c4c4 59 psi(ca) reg 8c 8c 8c 8c 60 ? t pll (dtpll) 68686868 61 ? t reg (dtreg) / toggle rate 94 94 94 94 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 15 90 17 93 64 jedec id code of infineon (1) c1 c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 00 66 jedec id code of infineon (3) 00 00 00 00 67 jedec id code of infineon (4) 00 00 00 00 68 jedec id code of infineon (5) 00 00 00 00 table 31 spd codes for hys64t[64/128/256]xx0hr?3?a (cont?d) product type hys72t64000hr?3?a hys72t128000hr?3?a hys72t128020hr?3?a hys72t256220hr?3?a organization 512mb 1gb 1gb 2gb 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2?5300r? 444 pc2?5300r? 444 pc2?5300r? 444 pc2?5300r? 444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex data sheet 45 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 69 jedec id code of infineon (6) 00 00 00 00 70 jedec id code of infineon (7) 00 00 00 00 71 jedec id code of infineon (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 37 37 37 37 74 product type, char 2 32 32 32 32 75 product type, char 3 54 54 54 54 76 product type, char 4 36 31 31 32 77 product type, char 5 34 32 32 35 78 product type, char 6 30 38 38 36 79 product type, char 7 30 30 30 32 80 product type, char 8 30 30 32 32 81 product type, char 9 48 30 30 30 82 product type, char 10 52 48 48 48 83 product type, char 11 33 52 52 52 84 product type, char 12 41 33 33 33 85 product type, char 13 20 41 41 41 86 product type, char 14 20 20 20 20 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 8x 7x 7x 1x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 table 31 spd codes for hys64t[64/128/256]xx0hr?3?a (cont?d) product type hys72t64000hr?3?a hys72t128000hr?3?a hys72t128020hr?3?a hys72t256220hr?3?a organization 512mb 1gb 1gb 2gb 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc2?5300r? 444 pc2?5300r? 444 pc2?5300r? 444 pc2?5300r? 444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 46 rev. 1.2, 2005-08 09122003-awkk-ztpq table 32 spd codes for hys72t[64/128]0x0hr?3s?a product type hys72t64000hr?3s?a hys72t128000hr?3s?a hys72t128020hr?3s?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r? 555 pc2?5300r? 555 pc2?5300r? 555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0e 0e 0e 4 number of column addresses 0a 0b 0a 5 dimm rank and stacking information 60 60 61 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 08 04 08 14 error checking sdram width 08 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 01 01 01 20 dimm type information 01 01 01 21 dimm attributes 04 05 05 22 component attributes 03 03 03 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 data sheet 47 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 80 01 80 32 t as.min and t cs.min [ns] 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 17 17 17 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 18 18 18 45 t qhs.max [ns] 22 22 22 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 53 53 53 48 psi(t-a) dram 78 78 78 49 ? t 0 (dt0) 4b4b4b 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 2e 2e 2e 51 ? t 2p (dt2p) 26 26 26 52 ? t 3n (dt3n) 26 26 26 53 ? t 3p.fast (dt3p fast) 2b2b2b table 32 spd codes for hys72t[64/128]0x0hr?3s?a product type hys72t64000hr?3s?a hys72t128000hr?3s?a hys72t128020hr?3s?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r? 555 pc2?5300r? 555 pc2?5300r? 555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 48 rev. 1.2, 2005-08 09122003-awkk-ztpq 54 ? t 3p.slow (dt3p slow) 1b1b1b 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 4a 4a 4a 56 ? t 5b (dt5b) 20 20 20 57 ? t 7 (dt7) 222222 58 psi(ca) pll c4 c4 c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 68 68 68 61 ? t reg (dtreg) / toggle rate 94 94 94 62 spd revision 12 12 12 63 checksum of bytes 0-62 43 be 45 64 jedec id code of infineon (1) c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 66 jedec id code of infineon (3) 00 00 00 67 jedec id code of infineon (4) 00 00 00 68 jedec id code of infineon (5) 00 00 00 69 jedec id code of infineon (6) 00 00 00 70 jedec id code of infineon (7) 00 00 00 71 jedec id code of infineon (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 36 31 31 77 product type, char 5 34 32 32 78 product type, char 6 30 38 38 79 product type, char 7 30 30 30 80 product type, char 8 30 30 32 table 32 spd codes for hys72t[64/128]0x0hr?3s?a product type hys72t64000hr?3s?a hys72t128000hr?3s?a hys72t128020hr?3s?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r? 555 pc2?5300r? 555 pc2?5300r? 555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex data sheet 49 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 81 product type, char 9 48 30 30 82 product type, char 10 52 48 48 83 product type, char 11 33 52 52 84 product type, char 12 53 33 33 85 product type, char 13 41 53 53 86 product type, char 14 20 41 41 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 1x 1x 1x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 table 32 spd codes for hys72t[64/128]0x0hr?3s?a product type hys72t64000hr?3s?a hys72t128000hr?3s?a hys72t128020hr?3s?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r? 555 pc2?5300r? 555 pc2?5300r? 555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 50 rev. 1.2, 2005-08 09122003-awkk-ztpq table 33 spd codes for hys72t256xx0hr?3s?a product type hys72t256020hr?3s?a hys72t256220hr?3s?a hys72t256040hr?3s?a organization 2gb 2gb 2 gbyte 72 72 72 2 ranks ( 4) 2 ranks ( 4) 4 ranks ( 8) label code pc2?5300r? 555 pc2?5300r? 555 pc2?5300r? 555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0e 0e 0e 4 number of column addresses 0b 0b 0a 5 dimm rank and stacking information 61 61 63 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 04 04 08 14 error checking sdram width 04 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 01 01 01 20 dimm type information 01 01 01 21 dimm attributes 07 07 07 22 component attributes 03 03 03 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 data sheet 51 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 01 01 80 32 t as.min and t cs.min [ns] 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 17 17 17 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 18 18 18 45 t qhs.max [ns] 22 22 22 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 53 53 53 48 psi(t-a) dram 78 78 78 49 ? t 0 (dt0) 4b4b4b 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 2e 2e 2e 51 ? t 2p (dt2p) 26 26 26 52 ? t 3n (dt3n) 26 26 26 53 ? t 3p.fast (dt3p fast) 2b2b2b table 33 spd codes for hys72t256xx0hr?3s?a product type hys72t256020hr?3s?a hys72t256220hr?3s?a hys72t256040hr?3s?a organization 2gb 2gb 2 gbyte 72 72 72 2 ranks ( 4) 2 ranks ( 4) 4 ranks ( 8) label code pc2?5300r? 555 pc2?5300r? 555 pc2?5300r? 555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 52 rev. 1.2, 2005-08 09122003-awkk-ztpq 54 ? t 3p.slow (dt3p slow) 1b1b1b 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 4a 4a 4a 56 ? t 5b (dt5b) 20 20 20 57 ? t 7 (dt7) 222222 58 psi(ca) pll c4 c4 c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 68 68 68 61 ? t reg (dtreg) / toggle rate 94 94 94 62 spd revision 12 12 12 63 checksum of bytes 0-62 c1 c1 49 64 jedec id code of infineon (1) c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 66 jedec id code of infineon (3) 00 00 00 67 jedec id code of infineon (4) 00 00 00 68 jedec id code of infineon (5) 00 00 00 69 jedec id code of infineon (6) 00 00 00 70 jedec id code of infineon (7) 00 00 00 71 jedec id code of infineon (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 32 32 32 77 product type, char 5 35 35 35 78 product type, char 6 36 36 36 79 product type, char 7 30 32 30 80 product type, char 8 32 32 34 table 33 spd codes for hys72t256xx0hr?3s?a product type hys72t256020hr?3s?a hys72t256220hr?3s?a hys72t256040hr?3s?a organization 2gb 2gb 2 gbyte 72 72 72 2 ranks ( 4) 2 ranks ( 4) 4 ranks ( 8) label code pc2?5300r? 555 pc2?5300r? 555 pc2?5300r? 555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex data sheet 53 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 81 product type, char 9 30 30 30 82 product type, char 10 48 48 48 83 product type, char 11 52 52 52 84 product type, char 12 33 33 33 85 product type, char 13 53 53 53 86 product type, char 14 41 41 41 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 1x 1x 0x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 table 33 spd codes for hys72t256xx0hr?3s?a product type hys72t256020hr?3s?a hys72t256220hr?3s?a hys72t256040hr?3s?a organization 2gb 2gb 2 gbyte 72 72 72 2 ranks ( 4) 2 ranks ( 4) 4 ranks ( 8) label code pc2?5300r? 555 pc2?5300r? 555 pc2?5300r? 555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 54 rev. 1.2, 2005-08 09122003-awkk-ztpq table 34 spd codes for hys72t[64/128]0x0hr?3.7?a product type hys72t64000hr?3.7?a hys72t128000hr?3.7?a hys72t128020hr?3.7?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?4200r? 444 pc2?4200r? 444 pc2?4200r? 444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0e 0e 0e 4 number of column addresses 0a 0b 0a 5 dimm rank and stacking information 60 60 61 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 08 04 08 14 error checking sdram width 08 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 00 00 00 20 dimm type information 01 01 01 21 dimm attributes 04 05 05 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 data sheet 55 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 80 01 80 32 t as.min and t cs.min [ns] 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 22 22 22 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 45 t qhs.max [ns] 28 28 28 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 51 51 51 48 psi(t-a) dram 78 78 78 49 ? t 0 (dt0) 3f3f3f 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 22 22 22 51 ? t 2p (dt2p) 1e 1e 1e 52 ? t 3n (dt3n) 1e 1e 1e table 34 spd codes for hys72t[64/128]0x0hr?3.7?a (cont?d) product type hys72t64000hr?3.7?a hys72t128000hr?3.7?a hys72t128020hr?3.7?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?4200r? 444 pc2?4200r? 444 pc2?4200r? 444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 56 rev. 1.2, 2005-08 09122003-awkk-ztpq 53 ? t 3p.fast (dt3p fast) 242424 54 ? t 3p.slow (dt3p slow) 171717 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 34 34 34 56 ? t 5b (dt5b) 1e 1e 1e 57 ? t 7 (dt7) 202020 58 psi(ca) pll c4 c4 c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 61 61 61 61 ? t reg (dtreg) / toggle rate 78 78 78 62 spd revision 11 11 11 63 checksum of bytes 0-62 11 8c 13 64 jedec id code of infineon (1) c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 66 jedec id code of infineon (3) 00 00 00 67 jedec id code of infineon (4) 00 00 00 68 jedec id code of infineon (5) 00 00 00 69 jedec id code of infineon (6) 00 00 00 70 jedec id code of infineon (7) 00 00 00 71 jedec id code of infineon (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 36 31 31 77 product type, char 5 34 32 32 78 product type, char 6 30 38 38 79 product type, char 7 30 30 30 table 34 spd codes for hys72t[64/128]0x0hr?3.7?a (cont?d) product type hys72t64000hr?3.7?a hys72t128000hr?3.7?a hys72t128020hr?3.7?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?4200r? 444 pc2?4200r? 444 pc2?4200r? 444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex data sheet 57 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 80 product type, char 8 30 30 32 81 product type, char 9 48 30 30 82 product type, char 10 52 48 48 83 product type, char 11 33 52 52 84 product type, char 12 2e 33 33 85 product type, char 13 37 2e 2e 86 product type, char 14 41 37 37 87 product type, char 15 20 41 41 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 3x 3x 3x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 table 34 spd codes for hys72t[64/128]0x0hr?3.7?a (cont?d) product type hys72t64000hr?3.7?a hys72t128000hr?3.7?a hys72t128020hr?3.7?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?4200r? 444 pc2?4200r? 444 pc2?4200r? 444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 58 rev. 1.2, 2005-08 09122003-awkk-ztpq table 35 spd codes for hys72t256xx0hr?3.7?a product type hys72t256020hr?3.7?a hys72t256220hr?3.7?a hys72t256040hr?3.7?a organization 2gb 2gb 2 gbyte 72 72 72 2 ranks ( 4) 2 ranks ( 4) 4 ranks ( 8) label code pc2?4200r? 444 pc2?4200r? 444 pc2?4200r? 444 jedec spd revision rev. 1.1 rev. 1.2 rev. 1.2 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0e 0e 0e 4 number of column addresses 0b 0b 0a 5 dimm rank and stacking information 61 61 63 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 04 04 08 14 error checking sdram width 04 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 00 01 01 20 dimm type information 01 01 01 21 dimm attributes 07 07 07 22 component attributes 01 03 03 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 data sheet 59 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 01 01 80 32 t as.min and t cs.min [ns] 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 22 22 22 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 45 t qhs.max [ns] 28 28 28 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 51 51 51 48 psi(t-a) dram 78 78 78 49 ? t 0 (dt0) 3f3f3f 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 22 22 22 51 ? t 2p (dt2p) 1e 1e 1e 52 ? t 3n (dt3n) 1e 1e 1e table 35 spd codes for hys72t256xx0hr?3.7?a (cont?d) product type hys72t256020hr?3.7?a hys72t256220hr?3.7?a hys72t256040hr?3.7?a organization 2gb 2gb 2 gbyte 72 72 72 2 ranks ( 4) 2 ranks ( 4) 4 ranks ( 8) label code pc2?4200r? 444 pc2?4200r? 444 pc2?4200r? 444 jedec spd revision rev. 1.1 rev. 1.2 rev. 1.2 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 60 rev. 1.2, 2005-08 09122003-awkk-ztpq 53 ? t 3p.fast (dt3p fast) 242424 54 ? t 3p.slow (dt3p slow) 171717 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 34 34 34 56 ? t 5b (dt5b) 1e 1e 1e 57 ? t 7 (dt7) 202020 58 psi(ca) pll c4 c4 c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 61 61 61 61 ? t reg (dtreg) / toggle rate 78 78 78 62 spd revision 11 12 12 63 checksum of bytes 0-62 8f 93 1b 64 jedec id code of infineon (1) c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 66 jedec id code of infineon (3) 00 00 00 67 jedec id code of infineon (4) 00 00 00 68 jedec id code of infineon (5) 00 00 00 69 jedec id code of infineon (6) 00 00 00 70 jedec id code of infineon (7) 00 00 00 71 jedec id code of infineon (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 32 32 32 77 product type, char 5 35 35 35 78 product type, char 6 36 36 36 79 product type, char 7 30 32 30 table 35 spd codes for hys72t256xx0hr?3.7?a (cont?d) product type hys72t256020hr?3.7?a hys72t256220hr?3.7?a hys72t256040hr?3.7?a organization 2gb 2gb 2 gbyte 72 72 72 2 ranks ( 4) 2 ranks ( 4) 4 ranks ( 8) label code pc2?4200r? 444 pc2?4200r? 444 pc2?4200r? 444 jedec spd revision rev. 1.1 rev. 1.2 rev. 1.2 byte# description hex hex hex data sheet 61 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 80 product type, char 8 32 32 34 81 product type, char 9 30 30 30 82 product type, char 10 48 48 48 83 product type, char 11 52 52 52 84 product type, char 12 33 33 33 85 product type, char 13 2e 2e 2e 86 product type, char 14 37 37 37 87 product type, char 15 41 41 41 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 3x 1x 0x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 table 35 spd codes for hys72t256xx0hr?3.7?a (cont?d) product type hys72t256020hr?3.7?a hys72t256220hr?3.7?a hys72t256040hr?3.7?a organization 2gb 2gb 2 gbyte 72 72 72 2 ranks ( 4) 2 ranks ( 4) 4 ranks ( 8) label code pc2?4200r? 444 pc2?4200r? 444 pc2?4200r? 444 jedec spd revision rev. 1.1 rev. 1.2 rev. 1.2 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 62 rev. 1.2, 2005-08 09122003-awkk-ztpq table 36 spd codes for hys72t[64/128]0x0hr?5?a product type hys72t64000hr?5?a hys72t128000hr?5?a hys72t128020hr?5?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?3200r? 333 pc2?3200r? 333 pc2?3200r? 333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0e 0e 0e 4 number of column addresses 0a 0b 0a 5 dimm rank and stacking information 60 60 61 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 60 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 08 04 08 14 error checking sdram width 08 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 00 00 00 20 dimm type information 01 01 01 21 dimm attributes 04 05 05 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 data sheet 63 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 28 28 28 31 module density per rank 80 01 80 32 t as.min and t cs.min [ns] 35 35 35 33 t ah.min and t ch.min [ns] 47 47 47 34 t ds.min [ns] 15 15 15 35 t dh.min [ns] 27 27 27 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 28 28 28 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 37 37 37 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 23 23 23 45 t qhs.max [ns] 2d 2d 2d 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 51 51 51 48 psi(t-a) dram 78 78 78 49 ? t 0 (dt0) 333333 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 1d 1d 1d 51 ? t 2p (dt2p) 1e 1e 1e 52 ? t 3n (dt3n) 1b 1b 1b 53 ? t 3p.fast (dt3p fast) 1e1e1e 54 ? t 3p.slow (dt3p slow) 171717 table 36 spd codes for hys72t[64/128]0x0hr?5?a (cont?d) product type hys72t64000hr?5?a hys72t128000hr?5?a hys72t128020hr?5?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?3200r? 333 pc2?3200r? 333 pc2?3200r? 333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 64 rev. 1.2, 2005-08 09122003-awkk-ztpq 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 28 28 28 56 ? t 5b (dt5b) 1b 1b 1b 57 ? t 7 (dt7) 1e1e1e 58 psi(ca) pll c4 c4 c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 59 59 59 61 ? t reg (dtreg) / toggle rate 5c 5c 5c 62 spd revision 11 11 11 63 checksum of bytes 0-62 3c b7 3e 64 jedec id code of infineon (1) c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 66 jedec id code of infineon (3) 00 00 00 67 jedec id code of infineon (4) 00 00 00 68 jedec id code of infineon (5) 00 00 00 69 jedec id code of infineon (6) 00 00 00 70 jedec id code of infineon (7) 00 00 00 71 jedec id code of infineon (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 36 31 31 77 product type, char 5 34 32 32 78 product type, char 6 30 38 38 79 product type, char 7 30 30 30 80 product type, char 8 30 30 32 81 product type, char 9 48 30 30 82 product type, char 10 52 48 48 table 36 spd codes for hys72t[64/128]0x0hr?5?a (cont?d) product type hys72t64000hr?5?a hys72t128000hr?5?a hys72t128020hr?5?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?3200r? 333 pc2?3200r? 333 pc2?3200r? 333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex data sheet 65 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 83 product type, char 11 35 52 52 84 product type, char 12 41 35 35 85 product type, char 13 20 41 41 86 product type, char 14 20 20 20 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 3x 3x 3x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 table 36 spd codes for hys72t[64/128]0x0hr?5?a (cont?d) product type hys72t64000hr?5?a hys72t128000hr?5?a hys72t128020hr?5?a organization 512mb 1gb 1gb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?3200r? 333 pc2?3200r? 333 pc2?3200r? 333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 66 rev. 1.2, 2005-08 09122003-awkk-ztpq table 37 spd codes for hys72t256xx0hr?5?a product type hys72t256020hr?5?a hys72t256220hr?5?a organization 2gb 2gb 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?3200r?333 pc2?3200r?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex 0 programmed spd bytes in eeprom 80 80 1 total number of bytes in eeprom 08 08 2 memory type (ddr2) 08 08 3 number of row addresses 0e 0e 4 number of column addresses 0b 0b 5 dimm rank and stacking information 61 61 6 data width 48 48 7 not used 00 00 8 interface voltage level 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 11 error correction support (non-ecc, ecc) 02 02 12 refresh rate and type 82 82 13 primary sdram width 04 04 14 error checking sdram width 04 04 15 not used 00 00 16 burst length supported 0c 0c 17 number of banks on sdram device 04 04 18 supported cas latencies 38 38 19 dimm mechanical characteristics 00 00 20 dimm type information 01 01 21 dimm attributes 07 07 22 component attributes 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 27 t rp.min [ns] 3c 3c data sheet 67 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 28 t rrd.min [ns] 1e 1e 29 t rcd.min [ns] 3c 3c 30 t ras.min [ns] 28 28 31 module density per rank 01 01 32 t as.min and t cs.min [ns] 35 35 33 t ah.min and t ch.min [ns] 47 47 34 t ds.min [ns] 15 15 35 t dh.min [ns] 27 27 36 t wr.min [ns] 3c 3c 37 t wtr.min [ns] 28 28 38 t rtp.min [ns] 1e 1e 39 analysis characteristics 00 00 40 t rc and t rfc extension 00 00 41 t rc.min [ns] 37 37 42 t rfc.min [ns] 69 69 43 t ck.max [ns] 80 80 44 t dqsq.max [ns] 23 23 45 t qhs.max [ns] 2d 2d 46 pll relock time 0f 0f 47 t case.max delta / ? t 4r4w delta 51 51 48 psi(t-a) dram 78 78 49 ? t 0 (dt0) 33 33 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 1d 1d 51 ? t 2p (dt2p) 1e 1e 52 ? t 3n (dt3n) 1b 1b 53 ? t 3p.fast (dt3p fast) 1e 1e 54 ? t 3p.slow (dt3p slow) 17 17 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 28 28 table 37 spd codes for hys72t256xx0hr?5?a (cont?d) product type hys72t256020hr?5?a hys72t256220hr?5?a organization 2gb 2gb 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?3200r?333 pc2?3200r?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes data sheet 68 rev. 1.2, 2005-08 09122003-awkk-ztpq 56 ? t 5b (dt5b) 1b 1b 57 ? t 7 (dt7) 1e 1e 58 psi(ca) pll c4 c4 59 psi(ca) reg 8c 8c 60 ? t pll (dtpll) 59 59 61 ? t reg (dtreg) / toggle rate 5c 5c 62 spd revision 11 11 63 checksum of bytes 0-62 ba ba 64 jedec id code of infineon (1) c1 c1 65 jedec id code of infineon (2) 00 00 66 jedec id code of infineon (3) 00 00 67 jedec id code of infineon (4) 00 00 68 jedec id code of infineon (5) 00 00 69 jedec id code of infineon (6) 00 00 70 jedec id code of infineon (7) 00 00 71 jedec id code of infineon (8) 00 00 72 module manufacturer location xx xx 73 product type, char 1 37 37 74 product type, char 2 32 32 75 product type, char 3 54 54 76 product type, char 4 32 32 77 product type, char 5 35 35 78 product type, char 6 36 36 79 product type, char 7 30 32 80 product type, char 8 32 32 81 product type, char 9 30 30 82 product type, char 10 48 48 83 product type, char 11 52 52 table 37 spd codes for hys72t256xx0hr?5?a (cont?d) product type hys72t256020hr?5?a hys72t256220hr?5?a organization 2gb 2gb 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?3200r?333 pc2?3200r?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex data sheet 69 rev. 1.2, 2005-08 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules spd codes 84 product type, char 12 35 35 85 product type, char 13 41 41 86 product type, char 14 20 20 87 product type, char 15 20 20 88 product type, char 16 20 20 89 product type, char 17 20 20 90 product type, char 18 20 20 91 module revision code 3x 3x 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 - 98 module serial number xx xx 99 - 127 not used 00 00 table 37 spd codes for hys72t256xx0hr?5?a (cont?d) product type hys72t256020hr?5?a hys72t256220hr?5?a organization 2gb 2gb 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?3200r?333 pc2?3200r?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules package outlines data sheet 70 rev. 1.30, 2006-03 09122003-awkk-ztpq 5 package outlines figure 8 package outline raw card f l-dim-240-11 ' , $ " # ! # ? - ! 8 " ? " u r r m a x a l l o w e d ? ! " # $ e t a i l o f c o n t a c t s ? ! ? x data sheet 71 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules package outlines figure 9 package outline raw card g l-dim-240-12 ' , $ " # ! # ? - ! 8 " ? " u r r m a x a l l o w e d ? ! " # $ e t a i l o f c o n t a c t s ? ! ? x hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules package outlines data sheet 72 rev. 1.30, 2006-03 09122003-awkk-ztpq figure 10 package outline raw card h l-dim-240-13 ' , $ " # ! # ? - ! 8 " ? " u r r m a x a l l o w e d ? ! " # $ e t a i l o f c o n t a c t s ? ! ? x data sheet 73 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules package outlines figure 11 package outline raw card j l-dim-240-20 ' , $ " # ! # ? - ! 8 " ? - ) . " u r r m a x a l l o w e d ? ! " # $ e t a i l o f c o n t a c t s ? ! ? x hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules package outlines data sheet 74 rev. 1.30, 2006-03 09122003-awkk-ztpq figure 12 package outline raw card l l-dim-240-40 ? $ e t a i l o f c o n t a c t s " u r r m a x a l l o w e d - ) . ? ? " ! # x ! # " ! ? ' , $ " # ? - ! 8 data sheet 75 rev. 1.30, 2006-03 09122003-awkk-ztpq hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules package outlines figure 13 package outline raw card n l-dim-240-44 * / ' & % $ ? % 0 $ ; & ? ? $ ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ? [ hys72t[64/128/256]xx0h r?[3/3s/3.7/5]?a registered ddr2 sdram modules product type nomenclature (ddr2 drams and dimms) data sheet 76 rev. 1.30, 2006-03 09122003-awkk-ztpq 6 product type nomenclature (ddr2 drams and dimms) infineon?s nomenclature uses simple coding combined with some propriatory coding. table 38 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 39 and for components in table 40 . table 38 nomenclature fields and examples example for field number 1234567891011 micro-dimm hys64t64020km?5?a ddr2 dram hyb 18 t 512 16 0 a c ?5 table 39 ddr2 dimm nomenclature field description values coding 1infineon modul prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type s s o-dimm m m icro-dimm r r egistered u u nbuffered f f ully buffered 10 speed grade ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the overall module memory density in mbytes as listed in column ?coding?. table 40 ddr2 dram nomenclature field description values coding 1 infineon component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status cfbga, lead-containing f fbga, lead-free 10 speed grade ?2.5 ddr2-800 6-6-6 ?3 ddr2-667 4-4-4 ?3s ddr2-667 5-5-5 ?3.7 ddr2-533 4-4-4 ?5 ddr2-400 3-3-3 published by infineon technologies ag www.infineon.com |
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