512k x 8 sram msm8512 - 020/025/35 issue 1.0 : january 1999 pin definition description the msm8512 is a 4mbit monolithic sram organised as 512k x 8 with access times from 20ns to 35ns available. the device is available in two 32 pin ceramic surface mount packages. the device has a low power standby version which supports data retention mode and is directly ttl compatible. all versions can be screened in accordance with mil- std-883c. block diagram pin functions a0~a18 address inputs d0~7 data input/output cs chip select oe output enable we write enable v cc power (+5v) gnd ground 524,288 x 8 cmos static ram features ? fast access times of 020/025/35 ns ? high density packages. ? operating power 950 mw (nom) ? standby power 75 mw (nom) -l version ? low voltage data retention. ? completely static operation ? directly ttl compatible ? may be processed in accordance with mil-std-883c package details pin count descripion package type 32 jlcc package j 32 lcc package w x address buffer row decoder d0 d7 we oe cs column i/o column decoder y address buffer i/o buffer 4,194,304 bit memory array a10 a11 a12 a13 a14 a15 a16 a17 a18 a9 a4 a8 a2 a3 a1 a0 a5 a6 a7 j / w d1 d2 d4 gn d d3 d5 d6 a12 a14 vcc a16 a18 a15 a17 14 15 18 16 17 19 20 4 3 32 2 1 31 30 d 0 a 0 a 3 a1 a2 a4 a5 a 6 a 7 d7 cs a11 a10 oe a9 a8 a13 we 21 22 25 23 24 26 27 28 29 13 12 9 11 10 8 7 6 5 11403 west bernado court, suite 100, san diego, ca 92127. tel no: (619) 674 2233, fax no: (619) 674 2230
issue 1.0 : january 1999 msm8512 - 020/025/30 2 absolute maximum ratings (1) voltage on any pin relative to v ss (2) v t -0.5 to +7.0 v power dissipation p t 1w storage temperature t stg -55 to +150 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc operating conditions recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - 6.0 v input low voltage v il -0.3 - 0.8 v operating temperature t a 0-70 o c t ai -40 - 85 o c (i suffix) t am -55 - 125 o c (m, mb suffix) dc electrical characteristics (v cc = 5.0v10%, t a =-55c to +125c) parameter symbol test condition min typ max unit input leakage current i li v in =0v to v cc -2 - 2 a output leakage current i lo cs=v ih , v i/o =0v to v cc , oe=v ih or we=v il -2 - 2 a operating supply current i cc1 cs=v il , v in =v ih or v il i i/o =0ma, min cycle, duty=100% - - 185 ma standby supply current i sb min cycle, cs=v ih - - 65 ma -l version only i sb1 cs 3 3 3 3 3 v cc -0.2v, v in 3 3 3 3 3 v cc -0.2v or 0.2v 3 3 3 3 3 v in f=0mhz - -15ma output voltage v ol i ol =8.0ma - - 0.4 v v oh i oh =-4.0ma 2.4 - - v capacitance (v cc =5v10%,t a =25c) parameter symbol test condition typ max unit input capacitance: c in v in = 0v - 8 pf i/o capacitance: c i/o v i/o = 0v - 8 pf note : this parameter is sampled and not 100% tested. ac test conditions output load * input pulse levels : 0v to 3.0v * input rise and fall times : 3ns * input and output timing reference levels: 1.5v * output load: see load diagram * v cc =5v10% 166w 30pf i/o pin 1.76v
msm8512 - 020/025/35 issue 1.0 : january 1999 3 low v cc data retention characteristics - l version only (t a =-55c to +125 o c) parameter symbol test condition min typ max unit v cc for data retention v dr cs 3 3 3 3 3 v cc -0.2v 2.0 - 5.5 v data retention current i ccdr v cc =3.0v, cs 3 3 3 3 3 v cc -0.2v, --8ma chip deselect to data retention t cdr see retention waveform 0- -ns operation recovery time t r see retention waveform 5- -ms ac operating conditions read cycle 20 25 35 parameter symbol min max min max min max units read cycle time t rc 20 - 25 - 35 - ns address access time t aa -20 -25 -35 ns chip select access time t acs -20 -25 -35 ns output enable to output valid t oe -10 -15 -15 ns output hold from address change t oh 5- 5- 5- ns chip selection to output in low z t clz 5- 5- 5- ns output enable to output in low z t olz 0- 0- 0- ns chip deselection to output in high z (3) t chz -10 010 010 ns output disable to output in high z (3) t ohz 010 010 010 ns write cycle 20 25 35 parameter symbol min max min max min max unit write cycle time t wc 20 - 25 - 35 - ns chip selection to end of write t cw 15 - 15 - 15 - ns address valid to end of write t aw 15 - 15 - 15 - ns address setup time t as 0- 0- 0- ns write pulse width t wp 15 - 15 - 15 - ns write recovery time t wr 0- 0- 0- ns write to output in high z t whz 010 010 010 ns data to write time overlap t dw 10 - 10 - 10 - ns data hold from write time t dh 0- 0- 0- ns output active from end of write t ow 5- 5- 5- ns
issue 1.0 : january 1999 msm8512 - 020/025/30 4 notes: (1) during the read cycle, we is high. (2) address valid prior to or coincident with cs transition low. (3) t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. read cycle timing waveform (1,2) write cycle no.1 timing waveform t t t t rc aa oe oh address oe cs t ohz(3) t olz t acs t clz t chz(3) data valid d0~7 high-z t as(3) t aw t cw(4) t wc address oe cs t wp(1) t ohz(3,9) we d0~7 out t t dw dh d0~7 in (6) t wr (2) t ow high-z high-z
msm8512 - 020/025/35 issue 1.0 : january 1999 5 write cycle no.2 timing waveform (5) cs t wr(2) t cw (4) (6) t aw t wc address t t t wp(1) dw t dh we d0~7 out d0~7 in whz(3,9) t as(3) t ow t oh (7) (8) high-z high-z ac characteristics notes (1) a write occurs during the overlap (t wp ) of a low cs and a low we. (2) t wr is measured from the earlier of cs or we going high to the end of write cycle. (3) during this period, i/o pins are in the output state. input signals out of phase must not be applied. (4) if the cs low transition occurs simultaneously with the we low transition or after the we low transition, outputs remain in a high impedance state. (5) oe is continuously low. (oe=v il ) (6) d out is in the same phase as written data of this write cycle. (7) d out is the read data of next address. (8) if cs is low during this period, i/o pins are in the output state. input signals out of phase must not be applied. (9) t whz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. low v cc data retention timing waveform t r t cdr 4.5v 2.2v 4.5v 2.2v 0v data retention mode vcc cs v dr cs>vcc-0.2v
issue 1.0 : january 1999 msm8512 - 020/025/30 6 package details 32 pin j leaded chip carrier - 'j' package all dimensions in mm (inches). all dimensions in mm (inches). 32 pad leadless chip carrier (lcc) - 'w' package 1.90 (0.075) no. 1 index 1.27 (0.050) typ 0.71 (0.028) typ 4.32 (0.170) 13.45 (0.530) 0.43 (0.017) typ 3.80 (0.150) 10.41 (0.410) 7.87 (0.310) 1.65 (0.065) 11.70 (0.460) 11.30 (0.445) 14.22 (0.560) 13.84 (0.545) 9.91 (0.390) 7.37 (0.290) 13.95 (0.510) 14.22 (0.560) 13.84 (0.545) no. 1 index 11.70 (0.460) 11.30 (0.445) 2.03 (0.080) max 1.27 (0.050) typ 0.64 (0.025) typ 1.27 (0.050) typ 7.87 (0.310) 7.37 (0.290) 10.42 (0.410) 9.92 (0.390) note : minimum order product - consult factory for details
msm8512 - 020/025/35 issue 1.0 : january 1999 7 visual and mechanical internal visual 2010 condition b or manufacturers equivalent 100% temperature cycle 1010 condition c (10 cycles,-65 c to +150 c) 100% constant acceleration 2001 condition e (y, only) (30,000g) 100% pre-burn-in electrical per applicable device specifications at t a =+25 c 100% burn-in method 1015,condition d,t a =+125 c,160hrs min 100% final electrical tests per applicable device specification static (dc) a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% functional a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% switching (ac) a) @ t a =+25 c and power supply extremes 100% b) @ temperature and power supply extremes 100% percent defective allowable (pda) calculated at post-burn-in at t a =+25 c 5% hermeticity 1014 fine condition a 100% gross condition c 100% external visual 2009 per vendor or customer specification 100% screen test method level mb component screening flow military screening procedure screening flow for high reliability product in accordance with mil-std-883 method 5004 is shown below.
issue 1.0 : january 1999 msm8512 - 020/025/30 8 ordering information msm8512jlmb - 020 speed 020 = 25ns 025 = 25ns 35 = 35ns temp. range/screening blank = commercial i = industrial m = military mb = screened in accordance with mil-std-883 power consumption blank = standard power l = low power package j = 32 pin jlcc w = 32 pin lcc memory organisation 8512 = 512k x 8 sram note : although this data is believed to be accurate, the information contained herein, is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director.
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