1/10 july 2001 n high speed: t pd =6.4ns (typ.) at v cc = 3.3v n 5v tolerant inputs n power-down protection on inputs n input voltage level: v il = 0.8v, v ih = 2v at v cc =3v n low power dissipation: i cc = 4 m a (max.) at t a =25c n low noise: v olp = 0.3v (typ.) at v cc =3.3v n symmetrical output impedance: |i oh | = i ol = 4 ma (min) at v cc = 3v n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 3.6v (1.2v data retention) n pin and function compatible with 74 series 573 n improved latch-up immunity description the 74lvx573 is a low voltage cmos octal d-type latch with 3 state output non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power, battery operated and low noise 3.3v applications. this 8 bit d-type latch is controlled by a latch enable input (le) and an output enable input (oe ). while the le input is held at a high level, the q outputs will follow the data input precisely. when the le is taken low, the q outputs will be latched precisely at the logic level of d input data. while the (oe ) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v. it combines high speed performance with the true cmos low power consumption. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lvx573 low voltage cmos octal d-type latch (3-state non inv.) with 5v tolerant inputs pin connection and iec logic symbols order codes package tube t & r sop 74lvx573m 74lvx573mtr tssop 74lvx573ttr tssop sop
74lvx573 2/10 input equivalent circuit pin description truth table x : dont care z : high impedance * : q outputs are latched at the time when the le input is taken low logic level logic diagram this logic diagram has not be used to estimate propagation delays pin no symbol name and function 1oe 3 state output enable input (active low) 2, 3, 4, 5, 6, 7, 8, 9 d0 to d7 data inputs 12, 13, 14, 15, 16, 17, 18, 19 q0 to q7 3-state latch outputs 11 le latch enable input 10 gnd ground (0v) 20 v cc positive supply voltage inputs output oe le d q hxxz l l x no change* lhll lhhh
74lvx573 3/10 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied recommended operating conditions 1) truth table guaranteed: 1.2v to 3.6v 2) v in from 0.8v to 2.0v dc specifications symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current - 20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2 to 3.6 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 2) (v cc = 3v) 0 to 100 ns/v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 2.0 2.0 2.0 3.6 2.4 2.4 2.4 v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 0.8 0.8 0.8 3.6 0.8 0.8 0.8 v oh high level output voltage 2.0 i o =-50 m a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 m a 2.9 3.0 2.9 2.9 3.0 i o =-4 ma 2.58 2.48 2.4 v ol low level output voltage 2.0 i o =50 m a 0.0 0.1 0.1 0.1 v 3.0 i o =50 m a 0.0 0.1 0.1 0.1 3.0 i o =4 ma 0.36 0.44 0.55 i oz high impedance output leakage current 3.6 v i = v ih or v il v o = v cc or gnd 0.25 2.5 2.5 m a i i input leakage current 3.6 v i = 5v or gnd 0.1 1 1 m a i cc quiescent supply current 3.6 v i = v cc or gnd 44040 m a
74lvx573 4/10 dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.3v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.3v. inputs under test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. ac electrical characteristics (input t r = t f = 3ns) 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low 2) parameter guaranteed by design (*) voltage range is 3.3v 0.3v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 3.3 c l = 50 pf 0.3 0.8 v v olv -0.8 -0.3 v ihd dynamic high voltage input (note 1, 3) 3.3 2.0 v ild dynamic low voltage input (note 1, 3) 3.3 0.8 symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time le to q 2.7 15 8.2 15.6 1.0 18.5 1.0 18.5 ns 2.7 50 10.7 19.1 1.0 22.0 1.0 22.0 3.3 (*) 15 6.4 10.1 1.0 12.0 1.0 12.0 3.3 (*) 50 8.9 13.6 1.0 15.5 1.0 15.5 t plh t phl propagation delay time d to q 2.7 15 7.6 14.5 1.0 17.5 1.0 17.5 ns 2.7 50 10.1 18.0 1.0 21.0 1.0 21.0 3.3 (*) 15 5.9 9.3 1.0 11.0 1.0 11.0 3.3 (*) 50 8.4 12.8 1.0 14.5 1.0 14.5 t pzl t pzh output enable time 2.7 15 7.8 15.0 1.0 18.5 1.0 18.5 ns 2.7 50 10.3 18.5 1.0 22.0 1.0 22.0 3.3 (*) 15 6.1 9.7 1.0 12.0 1.0 12.0 3.3 (*) 50 8.6 13.2 1.0 15.5 1.0 15.5 t plz t phz output disable time 2.7 50 12.1 19.1 1.0 22.0 1.0 22.0 ns 3.3 (*) 50 10.1 13.6 1.0 15.5 1.0 15.5 t w le pulse width, high 2.7 50 6.5 7.5 7.5 ns 3.3 (*) 50 5.0 5.0 5.0 t s setup time d to le high or low 2.7 50 5.0 5.0 5.0 ns 3.3 (*) 50 3.5 3.5 3.5 t h hold time d to le high or low 2.7 50 1.5 1.5 1.5 ns 3.3 (*) 50 1.5 1.5 1.5 t oslh t oshl output to output skew time (note 1,2) 2.7 50 0.5 1.0 1.5 1.5 ns 3.3 (*) 50 0.5 1.0 1.5 1.5
74lvx573 5/10 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /8 (per circuit) test circuit c l =15/50pf or equivalent (includes jig and probe capacitance) r l = r1 = 1k w or equivalent r t = z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 3.3 4101010pf c out output capacitance 3.3 6 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz 29 pf test switch t plh , t phl open t pzl , t plz v cc t pzh , t phz gnd
74lvx573 6/10 waveform 1 : le to qn propagation delays, le minimun pulse width, dn to le setup and hold times (f=1mhz; 50% duty cycle) waveform 2 : output enable and disable times (f=1mhz; 50% duty cycle)
74lvx573 7/10 waveform 3 : propagation delay time (f=1mhz; 50% duty cycle)
74lvx573 8/10 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s8 (max.) so-20 mechanical data po13l
74lvx573 9/10 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0087225c
74lvx573 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com
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