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br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 1/14 1k, 2k, 4k, bit eeproms for direct connection to serial port s br9010-w / br9010f-w / br9010fv - w / br9010rfv -w / BR9010RFVM-W br9020-w / br9020f-w / br9020fv - w / br9020rfv -w / br9020rfvm-w br9040-w / br9040f-w / br9040fv - w / br9040rfv -w / br9040rfvm-w t he b r 9 0 x x ser i e s ar e se ri al ee proms t hat ca n be c o nn ect ed d i re ctl y t o a s e r i a l p o rt a n d ca n b e e r a s e d a nd w r i t t e n ele c tri c a lly . w r i t i ng and re adi ng is p e rfo m ed i n w o rd un i t s, u s in g fo u r ty pe s o f ope ra tio n co mmand s. co mmu n i c a t ion occu rs th rou g h cs, sk, d i, an d d o pin s , w c pi n con t ro l i s u s ed to ini t ia te a w r ite di sa bl ed st a t e , en abl in g these eeproms to be used as one-time roms. during w r iting operat ion is checked via the internal st atus check. z a pplic a t ion general-purpose z f eatu r es 1) br9010-w / f - w / f v -w / rf v - w / rf vm-w (1k bit) : 64 w o rds 16bit br9020-w / f - w / f v -w / rf v - w / rf vm-w (2k bit) : 128w ords 16bit br9040-w / f - w / f v -w / rf v - w / rf vm-w (4k bit) : 256w ords 16bit 2) single pow er supply . 3) serial dat a i/o. 4) self-timed programming cy cle w i th auto-erase. 5) low supply current. active (5v) : 2ma (max . ) s t andby (5v) : 3 a (max . ) (cmos input ) 6) noise filter on the sk pin. w r it e protection w hen the supply is low . 7) w r ite protection by w c pin. 8) s p ace saving dip8/sop8/ssop-b8/msop8pin packages. 9) 100,000 erase/ w r ite cy cles endurance. 10) provide 10 y ears of date retention. 1 1 ) easy connection to serial port. 12) ?ffffh? stored in all address on shipped.
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 2/14 z blo ck d i ag ram 16bit 16bit cs r / b wc sk di do 6bit br9010 7bit br9020 8bit br9040 6bit br9010 7bit br9020 8bit br9040 command decode control clock generation write disable power supply voltage detector high voltage generator address decoder r / w amplifier address buffer command register data register 1,024bit br9010 2,048bit br9020 4,096bit br9040 eeprom array z t e rmina l func tion 3 4 5 6 7 8 1 2 1 2 3 4 5 6 7 8 cs sk di do gnd wc r / b v cc br90xx-w/rfv-w/rfvm-w br90xxf-w/fv-w pin no. pin name chip select input serial date clock input serial date input (op code, address) ground (0v) write control input ready/ busy status output power supply serial date output function
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 3/14 z a b so lu te maximu m ratin g s (t a = 25 c) parameter symbol limits unit ? 0.3 to + 7.0 v mw 800 ? 1 450 ? 2 300 ? 3 dip8 ssop-b8 sop8 msop8 310 ? 4 ? 65 to + 125 c ? 40 to + 85 c v cc pd tstg topr ? ? 0.3 to v cc + 0.3 v ? 1 degradation is done at 8.0mw/ ? c for operation above ta=25 ? c ? 2 degradation is done at 4.5mw/ ? c for operation above ta=25 ? c ? 3 degradation is done at 3.0mw/ ? c for operation above ta=25 ? c ? 4 degradation is done at 3.1mw/ ? c for operation above ta=25 ? c supply voltage power dissipation storage temperature operating temperature terminal voltage br9010-w, br9020-w, br9040-w br9010f-w, br9020f-w, br9040f-w br9010fv-w, br9010rfv-w, br9020fv-w, br9020rfv-w, br9040fv-w, br9040rfv-w BR9010RFVM-W, br9020rfvm-w, br9040rfvm-w z re c o mme nde d ope r a t ing condition (t a = 25 c) parameter symbol min. typ. max. unit v cc ? 5.5 v 2.7 2.7 ? 5.5 v v in 0 ? v cc v supply voltage write read input voltage
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 4/14 z electrical ch aracteristics unless otherw i se specified ( t a =? 40 to + 85 c, v cc = 2.7v to 5.5v) parameter min. typ. max. unit conditions ? i ol =2.1ma i oh = ? 0.4ma di pin di pin cs, sk, wc pin cs, sk, wc pin v in =0v to v cc ? ? ? ? ? ? ? ? ? ? ? ? symbol v il1 v ih1 v il2 v ih2 v ol v oh i li i lo i cc1 i cc2 i sb f sk ? 0.7 v cc ? 0.8 v cc 0 v cc ? 0.4 ? 1 ? 1 ? ? ? ? v v v v v v a a ma ma a mhz 0.3 v cc ? 0.2 v cc ? 0.4 v cc 2 1 3 2 1 1 v out =0v to v cc , cs=v cc cs, sk, di, wc=v cc , do, r / b=open f sk =2mhz, te / w=10ms (write) f sk =2mhz (read) input low voltage 1 input high voltage 1 input low voltage 2 input high voltage 2 output low voltage output high voltage input leakage current output leakage current operating current standby current clock frequency unless otherw i se specified ( t a =? 40 to + 85 c, v cc = 2.7v to 3.3v) parameter min. typ. max. unit conditions ? i ol =100 a i oh = ? 100 a di pin di pin cs, sk, wc pin cs, sk, wc pin v in =0v to v cc ? ? ? ? ? ? ? ? ? ? ? ? symbol v il1 v ih1 v il2 v ih2 v ol v oh i li i lo i cc1 i cc2 i sb f sk ? 0.7 v cc ? 0.8 v cc 0 v cc ? 0.4 ? 1 ? 1 ? ? ? ? v v v v v v a a ma ma a mhz 0.3 v cc ? 0.2 v cc ? 0.4 v cc 1.5 0.5 2 2 1 1 v out =0v to v cc , cs=v cc cs, sk, di, wc=v cc , do, r / b=open f sk =2mhz, te / w=10ms (write) f sk =2mhz (read) input low voltage 1 input high voltage 1 input low voltage 2 input high voltage 2 output low voltage output high voltage input leakage current output leakage current operating current standby current clock frequency
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 5/14 z a c op eratio n ch aracteristics ( t a =? 40 to + 85 c, v cc = 2.7 to 5.5v) parameter symbol min. typ. max. unit t css 100 ?? ns t csh 100 ?? ns t wch 100 ?? ns t dis 100 ?? ns t dih ?? 150 ns t pd1 ?? 150 ns t pd0 ?? 10 ms t e / w 250 ?? ns t cs ?? 150 ns t sv 0 ? 150 ns t oh 230 ?? ns t wh 230 ?? ns t wl 0 ?? ns 0 ?? ns t wcs chip select setup time clock high time clock low time clock high to output ready/busy status data in setup time data in hold time delay to output high delay to output low self-timed program cycle minimum chip select high time data output disable time( from cs) chip select hold time write control setup time write control hold time
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 6/14 z i / o circuit (1) input circuit di cs int. sk cs int. cs reset int. wc (2) output circuit oe int. do r/b
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 7/14 z op eratin g (1) instruction code 1010 1000 a0 a1 a2 a3 a4 a5 ( a6) ? 2 (a7) ? 1 a0 a1 a2 a3 a4 a5 ( a6) ? 2 (a7) ? 1 1010 0100 1010 0011 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d0 d1 ? d14 d15 (read data) d0 d1 ? d14 d15 (write data) 1010 0000 read write write enable (wen) write disable (wds) address and data must be transferred from lsb. br9020-w/f-w/fv-w/rfv-w/rfvm-w ? 1 = "0" br9010-w/f-w/fv-w/rfv-w/rfvm-w ? 1, 2 = "0" instruction start bit op code address data ? means either v ih or v il sy nchronous dat a input output t i ming cs sk di do wc t dis t dih t css t pd t oh t csh t cs t pd t wl t wh input data is clocked into the di pin on the rising edge of the clock sk output data is clocked out on the falling edge of the sk clock. the wc pin does not have any affect on the read, wen and wds operations. between instructions, cs must be brought high for greater than the minimum of t cs . if cs is maintained low, the next instruction isn't detected. fig.1
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 8/14 (2) w r it e enable / disable high or low fig.2 1 1 high-z h sk cs di do r / b wc l h l h l h 01 000 48 enable = 11 disable = 00 12 16 1 ) w h e n po w e r is fi rst ap p l i ed, th e d e v ic e h a s be e n h e l d in a re set st at us, w i t h re sp ect to t h e w r i t e ena b l e, i n t h e s a me w a y th e w r i t e d i s a bl e (w ds) i n str u ct io n is e x ecu t e d . bef o r e the w r i t e i n str u ct io n is e x ec ut ed, the de vic e must be re ce i v ed the w r ite en abl e (wen ) in stru cti o n . once the de vi ce i s done , the de vice re mai n s p r o g ramma b l e un til t h e w r ite disable (w ds) instruction is executed or the supply is removed from the device. 2) it is unnecessary to add the clock af ter 16 th clock. if the device is recieved the clock, the device ignores the clock. 3) as bo th o f the e nab le an d di sa bl e in stru cti o n s do n? t de pen d on th e st a t u s o f the wc pi n , the st a t e o f wc i s n ? t ca red during the instruction. 4 ) t h e i n str u cti o n is re co g n iz e d af te r t h e ri si n g ed ge of 8 t h c l o ck f o r th e ad dr ess fo llo w i n g 8 cl ocks fo r t h e o p c o de, bu t the specified address isn?t ca red during the instructions.
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 9/14 (3) read cy cle high or low fig.3 br9010-w / f--w / fv-w / rfv-w / rfvm-w 1 4 81 6 3 2 1 high-z h sk cs di do wc l h l h l 01 1 00 0 0 a0 a5 0 0 d0 d15 d15 d0 high-z standby t cs t oh r / b h read data (n) read data (n+1) high or low fig.4 br9020-w / f-w / fv-w / rfv-w / rfvm-w 1 4 81 6 3 2 4 8 1 high-z h sk cs di do r / b wc l h l h l h 01 1 00 0 0 a0 a6 0 d0 read data (n) read data (n+1) d15 d15 d0 high-z standby t cs t oh high or low fig.5 br9040-w / f-w / fv-w / rfv-w / rfvm-w 1 4 81 6 3 2 1 high-z h sk cs di do r / b wc l h l h l h 01 1 0 000 a0 a6 a7 d0 read data (n) read data (n+1) d15 d15 d0 high-z standby t cs t oh 1) on the falling edge of 16 th clock, the dat a stored in t he specified address (n) is clo cked out of the do pin. t he o u t put do is to gg l ed af te r the i n t e rn a l pro p aga ti on t pd o or t pd 1 on the fa ll in g ed ge o f s k . d u r i n g t pd 0 or t pd 1, t he data i s t he pr ev io us data or u n st a b l e , a n d t o t a ke in the d a ta, t pd i s n e e ded . (r e f e r to fi g.1 sy nchron ou s da t a i npu t ou tp u t timing.) 2 ) t he d a t a st ore d i n th e n e x t a ddre ss is c l oc ke d ou t of the d e v i c e o n th e fa ll in g e d g e of 3 2 nd c l oc k. t h e data stor ed in t he upper address ev er y 16 c l ocks is out put s e quent i ally by t he c o nt inual sk input. a l so t he r e ad oper at ion is r e s e t by cs high.
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 10/14 (4) w r ite cy cle fig.6 br9010-w / f-w / fv-w / rfv-w / rfvm-w 14 8 1 6 3 2 1 high-z high-z h sk cs di do wc l h l h l h l 01 0 0 1 00 00 a0 a5 d0 d 1 5 t wch t wcs t cs r / b h t sv t e/w fig.7 br9020-w / f-w / fv-w / rfv-w / rfvm-w r / b h t sv 14 8 1 6 3 2 1 high-z high-z h sk cs di do wc l h l h l h l 01 0 01 0 0 0 a0 a6 d0 d 1 5 t wch t e/w t wcs t cs fig.8 br9040-w / f-w / fv-w / rfv-w / rfvm-w r / b h t sv 14 8 1 6 3 2 1 high-z high-z h sk cs di do wc l h l h l h l 01 0 0 1 0 0 a0 a6 a7 d0 d 1 5 t wch t e/w t wcs t cs
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 11/14 1) during the w r ite instruction , cs mu st be brought low . how e ver once the w r ite oper ation st arted, cs may be either h i g h or l o w . bu t i n t he ca se of c o nn ect i n g t he w c p i n to t h e c s pi n. c s an d w c m u st be br ou g h t l o w d u r i n g p r o g r a mm in g c y c l e. (if the w c pin is b r o u ght h i gh d u ri n g the w r ite c y c l e, th e w r i t e o p e rat i on i s h a lte d . in t hat c a s e , t h e dat a of the specified addre ss is not guaranteed. it is necessary to rew r ite it.) 2) af te r the r / b pi n chan ged busy to re ady , on ce cs is b r ou gh t hi gh , th en cs ke e p low , w hich mean s th e st a t us o f b e i n g a b l e t o acc e pt a n i n str u ctio n. t he de vic e c a n t a ke i n t h e in p u t fr om sk a n d di, but i n t h e c a s e of k e ep in g c s low w i thout being brought high once, the input is cancel ed until being cs high once. 3) at the rising edge of 32 nd clock, the r / b pin w ill be driven low af ter the specified time delay (tsv). 4 ) d u r i ng p r o g r a mm in g, r / b is tied t o l o w b y t he d e v ic e (on th e ris i n g e d g e of sk t a ke n i n the last d a ta (d 15), i n t e rn a l ti mer st art s an d a u t o m a tic a ll y f i n i s h ed af ter t he dat a of m e mo r y c e ll is w r itt en sp en di n g te / w . sk co u l d b e e i th er h i g h or low at the time. 5) af te r in pu t w r ite i n stru ction , a l so the d o p i n w ill b e ab le to sh o w the st a t us o f r / b, i n th e ca se th at c s is fal l i n g from high to low w h ile sk is tied to low . (refer to ready / busy st a t us in the next p age.) (5) ready / busy st a t us (on the r / b pin, the do pin) 1)t he do pin output s the ready / busy st at us of the internal p a rt, w h ich show s w het her the device is ready to receive the next instruction or not. (high or low ) af t e r th e w r it e instr u ct io n is c o mp l e te d, if cs is b r o u ght fr om hig h t o l o w w h i l e s k is l o w , th e do p i n o u tp ut s t he internal st atus. (t he r / b pin may be no connection. 2) w hen w r itten to the memory cell, r / b st atus is out put af ter tsv spent from the rising edge of 32 th clock on sk. r / b = low : under w r iting af ter spending te / w operating the inte rnal timer , the device automat ically finishes w r iting. during te / w , the memory a rray is accessed and any instruction is not received. r / b= high : ready auto programming has been completed. t he device is ready to receive the next instruction. fig.9 r / b status output timing sk cs di do ready ready ready busy t pd t oh busy write instruction clock r / b high-z high-z
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 12/14 (6) about the direct connecti on betw een the di and do pins t he device can be used w i th the di pin connected to the do pin directly . but w hen the ready / busy st atus is output, be care ful about the bus conflict on t he port of the controller . z a tte ntion to us e (1 ) pow e r on / off 1) t he cs is brought high during pow er?up and pow er?dow n. 2) t h is device is in active st ate w h ile cs is low . 3 ) t he e x tr aor d i n a r y f u n c ti on or data c o l l a p s e m a y o c c u r i n th at c o nd iti on be ca us e of no is e etc, if po w e r ? u p an d pow er?dow n is done w i th cs brought low . in order to prevent above errors from happening, keep cs high during pow er-up and pow er-dow n. (good example) cs is brought hi gh during pow er?up and pow er-dow n. please t a ke more than 10ms betw een pow er?up and pow er-of f, or the internal circuit is not alw a y s r e s e t . (bad example) cs is brought low during pow er?up and pow er-dow n. t he cs pi n i s al w a ys lo w i n th is ca se, th e n o is e m a y for c e th e d e vi ce to m a k e m a lf u n cti o n or inadvertent w r ite. i t s o m e t i m e s o c c u r s i n t h e c a s e t h a t t h e c s p i n i s h i - z . v cc v cc gnd v cc gnd cs good bad fig.10 (2 ) noise rejection 1) sk noise if sk l i n e ha s a l o t o f n o i s e fo r ri sing ti me o f sk, the d e vi ce may reco gn ize th e n o i s e as a cl ock an d the n clo ck w ill be shif ted. 2) wc noise if w c line has noise during w r ite cy cle (te / w ) , there may be a chance to deny the programming. 3) vcc noise it re co mme nde d th a t cap a ci to r i s pu t be tw een vc c an d gn d to p r e v en t the s e ca se , si n c e i t is p o ssibl e to o ccur malfunction by the ef fect of noise or surge on pow er line.
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 13/14 (3) instruction mode cancel 1) read instruction 32 clocks start bit 4 bit 4 bit 8 bit 16 bit it is possible to be canceled for any timing. data do d15 opcode address sk cs di do wc high or low fig.11 how to cancel : cs is brought high. 2) w r ite instruction 32 clocks start bit 4 bit c 4 bit 8 bit 16 bit do d15 opecode address data sk cs di r / b wc t e / w d b a fig.12 how to cancel a cs is brought high to cancel the instruct ion, and w c may be either high or low . b i n cas e th at w c i s bro u ght hi g h for a mo me nt, or cs i s br ou gh t hi gh, th e w r i t e i n str u cti o n is can c el ed, th e d a t a o f the specified address is not changed. c w h en w c is b r o u ght h i g h , or t h e d e v i ce i s pow e r e d do w n (b ut t h e l a tt er w a y i s n o t r e c o mm en de d), th e i n str u ctio n is canceled but the specified dat a is not guaranteed. send t he instruction again. d w hen cs is brought high during r/b hi gh, the device is reset and ready to receive a next instruction. not e : t he document may be strategic te chnical dat a subject to cocom regulations.
br9010-w / f-w / fv -w / rfv - w / rf vm-w / br9020-w / f-w / fv -w / memory ic rfv - w / rfvm-w / br9040-w / f-w / fv -w / rfv - w / rfvm-w rev.a 14/14 z ex te rna l dime ns ions (unit : mm) dip8 ssop-b8 msop8 sop8 5 4 8 1 0.1 6.4 0.3 4.4 0.2 3.0 0.2 0.22 0.1 1.15 0.1 0.65 (0.52) 0.15 0.1 0.3min. 0.1 0.3min. 0.15 0.1 0.4 0.1 0.11 6.2 0.3 4.4 0.2 5.0 0.2 85 4 1 1.27 1.5 0.1 0.1 4 1 5 8 2.9 0.1 0.475 0.65 4.0 0.2 0.6 0.2 0.29 0.15 2. 8 0. 1 0.75 0.05 0.08 0.05 0.9max. 0.08 s 0.08 m 0.145 + 0.05 ? 0.03 0.22 + 0.05 ? 0.04 0.5 0.1 3.2 0.2 3.4 0.3 85 14 9.3 0.3 6.5 0.3 0.3 0.1 0.51min. 2.54 0 ~ 15 7.62 br9010-w, br9020-w, br9040-w br9010f-w, br9020f-w, br9040f-w br9010fv-w, br9010rfv-w br9020fv-w, br9020rfv-w br9040fv-w, br9040rfv-w BR9010RFVM-W, br9020rfvm-w, br9040rfvm-w
appendix appendix1-rev1.1 the products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of with would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. about export control order in japan products described herein are the objects of controlled goods in annex 1 (item 16) of export trade control order in japan. in case of export from japan, please confirm if it applies to "objective" criteria or an "informed" (by miti clause) on the basis of "catch all controls for non-proliferation of weapons of mass destruction.

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