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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers description the m37207mf-xxxsp/fp and M37207M8-XXXSP are single-chip microcomputers designed with cmos silicon gate technology. it is housed in a 64-pin shrink plastic molded dip or a 80-pin plastic molded qfp. in addition to their simple instruction sets, the rom, ram and i/o addresses are placed on the same memory map to enable easy pro- gramming. the m37207mf-xxxsp/fp has a pwm function and an osd func- tion, so it is useful for a channel selection system for tv. the fea- tures of the m37207efsp/fp are similar to those of the m37207mf- xxxsp/fp except that these chips have a built-in prom which can be written electrically. the difference between m37207mf-xxxsp/ fp and M37207M8-XXXSP are the rom size, ram size, rom size for display and kinds of character. accordingly, the following descrip- tions will be for the m37207mf-xxxsp/fp unless otherwise noted. ? multi-master i 2 c-bus interface ............................... 1 (3 systems) ? power dissipation in high-speed mode ........................................................ 165 mw (at v cc = 5.5 v, 8 mhz oscillation frequency, crt on) in low-speed mode ......................................................... 0.33 mw (at v cc = 5.5 v, 32 khz oscillation frequency) ? a-d comparator (6-bit resolution) ................................ 8 channels ? pwm output circuit ...................................... 14-bit 5 1, 8-bit 5 10 ? interrupt interval determination circuit ........................................ 1 ? rom correction function .......................................... 32 bytes 5 2 ? crt display function number of display characters ............... 24 characters 5 3 lines (16 lines maximum) kinds of characters .................. 256 kinds (M37207M8-XXXSP) 384 kinds (m37207mf-xxxsp/fp, m37207efsp/fp) character display area .......................................... 12 5 16 dots kinds of character sizes ................................................. 4 kinds kinds of character colors (it can be specified by the character) maximum 15 kinds (r, g, b, i) kinds of character background colors (it can be specified by the character) maximum 7 kinds (r, g, b) 1/2-character unit color specification is possible. kinds of raster colors (maximum 15 kinds) display position horizontal .................................................................. 64 levels vertical .................................................................... 128 levels bordering (horizontal and vertical) wipe function scanning line double count mode display is possible. application tv features ? number of basic instructions .................................................... 71 ? memory size ................................................................................. rom ...................... 32k bytes (M37207M8-XXXSP) 62k bytes (m37207mf-xxxsp/fp, m37207efsp/fp) ram ...................... 512 bytes (M37207M8-XXXSP) 960 bytes (m37207mf-xxxsp/fp, m37207efsp/fp) rom correction memory ............................ 64 bytes rom for display ....... 8k bytes (M37207M8-XXXSP) 12k bytes (m37207mf-xxxsp/fp, m37207efsp/fp) ram for display ........................................ 144 bytes ? minimum instruction execution time ........................................ 0.5 s (at 8 mhz oscillation frequency) ? power source voltage .................................................. 5 v 10 % ? subroutine nesting ............................................ 128 levels (max.) ? interrupts ...................................................... 15 types, 14 vectors ? 8-bit timers ................................................................................. 6 ? programmable i/o ports (ports p0, p1, p2, p3 0 Cp3 6 , p4, p6) ....................................... 47 ? input ports (ports p7 0 , p7 1 ) ....................................................... 2 ? output ports (ports p5 2 Cp5 6 ) ..................................................... 5 ? 12 v withstand ports ................................................................. 10 ? led drive ports .......................................................................... 4 ? serial i/o ....................................... 8-bit 5 1 channel (2 systems) mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 2 pin configuration (top view) outline 64p4b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 p6 5 /pwm5 p4 1 /s clk2 /scl3/x cout osc1/p7 0 /ad4 osc2/p7 1 /ad5 p3 6 /int2/ad2 p3 5 /ad1 p3 4 /int1 d-a/ad3 p6 0 /pwm0 p6 1 /pwm1 p6 6 /pwm6 p6 7 /pwm7 p3 3 /tim3 p3 2 /tim2/ad6 p3 1 p3 0 p4 7 / s rdy1 /pwm8 p4 6 /s in1 /pwm9 p4 3 / s rdy2 /scl2/ad7 p4 2 /s in2 /sda2/ad8 p4 0 /s out2 /sda3/x cin v cc h sync v sync r/p5 2 g/p5 3 b/p5 4 i/p5 5 /tim1 overflow p0 7 p1 1 p1 3 p1 5 p1 6 p1 7 p2 0 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p2 1 p6 2 /pwm2 p6 3 /pwm3 p6 4 /pwm4 p4 5 /s clk1 /scl1 p4 4 /s out1 /sda1 out/p5 6 p0 0 p0 4 p0 5 p0 6 22 23 24 25 26 43 42 41 40 39 m37207mf-xxxsp, M37207M8-XXXSP m37207efsp f cnv ss reset x out x in v ss 27 28 29 30 31 32 38 37 36 35 34 33 p0 1 p0 2 p0 3 p1 0 p1 2 p1 4 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 3 pin configuration (top view) outline 80p6n-a nc: unconnected p0 7 55 43 reset cnv ss x in p0 4 p0 5 p0 6 28 40 39 37 38 36 35 34 33 32 31 30 29 27 26 25 51 41 44 45 46 47 48 50 58 52 59 57 56 60 61 63 62 42 49 nc nc nc nc nc nc nc nc nc nc nc nc nc 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 24 23 22 21 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 nc 64 54 53 p6 5 /pwm5 p6 0 /pwm0 p6 1 /pwm1 p6 6 /pwm6 p6 7 /pwm7 p3 3 /tim3 p3 2 /tim2/ad6 p3 1 p3 0 p4 6 /s in1 /pwm9 p6 2 /pwm2 p6 3 /pwm3 p6 4 /pwm4 p4 5 /s clk1 /scl1 f x out v ss osc1/p7 0 /ad4 osc2/p7 1 /ad5 p3 6 /int2/ad2 p3 5 /ad1 p3 4 /int1 d-a/ad3 v cc h sync v sync r/p5 2 g/p5 3 b/p5 4 i/p5 5 /tim1 overflow p1 1 p1 3 p1 5 p1 6 p1 7 p2 0 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p2 1 out/p5 6 p0 0 p0 1 p0 2 p0 3 p1 0 p1 2 p1 4 m37207mf-xxxfp, m37207effp nc nc p4 7 / s rdy1 /pwm8 p4 4 /s out1 /sda1 p4 3 / s rdy2 /scl2/ad7 p4 2 /s in2 /sda2/ad8 p4 1 /s clk2 /scl3/x cout p4 f /s out2 /sda3/x cin mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 4 functional block diagram of M37207M8-XXXSP clock input clock output x in x out reset input v cc v ss cnv ss clock output for crt/ sub-clock output input ports p7 0 , p7 1 osc1 osc2 clock input for crt/ sub-clock input p1 (8) p0(8) p2 (8) s out1 s clk1 s in1 si/o (8) p6 (8) int1 int2 p5 (5) i b g r h sync v sync a-d comparator 8-bit arithmetic and logical unit accumulator a (8) timer 6 t6 (8) timer 5 t5 (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit tim2 tim3 instruction register (8) instruction decoder control signal processor status register ps (8) stack pointer s (8) index register y (8) index register x (8) rom 64 k bytes program counter pc l (8) program counter pc h (8) ram 960 bytes data bus clock generating circuit 30 31 29 reset 64 32 27 1 2 address bus 41 42 43 44 45 46 47 48 33 34 35 36 37 38 39 40 34 5 15 16 17 18 62 63 i/o ports p0 0 ?0 7 i/o ports p1 0 ?1 7 i/o ports p2 0 ?2 7 i/o ports p3 0 ?3 6 i/o ports p6 0 ?6 7 sync input 12 11 10 9 87 14 13 58 59 60 61 57 output ports p5 2 ?5 6 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 pwm7 28 timing output f out s rdy1 49 50 51 52 53 54 55 56 multi-master i 2 c-bus interface scl2 sda1 scl1 sda2 scl3 sda3 8-bit pwm circuit s out2 s clk2 s in2 s rdy2 p4 (8) 25 24 23 22 21 20 19 i/o ports p4 0 ?4 7 26 6 d-a 14-bit pwm circuit a-d comparator crt circuit p3 (7) x cin x cout (note 1) (note 2) note 1: M37207M8-XXXSP has a 512 bytes ram. note 2: M37207M8-XXXSP has a 32 k bytes rom. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 5 number of basic instructions instruction execution time clock frequency memory size input/output ports serial i/o multi-master i 2 c-bus interface a-d comparator pwm output circuit timers rom correction function subroutine nesting interrupt interval determination circuit interrupt clock generating circuit p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 , p3 1 p3 2 Cp3 6 p4 0 Cp4 7 p5 2 Cp5 6 p6 0 Cp6 7 p7 0 , p7 0 rom ram crt rom crt ram parameter 71 0.5 m s (the minimum instruction execution time, at 8 mhz oscillation fre- quency) 8 mhz (maximum) 32 k bytes 64 k bytes 512 bytes 960 bytes 64 bytes 8k bytes 12k bytes 144 bytes 8-bit 5 1 (cmos input/output structure) 8-bit 5 1 (cmos input/output structure) 8-bit 5 1 (cmos input/output structure) 2-bit 5 1 (cmos input/output structure) 5-bit 5 1 (n-channel open-drain output structure, can be used as external clock input pins, a-d input pins, int input pins) 8-bit 5 1 (n-channel open-drain output structure, can be used as serial i/o pins, a-d input pins, pwm output pins, multi-master i 2 c-bus interface, sub-clock i/o pins) 5-bit 5 1 (cmos output structure, can be used as crt output pins, an external clock output pin) 8-bit 5 1 (n-channel open-drain output structure, can be used as pwm output) 2-bit 5 1 (can be used as crt display clock i/o pins, analog input pins) 8-bit 5 1 (2 systems) 1 (3 systems) 8 channels (6-bit resolution) 14-bit 5 1, 8-bit 5 10 8-bit timer 5 6 32 bytes 5 2 128 levels (maximum) 1 external interrupt 5 2, internal timer interrupt 5 6, serial i/o interrupt 5 1, crt interrupt 5 1, multi-master i 2 c-bus interface interrupt 5 1, f(x in )/4096 interrupt 5 1, v sync interrupt 5 1, brk interrupt 5 1 2 built-in circuits (externally connected to a ceramic resonator or a quartz- crystal oscillator) i/o i/o i/o i/o i/o i/o output i/o input functions functions rom correction memory M37207M8-XXXSP m37207mf-xxxsp/fp , m37207efsp/fp M37207M8-XXXSP m37207mf-xxxsp/fp , m37207efsp/fp M37207M8-XXXSP m37207mf-xxxsp/fp , m37207efsp/fp mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 6 power source voltage power dissipation operating temperature range device structure package crt display function number of display characters character display area kinds of character sizes kinds of character colors display position (horizontal, vertical) M37207M8-XXXSP kinds of characters crt on crt off crt off functions 5 v 10 % 165 mw typ. (at oscillation frequency f(x in ) = 8 mhz, f osc = 8 mhz) 82.5 mw typ. (at oscillation frequency f(x in ) = 8 mhz) 0.33 mw typ. (at oscillation frequency f clk = 32 khz, f(x in ) = stopped) 1.1 mw (maximum) C10 c to 70 c cmos silicon gate process 64-pin shrink plastic molded dip 80-pin plastic molded qfp 24 characters 5 3 lines (maximum 16 lines by software) 12 5 16 dots 256 kinds 384 kinds 4 kinds maximum 15 kinds (r, g, b, i); can be specified by the character 64 levels (horizontal) 5 128 levels (vertical) parameter functions (continued) in high-speed mode in low-speed mode in stop mode m37207mf-xxxsp, M37207M8-XXXSP m37207efsp m37207mf-xxxfp, m37207effp m37207mf-xxxsp/fp, m37207efsp/fp mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 7 power source cnv ss reset input clock input clock output i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p3 analog input external clock input external interrupt input i/o port p4 serial i/o data input/output serial i/o synchro- nous clock input/ output serial i/o receive enable signal output multi-master i 2 c- bus interface sub-clock input sub-clock output analog input pwm output input input output i/o i/o i/o i/o i/o input input input i/o i/o i/o output i/o input output input output pin description pin functions apply voltage of 5 v 10 % (typical) to v cc and av cc , and 0 v to v ss . connected to v ss . to enter the reset state, the reset input pin must be kept at a l for 2 m s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this l condition should be maintained for the required time. this chip has an internal clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. port p0 is an 8-bit i/o port with direction register allowing each i/o bit to be individually programmed as input or output. at reset, this port is set to input mode. the output structure is cmos output. see notes at end of table for full details of port p0 functions. port p1 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. port p2 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. ports p3 0 , p3 1 are 2-bit i/o ports and have basically the same functions as port p0. the output structure is cmos output. ports p3 2 Cp3 6 are 5-bit i/o ports and have basically the same functions as port p0. the output structure is n-channel open-drain output. pins p3 2 , p3 5 , p3 6 are also used as analog input pins ad6, ad1 and ad2 respectively. pins p3 2 , p3 3 are also used as external clock input pins tim2, tim3 respectively. pins p3 4 , p3 6 are also used as external interrupt input pins int1, int2. port p4 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is n-channel open-drain output. pins p4 0 , p4 2 , p4 4 , p4 6 are also used as serial i/o data input/output pins s out2 , s in2 , s out1 , s in1 respectively. the output structure is n-channel open-drain output. pins p4 1 , p4 5 are also used as serial i/o synchronous clock input/output pins s clk2 , s clk1 respectively. _____ _____ pins p4 3 , p4 7 are also used as serial i/o receive enable signal output pins s rdy2 , s rdy1 respectively. the output structure is n-channel open-drain output. pins p4 0 Cp4 5 are also used as sda3, scl3, sda2, scl2, sda1, scl1 respectively when multi-master i 2 c-bus interface is used. the output structure is n-channel open- drain output. pin p4 0 is also used as sub-clock input pin x cin . pin p4 1 is also used as sub-clock output pin x cout . the output structure is n-channel open-drain output. pins p4 2 , p4 3 are also used as analog input pins ad8, ad7 respectively. pins p4 6 , p4 7 are also used as pwm output pins pwm9, pwm8 respectively. the output structure is n-channel open-drain output. input/ output name v cc, v ss cnv ss ______ reset x in x out p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 , p3 1 p3 2 /tim2/ ad6, p3 3 /tim3, p3 4 /int1, p3 5 /ad1, p3 6 /int2/ ad2 p4 0 /s out2 / sda3/x cin , p4 1 /s clk2 / scl3/ x cout , p4 2 / s in2 /sda2/ ad8, _____ p4 3 /s rdy2 / scl2/ad7, p4 4 /s out1 / sda1, p4 5 /s clk1 / scl1, p4 6 /s in1 / pwm9, _____ p4 7 /s rdy1 / pwm8 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 8 output port p5 crt output timer 1 overflow signal output i/o port p6 pwm output input port p7 clock input for crt display clock output for crt display analog input h sync input v sync input timing output da output analog input pin description (continued) r/p5 2 , g/p5 3 , b/p5 4 , i/p5 5 /tim1 overflow, out/p5 6 p6 0 /pwmC p6 7 /pwm7 osc1/p7 0 / ad4, osc2/p7 1 / ad5 h sync v sync f d-a/ad3 output output output i/o output input input output input input input output output input ports p5 2 Cp5 6 are 5-bit output ports. the output structure is cmos output. pins p5 2 Cp5 6 are also used as crt output pins r, g, b, i, out respectively. the output structure is cmos output. pin p5 5 is also used as timer 1 overflow signal output pin tim1 overflow. the output structure is cmos output. port p6 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is n-channel open-drain output. pins p6 0 Cp6 7 are also used as pwm output pins pwm0Cpwm7. the output structure is cmos output. ports p7 0 , p7 1 are 2-bit input port. pin p7 0 is also used as crt display clock input pin osc1. pin p7 1 is also used as crt display clock output pin osc2. the output structure is cmos output. pins p7 0 , p7 1 are also used as analog input pins ad4, ad5 respectively. this is a horizontal synchronous signal input for crt display. this is a vertical synchronous signal input for crt display. this is a timing output pin. this pin has reset-out output function. the output structure is cmos output. this is an output pin for 14-bit pwm. the d-a pin is also used as analog input pin ad3. note : as shown in the memory map (figure 5), port p0 is accessed as a memory at address 00c0 16 of zero page. port p0 has the port p0 direction register (address 00c1 16 of zero page) which can be used to program each bit as an input (0) or an output (1). the pins programmed as 1 in the direction register are output pins. when pins are programmed as 0, they are input pins. when pins are programmed as output pins, the output data are written into the port latch and then output. when data is read from the output pins, the output pin level is not read but the data of the port latch is read. this allows a previously-output value to be read correctly even if the output l voltage has risen, for example, because a light emitting diode was directly driven. the input pins float, so the values of the pins can be read. when data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. pin name input/ output functions mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 9 n-channel open-drain output ports p4 6 , p4 7 , p6 0 Cp6 7 note : each port is also used as follows: p4 6 : s in1 /pwm9 _____ p4 7 : s rdy1 /pwm8 p6 0 Cp6 7 : pwm0Cpwm7 fig. 1. i/o pin block diagram (1) ports p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , d-a data bus direction register port latch ports p4 6 , p4 7 , p6 0 Cp6 7 data bus direction register port latch ports p3 2 Cp3 6 , p4 2 Cp4 5 data bus direction register port latch n-channel open-drain output ports p3 2 Cp3 6 , p4 2 Cp4 5 note : each port is also used as follows: p3 2 : tim2/ad6 p3 3 : tim3 p3 4 : int1 p3 5 : ad1 p3 6 : int2/ad2 p4 2 : s in2 /sda2/ad8 _____ p4 3 : s rdy2 /scl2/ad7 p4 4 : s out1 /sda1 p4 5 : s clk1 /scl1 cmos output ports p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , d-a note : d-a pin is also used as ad3. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 10 r, g, b, i, out, ? h sync , v sync internal circuit internal circuit fig. 2. i/o pin block diagram (2) schmidt input h sync , v sync cmos output p5 2 Cp5 5 , f note : each port is also used as follows: p5 2 : r p5 3 : g p5 4 : b p5 5 : i/tim1 p5 6 : out p5 2 Cp5 5 , f mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 11 functional description central processing unit (cpu) this microcomputer uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instructions or the series 740 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 12 memory special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom rom is used for storing user programs as well as the interrupt vector area. ram for display ram for display is used for specifying the character codes and col- ors to display. rom for display rom for display is used for storing character data. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. fig. 4. memory map rom correction memory (ram) this is used as the program area for rom correction. 0000 16 00c0 16 00ff 16 01ff 16 033f 16 0800 16 sfr area not used not used ffff 16 ffde 16 ff00 16 0300 16 interrupt vector area not used 10000 16 11fff 16 1ffff 16 rom for display (8 k bytes) for m37207m8 special page rom (32 k bytes) for m37207m8 ram for display (144 bytes) (see note) zero page note: refer to table 9. contents of crt display ram. 0204 16 021b 16 02c0 16 02ff 16 2 page register not used 06d7 16 0600 16 not used rom correction memory (64 bytes) block 1: addresses 02c0 16 to 02df 16 block 2: addresses 02e0 16 to 02ff 16 8000 16 04ff 16 12fff 16 rom for display (12 k bytes) for m37207mf rom (62 k bytes) for m37207mf ram (512 bytes) for m37207m8 ram (960 bytes) for m37207mf mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 13 fig. 5. memory map of special function register (sfr) n sfr area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 control register (d5) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o regsiter (sio) bit allocation state immediately after reset : 0 immediately after reset : undefined immediately after reset 0 1 ? mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 14 fig. 6. memory map of special function register (sfr) b7 b0 bit allocation state immediately after reset b7 b0 : 0 immediately after reset : undefined immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address crt control register 1 (cc) crt port control register (crtp) wipe start register (??) a-d control register 1 (adm) timer 1 (tm1) vertical register 2 (cv2) color register 0 (co0) color register 1 (co1) character size register (cs) border selection register (md) register horizontal register (hr) vertical register 1 (cv1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer mode register 1 (tmr1) timer mode register 2 (tmr2) pwm5 register (pwm5) pwm8 register (pwm8) pwm9 register (pwm9) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) color register 2 (co2) color register 3 (co3) wipe mode register (sl) cpu mode register (cpum) n sfr area (addresses e0 16 to ff 16 ) hr0hr1hr2hr3hr4hr5 cv10cv11cv12cv13cv14cv15 cv16 cv20cv21cv22cv23cv24cv25cv26 cs10cs11cs20cs21 md10md20 co01co02co03co05 co11co12co13co15 co21co22co23co25 co31co32co33co35 cc0cc1cc2 vsyc r/g/b irgb hsyc sl0sl1 adm0adm1 adm2adm4 tmr10tmr11tmr12tmr13tmr14 cm2 tm1r tm2rtm3rtm4rcrtrvscriicr ck0 msr it1rit2r s1r tm1e tm2etm3etm4ecrtevsceiice it1e it2e siemse ? 0 ?????? ? 0 ?????? ???? 00?? ?? 00??? ? 00 16 ? 00 00 0 00 ff 16 07 16 ff 16 07 16 ? ? 00 0 00 11 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 sl2sl3sl4sl5sl6 tmr15tmr16tmr17 cm7 cm6 cm5 tm56r tm56etm56c ck0 01 11 0 010 0 cv30cv31cv32cv33cv34cv35cv36 ? 0 ?????? cs30cs31 cs7 md11md21md31 md30 co00 co11 co22 co33 co04 co14 co24 co34 co06 co16 co26 co36 co07 co17 co27 co37 00 16 0 cc3cc4cc5cc6 00 16 00 16 00 16 tmr20tmr21tmr22tmr23tmr24tmr25tmr26tmr27 ? ? ? vertical register 3 (cv3) display block counter (cbc) pwm6 register (pwm6) pwm7 register (pwm7) mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 15 fig. 7. memory map of 2 page register address register n sfr area (addresses 204 16 to 21b 16 ) 210 16 211 16 212 16 213 16 214 16 215 16 216 16 217 16 218 16 219 16 21a 16 21b 16 rom correction address 1 (high-order) rom correction address 1 (low-order) rom correction address 2 (high-order) rom correction address 2 (low-order) rom correction enable register (rcr) b7 b0 bit allocation state immediately after reset b7 b0 : 0 immediately after reset : undefined immediately after reset 0 1 ? mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 16 fig. 8. internal state of processor status register and program counter at reset b7 b0 b7 b0 1 register processor status register (ps) bit allocation state immediately after reset program counter (pc h ) program counter (pc l ) i zcdbtv n????? ?? contents of address ffff 16 contents of address fffe 16 : 0 immediately after reset : undefined immediately after reset 0 1 ? mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 17 interrupts interrupts can be caused by 15 different sources consisting of 3 ex- ternal, 10 internal, 1 software, and reset. interrupts are vectored in- terrupts with priorities as shown in table 1. reset is also included in the table because its operation is similar to an interrupt. when an interrupt is accepted, (1) the contents of the program counter and processor status register are automatically stored into the stack. (2) the interrupt disable flag i is set to 1 and the corresponding interrupt request bit is set to 0. (3) the jump destination address stored in the vector address enters the program counter. other interrupts are disabled when the interrupt disable flag is set to 1. all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit. the interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. figures 10 to 13 show the inter- rupt-related registers. interrupts other than the brk instruction interrupt and reset are ac- cepted when the interrupt enable bit is 1, interrupt request bit is 1, and the interrupt disable flag is 0. the interrupt request bit can be set to 0 by a program, but not set to 1. the interrupt enable bit can be set to 0 and 1 by a program. reset is treated as a non-maskable interrupt with the highest priority. figure 9 shows interrupt control. interrupt causes (1) v sync and crt interrupts the v sync interrupt is an interrupt request synchronized with the vertical sync signal. the crt interrupt occurs after character block display to the crt is completed. (2) int1, int2 interrupts with an external interrupt input, the system detects that the level of a pin changes from l to h or from h to l, and generates an interrupt request. the input active edge can be selected by bits 3 and 4 of the interrupt interval determination control register (address 00d8 16 ) : when this bit is 0, a change from l to h is detected; when it is 1, a change from h to l is detected. note that all bits are cleared to 0 at reset. (3) timer 1, 2, 3 and 4 interrupts an interrupt is generated by an overflow of timer 1, 2, 3 or 4. (4) serial i/o interrupt this is an interrupt request from the clock synchronous serial i/o function. priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vector addresses ffff 16 , fffe 16 fffd 16 , fffc 16 fffb 16 , fffa 16 fff9 16 , fff8 16 fff7 16 , fff6 16 fff5 16 , fff4 16 fff3 16 , fff2 16 fff1 16 , fff0 16 ffef 16 , ffee 16 ffed 16 , ffec 16 ffeb 16 , ffea 16 ffe7 16 , ffe6 16 ffe3 16 , ffe2 16 ffdf 16 , ffde 16 interrupt source reset crt interrupt int1 interrupt int2 interrupt timer 4 interrupt f(x in )/4096 interrupt v sync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt serial i/o interrupt multi-master i 2 c-bus interface interrupt timer 5 6 interrupt brk instruction interrupt remarks non-maskable active edge selectable active edge selectable active edge selectable source switch by software (see note) non-maskable (software interrupt) table 1. interrupt vector addresses and priority note : switching a source during a program causes an unnecessary interrupt. therefore, set a source at initializing of program. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 18 (5) f(x in )/4096 interrupt this interrupt occurs regularly with a f(x in )/4096 period. set bit 0 of the pwm output control register 1 to 0. (6) multi-master i 2 c-bus interface interrupt this is an interrupt request related to the multi-master i 2 c-bus interface. (7) timer 5 6 interrupt an interrupt is generated by an overflow of timer 5 or 6. their priorities are same, and can be switched by software. (8) brk instruction interrupt this software interrupt has the least significant priority. it does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag i (non-maskable). fig. 9. interrupt control interrupt request bit interrupt enable bit interrupt disable flag i brk instruction reset interrupt request mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 19 fig. 10. interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc b name functions after reset rw interrupt request register 1 0 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit (tm1r) 1 timer 2 interrupt request bit (tm2r) 2 timer 3 interrupt request bit (tm3r) 3 timer 4 interrupt request bit (tm4r) 4 crt interrupt request bit (crtr) 5v sync interrupt request bit (vscr) 6 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] multi-master i 2 c-bus interface interrupt request bit (iicr) 0 : no interrupt request issued 1 : interrupt request issued ] 16 ] r r r r r r r 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?. r 0 fig. 11. interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd b name functions after reset rw interrupt request register 2 0 int1 interrupt request bit (itir) 0 : no interrupt request issued 1 : interrupt request issued 1 int2 interrupt request bit (it2r) 2 serial i/o interrupt request bit (sir) 4 f(x in )/4096 interrupt request bit (msr) 3,6 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are ?. 7 fix this bit to ?.? 0 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 ] : ??can be set by software, but ??cannot be set. 0 ] 0 0 ] 0 ] 0 ] 0 : no interrupt request issued 1 : interrupt request issued 16 ] r r r r r rw 5 timer 5 ?6 interrupt request bit (tm56r) 0 : no interrupt request issued 1 : interrupt request issued 0 ] r mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 20 fig. 12. interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b name functions after reset rw interrupt control register 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 1 timer 2 interrupt enable bit (tm2e) 2 timer 3 interrupt enable bit (tm3e) 3 4 crt interrupt enable bit (crte) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 0 rw rw rw rw rw r 0 r 6 timer 4 interrupt enable bit (tm4e) 0 : interrupt disabled 1 : interrupt enabled 5 v sync interrupt enable bit (vsce) 0 : interrupt disabled 1 : interrupt enabled 0rw multi-master i 2 c-bus interface interrupt enable bit (iice) 0 : interrupt disabled 1 : interrupt enabled w nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 7 fig. 13. interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name functions after reset rw interrupt control register 2 0 int1 interrupt enable bit (it1e) 0 : interrupt disabled 1 : interrupt enabled 1 int2 interrupt enable bit (it2e) 2 serial i/o interrupt enable bit (sie) 3, 6 fix these bits to 0. 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 0 rw rw rw rw 4 f(x in )/4096 interrupt enable bit (mse) 0 : interrupt disabled 1 : interrupt enabled 0rw 5 timer 5 ? 6 interrupt enable bit (tm56e) 0 : interrupt disabled 1 : interrupt enabled 0rw 7 timer 5 ? 6 interrupt switch bit (tm56c) 0 : timer 5 1 : timer 6 0rw mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 21 timers the m37267m6-xxxsp has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5 and timer 6. all timers are 8-bit timers with the 8-bit timer latch. the timer block diagram is shown in figure 17 . 0 . all of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. by writing a count value to the correspond- ing timer latch (addresses 00f0 16 to 00f3 16 : timers 1 to 4, addresses 020c 16 and 020d 16 : timers 5 and 6), the value is also set to a timer, simultaneously. the count value is decremented by 1. the timer interrupt request bit is set to 1 by a timer overflow at the next count pulse after the count value reaches 00 16. (1) timer 1 timer 1 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? f(x in )/4096 or f(x cin )/4096 ? f(x cin ) ? external clock from the tim2 pin the count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 1 interrupt request occurs at timer 1 overflow. (2) timer 2 timer 2 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? timer 1 overflow signal ? external clock from the tim2 pin the count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 1 overflow signal is a count source for timer 2, timer 1 functions as an 8-bit prescaler. timer 2 interrupt request occurs at timer 2 overflow. (3) timer 3 timer 3 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? external clock from the tim3 pin the count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00f5 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 3 interrupt request occurs at timer 3 overflow. (4) timer 4 timer 4 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? f(x in )/2 or f(x cin )/2 ? timer 3 overflow signal the count source of timer 3 is selected by setting bits 1 and 4 of timer mode register 2 (address 00f5 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 3 overflow signal is a count source for timer 4, the timer 3 functions as an 8-bit prescaler. timer 4 interrupt request occurs at timer 4 overflow. (5) timer 5 timer 5 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? f(x cin ) ? timer 4 overflow signal the count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00f4 16 ) and bit 7 of timer mode register 2 (ad- dress 00f5 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 5 interrupt request occurs at timer 5 overflow. (6) timer 6 timer 6 can select one of the following count sources: ? f(x in )/16 or f(x cin )/16 ? timer 5 overflow signal the count source of timer 6 is selected by setting bit 7 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 5 overflow signal is a count source for timer 6, timer 5 functions as an 8-bit prescaler. timer 6 interrupt request occurs at timer 6 overflow. at reset, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. the f(x in ) ] /16 is se- lected as the timer 3 count source. the internal reset is released by timer 4 overflow in this state and the internal clock is connected. at execution of the stp instruction, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. however, the f(x in ) ] /16 is not selected as the timer 3 count source. so set bit 0 of timer mode register 2 (address 00f5 16 ) to 0 before execution of the stp instruction (f(x in ) ] /16 is selected as timer 3 count source). the internal stp state is released by timer 4 overflow in this state and the internal clock is connected. as a result of the above procedure, the program can start under a stable clock. ] : when bit 7 of the cpu mode register (cm 7 ) is 1, f(x in ) be- comes f(x cin ). the timer-related registers is shown in figures 14 to 16. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 22 fig. 14. timer mode register 1 fig. 15. timer mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 1 (tmr1) [address 00f4 16 ] b after reset w timer mode register 1 0 1 2 3 4 name functions timer 1 count source selection bit 1 (tmr10, tmr15) b5 b0 0 0: f(x in )/16 or f(x cin )/16 (see note) 0 1: f(x in )/4096 or f(x cin )/4096 (see note) 1 0: f(xc in ) 1 1: external clock from tim2 pin timer 2 count source selection bit 1 (tmr11) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin timer 1 count stop bit (tmr12) 0: count start 1: count stop timer 2 count stop bit (tmr13) 0: count start 1: count stop timer 2 count source selection bit 2 (tmr14) r 0 0 0 0 0 wr wr wr wr wr 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 6 timer 5 count source selection bit 2 (tmr16) 0: timer 2 overflow 1: timer 4 overflow 0wr 7 timer 6 internal count source selection bit (tmr17) 0wr 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tmr2) [address 00f5 16 ] b after reset rw timer mode register 2 0 name functions timer 3 count source selection bit (tmr20) 0 rw 1 timer 4 count source selection bit 2 (tmr21) 0rw 2 3 0 timer 3 count stop bit (tmr22) 0: count start 1: count stop timer 4 count stop bit (tmr23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tmr25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tmr26) 0: count start 1: count stop 0 rw rw rw rw rw 7 timer 5 count source selection bit 1 (tmr27) 0: count source selected by bit 0 of tmr3 1: count source selected by bit 6 of tmr1 0 : f(x in )/16 or f(x cin )/16 (see note) 1 : external clock from tim3 pin 0 : timer 3 overflow signal 1 : f(x in )/16 or f(x cin )/16 (see note) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. 4 timer 4 count source selection bit 1 (tmr24) 0rw 0: count source selected by bit 1 of tmr2 1 : f(x in )/2 or f(x cin )/2 (see note) mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 23 fig. 16. timer mode register 3 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 3 (tmr3) [address 020b 16 ] b after reset rw timer mode register 3 0 name functions timer 5 count source selection bit 3 (tmr30) 0rw 0r 0 : f(x in )/16 or f(x cin )/16 (see note) 1 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. 1 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 24 fig. 17. timer block diagram 1/4096 1/2 cm 7 tmr1 5 1/8 8 8 8 tmr1 0 tmr1 2 tmr1 4 tmr1 1 tmr1 3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 data bus timer 1 interrupt request timer 2 interrupt request timer 3 interrupt request reset stp instruction tmr2 0 tmr2 2 timer 4 interrupt request tmr2 4 tmr2 3 tmr2 1 tmr1 6 timer 5 interrupt request tmr2 7 tmr2 5 timer 6 interrupt request tmr1 7 tmr2 6 x cin x in tim2 tim3 selection gate : connected to black side at reset. tmr1 : timer mode register 1 tmr2 : timer mode register 2 tmr3 : timer mode register 3 cm : cpu mode register ff 16 07 16 tmr1 5 tmr3 0 timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) timer 3 latch(8) timer 4 latch (8) timer 3 (8) timer 4 (8) timer 5 latch (8) timer 5 (8) timer 6 (8) timer 6 latch (8) notes 1: high pulse width of external clock inputs tim2 and tim3 needs 4 machine cycles or more. 2: when the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: in the stop mode or the wait mode, external clock inputs tim2 and tim3 cannot be used. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 25 serial i/o this microcomputer has a built-in serial i/o which can either transmit or receive 8-bit data serially in clock synchronous mode. the serial i/o block diagram is shown in figure 18. the synchronous clock i/o pin (s clk ), and data i/o pins (s out , s in ), receive enable ____ signal output pin ( s rdy ) also function as port p4. bit 2 of the serial i/o mode register (address 00de 16 ) selects whether the synchronous clock is supplied internally or externally (from the pins s clk1 , s clk2 ). when an internal clock is selected, bits 1 and 0 select whether f(x in ) or f(x cin ) is divided by 8, 16, 32, or 64. to use pins for serial i/o, set the corresponding bits of the port p4 direction register (address 00c9 16 ) to 0. the operation of the serial i/o is described below. the operation differs depending on the clock source; external clock or internal clock. fig. 18. serial i/o block diagram 8 serial i/o shift register (8) data bus serial i/o interrupt request selection gate : connected to black side at reset. synchronous circuit frequency divider 1/81/4 1/16 sm 1 sm 0 serial i/o counter (8) sm5 : lsb msb s sm2 1/2 x in 1/2 (address 00df 16 ) x cin cm7 1/2 (note) note : when the data is set in the serial i/o register (address 00df 16 ), the register functions as the serial i/o shift register. p4 3 latch sm6 scl2 csio s rdy2 s clk2 s out2 sm4 p4 1 latch sm7 scl3 sm3 csio p4 0 latch sm7 sda3 sm3 csio sm6 p4 0 latch sda2 s in2 s rdy1 p4 7 latch sic3 pwm8 sic7 s clk1 p4 5 latch sic4 scl1 sic5 s out1 p4 4 latch sic4 sda1 sic5 s in1 sic6 pwm9 p4 6 latch csio cm : cpu mode register sm : serial i/o mode register sic : serial i/o control register csio : bit 1 of serial i/o control register mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 26 fig. 19. serial i/o timing (for lsb first) ____ internal clock : the s rdy signal goes to high during the write cycle by writing data into the serial i/o register (address 00dd 16 ). after the ____ write cycle, the s rdy signal goes to l (receive enable state). the ____ s rdy signal goes to h at the next falling edge of the transfer clock for the serial i/o register. the serial i/o counter is set to 7 during write cycle into the serial i/ o register (address 00dd 16 ), and transfer clock goes high forcibly. at each falling edge of the transfer clock after the write cycle, serial data is output from the s out pin. transfer direction can be selected by bit 5 of the serial i/o mode register. at each rising edge of the transfer clock, data is input from the s in pin and data in the serial i/o register is shifted 1 bit. after the transfer clock has counted 8 times, the serial i/o counter becomes 0 and the transfer clock stops at high. at this time the interrupt request bit is set to 1. external clock : when an external clock is selected as the clock source, the interrupt request is set to 1 after the transfer clock has counted 8 counts. however, transfer operation does not stop, so the clock should be controlled externally. use the external clock of 1 mhz or less with a duty cycle of 50%. the serial i/o timing is shown in figure 19. when using an external clock for transfer, the external clock must be held at h for initializing the serial i/o counter. when switching between an internal clock and an external clock, do not switch during transfer. also, be sure to ini- tialize the serial i/o counter after switching. notes 1: on programming, note that the serial i/o counter is set by writing to the serial i/o register with the bit managing in- structions such as seb and clb. 2: when an external clock is used as the synchronous clock, write transmit data to the serial i/o register when the trans- fer clock input level is high. synchronous clock transfer clock serial i/o register write signal serial i/o output s out d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (see note) serial i/o input s in note : when an internal clock is selected, the s out pin is at high-impedance after transfer is completed. interrupt request bit is set to 1 receive signal enable s rdy mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 27 fig. 20. serial i/o mode register fig. 21. serial i/o control register b7 b6 b5 b4 b3 b2 b1 b0 serial i/o mode register (sm) [address 00de 16 ] b name functions after reset rw serial i/o mode register 0, 1 internal synchronous clock selection bits (sm0, sm1) (see note 1) b1 b0 0 0: f(x in )/4 or f(x cin )/4 0 1: f(x in )/16 or f(x cin )/16 1 0: f(x in )/32 or f(x cin )/32 1 1: f(x in )/64 or f(x cin )/64 2 synchronous clock selection bit (sm2) 3, 7 ports p4 0 , p4 1 function selection bits (sm3, sm7) p4 0 /s out2 / sda3/x cin p4 0 s out2 sda3 0: external clock 1: internal clock 0 0 0 rw rw rw 4, 6 ports p4 2 , p4 3 function selection bits (sm4, sm6) 5 transfer direction selection bit (sm5) 0: lsb first 1: msb first 0rw p4 1 /s clk2 / scl3/x cout p4 1 s clk2 scl3 b7 5 0 1 b3 0 1 p4 2 /s in2 / sda2/ad8 p4 2 sda2 p4 2 sda2 0rw p4 3 /s rdy2 / scl2/ad7 p4 3 s rdy2 sda2 b6 0 1 0 1 b4 0 1 notes 1: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. 2: when using ports p4 0 Cp4 3 as serial i/o pins, set bit 1 of the serial control register to 1. (see note 2) (see note 2) b7 b6 b5 b4 b3 b2 b1 b0 serial i/o control register (sic) [address 0207 16 ] b name functions after reset rw serial i/o control register 0 input signal to sift register selection bit (sic0) csio b0 0 0: input signal from s in1 0 1: input signal from s out1 (see note 1) 1 0: input signal from s in2 1 1: input signal from s out2 (see note 1) 1 serial i/o pin switch bit (csio) 0: s out1 , s clk1 , s in1 , s rdy1 1: s out2 , s clk2 , s in2 , s rdy2 0 0 rw rw notes 1: when inputting data from the s out pin, set ff 16 to the serial i/o register. 2: when using ports p4 4 Cp4 7 as serial i/o pins, set bit 1 of the serial i/o control register to 0. 3, 7 ports p4 7 function selection bits (sm3, sm7) (see note 2) p4 7 /s rdy1 /pwm8 p4 7 s rdy1 pwm8 0rw 4, 5 ports p4 4 , p4 5 function selection bits (sm4, sm6) (see note 2) 6 ports p4 6 function selection bits (sic6) (see note 2) b7 0 1 b3 5 0 1 p4 4 /s out1 / sda1 p4 4 s out1 sda1 0rw p4 5 /s clk1 / scl1 p4 5 s clk1 scl1 b5 0 1 b4 5 0 1 p4 6 /s in1 /pwm9 p4 6 pwm9 0rw b6 0 1 2 i 2 c-bus connection ports switch bit (sic2) 0: sda2, scl2, sda1, scl1 1: sda3, scl3 0rw mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 28 serial i/o common transmission/reception mode by writing 1 to bit 0 of the serial i/o control register, signals s in and s out are switched internally to be able to transmit or receive the serial data. figure 22 shows signals on serial i/o common transmission/recep- tion mode. note : when receiving the serial data after writing ff 16 to the serial i/o register. fig. 22. signals on serial i/o common transmission/reception mode s in2 s clk1 s out1 s in1 s clk2 s out2 csio clock 1 1 0 0 1 1 serial i/o shift register (8) sic0 csio 0 0 sic0 : bit 0 of seriali/o control register csio : bit 1 of serial i/o control register 29 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 2. multi-master i 2 c-bus interface functions item format communication mode scl clock frequency f : system clock = f(x in )/2 note: we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the con- trol function (bits 6 and 7 of the i 2 c control register at address 00f9 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 23 shows a block diagram of the multi-master i 2 c-bus inter- face and table 2 shows multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. fig. 23. block diagram of multi-master i 2 c-bus interface i 2 c address register (s0d) b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i c data shift register b0 data control circuit i 2 c clock control register (s2) system clock ( f ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i c status register (s1) b7 b0 bsel1 bsel0 10bit sad als bc2 bc1 bc0 i 2 c clock control register (s1d) bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 al circuit eso 2 2 30 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller (1) i 2 c data shift register the i 2 c data shift register (s0 : address 00d9 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00dc 16 ) is 1. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00f8 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the eso bit value. note: to write data into the i 2 c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. fig. 24. i 2 c data shift register fig. 25. i 2 c address register (2) i 2 c address register the i 2 c address register (address 00da 16 ) consists of a 7-bit slave ___ address and a read /write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. ____ n bit 0: read /write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. n bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. b7 b6 b5 b4 b3 b2 b1 b0 i c data shift register1(s0) [address 00d9 16 ] b functions after reset r w i c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate 2 2 note: 2 to write data into the i c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. name d0 to d7 rw b7 b6 b5 b4 b3 b2 b1 b0 0 read/write bit (rbw) 1 to 7 slave address (sad0 to sad6) 0: read 1: write 0 0the address data transmitted from the master is compared with the contents of these bits. i 2 c address register i 2 c address register (s0d) [address 00da 16 ] b name functions after reset rw r rw 31 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller (3) i 2 c clock control register the i 2 c clock control register (address 00dd 16 ) is used to set ack control, scl mode and scl frequency. n bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. refer to figure 26. n bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the stan- dard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. n bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made low (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made high (ack is not returned). ] ack clock: clock for acknowledgement n bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit gener- ated by the data receiving device. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. fig. 26. i 2 c clock control register b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2 : address 00dd 16 ) i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0 : standard clock mode 1 : high-speed clock mode 0 standard clock mode b name functions after reset rw 0 0 0 ack bit (ack bit) ack clock bit (ack) 0 : ack is returned. 1 : ack is not returned. 0 : no ack clock 1 : ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 33303 setup disabled 25004 100 400 (see note) 05 83.3 16606 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f (at f = 4 mhz, unit : khz) note: at 400 khz in the high-speed clock mode, the duty is as below . 0 period : 1 period = 3 : 2 in the other cases, the duty is as below. 0 period : 1 period = 1 : 1 setup value of ccr4Cccr0 rw rw rw rw 32 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller (4) i 2 c control register the i 2 c control register (address 00dc 16 ) controls the data commu- nication format. n bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. n bit 3: i 2 c interface use enable bit (eso) this bit enables usage of the multimaster i 2 c bus interface. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when eso = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 c status register at address 00f8 16 ). ? writing data to the i 2 c data shift register (address 00f6 16 ) is dis- abled. n bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to (5) i 2 c status register, bit 1) is received, trans- mission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recog- nized. fig. 28. i 2 c control register n bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00f7 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. n bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits controls the connection between scl and ports or sda and ports (refer to figure 28). fig. 27. connection port control by bsel0 and bsel1 0 1 bsel0 0 1 bsel1 scl1/p4 5 scl2/p4 3 multi-master i 2 c-bus interface scl sda scl3/p4 1 0 1 ciic (note 2) 0 1 bsel0 0 1 bsel1 sda1/p4 4 sda2/p4 2 sda3/p4 0 0 1 ciic (note 2) notes 1 : when using multi-master i 2 c-bus interface, set bits 3 to 7 of the serial i/o mode register (address 00de 16 ) to 1. 2 : ciic is bit 2 of the serial i/o control register (address 0207 16 ) (refer to figure 21). b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c-bus interface use enable bit (eso) 0 : disabled 1 : enabled 4 data format selection bit (als) 0 : addressing mode 1 : free data format 5 addressing format selection bit (10bit sad) 0 : 7-bit addressing format 1 : 10-bit addressing format 6, 7 connection control bits between i c-bus interface and ports b7 b6 connection port (see note) 0 0 : none 0 1 : scl1, sda1 1 0 : scl2, sda2 1 1 : scl1, sda1 scl2, sda2 0 0 0 0 0 i 2 c control register (s1d : address 00dc 16 ) i 2 c control register b name functions after reset rw note: when using ports p1 1 -p1 4 as i c-bus interface, the output structure changes automatically from cmos output to n-channel open-drain output. 2 2 rw rw rw rw rw 33 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller (5) i 2 c status register the i 2 c status register (address 00db 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. n bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by execut- ing a write instruction to the i 2 c data shift register (address 00d9 16 ). n bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start con- dition. ] general call: the master transmits the general call address 00 16 to all slaves. n bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions. ? the address data immediately after occurrence of a start condition matches the slave address stored in the high-order 7 bits of the i 2 c address register (address 00da 16 ). ? a general call is received. in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition. ? when the address data is compared with the i 2 c address register (8 bits consists of slave address and rbw), the first bytes match. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00d9 16 ). n bit 3: arbitration lost ] detecting flag (al) in the master transmission mode, when a device other than the mi- crocomputer sets the sda to l,, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the mst bit is set to 0. when arbitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. ] arbitration lost: the status in which communication as a master is disabled. n bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to 0 in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 30 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in any one of the following conditions. ? executing a write instruction to the i 2 c data shift register (address 00f6 16 ). ? when the eso bit is 0 ? at reset the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception 34 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller n bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condi- tion duplication prevention function (note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the eso bit of the i 2 c control register (address 00dc 16 ) is 0 and at reset, the bb flag is kept in the 0 state. n bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a trans- mitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00dc 16 ) is 0 in the slave reception mode is selected, the trx bit is set to 1 __ (transmit) if the least significant bit (r/w bit) of the address data trans- __ mitted by the master is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication prevention function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset n bit 7: communication mode specification bit (master/slave speci- fication bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when ar- bitration lost is detected ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? at reset note: the start condition duplication prevention function disables the start condition generation, reset of bit counter reset, and scl output, when the following condition is satisfied: ? a start condition is set by another master device. 35 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller fig. 30. interrupt request signal generation timing fig. 29. i 2 c status register scl pin iicirq b7 b6 b5 b4 b3 b2 b1 b0 i 2 c status register (s1) [address 00db 16 ] i 2 c status register 0 3 4 5 6, 7 b7 b6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 0 0 b name functions after reset rw communication mode specification bits (trx, mst) 0 : bus free 1 : bus busy bus busy flag (bb) 0 : interrupt request issued 1 : no interrupt request issued i 2 c-bus interface interrupt request bit (pin) 0 : not detected 1 : detected arbitration lost detecting flag (al) (see note) 0 : address mismatch 1 : address match slave address comparison flag (aas) (see note) 0 : no general call detected 1 : general call detected general call detecting flag (ad0) (see note) 0 : last bit = 0 1 : last bit = 1 last receive bit (lrb) (see note) note : these bits and flags can be read out, but cannnot be written. indeterminate r r r r r rw 0 rw 36 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller (9) start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 33 and table 4. only when the 3 conditions of table 4 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq is generated to the cpu. (8) stop condition generation method when the es0 bit of the i 2 c control register (address 00dc 16 ) is 1, execute a write instruction to the i 2 c status register (address 00db 16 ) for setting the mst bit and the trx bit to 1 and the bb bit to 0. a stop condition will then be generated. the stop condition genera- tion timing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 32 for the stop condition generation timing diagram, and table 3 for the start condition/stop condition generation timing table. fig. 32. stop condition generation timing diagram fig. 33. start condition/stop condition detect timing diagram table 4. start condition/stop condition detect conditions table 3. start condition/stop condition generation timing table item setup time hold time set/reset time for bb flag standard clock mode 5.0 s (20 cycles) 5.0 s (20 cycles) 3.0 s (12 cycles) high-speed clock mode 2.5 s (10 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles) note: absolute time at f = 4 mhz. the value in parentheses de- notes the number of f cycles. i 2 c status register write signal reset time for bb flag hold time setup time scl sda bb flag hold time setup time scl sda (start condition) sda (stop condition) scl release time hold time setup time (6) start condition generation method when the eso bit of the i 2 c control register (address 00dc 16 ) is 1, execute a write instruction to the i 2 c status register (address 00db 16 ) to set the mst, trx and bb bits to 1. a start condition will then be generated. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generation timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 31 for the start condition gen- eration timing diagram, and table 3 for the start condition/stop condition generation timing table. fig. 31. start condition generation timing diagram (7) restart condition generation method to generate the restart condition, take the following sequence: set 20 16 to the i 2 c status register (s1). write a transmit data to the i 2 c data shift register. set f0 16 to the i 2 c status register (s1) again. 37 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller (10) address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats is described below. 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00dc 16 ) to 0. the first 7-bit ad- dress data transmitted from the master is compared with the high- order 7-bit slave address stored in the i 2 c address register (ad- dress 00da 16 ). at the time of this comparison, address compari- son of the rbw bit of the i 2 c address register (address 00da 16 ) is not made. for the data transmission format when the 7-bit ad- dressing format is selected, refer to figure 34, (1) and (2). 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00dc 16 ) to 1. an address compari- son is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00da 16 ). at the time of this comparison, an ad- dress comparison between the rbw bit of the i 2 c address regis- __ ter (address 00da 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit __ addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00db 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 00d9 16 ), make an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2nd bytes matches the slave address, set the rbw bit of the i 2 c address register (address 00da 16 ) to 1 by software. this __ processing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00da 16 ). for the data transmis- sion format when the 10-bit addressing format is selected, refer to figure 34, (3) and (4). (11) example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 00da 16 ) and 0 in the rbw bit. set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 00dd 16 ). set 10 16 in the i 2 c status register (address 00db 16 ) and hold the scl at the high. set a communication enable status by setting 48 16 in the i 2 c control register (address 00dc 16 ). set the address data of the destination of transmission in the high- order 7 bits of the i 2 c data shift register (address 00d9 16 ) and set 0 in the least significant bit. set f0 16 in the i 2 c status register (address 00db 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. set transmit data in the i 2 c data shift register (address 00d9 16 ). at this time, an scl and an ack clock automatically occurs. when transmitting control data of more than 1 byte, repeat step . set d0 16 in the i 2 c status register (address 00db 16 ). after this, if ack is not returned or transmission ends, a stop condition will be generated. (12) example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode, using the addressing format, is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 00da 16 ) and 0 in the rbw bit. set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 00dd 16 ). set 10 16 in the i 2 c status register (address 00db 16 ) and hold the scl at the high. set a communication enable status by setting 48 16 in the i 2 c control register (address 00dc 16 ). when a start condition is received, an address comparison is made. ?when all transmitted addresses are 0 (general call) : ad0 of the i 2 c status register (address 00db 16 ) is set to 1 and an interrupt request signal occurs. ?when the transmitted addresses match the address set in : aas of the i 2 c status register (address 00db 16 ) is set to 1 and an interrupt request signal occurs. ?in the cases other than the above : ad0 and aas of the i 2 c status register (address 00db 16 ) are set to 0 and no interrupt request signal occurs. set dummy data in the i 2 c data shift register (address 00d9 16 ). when receiving control data of more than 1 byte, repeat step . when a stop condition is detected, the communication ends. 38 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller fig. 34. address data communication format s slave address a data a data a/a p r/w 7 bits ? 1 to 8 bits 1 to 8 bits s slave address a data a data ap 7 bits ? 1 to 8 bits 1 to 8 bits (1) a master-transmitter transmits data to a slave-receiver s slave address 1st 7 bits a a data 7 bits ? 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitter slave address 2nd byte a data a/a p 1 to 8 bits s slave address 1st 7 bits a a 7 bits ? 8 bits 7 bits (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address slave address 2nd byte data 1 to 8 bits sr slave address 1st 7 bits a data ap 1 to 8 bits? (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s : start condition p : stop condition a : ack bit r/w : read/write bit sr : restart condition from master to slave from slave to master r/w r/w r/w r/w mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 39 pwm output function this microcomputer is equipped with a 14-bit pwm (da) and ten 8- bit pwms (pwm0Cpwm9). da has a 14-bit resolution with the mini- mum resolution bit width of 250 ns and a repeat period of 4096 m s (for f(x in ) = 8 mhz). pwm0Cpwm9 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 m s and repeat period of 1024 m s (for f(x in ) = 8 mhz). figure 35 shows the pwm block diagram. the pwm timing generat- ing circuit applies individual control signals to pwm0Cpwm9 using f(x in ) divided by 2 as a reference signal. (1) data setting when outputting da, first set the high-order 8 bits to the da-h regis- ter (address 00ce 16 ), then the low-order 6 bits to the da-l register (address 00cf 16 ). when outputting pwm0Cpwm9, set 8-bit output data to the pwmi register (i means 0 to 9; addresses 00d0 16 to 00d4 16 , 00f6 16 to 00fa 16 ). (2) transferring data from registers to latches the data written to the 8-bit pwm register is transferred to the pwm latch in each 8-bit pwm cycle period. for 14-bit pwm, the data is transferred in the next high-order 8-bit period after the write. the signals output to the pwm pins correspond to the contents of these latches. when data in each pwm register is read, data in these latches has already been read allowing the data output by the pwm to be confirmed. however, bit 7 of the da-l register indicated the completion of the data transfer from the da register to the da latch. when bit 7 is 0, the transfer has been completed. when bit 7 is 1, the transfer has not yet begun. (3) operating of 8-bit pwm the following explains pwm operation. first, set the bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automatically), so that the pwm count source is supplied. pwm0Cpwm7 are also used as pins p6 0 Cp6 7, pwm8, pwm9 are also used as ports pins p4 7 , p4 6 , respectively. for pwm0Cpwm9, set the corresponding bits of the ports p4 or p6 direction register to 1 (output mode). and select each output polarity by bit 3 of pwm output control register 2(address 00d6 16 ). then, for pwm0Cpwm5, set bits 2 to 7 of pwm output control register 1 to 1 (pwm output). for pwm6 and pwm7, set bits 0 and 1 of the pwm output control register 2 to 1. for pwm8 and pwm9, set bits 3, 6 and 7 of the serial i/o control register to 1. the pwm waveform is output from the pwm output pins by setting these registers. figure 36 shows the 8-bit pwm timing. one cycle (t) is composed of 256 (2 8 ) segments. the 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. refer to figure 36 (a). the 8-bit pwm outputs waveform which is the logical sum (or) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit pwm register. several examples are shown in figure 36 (b). 256 kinds of output (high area: 0/256 to 255/256) are selected by changing the contents of the pwm register. a length of entirely high output cannot be output, i.e. 256/256. (4) operating of 14-bit pwm as with 8-bit pwm, set the bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automati- cally), so that the pwm count source is supplied. next, select the output polarity by bit 2 of pwm output control register 2 (address 00d6 16 ). then, the 14-bit pwm outputs from the d-a output pin by setting bit 1 of pwm output control register 1 to 0 (at reset, this bit already set to 0 automatically) to select the da output. the output example of the 14-bit pwm is shown in figure 37. the 14-bit pwm divides the data of the da latch into the low-order 6 bits and the high-order 8 bits. the fundamental waveform is determined with the high-order 8-bit data d h . a high area with a length t 5 d h (high area of funda- mental waveform) is output every short area of t = 256 t = 64 m s ( t is the minimum resolution bit width of 250 ns). the h level area increase interval (t m ) is determined with the low-order 6-bit data d l . the high are of smaller intervals t m shown in table 5 is longer by t than that of other smaller intervals in pwm repeat period t = 64t. thus, a rectangular waveform with the different high width is output from the d-a pin. accordingly, the pwm output changes by t unit pulse width by changing the contents of the da-h and da-l registers. a length of entirely high cannot be output, i. e. 256/256. (5) output after reset at reset, the output of ports p6 0 Cp6 7, p4 6 and p4 7 are in the high- impedance state, and the contents of the pwm register and the pwm circuit are undefined. note that after reset, the pwm output is undefined until setting the pwm register. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 40 pwm1 register (address : 00d1 16 ) 8 8-bit pwm circuit pn 3 p6 0 pw2 d6 0 pwm0 p6 1 pw3 d6 1 pwm1 p6 2 pw4 d6 2 pwm2 p6 3 pw5 d6 3 pwm3 p6 4 pw6 d6 4 pwm4 p6 5 pw7 d6 5 pwm5 inside of is as same contents with the others. selection gate : connected to black side at reset. pass gate pw : pwm output countrol register 1 pn : pwm output control register 2 p6 6 pn0 d6 6 pwm6 p6 7 pn1 d6 7 pwm7 d6 : port p6 direction register d4 : port p4 direction register s rdy1 sic3 d4 7 pwm8 p4 7 sic 7 p4 6 sic6 d4 6 pwm9 sic : serial i/o control register pwm2 register (address : 00d2 16 ) pwm3 register (address : 00d3 16 ) pwm4 register (address : 00d4 16 ) pwm5 register (address : 00f6 16 ) pwm6 register (address : 00f7 16 ) pwm7 register (address : 00f8 16 ) pwm8 register (address : 00f9 16 ) pwm9 register (address : 00fa 16 ) d-a/ad3 da-h register (address : 00ce 16 ) 1/2 x in timing generator for pwm pwm0 register (address : 00d0 16 ) 14-bit pwm circuit pn2 pn4 pw1 d-a msb da latch (14-bits) lsb 8 7 14 6 pw0 da-l register (address : 00cf 16 ) a-d msb b7 data bus pwm0 latch lsb b5 b0 b0b7 b0 b7 lsb table 5. relation between the low-order 6-bit data and high- level area increase interval area longer by t than that of other t m (m = 0 to 63) nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................. 57, 59, 61, 63 low-order 6 bits of data 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 fig. 35. pwm block diagram mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 41 fig. 36. 8-bit pwm timing (a) pulses showing the weight of each bit 1 3 5 7 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 8 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 128 bit 0 pwm output t = 4 m s t = 1024 m s f(x in ) = 8 mhz (b) example of 8-bit pwm t 00 16 (0) 01 16 (1) 18 16 (24) ff 16 (255) t = 256 t mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 42 fig. 37. 14-bit pwm (da) output example (at f(x in ) = 8 mhz) 250 ns b7 b0b6 b5 b4 b3 b2 b1 0 0 01 011 0 b13 b6 0 0 010 110 b0b5 1010 00 set 2c 16 to da-h register. [da-h register] d h at writing of da-l b0b6 b5 b4 b3 b2 b1 0 10 100 set 28 16 to da-l register. [da-l register] d l at writing of da-l undefined these bits decide h level area of fundamental waveform. these bits decide smaller interval tm in which h leval area is [h level area of fundamental waveform + t ]. = minimum resolution bit width 250 ns high-order 8-bit value of da latch 5 h level area of fundamental waveform ff 00d3fe fd d6 d4 02 01d5 14-bit pwm output 8-bit counter 250 ns 5 44 ff 00d3fe fd d6 d4 02 01d5 14-bit pwm output 8-bit counter 250 ns 5 44 fundamental waveform waveform of smaller interval tm specified by low-order 6 bits fundamental waveform of smaller interval tm which is not specified by low-order 6 bits is not changed. 14-bit pwm output low-order 6-bit output of da latch 250 ns 5 44 t = 250 ns t = 4096 s repeat period t 0 t 1 t 2 t 3 t 4 t 5 t 59 t 60 t 61 t 62 t 63 [da latch] b7 2c 2b 2a 03 02 01 00 2c 2b 2a 03 02 01 002d 2d latch transfer complete bit transfer complete transfer is not completed (automatically set at writing) 0 1 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 43 fig. 38. pwm output control register 1 b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 1 (pw) [address 00d5 b after reset rw pwm output control register 1 0 1 2 3 4 0 name functions da, pwm count source selection bit (pw0) 0 : count source supply 1 : count source stop p6 0 /pwm0 output selection bit (pw2) 0: p6 0 output 1: pwm0 output p6 1 /pwm1 output selection bit (pw3) 0: p6 1 output 1: pwm1 output p6 2 /pwm2 output selection bit (pw4) 0: p6 2 output 1: pwm2 output 5 p6 3 /pwm3 output selection bit (pw5) 0: p6 3 output 1: pwm3 output 6 p6 4 /pwm4 output selection bit (pw6) 0: p6 4 output 1: pwm4 output da/pn4 output selection bit (pw1) 0 : da output 1 : pn4 output 7 p6 5 /pwm5 output selection bit (pw7) 0: p6 5 output 1: pwm5 output 0 0 0 0 0 0 0 16 ] rw rw rw rw rw rw rw rw fig. 39. pwm output control register 2 b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 2 (pn) [address 00d6 b after reset rw pwm output control register 2 name functions 16 ] 2 3 4 da output polarity selection bit (pn3) 0 : positive polarity 1 : negative polarity pwm output polarity selection bit (pn4) da general-purpose output bit (pn5) 0 : output low 1 : output high 5 to 7 0 0 0 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 : positive polarity 1 : negative polarity rw rw rw r 0 p6 6 /pwm6 output selection bit (pn0) 0 : p6 6 output 1 : pwm6 output 0rw 1 p6 7 /pwm7 output selection bit (pn1) 0 : p6 7 output 1 : pwm7 output 0rw mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 44 a-d comparator a-d comparator consists of 6-bit d-a converter and comparator. a-d comparator block diagram is shown in figure 40. the reference voltage v ref for d-a conversion is set by bits 0 to 5 of the a-d control register 2 (address 020a 16 ). the comparison result of the analog input voltage and the reference voltage v ref is stored in bit 4 of the a-d control register 1 (address 00ef 16 ). for a-d comparison, set 0 to corresponding bits of the direction register to use ports as analog input pins. write the data for select of analog input pins to bits 0 to 2 of the a-d control register 1 and write the digital value corresponding to v ref to be compared to the bits 0 to 5 a-d control register 2. the voltage comparison starts by writing to the a-d control register 2, and it is completed after 16 machine cycles (nop instruction 5 8). fig. 40. a-d comparator block diagram a-d control register 1 bits 0 to 2 comparator control data bus bit 4 switch tree a-d control register 2 resistor ladder compa- rator analog signal switch bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a-d control register 1 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 45 fig. 41. a-d control register 1 fig. 42. a-d control register 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (adm) [address 00ef 16 ] b after reset rw a-d control register 1 0 to 2 analog input pin selection bits (adm0 to adm2) name functions b2 b1 b0 0 0 0 : ad1 0 0 1 : ad2 0 1 0 : ad3 0 1 1 : ad4 1 0 0 : ad5 1 0 1 : ad6 1 1 0 : ad7 1 1 1 : ad8 4 storage bit of comparison result (adm4) 0: input voltage < reference voltage 1: input voltage > reference voltage 0 indeterminate 0 3, 5 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. rw r r b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 2(adc) [address 020a 16 ] b after reset rw a-d control register 2 0 to 5 6, 7 indeterminate 0 name functions d-a converter set bits (adc0 to adc5) b0b1b2 b3 b4 b5 nothing is assigned. these bits are write disable bits. when these bits are reed out, the values are 0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3/128vcc : 5/128vcc : 123/128vcc : 125/128vcc : 127/128vcc : 1/128vcc rw r mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 46 crt display functions (1) outline of crt display functions table 6 outlines the crt display functions of this microcomputer. this microcomputer incorporates a crt display circuit of 24 charac- ters 5 3 lines. crt display is controlled by the crt control register. up to 256 kinds of characters can be displayed. the colors can be specified for each character and up to 4 kinds of colors can be dis- played on one screen. a combination of up to 15 colors can be ob- tained by using each output signal (r, g, b and i). characters are displayed in a 12 5 16 dots configuration to obtain smooth character patterns (refer to figure 43). the following shows the procedure how to display characters on the crt screen. write the display character code in the display ram. specify the display color by using the color register. write the color register in which the display color is set in the dis- play ram. specify the vertical position by using the vertical position register. specify the character size by using the character size register. specify the horizontal position by using the horizontal position register. write the display enable bit to the designated block display flag of the crt control register 1. when this is done, the crt display starts according to the input of the v sync signal. the crt display circuit has an extended display mode. this mode allows multiple lines (4 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewrit- ing data in the block for which display is terminated by software. figure 44 shows the crt display control register 1. figure 45 shows the block diagram of the crt display circuit. table 6. outline of crt display functions parameter number of display characters character display area kinds of characters kinds of character sizes color display expansion raster coloring character background coloring functions 24 characters 5 3 lines 12 5 16 dots (refer to figure 43) 256 kinds 4 kinds 1 screen : 4 kinds, maximum 15 kinds a character possible (multiline display) possible (maximum 15 kinds) possible (a character unit, 1 screen : 4 kinds, maximum 7 kinds) kinds of colors coloring unit mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 47 fig. 43. crt display character configuration 12 dots 16 dots fig. 44. crt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 crt control register 1 (cc) [address 00ea 16 ] b name functions after reset r w crt control register 1 0 all-blocks display control bit (cc0) (see note) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 block 2 display control bit (cc2) rw rw rw 7 0 note: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. fix this bit to 0. r w 0 3 0 : block 3 display off 1 : block 3 display on 0 block 3 display control bit (cc3) rw 4 0 : ordinary mode 1 : 1/2-character unit color specification mode 0 block 1 color specification mode switch bit (cc4) rw 5 0 : oscillation stopped 1 : oscillation enabled 0 display oscillation stop bit (cc5) rw 6 0 : ordinary 256 count mode 1 : double count mode 0 scanning line double count mode flag(cc6) rw mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 48 fig. 45. block diagram of crt display circuit crt control register (address 00ea 16 , 0208 16 ) vertical position registers (addresses 00e1 16 to 00e3 16 ) character size register (address 00e4 16 ) horizontal position register (address 00e0 16 ) border selection register (address 00e5 16 ) display oscillation circuit osc1 osc2 display position control circuit h sync v sync display control circuit 13 bytes 5 24 characters 5 1 line + 11bytes 5 24 characters 5 2 lines color registers (addresses 00e6 16 to 00e9 16 ) crt port control register (address 00ec 16 ) data bus rom for display 12 dots 5 16 dots 5 256 characters shift register 12 bits shift register 12 bits output circuit r g b i out border ram ram for display mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 49 (2) display position the display positions of characters are specified in units called a block. there are 3 blocks, blocks 1 to 3. up to 24 characters can be displayed in each block (refer to (4) memory for display). the display position of each block can be set in both horizontal and vertical directions by software. the display position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4t c (t c = oscillating cycle for display). the display position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. block 2 is displayed after the display of block 1 is completed (refer to figure 46 (a)). accordingly, if the display of block 2 starts during the display of block 1, only block 1 is displayed. similarly, when multiline display, block 1 is displayed after the display of block 2 is completed (refer to figure 46 (b)). the vertical position can be specified from 128-step positions (4 scan- ning lines per a step) for each block by setting values 00 16 to 7f 16 to bits 0 to 6 in the vertical position register (addresses 00e1 16 to 00e3 16 ). figure 48 shows the vertical position register. fig. 46. display position (hr) cv1 cv2 block 1 block 2 (a)example when each block is separated cv1 cv2 block 1 block 2 block 1 (second) cv1 no display no display (b)example when block 2 overlaps with block 1 block 3 cv3 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 50 the display position in the vertical direction is determined by count- ing the horizontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of h sync signal from after fixed cycle of rising edge (falling edge) of v sync signal. so interval from rising edge (falling edge) of v sync signal to rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) for avoiding jitter. the polarity of h sync and v sync signals can select with the crt port control register (address 00ec 16 ). fig. 48. vertical position register i fig. 47. supplement explanation for display position when bits 0 and 1 of the crt port control register (address 00ec 16 ) are set to 1 (negative polarity) v sync signal input v sync control signal in microcomputer 0.125 to 0.50 [ m s] ( at f(x in ) = 8mhz) period of counting h sync signal (note 2) h sync signal input not count 12345 notes 1 : the vertical position is determined by counting falling edge of h sync signal after rising edge of v sync control signal in the microcomputer. 2 : do not generate falling edge of h sync signal near rising edge of v sync control signal in microcomputer to avoid jitter. 8 machine cycles or more 8 machine cycles or more b7 b6 b5 b4 b3 b2 b1 b0 vertical position register i (cvi) (i = 1 to 3) [addresses 00e1 16 to 00e3 16 ] b name functions after reset r w vertical position register i 0 to 6 7 vertical display start positions 128 steps (00 16 to 7f 16 ) indeterminate 0 (cvi : cvi0 to cvi6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 51 the horizontal position is common to all blocks, and can be set in 64 steps (where 1 step is 4t osc , t osc being the display oscillation pe- riod) as values 00 16 to 3f 16 in bits 0 to 5 of the horizontal position register (address 00e0 16 ). the structure of the horizontal position register is shown in figure 49. fig. 49. horizontal position register b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hr) [address 00e0 16 ] b name functions after reset rw horizontal position register 0 to 5 6 horizontal display start positions (hr0 to hr5) 64 steps (00 16 to 3f 16 ) 0 0nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r 0 7 0 fix this bit to 0. r w mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 52 (3) character size the size of characters to be displayed can be from 4 sizes for each block. use the character size register (address 00e4 16 ) to set a char- acter size. the character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3; the character size of block 3 can be specified by using bits 4 and 5. figure 51 shows the character size register. the character size can be selected from 4 sizes: minimum size, me- dium size, large size and extra large size. each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (t c ) in the width (hori- zontal) direction. the minimum size consists of [1 scanning line] 5 [1t c ]; the medium size consists of [2 scanning lines] 5 [2t c ]; the large size consists of [3 scanning lines] 5 [3t c ]; and the extra large size consists of [4 scanning lines] 5 [4t c ]. table 7 shows the relation between the set values in the character size register and the charac- ter sizes. fig. 50. display start position of each character size (horizontal direction) mini- mum medium large horizontal display start position extra large mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 53 csn1 0 1 0 1 set values of character size register csn0 0 0 1 1 character size minimum medium large extra large width (horizontal) direction t c : oscillating cycle for display 1t c 2t c 3t c height (vertical) direction scanning lines 1 2 3 4 4t c note: the display start position in the horizontal direction is not affected by the character size. in other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to figure 50). table 7. relation between set values in character size register and character sizes fig. 51. character size register b7 b6 b5 b4 b3 b2 b1 b0 character size register (cs) [address 00e4 16 ] b name functions after reset r w character size register 0, 1 character size of block 1 selection bits (cs10, cs11) b1 b0 0 0 : minimum size 0 1 : medium size 1 0 : large size 1 1 : extra large size indeterminate 2, 3 character size of block 2 selection bits (cs20, cs21) indeterminate rw rw 6 indeterminate nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. r 4, 5 character size of block 2 selection bits (cs30, cs31) indeterminate rw 7 out signal output switch bit (cs7) 0 : out signal output 1 : mute signal output (see note) indeterminate rw note: this erases a video signal on an entire screen. b3 b2 0 0 : minimum size 0 1 : medium size 1 0 : large size 1 1 : extra large size b5 b4 0 0 : minimum size 0 1 : medium size 1 0 : large size 1 1 : extra large size mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 54 (4) memory for display there are 2 types of memory for display : crt display rom (ad- dresses 10000 16 to 12fff 16 ) used to store character dot data (masked) and crt display ram (addresses 0600 16 to 06d7 16 ) used to specify the colors and characters to be displayed. the following describes each type of display memory. rom for display (addresses 10000 16 to 12fff 16 ) the crt display rom contains dot pattern data for characters to be displayed. for characters stored in this rom to be actually displayed, it is necessary to specify them by writing the character code inherent to each character (code based on the addresses in the crt display rom) into the crt display ram. the character code list is shown in table 8. the crt display rom has a capacity of 12 k bytes. since 32 bytes are required for 1 character data, the rom can stores up to 384 kinds of characters. the crt display rom space is broadly divided into 2 areas. the [vertical 16 dots] 5 [horizontal (left side) 8 dots] data of display char- acters are stored in addresses 10000 16 to 107ff 16 , 11000 16 to 117ff 16 and 12000 16 to 127ff 16 ; the [vertical 16 dots] 5 [horizontal (right side) 4 dots] data of display characters are stored in addresses 10800 16 to 10fff 16 , 11800 16 to 11fff 16 and 12800 16 to 12fff 16 (refer to figure 52). note however that the high-order 4 bits in the data to be written to addresses 10800 16 to 10fff 16 , 11800 16 to 11fff 16 and 12800 16 to 12fff 16 must be set to 1 (by writing data fx 16 ). fig. 52. display character stored data 10xxf 16 , 11xxf 16 , or 12xxf 16 10xxf 16 +800 16 , 11xxf 16 +800 16 , or 12xxf 16 +800 16 00 0 0 0 0 0 0 0 0 0 0 1 1 1 000000 0000000 0000010 0000101 0001000 0001000 0001000 0010000 0 1 01 1111 001 0100000 0100000 0100000 0000000 0000101 0000010 0 1111 000 0000 0000 0 000 0000 0000 0000 0100 0 100 0100 0010 0010 0010 0 000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 b7 b0 b7 b0b3 10xx0 16 , 11xx0 16 , or 12xx0 16 10xx0 16 +800 16 , 11xx0 16 +800 16 , or 12xx0 16 +800 16 0 0000 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 55 table 8. character code list (partially abbreviated) 000 16 001 16 002 16 003 16 : 07e 16 07f 16 080 16 081 16 : 17d 16 17e 16 17f 16 character code 10800 16 to 1080f 16 10810 16 to 1081f 16 10820 16 to 1082f 16 10830 16 to 1083f 16 : 10fe0 16 to 10fef 16 10ff0 16 to 10fff 16 11800 16 to 1180f 16 11810 16 to 1181f 16 : 12fd0 16 to 12fdf 16 12fe0 16 to 12fef 16 12ff0 16 to 12fff 16 10000 16 to 1000f 16 10010 16 to 1001f 16 10020 16 to 1002f 16 10030 16 to 1003f 16 : 107e0 16 to 107ef 16 107f0 16 to 107ff 16 11000 16 to 1100f 16 11010 16 to 1101f 16 : 127d0 16 to 127df 16 127e0 16 to 127ef 16 127f0 16 to 127ff 16 left 8 dots lines character data storage address right 4 dots lines mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 56 most significant bit bit 4 at 0680 16 bit 4 at 0681 16 bit 4 at 0682 16 ; bit 4 at 0695 16 bit 4 at 0696 16 bit 4 at 0697 16 0698 16 to 069f 16 bit 4 at 06a0 16 bit 4 at 06a1 16 bit 4 at 06a2 16 ; bit 4 at 06b5 16 bit 4 at 06b6 16 bit 4 at 06b7 16 06b8 16 to 06bf 16 ram for display (addresses 0600 16 to 06d7 16 ) the crt display ram is allocated at addresses 0600 16 to 06d7 16 , and is divided into a display character code specification part and display color specification part for each block. table 9 shows the contents of the crt display ram. for example, to display 1 character position (the left edge) in block 1, write the character code in address 0600 16 and write the color register no. to the low-order 2 bits (bits 0 and 1) in address 0680 16 . the color register no. to be written here is one of the 4 color regis- ters in which the color to be displayed is set in advance. for details on color registers, refer to (5) color registers. the structure of the crt display ram is shown in figure 53. block 1 1st character 2nd character 3rd character ; 22nd character 23rd character 24th character color specification 0640 16 0641 16 0642 16 ; 0655 16 0656 16 0657 16 0658 16 to 067f 16 1st character 2nd character 3rd character ; 22nd character 23rd character 24th character block bit 4 at 06c0 16 bit 4 at 06c1 16 bit 4 at 06c2 16 ; bit 4 at 06d5 16 bit 4 at 06d6 16 bit 4 at 06d7 16 06d8 16 to 06ff 16 table 9. contents of crt display ram not used block 2 not used not used block 2 display position (from left) 1st character 2nd character 3rd character ; 22nd character 23rd character 24th character character code specification low-order 8 bits 0600 16 0601 16 0602 16 ; 0615 16 0616 16 0617 16 0618 16 to 061f 16 0620 16 0621 16 0622 16 ; 0635 16 0636 16 0637 16 0638 16 to 063f 16 0680 16 0681 16 0682 16 ; 0695 16 0696 16 0697 16 0698 16 to 069f 16 06a0 16 06a1 16 06a2 16 ; 06b5 16 06b6 16 06b7 16 06b8 16 to 06bf 16 06c0 16 06c1 16 06c2 16 ; 06d5 16 06d6 16 06d7 16 06d8 16 to 06ff 16 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 57 [color specification] b1 b0 0 0 : color register 0 specification 0 1 : color register 1 specification 1 0 : color register 2 specification 1 1 : color register 3 specification color register specification on left side (in ordinary 1/2-character unit color specification mode ) 0 block 1 [character specification] specify 384 characters (000 16 to 17f 16 ) (note) character code 70 1 st character : 0680 16 24th character : 0697 16 1 st character : 0600 16 24th character : 0617 16 70 b3 b2 0 0 : color register 0 specification 0 1 : color register 1 specification 1 0 : color register 2 specification 1 1 : color register 3 specification color register specification on right side (in 1/2-character unit color specification mode) 4 0 4 (block 3 : 0640 16 to 0657 16 ) (block 3 : 06c0 16 to 06d7 16 ) note : set values except 07e 16 , 07f 16 . to specify 384 characters (000 16 to 17f 16 ) (note) character code b1 b0 0 0 : color register 0 specification 0 1 : color register 1 specification 1 0 : color register 2 specification 1 1 : color register 3 specification color register specification block 2 [character specification] 1 st character : 0620 16 24th character : 0637 16 to to [color specification] 1 st character : 06a0 16 24th character : 06b7 16 to fig. 53. structure of ram for display mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 58 (5) color registers the color of a displayed character can be specified by setting the color to one of the 4 registers (co0 to co3: addresses 00e6 16 to 00e9 16 ) and then specifying that color register with the crt display ram. there are 4 color outputs; r, g, b and i. by using a combina- tion of these outputs, it is possible to set 2 4 C1 (when no output) = 15 colors. however, since only 4 color registers are available, up to 4 colors can be disabled at one time. r, g, b and i outputs are set by using bits 0 to 3 in the color register. bit 5 is used to specify whether a character output or blank output. bits 4, 6 and 7 are used to specify character background color. fig- ure 54 shows the structure of the color register. fig. 54. color register n b7 b6 b5 b4 b3 b2 b1 b0 color register n (co0 to co3) (n = 0 to 3) [addresses 00e6 16 to 00e9 16 ] b name functions after reset r w color register n 0 0 1 b signal output selection bit (con1) 0 : no character is output 1 : character is output 0 2 g signal output selection bit (con2) 0 : no character is output 1 : character is output 0 3 r signal output selection bit (con3) 0 : no character is output 1 : character is output 0 4 b signal output (background) selection bit (con4) 0 : no background color is output 1 : background color is output 0 5 out signal output control bit (con5) 0 : character is output 1 : blank is output 0 6 g signal output (background) selection bit (con6) 0 : no background color is output 1 : background color is output 0 7 r signal output (background) selection bit (con7) 0 : no background color is output 1 : background color is output 0 (see notes 1,2) (see notes 1, 2) notes 1: when bit 5 = 0 and bit 4 = 1, there is output same as a character or border output from the out pin. 2: when bit 5 = 0 and bit 4= 0, there is no output from the out pin. rw rw rw rw rw rw rw rw i signal output selection bit (con0) 0 : no character is output 1 : character is output mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 59 fig. 55. display example example 12 16 unwanted dots color registers (addresses 00e6 16 to 00e9 16 ) character 1 2 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 bit 7 bit 6 0 0 0 0 0 0 0 0 (r) (g) (b) (i) (r background) (out) 3 4 a b c g (green) 12 a 34 bc g+b (cyan) b (blue) r (red) g+b (cyan) r (red) r (red) tv screen character background b (blue) (g background) (b background) note : if border and background color are applied to a character in contact with a 12 5 16 -dot frame in the same block, the border (1 dot) is protruded from the frame. table 10. colorling to character background by r,g,b output signals color register bit 7 (b) bit 6 (g) bit 3 (r) 000 001 010 011 100 101 110 111 rgb output color black red green yellow blue magenta cyan white mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 60 table 11. display example of character background coloring (when green is set for a character and blue is set for background color) color registers con 7 con 6 con 5 con 4 con 3 con 2 con 1 g output b output out output character output 5 0100 no output green tv image is displayed on the character background. 5 5 1 1 0 0 no output same output as character a 5 green 0 blank output green 01100 01 background character a blue 00 0 100 blank output 01 black no output 0 0 con 0 0 no output 0 (note 1) (note 1) video signal and character color (green) are not mixed. tv image on the character background is not displayed. tv image on the character background is not displayed. green notes 1: when co n5 = 0 and co n4 = 1, there is output same as a character or border output from the out pin. when co n5 = 0 and co n4 = 0, there is no output from the out pin. 2: the portion a in which character dots are displayed is not mixed with any tv video signal. 3: the wavy-lined arrows in the table denote video signals. 4: n : 0 to 3, 5 : 0 or 1 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 61 ? the color on the left side : this is set to the color of the color register which is specified by bits 0 and 1 at the color specification addresses (addresses 0680 16 to 0697 16 ) in the crt display ram. ? the color on the right side : this is set to the color of the color register which is specified by bits 2 and 3 at the color specification addresses (addresses 0680 16 to 0697 16 ) in the crt display ram. fig. 56. difference between ordinary color specification mode and 1/2-character unit color specification mode color of the color register specified by bits 0 and 1 at address 0680 16 . block 1 (a) display in the ordinary mode color of the color register specified by bits 0 and 1 at address 0681 16 . block 2 color of the color register specified by bits 2 and 3 at address 0681 16 . color of the color register specified by bits 0 and 1 at address 0681 16 . (b) display in the 1/2-character unit color specification mode color of the color register specified by bits 2 and 3 at address 0680 16 . color of the color register specified by bits 0 and 1 at address 0680 16 . (6) 1/2-character unit color specification mode by setting 1 to bit 4 of crt control register 1 (address 00ea 16 ) it is possible to specify colors, in units of a 1/2-character size (16 dots high 5 6 dots wide), to characters in only block 1. in the 1/2-character unit color specification mode, colors of display characters in block 1 are specified as follows: mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 62 fig. 57. example of border aa aa a aa aa a a aa aa aa aa a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a aa aa aa a a aa aa aa aa a a a a a a aa aa aa aa a a a a aa aa a a aa aa aa aa aa aa a a aa aa aa aa a a aa a aa a aa aa aa aa aa aa aa aa aa aa a a aa aa a a aa aa aa aa aa aa a a aa aa aa aa aa aa a a aa aa aa aa a a aa aa a a aa aa aa aa aa aa aa aa aa aa a a aa aa aa aa (7) character border function an border of 1 clock (1 dot) equivalent size can be added to a char- acter to be displayed in both horizontal and vertical directions. the border is output from the out pin. border can be specified in units of block by using the border selec- tion register (address 00e5 16 ). the setting of the border takes prior- ity of the setting by bit 5 of the color register, however, the border of the character to which a background color has been set cannot be output. figure 58 shows the border selection register. table 12 shows the relationship between the values set in the border selection regis- ter and the character border function. mitsubishi microcomputers m37207mf-xxxsp/fp , M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 63 border selection register example of output functions mdn 1 5 0 border including character output ordinary r, g, b, i output out output r, g, b, i output out output table 12. relationship between set value in border selection register and character border function 1 border only output r, g, b, i output out output mdn 1 0 1 1 fig. 58. border selection register b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out output border selection bit (md10) 0 : same output as character output 1 : border output indeterminate 1 indeterminate 2 block 2 out output border selection bit (md20) 0 : same output as character output 1 : border output indeterminate rw rw rw 0 6, 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r block 1 out output switch bit (md11) 0 : border including character 1 : border only 3 indeterminate rw block 2 out output switch bit (md21) 0 : border including character 1 : border only 4 block 3 out output border selection bit (md30) 0 : same output as character output 1 : border output indeterminate rw 5 indeterminate rw block 3 out output switch bit (md31) 0 : border including character 1 : border only mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 64 (8) multiline display this microcomputer can ordinarily display 3 lines on the crt screen by displaying 3 blocks at different vertical positions. in addition, it can display up to 16 lines by using crt interrupts. a crt interrupt request occurs at the point at which display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. note: a crt interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display with the display control bit of the crt control reg- ister 1 (address 00ea 16 ), a crt interrupt request does not occur (refer to figure 59). fig. 59. timing of crt interrupt request block 1 (on display) ?rt interrupt request on display (crt interrupt request occurs at the end of block display) block 2 (on display) block 1' (on display) block 2' (on display) ?rt interrupt request ?rt interrupt request ?rt interrupt request block 1 (on display) ?rt interrupt request off display (crt interrupt request does not occur at the end of block display) block 2 (on display) block 1' (off display) block 2' (off display) ?rt interrupt request no ?rt interrupt request no ?rt interrupt request mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 65 fig. 60. display counter fig. 61. timing of crt interrupt request and display counter value the display block counter counts the number of times the display of a block has been completed, and its contents are incremented by 1 each time the display of one block is completed. to provide multi-line display, enable crt interrupts by clearing the interrupt disable flag to 0 and setting the crt interrupt enable bit (bit 4 of address 00fe 16 ) to 1. after that, process the following sequence within the crt interrupt processing routine: ead the value of the display block counter. the block for which display is terminated (i.e., the cause of crt interrupt generation) can be determined by the value read in . replace the display character data and vertical display position of that block with the character data (contents of crt display ram) and vertical display position (contents of vertical position register) to be displayed next. figure 60 shows the structure of the display block counter. 0 block 1 block 2 count value block 3 block 1 1 2 3 4 interrupt position b7 b6 b5 b4 b3 b2 b1 b0 display block counter (cbc) [address 00eb 16 ] b name functions after reset r w display block counter 0 to 3 number of blocks which are being displayed or has displayed (incremented each time a block is displayed) indeterminate rw 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r 4 to 7 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 66 (9) scanning line double count mode 1 dot in a displayed character is normally shown with 1 scanning line. in the scanning double count mode, 1 dot can be shown with 2 scan- ning lines. as a result, the displayed dot is extended 2 times the normal size in the vertical direction only (that is to say, the height of a character is extended twofold.) in addition, because the scanning line count is doubled, the display start position of a character becomes also twofold position in the vertical direction. in other words, the contents of the vertical position register is as fol- lows: ? in ordinary mode 256 steps as values 00 16 to ff 16 (4 scanning lines per step) ? in scanning line double count mode 128 steps as values 00 16 to 7f 16 (8 scanning lines per step) if the contents of the vertical position register for a block are set in the range of 80 16 to ff 16 in the scanning line double count mode, that block cannot be displayed (not output to the crt screen). the scanning line double count mode is specified by setting bit 6 of the crt control register 1 (address 00ea 16 ) to 1. since this function works in units of a screen, even if the mode is changed during display of 1 screen, the mode before the change remains until the display of the next screen. fig. 62. display in ordinary mode and in scanning line double count mode scanning line 32 lines a 5 2 vertical position a 5 2 (a) display in the ordinary mode (b) display in the scanning line double count mode vertical position a scanning line 16 lines mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 67 (10) wipe function wipe mode this microcomputer allows the display area to be gradually expanded or shrunk in the vertically direction in units of 1h (h: h sync signal). there are 3 modes for this scroll method. each mode has down and up modes, providing a total of 6 modes. table 13 shows the contents of each wipe mode. table 13. wipe operation in each mode and values of wipe mode register off mode wipe operation wipe mode register bit 2 bit 1 bit 0 down up appear from upper side 001 101 1 down up on off af bcde sx tuvw gl hijk mr nopq down up 010 110 down up off on af bcde sx tuvw gl hijk mr nopq down up 011 111 down up on off sx tuvw gl hijk mr nopq 2 3 af bcde erase from lower side erase from upper side appear from lower side erase from both upper and lower sides appear to both upper and lower sides mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 68 wipe speed the wipe speed is determined by the vertical synchronization (v sync ) signal. for the ntsc interlace method, assuming that v sync = 16.7 ms, 262.5 h sync signals (per field) we obtain the wipe speed as shown in table 14. wipe resolution varies with each wipe mode. in mode 1 and mode 2, one of 3 resolutions (1h, 2h, 4h) can be selected. in mode 3, wipe is done in units of 4h only. table 14. wipe speed (ntsc interlace method, h = 262.5) wipe speed (entire screen) 16.7 (ms) 5 262.5 ? 1 4 (s) 16.7 (ms) 5 262.5 ? 2 2 (s) 16.7 (ms) 5 262.5 ? 4 1 (s) table 15. wipe mode and wipe resolution wipe resolution 1h unit 2h unit 4h unit wipe resolution 1h unit 2h unit 4h unit 4h unit wipe speed about 4 (s) about 2 (s) about 1 (s) about 1 (s) mode mode 1 mode 2 mode 3 fig. 63. structure of wipe mode register b7 b6 b5 b4 b3 b2 b1 b0 wipe mode register (sl) [address 00ed 16 ] b name functions after reset r w wipe mode register 0, 1 wipe mode selection bits (sl0, sl1) b1 b0 0 0 : wipe is not available 0 1 : mode 1 1 0 : mode 2 1 1 : mode 3 0 2 direction mode selection bits (sl2) 0 rw rw 7 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. r 3, 4 wipe unit selection bits (sl3, sl4) 0 rw 0: down mode 1: up mode b4 b3 0 0 : 1h unit 0 1 : 2h unit 1 0 : 3h unit 1 1 : do not set 5, 6 stop mode selection bits (sl5, sl6) 0 rw b6 b5 0 0 : stop at the 312nd h 0 1 : stop at the 156th h 1 0 : stop at the 256th h 1 1 : stop at the 128th h mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 69 fig. 65. port control register (11) crt output pin control the crt output pins r, g, b, i and out can also function as ports p5 2 , p5 3 , p5 4 , p5 5 and p5 6 . set the corresponding bit of the port p5 control register (address 00cb 16 ) to 0 to specify these pins as crt output pins, or set it to 1 to specify it as a general-purpose port p5 pins. the input polarity of signals h sync and v sync and output polarity of signals r, g, b, i and out can be specified with the bits of the crt port control register (address 00ec 16 ). set a bit to 0 to specify posi- tive polarity; set it to 1 to specify negative polarity. the crt clock i/o pins osc1, osc2 are controlled with the port control register (address 0206 16 ). the crt port control register is shown in figure 64. the port control register is shown in figure 65. fig. 64. crt port control register b7 b6 b5 b4 b3 b2 b1 b0 crt port control register (crtp) [address 00ec 16 ] b name functions after reset r w crt port control register 0h sync input polarity switch bit (hsyc) 0 : positive polarity 1 : negative polarity 0 1 0 : positive polarity 1 : negative polarity 0 2 r, g, b output polarity switch bit (r/g/b) 0 : positive polarity 1 : negative polarity 0 3 i output polarity switch bit (i) 0 : positive polarity 1 : negative polarity 0 4 out output polarity switch bit (out) 0 : positive polarity 1 : negative polarity 0 5 r signal output switch bit (r) 0 : r signal output 1 : mute signal output 0 6 g signal output switch bit (g) 0 : g signal output 1 : mute signal output 0 7 b signal output switch bit (b) 0 : b signal output 1 : mute signal output 0 v sync input polarity switch bit (vsyc) rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 port control register (p7d) [address 0206 16 ] b name functions after reset r w port control register 0, 1 port p7 data input bits (p7d0, p7d1) when only op1 = 0 and op0 = 1, input data is valid. (see note) indeterminate 2 d-a/ad3 function selection bit (p7d2) 0 rw rw 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. r 4p4 0 /x cin , p4 1 /x cout function selection bit (p7d4) 0 : p4 0 , p4 1 1 : x cin , x cout 0 rw note: op is the crt clock selection register. 0: ad3 1: d-a 3, 5 to 7 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 70 fig. 66. example of raster coloring fig. 67. crt control register 2 (12) raster coloring function an entire screen (raster) can be colored by switching each of the r, g, and b pins to mute output. r, g, b are controlled with the crt port control register; i is controlled with the crt control register 2; out is controlled with the character size register. 15 raster colors can be obtained. if the out pin has been set to raster coloring output, a raster color- ing signal is always output during 1 horizontal scanning period. this setting is necessary for erasing a background tv image. if the r, g, and b pins have been set to mute signal output, a raster coloring signal is output in the part except a no-raster colored char- acter (in figure 66, a character o) during 1 horizontal scanning period. this ensures that character colors do not mix with the raster color. in this case, mute signal is output from the out pin. an example in which a magenta character i and a red character o are displayed with blue raster coloring is shown in figure 66. a'a red blue h sync r b out signals across a C a' b7 b6 b5 b4 b3 b2 b1 b0 crt control register 2 (cbr) [address 0208 16 ] b name functions after reset r w crt control register 2 0 i signal output switch bit (cbr0) 0: i signal output 1: mute signal output 0 1 i/tim1 function switch bit (cbr1) 0 rw rw 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. r 0: i output or mute output 1: 1/2 clock ouput of timer 1 2 to 7 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 71 fig. 68. crt clock selection register (13) clock for display as a clock for display to be used for crt display, it is possible to select one of the following 3 types. ? main clock supplied from the x in pin ? clock from the lc or rc supplied from the pins osc1 and osc2. ? clock from the ceramic resonator or quartz-crystal oscillator sup- plied from the pins osc1 and osc2. this clock for display can be selected for each block by the crt clock selection register (address 0209 16 ). when selecting the main clock, set the oscillation frequency to 8 mhz. b7 b6 b5 b4 b3 b2 b1 b0 crt clock selection register (op) [address 0209 16 ] b name functions after reset r w crt clock selection register 0, 1 crt clock selection bits (op0, op1) 0 since the main clock is used as the clock for display, the oscillation frequency is limited. because of this, the character size in width (horizontal) direction is also limited. in this case, pins osc1 and osc2 are also used as input ports p7 0 and p7 1 respectively. the clock for display is supplied by connecting the following across the pins osc1 and osc2. ? a ceramic resonator only for crt display and a feedback resistor ? a quartz-crystal oscillator only for crt display and a feedback resistor (see note) 2 to 6 0 0 b1 the clock for display is supplied by connecting rc or lc across the pins osc1 and osc2. functions 10 b0 crt oscillation frequency = f(x in ) notes 1: it is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins x in and x out . 2: cc6 is the scnanning line double count mode flag. 0 1 11 rw r cc6 cc6 = 0 or 1 cc6 = 0 cc6 = 0 1 0 do not set. 7 0 fix this bits to 0. rw nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos micr ocomputer f or vol tage synthesizer and on-screen displa y contr oller 72 interrupt interval determination function this microcomputer incorporates an interrupt interval determination circuit. this interrupt interval determination circuit has an 8-bit binary up counter as shown in figure 69. using this counter, it determines an interval on the int1 or int2 (refer to figure 72) . the following describes how the interrupt interval is determined. 1. the interrupt input to be determined (int1 input or int2 input) is selected by using bit 2 in the interrupt interval determination con- trol register (address 00d8 16 ). when this bit is cleared to 0, the int1 input is selected ; when the bit is set to 1, the int2 input is selected. 2. when the int1 input is to be determined, the polarity is selected by using bit 3 of the interrupt interval determination control register ; when the int2 input is to be determined, the polarity is selected by using bit 4 of the interrupt interval determination control register. when the relevant bit is cleared to 0, determination is made of the interval of a positive polarity (rising transition) ; when the bit is set to 1, determination is made of the interval of a negative po- larity (falling transition). 3. the reference clock is selected by using bit 1 of the interrupt inter- val determination control register. when the bit is cleared to 0, a 32 m s clock is selected ; when the bit is set to 1, a 16 m s clock is selected (based on an oscillation frequency of 8mhz in either case). 4. simultaneously when the input pulse of the specified polarity (rising or falling transition) occurs on the int1 pin (or int2 pin), the 8-bit binary up counter starts counting up with the selected reference clock (32 m s or 16 m s). 5. simultaneously with the next input pulse, the value of the 8-bit binary up counter is loaded into the interrupt interval determina- tion register (address 00d7 16 ) and the counter is immediately re- set (00 16 ). the reference clock is input in succession even after the counter is reset, and the counter restarts counting up from 00 16 . 6. when count value fe 16 is reached, the 8-bit binary up counter stops counting. then, simultaneously when the next reference clock is input, the counter sets value ff 16 to the interrupt inter- val determination register. the reference clock is generated by setting bit 0 of pwm mode register 1 to 0. fig. 69. block diagram of interrupt interval determination circuit 8 data bus control circuit connected to black colored side at rest. selection gate : (address 00d7 16 ) 32 m s re1 16 m s 8-bit binary up counter (8) interrupt interval determination register (8) re0 8 int1 (note) re2 int2 (note) note: the pulse width of external interrupt int1 and int2 needs 5 or more machine cycles. re : interrupt interval determination control register mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 73 fig. 70. interrupt interval determination control register int1 or int2 input count interval fig. 71. measuring interval b7 b6 b5 b4 b3 b2 b1 b0 interrupt interval determination control register (re) [address 00d8 16 ] b name functions after reset r w interrupt interval determination control register 0 interrupt interval determination circuit operation control bit (re0) 0 : stopped 1 : operating 0 1 reference clock selection bit (re1) 0 : 16 m s 1 : 32 m s (at f(x in ) = 8 mhz) 0 2 external interrupt input pin selection bit (re2) 0 : int1 input 1 : int2 input 0 3 int1 pin input polarity switch bit (re3) 0 : positive polarity input 1 : negative polarity input 0 4 int2 pin input polarity switch bit (re4) 0 : positive polarity input 1 : negative polarity input 0 5 to 7 0 rw rw rw rw rw r nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 74 rom correction function this can correct program data in rom. up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the rom cor- rection memory in ram. the rom memory for correction is 32 bytes 5 2 blocks. block 1 : addresses 02c0 16 to 02df 16 block 2 : addresses 02e0 16 to 02ff 16 set the address of the rom data to be corrected into the rom cor- rection address register. when the value of the counter matches the rom data address in the rom correction address, the main pro- gram branches to the correction program stored in the rom memory for correction. to return from the correction program to the main pro- gram, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. when the blocks 1 and 2 are used in series, the above instruction is not needed at the end of the block 1. the rom correction function is controlled by the rom correction enable register. notes 1 : specify the first address (op code address) of each instruction as the rom correction address. 2 : use the jmp instruction (total of 3 bytes) to return from the correction program to the main program. 3 : do not set the same rom correction address to the blocks 1 and 2. fig. 72. rom correction address registers fig. 73. rom correction enable register 0217 16 rom correction address 1 (high-order) 0218 16 rom correction address 1 (low-order) 0219 16 rom correction address 2 (high-order) 021a 16 rom correction address 2 (low-order) b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 021b 16 ] b after reset rw rom correction enable register 0 block 1 enable bit (rc0) name functions 0: disabled 1: enabled 1 block 2 enable bit (rc1) 0: disabled 1: enabled 4 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 rw rw r 00 2, 3 fix these bits to0. 0 rw mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 75 power source voltage 0 v reset input voltage 0 v 4.5 v 0.6 v poweron vcc reset vss microcomputer 1 5 4 3 0.1 m f m51953al reset circuit when the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 v 10 %, hold the ______ reset pin at low for 2 s or more, then return is to high. then, as shown in figure 75, reset is released and the program starts from the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address. the internal state of microcomputer at reset are shown in figure 75. an example of the reset circuit is shown in figure 74. the reset input voltage must be kept 0.6 v or less until the power source voltage surpasses 4.5 v. fig. 74. example of reset circuit fig. 75. reset sequence x in f reset internal reset sync address data 32768 count of x in clock cycle (note 3) reset address from the vector table ? ? 01, s 01, s-1 01, s-2 fffe ffff ad h , ad l ? ? ? ? ? ad l ad h notes 1 : : : f(x in ) and f( f ) are in the relation : f(x in ) = 2f ( f ). 2 a question mark (?) indicates an undefined state that depends on the previous state. 3 immediately after a reset, timer 3 and timer 4 are connected by hardware. at this time, ff 16 is set in timer 3 and 07 16 is set to timer 4. timer 3 counts down with f(x in )/16, and reset state is released by the timer 4 overflow signal. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 76 fig. 76. ceramic resonator circuit example fig. 77. external clock input circuit example (3) low-speed mode if the internal clock is generated from the sub-clock (x cin ), a low power consumption operation can be realized by stopping only the main clock x in . to stop the main clock, set bit 6 (cm 6 ) of the cpu mode register (00fb 16 ) to 1. when the main clock x in is restarted, the program must allow enough time to for oscillation to stabilize. note that in low-power-consumption mode the x cin -x cout drivability can be reduced, allowing even lower power consumption (20 m a with f (x cin ) = 32khz). to reduce the x cin -x cout drivability, clear bit 5 (cm 5 ) of the cpu mode register (00fb 16 ) to 0. at reset, this bit is set to 1 and strong drivability is selected to help the oscillation to start. when an stp instruction is executed, set this bit to 1 by soft- ware before executing. clock generating circuit this microcomputer has 2 built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no external re- sistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . when using x cin -x cout as sub-clock, clear bits 7 and 6 of the mixing control register to 0. to supply a clock signal externally, input it to the x in (x cin ) pin and make the x out (x cout ) pin open. when not using x cin clock, connect the x cin to v ss and make the x cout pin open. after reset has completed, the internal clock f is half the frequency of x in . immediately after poweron, both the x in and x cin clock start oscillating. to set the internal clock f to low-speed operation mode, set bit 7 of the cpu mode register (address 00fb 16 ) to 1. oscillation control (1) stop mode the built-in clock generating circuit is shown in figure 78. when the stp instruction is executed, the internal clock f stops at high. at the same time, timers 3 and 4 are connected by hardware and ff 16 is set in timer 3 and 07 16 is set in the timer 4. select f(x in )/16 or f(x cin )/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to 0 before the execution of the stp instruction). more- over, set the timer 3 and timer 4 interrupt enable bits to disabled (0) before execution of the stp instruction. the oscillator restarts when external interrupt is accepted. however, the internal clock f keeps its high until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. (2) wait mode when the wit instruction is executed, the internal clock f stops in the h level but the oscillator continues running. this wait state is released at reset or when an interrupt is accepted (note). since the oscillator does not stop, the next instruction can be executed at once. note: in the wait mode, the following interrupts are invalid. (1) v sync interrupt (2) crt interrupt (3) f(x in )/4096 interrupt (4) timer 1 and 2 interrupts using tim2 pin input as count source (5) timer 1 interrupt using f(x in )/4096 or f(x cin )/4096 as count source (6) timer 3 interrupt using tim3 pin input as count source (7) multi-master i 2 c-bus interface interrupt (8) timer 4 interrupt using f(x in )/2 or f(x cin )/2 as count souce x cin x in c cin microcomputer x cout r f r d c cout x out c in c out 26 25 30 31 x cin microcomputer external oscillation circuit or external pulse x cout x in x out open open external oscillation circuit vcc vss vcc vss mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 77 fig. 78. clock generating circuit block diagram x cin x cout p4 0 /x cin , p4 1 /x cout function selection bit (notes 1, 4) internal system clock selection bit (notes 1, 3) internal system clock selection bit (notes 1, 3) main clock (x in Cx out ) stop bit (notes 1, 3) r sq stp instruction wit instruction r s q reset interrupt disable flag i interrupt request r s q reset stp instruction timing (internal clock) timer 3 count source selection bit (notes 1,2) 1 timer 3 count stop bit (notes 1, 2) timer 4 count stop bit (notes 1, 2) timer 3 timer 4 1/2 1/8 x out x in 1 0 0 notes 1: 2: 3: 4: the value at reset is 0. refer to the structure of timer mode register 2. refer to the structure of cpu mode register (next page). refer to the structure of port control register. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 78 fig. 79. state transitions of system clock reset the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. the f indicates the internal clock. wit instruction cm7 : internal system clock selection bit 0 : x in Cx out selected (high-speed mode) 1 : x cin Cx cout selected (low-speed mode) cpu mode register (address : 00fb 16 ) cm6 : main clock (x in Cx out ) stop bit 0 : oscillating 1 : stopped 8mhz oscillating 32khz oscillating f is stopped (high) timer operating 8mhz oscillating 32khz oscillating f( f ) = 4mhz 8mhz stopped 32khz stopped f is stopped (high) 8mhz oscillating 32khz oscillating f is stopped (high) timer operating (note 3) 8mhz oscillating 32khz oscillating f( f ) = 16khz 8mhz stopped 32khz stopped f is stopped (high) 8mhz stopped 32khz stopped f = stopped (high) 8mhz stopped 32khz oscillating f( f ) = 16khz 8mhz stopped 32khz oscillating f is stopped (high) timer operating (note 3) interrupt stp instruction interrupt (note 1) wit instruction interrupt wit instruction interrupt stp instruction interrupt (note 2) stp instruction interrupt (note 2) xc = 1 xc = 0 cm6 = 1 cm6 = 0 external int, timer interrupt, or si/o interrupt external int, or si/o interrupt notes 1: when the stp state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: the delay after the stp state ends is approximately 2s. 3: when the internal clock f divided by 8 is used as the timer count source, the frequency of the count source is 2khz. the program must allow time for 8mhz oscillation to stabilize high-speed operation start mode wit instruction 8mhz oscillating 32khz oscillating f is stopped (high) timer operating 8mhz oscillating 32khz oscillating f( f ) = 4mhz 8mhz stopped 32khz stopped f is stopped (high) interrupt stp instruction interrupt (note 1) cm7 = 1 cm7 = 0 external int, timer interrupt, or si/o interrupt external int port control register (address : 0206 16 ) xc: p4 0 /x cin , p4 1 /x cout function selection bit 0 : p4 0 , p4 1 1 : x cin , x cout mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 79 addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to series 740 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 80 name of programming adapter pca4762 pca7417 product m37207efsp m37207effp data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (32-pin dip type 27c101, three identical copies) prom programming method the built-in prom of the one time prom version (blank) and the built-in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. the prom of the one time prom version (blank) is not tested or screened in the assembly process nor any following processes. to ensure proper operation after programming, the procedure shown in figure 82 is recommended to verify programming. fig. 82. programming and testing of one time prom version programming with prom programmer screening (caution) (150? for 40 hours) verification with prom programmer functional check in target device caution : the screening temperature is far higher than the storage temperature. never expose to 150? exceeding 100 hours. mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 81 min. 4.5 0 0.8v cc 0.7v cc 0 0 0 7.9 29 6.0 typ. 5.0 0 8.0 32 max. 5.5 0 v cc v cc 0.4 v cc 0.3 v cc 0.2 v cc 1 2 1 10 6 8.1 35 13 100 1 400 power source voltage (note 4), during cpu, crt operation power source voltage high input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 6, p6 0 Cp6 7 , p7 0 , p7 1 , h sync , v sync , ______ reset, x in , x cin , osc1, p4 0 Cp4 7 (including when using serial i/o) high input voltage sda3, scl3, s da2, scl2, sda1, scl1 (when using i 2 c-bus) low input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1, p3 5, p4 0 Cp4 7 , p7 0 , p7 1 low input voltage sda3, scl3, sda2, scl2, sda1, scl1 (when using i 2 c-bus) low input voltage ______ h sync , v sync , reset, p3 2 Cp3 4 , p3 6 , p4 1 , p4 2 , p4 4 Cp4 6 , x in , x cin , osc1 when using serial i/o; s out2 , s clk2 , s in2 , s out1 , s clk1 , s in1 high average output current (note 1) r, g, b, i, out, d-a, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 low average output current (note 2) r, g, b, i, out, d-a, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 6 low average output current (note 2) p4 6 , p4 7 , p6 0 Cp6 7 low average output current (note 3) p2 4 Cp2 7 low average output current (note 2) p4 0 Cp4 5 oscillation frequency (for cpu operation) (note 5) x in oscillation frequency (for sub-clock operation) (note 7)x cin oscillation frequency (for crt display) (note 6) osc1 input frequency tim2, tim3, int1, int2 input frequency s clk1 , s clk2 input frequency scl1, scl2, scl3 symbol v cc v i v i v o v o i oh i ol1 i ol2 i ol3 i ol4 p d t opr t stg absolute maximum ratings conditions all voltages are based on v ss . output transistors are cut off. t a = 25 c ratings C0.3 to 6 C0.3 to 6 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 C0.3 to 13 0 to 1 (note 1) 0 to 2 (note 2) 0 to 1 (note 2) 0 to 10 (note 3) 0 to 6 (note 2) 550 C10 to 70 C40 to 125 unit v v v v v ma ma ma ma ma mw c c parameter v v v v v v v ma ma ma ma ma mhz khz mhz khz mhz khz recommended operating conditions (t a = C10 c to 70 c, v cc = 5 v 10 %, unless otherwise noted) v cc v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 i ol2 i ol3 i ol4 f(x in ) f(x cin ) f osc f hs1 f hs2 f hs3 symbol parameter unit limits power source voltage v cc input voltage cnv ss input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 6 , p4 0 Cp4 7 , p6 0 Cp6 7 , p7 0 , p7 1 ,osc1, x in , h sync , ______ v sync , reset, x cin , ad1Cad8 output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 6 , p4 0 Cp4 5 , r, g, b, i, out, d-a, x out , x cout , osc2 output voltage p4 6 , p4 7 , p6 0 Cp6 7 circuit current r, g, b, i, out, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , d-a circuit current r, g, b, i, out, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 ,p3 0 Cp3 6 , d-a circuit current p4 6 , p4 7 , p6 0 Cp6 7 circuit current p2 4 Cp2 7 circuit current p4 0 Cp4 5 power dissipation operating temperature storage temperature mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 82 i cc v oh v ol v t+ Cv tC i izh i izl i ozh r bs power source current high output voltage r, g, b, i, out, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , d-a, p3 0 , p3 1 low output voltage r, g, b, i, out, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 6 , d-a low output voltage p4 6 , p4 7 , p6 0 Cp6 7 low output voltage p2 4 Cp2 7 low output voltage p4 0 Cp4 5 hysteresis ______ reset hysteresis (note 8) h sync , v sync , p3 2 , p3 3 , p3 4 , p3 6 , p4 0 Cp4 6 , high input leak current ______ reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 6 , p4 0 Cp4 7 , ad1Cad8 low input leak current ______ reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 6 , p4 0 Cp4 6 , p6 0 Cp6 7 , ad1Cad8 high output leak current p4 6 , p4 7 , p6 0 Cp6 7 i 2 c-busbus switch connection resistor (between scl1 and scl2, sda1 and sda2) min. 2.4 electric characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) limits typ. 15 30 100 2 60 1 0.5 0.5 max. 30 45 200 4 100 10 0.4 0.4 3.0 0.4 0.6 0.7 1.3 5 5 10 130 symbol parameter test conditions unit ma m a ma m a v v v m a m a m a w wait mode stop mode system operation crt off crt on v cc = 5.5 v, f(x in ) = 8 mhz notes 1: the total current that flows out of the ic must be 20 ma or less. 2: the total input current to ic (i ol1 + i ol2 + i ol4 ) must be 30 ma or less. 3: the total average input current for ports p2 4 Cp2 7 to ic must be 20 ma or less. 4: connect 0.022 m f or more capacitor externally between the power source pins v cc Cv ss so as to reduce power source noise. also connect 0.068 m f or more capacitor externally between the pins v cc Ccnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. 6: use a rc or an lc for the crt oscillation circuit. 7: when using the sub-clock, set f clk < f cpu /3. 8: p3 2 Cp3 4 ,p3 6 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p4 0 Cp4 6 have the hysteresis when these pins are used as serial i/o pins. v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32khz, crt off, low-power dissipation mode set (cm 5 = 0, cm 6 = 1) v cc = 5.5 v, f(x in ) = 8 mhz v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32khz, low-power dissipation mode set (cm 5 = 0, cm 6 = 1) v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 0 v cc = 4.5 v i oh = C0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 10.0 ma v cc = 4.5 v i ol = 3 ma i ol = 6 ma v cc = 5.0 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 5.5 v v o = 12 v v cc = 4.5 v mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 83 multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition l period of scl clock rising time of both scl and sda signals data hold time h period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd:sta t low t r t hd:dat t high t f t su:dat t su:sta t su:sto min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 m s m s m s ns m s m s ns ns m s m s unit standard clock mode high-speed clock mode parameter symbol note: c b = total capacitance of 1 bus line fig. 83. definition diagram of timing on multi-master i 2 c-bus resolution absolute accuracy max. 6 2 bits lsb min. 0 limits typ. unit test conditions parameter symbol 1 note: when vcc = 5 v, 1 lsb = 5/64 v. a-d comparator characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) sda scl p t buf s t hd : sta t low t r t hd : dat t high t f t su : dat t su : sta sr p t su : sto t hd : sta s sr p : start condition : restart condition : stop condition mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 84 package outline 64p4b 80p6nCa mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 85 gzzCsh08C83b < 48b0 > 740 family mask rom confirmation form single-chip microcomputer m37207mf-xxxsp/fp mitsubishi electric mask rom number date : supervisor signature receipt section head signature h customer company name date issued date : tel ( ) note : please fill in all items marked h . submitted by supervisor issuance signature h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 0000 16 product name ascii code : m37207mf C 000f 16 ffff 16 set ff 16 in the shaded area. write the ascii codes that indicates the product name of m37207mfC to addresses 0000 16 to 000f 16 . (1) (2) eprom type (indicate the type used) 0800 16 character rom 1-a 10800 16 12800 16 h 2. mark specification mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (64p4b for m37207mf-xxxsp, 80p6n for m37207mf-xxxfp) and attach to the mask rom confirmation form. (1/3) do you set ff 16 in the shaded area (set f 16 in the low-order 4-bit shaded area) ? do you write the ascii codes that indicates the product name of m37207mfC to addresses 0000 16 to 000f 16 ? eprom data check item (refer the eprom data and check in the appropriate box) ? yes ? yes l l 10000 16 11800 16 character rom 2-a data rom 62k bytes 11000 16 rom 1-b 12000 16 13000 16 1ffff 16 character rom 3-a character rom 2-b character rom 3-b character microcomputer name : m37207mf-xxxsp m37207mf-xxxfp mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 86 gzz?h08?3b <48b0 > 740 family mask rom confirmation form single-chip microcomputer m37207mf-xxxsp/fp mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 3 7 16 ? = 3 2 16 ? = 30 16 ? = 3 7 16 ? = 4d 16 ? = 46 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 0000 16 to 000f 16 store the product name, and addresses 10000 16 to 12fff 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. write the data correctly. inputting the name of the product with the ascii code ascii codes ?37207mf-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data by dividing it into character rom1, character rom2 and character rom3. for the character rom data, see the next page and on. 2. writing the product name and character rom data onto eproms (2/3) mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 87 gzz?h08?3b< 48b0 > 740 family mask rom confirmation form single-chip microcomputer m37207mf-xxxsp/fp mitsubishi electric the structure of character rom (divided of 12 5 16 dots font) example character code ? 16 character rom address 10000 16 +m000 16 +n0 16 +0 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 00 16 04 16 04 16 0a 16 0a 16 11 16 11 16 11 16 20 16 20 16 3f 16 40 16 40 16 40 16 00 16 00 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 character rom1 f 16 (3/3) 10000 16 +m000 16 +n0 16 +1 16 10000 16 +m000 16 +n0 16 +2 16 10000 16 +m000 16 +n0 16 +3 16 10000 16 +m000 16 +n0 16 +4 16 10000 16 +m000 16 +n0 16 +5 16 10000 16 +m000 16 +n0 16 +6 16 10000 16 +m000 16 +n0 16 +7 16 10000 16 +m000 16 +n0 16 +8 16 10000 16 +m000 16 +n0 16 +9 16 10000 16 +m000 16 +n0 16 +a 16 10000 16 +m000 16 +n0 16 +b 16 10000 16 +m000 16 +n0 16 +c 16 10000 16 +m000 16 +n0 16 +d 16 10000 16 +m000 16 +n0 16 +e 16 10000 16 +m000 16 +n0 16 +f 16 10800 16 +m000 16 +n0 16 +0 16 10800 16 +m000 16 +n0 16 +1 16 10800 16 +m000 16 +n0 16 +2 16 10800 16 +m000 16 +n0 16 +3 16 10800 16 +m000 16 +n0 16 +4 16 10800 16 +m000 16 +n0 16 +5 16 10800 16 +m000 16 +n0 16 +6 16 10800 16 +m000 16 +n0 16 +7 16 10800 16 +m000 16 +n0 16 +8 16 10800 16 +m000 16 +n0 16 +9 16 10800 16 +m000 16 +n0 16 +a 16 10800 16 +m000 16 +n0 16 +b 16 10800 16 +m000 16 +n0 16 +c 16 10800 16 +m000 16 +n0 16 +d 16 10800 16 +m000 16 +n0 16 +e 16 10800 16 +m000 16 +n0 16 +f 16 character rom addresscharacter rom data character rom data (k = ? 16 ? to ?7f 16 ? (m = ? 16 ? to ? 16 ? (n= ? 16 ? to ?f 16 ? character rom2 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 88 gzzCsh10C49b < 61a0 > 740 family mask rom confirmation form single-chip microcomputer M37207M8-XXXSP mitsubishi electric mask rom number date : supervisor signature receipt section head signature h customer company name date issued date : tel ( ) note : please fill in all items marked h . submitted by supervisor issuance signature h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 0000 16 product name ascii code : m37207m8 C 000f 16 ffff 16 set ff 16 (f 16 in the high-order 4-bit shaded area) in the shaded area. write the ascii codes that indicate the product name of m37207m8C to addresses 0000 16 to 000f 16 . (1) (2) eprom type (indicate the type used) 8000 16 character rom 1-a 10800 16 h 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill out the appropriate mark specification form (64p4b for M37207M8-XXXSP) and attach to the mask rom confirmation form. (1/3) is ff 16 in the shaded area (set f 16 in the high-order 4-bit shaded area) ? are the ascii codes that indicates the product name of m37207m8C to addresses 0000 16 to 000f 16 ? eprom data check item (confirm the eprom data and check the appropriate box) ? yes ? yes l l 10000 16 11800 16 character rom 2-a data rom 32 k bytes 11000 16 rom 1-b 12000 16 1ffff 16 character rom 2-b character microcomputer name : M37207M8-XXXSP mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 89 gzz?h10?9b <61a0 > 740 family mask rom confirmation form single-chip microcomputer M37207M8-XXXSP mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 3 7 16 ? = 3 2 16 ? = 30 16 ? = 3 7 16 ? = 4d 16 ? = 38 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 0000 16 to 000f 16 store the product name, and addresses 10000 16 to 11fff 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. please make sure the data is written correctly. how to input the name of the product with the ascii code : ascii codes ?37207m8-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. for the character rom data, see the next page and on. 2. how to write the product name and character rom data onto eproms (2/3) mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller 90 90 gzz?h10?9b< 61a0 > 740 family mask rom confirmation form single-chip microcomputer M37207M8-XXXSP mitsubishi electric the structure of character rom (divided of 12 5 16 dots font) example character code ? 16 character rom address 10000 16 +m000 16 +n0 16 +0 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 00 16 04 16 04 16 0a 16 0a 16 11 16 11 16 11 16 20 16 20 16 3f 16 40 16 40 16 40 16 00 16 00 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 character rom1 f 16 (3/3) 10000 16 +m000 16 +n0 16 +1 16 10000 16 +m000 16 +n0 16 +2 16 10000 16 +m000 16 +n0 16 +3 16 10000 16 +m000 16 +n0 16 +4 16 10000 16 +m000 16 +n0 16 +5 16 10000 16 +m000 16 +n0 16 +6 16 10000 16 +m000 16 +n0 16 +7 16 10000 16 +m000 16 +n0 16 +8 16 10000 16 +m000 16 +n0 16 +9 16 10000 16 +m000 16 +n0 16 +a 16 10000 16 +m000 16 +n0 16 +b 16 10000 16 +m000 16 +n0 16 +c 16 10000 16 +m000 16 +n0 16 +d 16 10000 16 +m000 16 +n0 16 +e 16 10000 16 +m000 16 +n0 16 +f 16 10800 16 +m000 16 +n0 16 +0 16 10800 16 +m000 16 +n0 16 +1 16 10800 16 +m000 16 +n0 16 +2 16 10800 16 +m000 16 +n0 16 +3 16 10800 16 +m000 16 +n0 16 +4 16 10800 16 +m000 16 +n0 16 +5 16 10800 16 +m000 16 +n0 16 +6 16 10800 16 +m000 16 +n0 16 +7 16 10800 16 +m000 16 +n0 16 +8 16 10800 16 +m000 16 +n0 16 +9 16 10800 16 +m000 16 +n0 16 +a 16 10800 16 +m000 16 +n0 16 +b 16 10800 16 +m000 16 +n0 16 +c 16 10800 16 +m000 16 +n0 16 +d 16 10800 16 +m000 16 +n0 16 +e 16 10800 16 +m000 16 +n0 16 +f 16 character rom addresscharacter rom data character rom data (k = ? 16 ? to ?7f 16 ? (m = ? 16 ? to ? 16 ? (n= ? 16 ? to ?f 16 ? character rom2 m i t s u b i s h i m i c r o c o m p u t e r s m 3 7 2 0 7 m f - x x x s p / f p , m 3 7 2 0 7 m 8 - x x x s p m 3 7 2 0 7 e f s p / f p s i n g l e - c h i p 8 - b i t c m o s m i c r o c o m p u t e r f o r v o l t a g e s y n t h e s i z e r a n d o n - s c r e e n d i s p l a y c o n t r o l l e r 9 1 9 1 6 4 p 4 b ( 6 4 - p i n s h r i n k d i p ) m a r k s p e c i f i c a t i o n f o r m m i t s u b i s h i m i c r o c o m p u t e r s m 3 7 2 0 7 m f - x x x s p / f p , m 3 7 2 0 7 m 8 - x x x s p m 3 7 2 0 7 e f s p / f p s i n g l e - c h i p 8 - b i t c m o s m i c r o c o m p u t e r f o r v o l t a g e s y n t h e s i z e r a n d o n - s c r e e n d i s p l a y c o n t r o l l e r 9 2 8 0 p 6 n ( 8 0 - p i n q f p ) m a r k s p e c i f i c a t i o n f o r m 93 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller appendix pin configuration (top view) outline 64p4b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 p6 5 /pwm5 p4 1 /s clk2 /scl3/x cout osc1/p7 0 /ad4 osc2/p7 1 /ad5 p3 6 /int2/ad2 p3 5 /ad1 p3 4 /int1 d-a/ad3 p6 0 /pwm0 p6 1 /pwm1 p6 6 /pwm6 p6 7 /pwm7 p3 3 /tim3 p3 2 /tim2/ad6 p3 1 p3 0 p4 7 / s rdy1 /pwm8 p4 6 /s in1 /pwm9 p4 3 / s rdy2 /scl2/ad7 p4 2 /s in2 /sda2/ad8 p4 0 /s out2 /sda3/x cin v cc h sync v sync r/p5 2 g/p5 3 b/p5 4 i/p5 5 /tim1 overflow p0 7 p1 1 p1 3 p1 5 p1 6 p1 7 p2 0 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p2 1 p6 2 /pwm2 p6 3 /pwm3 p6 4 /pwm4 p4 5 /s clk1 /scl1 p4 4 /s out1 /sda1 out/p5 6 p0 0 p0 4 p0 5 p0 6 22 23 24 25 26 43 42 41 40 39 m37207mf-xxxsp, M37207M8-XXXSP m37207efsp f cnv ss reset x out x in v ss 27 28 29 30 31 32 38 37 36 35 34 33 p0 1 p0 2 p0 3 p1 0 p1 2 p1 4 94 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller pin configuration (top view) outline 80p6n-a nc: unconnected p0 7 55 43 reset cnv ss x in p0 4 p0 5 p0 6 28 40 39 37 38 36 35 34 33 32 31 30 29 27 26 25 51 41 44 45 46 47 48 50 58 52 59 57 56 60 61 63 62 42 49 nc nc nc nc nc nc nc nc nc nc nc nc nc 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 24 23 22 21 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 nc 64 54 53 p6 5 /pwm5 p6 0 /pwm0 p6 1 /pwm1 p6 6 /pwm6 p6 7 /pwm7 p3 3 /tim3 p3 2 /tim2/ad6 p3 1 p3 0 p4 6 /s in1 /pwm9 p6 2 /pwm2 p6 3 /pwm3 p6 4 /pwm4 p4 5 /s clk1 /scl1 f x out v ss osc1/p7 0 /ad4 osc2/p7 1 /ad5 p3 6 /int2/ad2 p3 5 /ad1 p3 4 /int1 d-a/ad3 v cc h sync v sync r/p5 2 g/p5 3 b/p5 4 i/p5 5 /tim1 overflow p1 1 p1 3 p1 5 p1 6 p1 7 p2 0 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p2 1 out/p5 6 p0 0 p0 1 p0 2 p0 3 p1 0 p1 2 p1 4 m37207mf-xxxfp, m37207effp nc nc p4 7 / s rdy1 /pwm8 p4 4 /s out1 /sda1 p4 3 / s rdy2 /scl2/ad7 p4 2 /s in2 /sda2/ad8 p4 1 /s clk2 /scl3/x cout p4 f /s out2 /sda3/x cin 95 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller memory map 0000 16 00c0 16 00ff 16 01ff 16 033f 16 0800 16 sfr area not used not used ffff 16 ffde 16 ff00 16 0300 16 interrupt vector area not used 10000 16 11fff 16 1ffff 16 rom for display (8 k bytes) for m37207m8 special page rom (32 k bytes) for m37207m8 ram for display (144 bytes) (see note) zero page note: refer to table 9. contents of crt display ram. 0204 16 021b 16 02c0 16 02ff 16 2 page register not used 06d7 16 0600 16 not used rom correction memory (64 bytes) block 1: addresses 02c0 16 to 02df 16 block 2: addresses 02e0 16 to 02ff 16 8000 16 04ff 16 12fff 16 rom for display (12 k bytes) for m37207mf rom (62 k bytes) for m37207mf ram (512 bytes) for m37207m8 ram (960 bytes) for m37207mf 96 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller memory map of special function register (sfr) n sfr area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 control register (d5) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o regsiter (sio) bit allocation state immediately after reset : 0 immediately after reset : undefined immediately after reset 0 1 ? 97 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller b7 b0 bit allocation state immediately after reset b7 b0 : 0 immediately after reset : undefined immediately after reset 0 1 ? 98 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller address register n sfr area (addresses 204 16 to 21b 16 ) 210 16 211 16 212 16 213 16 214 16 215 16 216 16 217 16 218 16 219 16 21a 16 21b 16 rom correction address 1 (high-order) rom correction address 1 (low-order) rom correction address 2 (high-order) rom correction address 2 (low-order) rom correction enable register (rcr) b7 b0 bit allocation state immediately after reset b7 b0 : 0 immediately after reset : undefined immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 ?? p7d0 00 16 00 16 0 000 00 op1op0 00 16 00 16 0 00 16 ?? 0 0?? ?? 00 16 p7d1p7d2p7d4 cbr0cbr1 adc0adc1adc2adc3adc4adc5 sic0sic1sic2sic3sic4sic5sic8sic7 tmr30 ? ? ? ? 00 rc1 rc0 ? ? ? ? 00 16 00 16 00 16 00 16 ? ??? 00 0 0 ? ? ? 204 16 205 16 206 16 207 16 208 16 209 16 20a 16 20b 16 20c 16 20d 16 20e 16 20f 16 timer 5 (t5) timer 6 (t6) port control register (p7d) serial i/o control register (sic) crt control register 2 (cbr) crt clock selection register (op) a-d control register (adc) timer mode register (tmr3) 99 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller internal state of processor status register and program counter at reset b7 b0 b7 b0 1 register processor status register (ps) bit allocation state immediately after reset program counter (pc h ) program counter (pc l ) i zcdbtv n????? ?? contents of address ffff 16 contents of address fffe 16 : 0 immediately after reset : undefined immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 100 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: values immediately after reset release bit attributes (note 1) (note 2) bits 2: bit attributes??????the attributes of control register bits are classified into 3 types : read-only, write-only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is assigned notes 1: values immediately after reset release 0??????0 after reset release 1??????1 after reset release ???????indeterminate after reset release ??????read enabled ??????read disabled r??????read ??????write enabled ??????write disabled ??????0 can be set by software, but 1 cannot be set. w??????write 5 ] b7 b6 b5 b4 b3 b2 b1 b0 b after reset rw cpu mode register 0, 1 2 3, 4 0 1 1 name functions processor mode bits (cm0, cm1) 0 0: single-chip mode 0 1: 1 0: not available 1 1: fix these bits to 1. 0 stack page selection bit (note) (cm2) 1 b1 b0 0: 0 page 1: 1 page 100 5 nothing is assigned. this bit is write disable bit. when this bit is read out, the value is 0. 6, 7 0 clock switch bits (cm6, cm7) 0 0: f(x in ) = 8 mhz 0 1: f(x in ) = 12 mhz 1 0: f(x in ) = 16 mhz 1 1: do not set b7 b6 cpu mode register (cpum) (cm) [address fb 16 ] rw rw rw rw rw [example] 5 101 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller port pi direction register port p3 direction register addresses 00c1 16 , 00c3 16 , 00c5 16 , 00cd 16 address 00c7 16 b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (di) (i=0,1,2, 6) [addresses 00c1 16, 00c3 16 , 00c5 16 , 00cd 16 ] b name functions after reset r w port pi direction register 0 0 : port pi 0 input mode 1 : port pi 0 output mode 0 1 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 0 : port pi 2 input mode 1 : port pi 2 output mode 0 3 0 : port pi 3 input mode 1 : port pi 3 output mode 0 4 0 : port pi 4 input mode 1 : port pi 4 output mode 0 5 0 : port pi 5 input mode 1 : port pi 5 output mode 0 6 0 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 port p3 direction register (d3) [address 00c7 16 ] b name functions after reset rw port p3 direction register 0 0 : port p3 0 input mode 1 : port p3 0 output mode 0 1 0 : port p3 1 input mode 1 : port p3 1 output mode 0 2 0 : port p3 2 input mode 1 : port p3 2 output mode 0 0 port p3 direction register nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw rw rw r 3 0 : port p3 3 input mode 1 : port p3 3 output mode 0rw 6 0rw 7 0 : port p3 4 input mode 1 : port p3 4 output mode 0rw 0 : port p3 5 input mode 1 : port p3 5 output mode 0rw 4 5 0 : port p3 6 input mode 1 : port p3 6 output mode 102 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller port p5 control register pwm output control register 1 address 00cb 16 address 00d5 16 b7 b6 b5 b4 b3 b2 b1 b0 port p5 control register (d5) [address 00cb 16 ] b name functions after reset r w port p5 control register 0 0 2 3 0 : g signal output 1 : port p5 3 output 0 0 r rw rw rw 0, 1, 7 port p5 3 output signal selection bit (g) 4 0 : b signal output 1 : port p5 4 output 0rw port p5 4 output signal selection bit (b) 0rw 0 : r signal output 1 : port p5 2 output port p5 2 output signal selection bit (r) 5 0 : i/tim1 overflow signal output 1 : port p5 5 output port p5 5 output signal selection bit (i) 6 0 : out signal output 1 : port p5 6 output port p5 6 output signal selection bit (out) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 1 (pw) [address 00d5 b after reset rw pwm output control register 1 0 1 2 3 4 0 name functions da, pwm count source selection bit (pw0) 0 : count source supply 1 : count source stop p6 0 /pwm0 output selection bit (pw2) 0: p6 0 output 1: pwm0 output p6 1 /pwm1 output selection bit (pw3) 0: p6 1 output 1: pwm1 output p6 2 /pwm2 output selection bit (pw4) 0: p6 2 output 1: pwm2 output 5 p6 3 /pwm3 output selection bit (pw5) 0: p6 3 output 1: pwm3 output 6 p6 4 /pwm4 output selection bit (pw6) 0: p6 4 output 1: pwm4 output da/pn4 output selection bit (pw1) 0 : da output 1 : pn4 output 7 p6 5 /pwm5 output selection bit (pw7) 0: p6 5 output 1: pwm5 output 0 0 0 0 0 0 0 16 ] rw rw rw rw rw rw rw rw 103 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller interrupt interval determination control register address 00d6 16 address 00d8 16 pwm output control register b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 2 (pn) [address 00d6 b after reset rw pwm output control register 2 name functions 16 ] 2 3 4 da output polarity selection bit (pn3) 0 : positive polarity 1 : negative polarity pwm output polarity selection bit (pn4) da general-purpose output bit (pn5) 0 : output low 1 : output high 5 to 7 0 0 0 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 : positive polarity 1 : negative polarity rw rw rw r 0 p6 6 /pwm6 output selection bit (pn0) 0 : p6 6 output 1 : pwm6 output 0rw 1 p6 7 /pwm7 output selection bit (pn1) 0 : p6 7 output 1 : pwm7 output 0rw b7 b6 b5 b4 b3 b2 b1 b0 interrupt interval determination control register (re) [address 00d8 16 ] b name functions after reset r w interrupt interval determination control register 0 interrupt interval determination circuit operation control bit (re0) 0 : stopped 1 : operating 0 1 reference clock selection bit (re1) 0 : 16 m s 1 : 32 m s (at f(x in ) = 8 mhz) 0 2 external interrupt input pin selection bit (re2) 0 : int1 input 1 : int2 input 0 3 int1 pin input polarity switch bit (re3) 0 : positive polarity input 1 : negative polarity input 0 4 int2 pin input polarity switch bit (re4) 0 : positive polarity input 1 : negative polarity input 0 5 to 7 0 rw rw rw rw rw r nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 104 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller i 2 c adress register i 2 c data shift register address 00d9 16 address 00da 16 b7 b6 b5 b4 b3 b2 b1 b0 i c data shift register1(s0) [address 00d9 16 ] b functions after reset r w i c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate 2 2 note: 2 to write data into the i c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. name d0 to d7 rw b7 b6 b5 b4 b3 b2 b1 b0 0 read/write bit (rbw) 1 to 7 slave address (sad0 to sad6) 0: read 1: write 0 0the address data transmitted from the master is compared with the contents of these bits. i 2 c address register i 2 c address register (s0d) [address 00da 16 ] b name functions after reset rw r rw 105 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller i 2 c control register i 2 c status register address 00dc 16 address 00db 16 b7 b6 b5 b4 b3 b2 b1 b0 i 2 c status register (s1) [address 00db 16 ] i 2 c status register 0 3 4 5 6, 7 b7 b6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 0 0 b name functions after reset rw communication mode specification bits (trx, mst) 0 : bus free 1 : bus busy bus busy flag (bb) 0 : interrupt request issued 1 : no interrupt request issued i 2 c-bus interface interrupt request bit (pin) 0 : not detected 1 : detected arbitration lost detecting flag (al) (see note) 0 : address mismatch 1 : address match slave address comparison flag (aas) (see note) 0 : no general call detected 1 : general call detected general call detecting flag (ad0) (see note) 0 : last bit = 0 1 : last bit = 1 last receive bit (lrb) (see note) note : these bits and flags can be read out, but cannnot be written. indeterminate r r r r r rw 0 rw b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c-bus interface use enable bit (eso) 0 : disabled 1 : enabled 4 data format selection bit (als) 0 : addressing mode 1 : free data format 5 addressing format selection bit (10bit sad) 0 : 7-bit addressing format 1 : 10-bit addressing format 6, 7 connection control bits between i c-bus interface and ports b7 b6 connection port (see note) 0 0 : none 0 1 : scl1, sda1 1 0 : scl2, sda2 1 1 : scl1, sda1 scl2, sda2 0 0 0 0 0 i 2 c control register (s1d : address 00dc 16 ) i 2 c control register b name functions after reset rw note: when using ports p1 1 -p1 4 as i c-bus interface, the output structure changes automatically from cmos output to n-channel open-drain output. 2 2 rw rw rw rw rw 106 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller serial i/o mode register i 2 c clock control register address 00dd 16 address 00de 16 b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2 : address 00dd 16 ) i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0 : standard clock mode 1 : high-speed clock mode 0 standard clock mode b name functions after reset rw 0 0 0 ack bit (ack bit) ack clock bit (ack) 0 : ack is returned. 1 : ack is not returned. 0 : no ack clock 1 : ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 33303 setup disabled 25004 100 400 (see note) 05 83.3 16606 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f (at f = 4 mhz, unit : khz) note: at 400 khz in the high-speed clock mode, the duty is as below . 0 period : 1 period = 3 : 2 in the other cases, the duty is as below. 0 period : 1 period = 1 : 1 setup value of ccr4Cccr0 rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 serial i/o mode register (sm) [address 00de 16 ] b name functions after reset rw serial i/o mode register 0, 1 internal synchronous clock selection bits (sm0, sm1) (see note 1) b1 b0 0 0: f(x in )/4 or f(x cin )/4 0 1: f(x in )/16 or f(x cin )/16 1 0: f(x in )/32 or f(x cin )/32 1 1: f(x in )/64 or f(x cin )/64 2 synchronous clock selection bit (sm2) 3, 7 ports p4 0 , p4 1 function selection bits (sm3, sm7) p4 0 /s out2 / sda3/x cin p4 0 s out2 sda3 0: external clock 1: internal clock 0 0 0 rw rw rw 4, 6 ports p4 2 , p4 3 function selection bits (sm4, sm6) 5 transfer direction selection bit (sm5) 0: lsb first 1: msb first 0rw p4 1 /s clk2 / scl3/x cout p4 1 s clk2 scl3 b7 5 0 1 b3 0 1 p4 2 /s in2 / sda2/ad8 p4 2 sda2 p4 2 sda2 0rw p4 3 /s rdy2 / scl2/ad7 p4 3 s rdy2 sda2 b6 0 1 0 1 b4 0 1 notes 1: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. 2: when using ports p4 0 Cp4 3 as serial i/o pins, set bit 1 of the serial control register to 1. (see note 2) (see note 2) 107 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller vertical position register i horizontal position register addresses 00e1 16 , 00e3 16 address 00e0 16 b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hr) [address 00e0 16 ] b name functions after reset rw horizontal position register 0 to 5 6 horizontal display start positions (hr0 to hr5) 64 steps (00 16 to 3f 16 ) 0 0nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r 0 7 0 fix this bit to 0. r w b7 b6 b5 b4 b3 b2 b1 b0 vertical position register i (cvi) (i = 1 to 3) [addresses 00e1 16 to 00e3 16 ] b name functions after reset r w vertical position register i 0 to 6 7 vertical display start positions 128 steps (00 16 to 7f 16 ) indeterminate 0 (cvi : cvi0 to cvi6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r 108 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller border selection register character size register address 00e4 16 address 00e5 16 b7 b6 b5 b4 b3 b2 b1 b0 character size register (cs) [address 00e4 16 ] b name functions after reset r w character size register 0, 1 character size of block 1 selection bits (cs10, cs11) b1 b0 0 0 : minimum size 0 1 : medium size 1 0 : large size 1 1 : extra large size indeterminate 2, 3 character size of block 2 selection bits (cs20, cs21) indeterminate rw rw 6 indeterminate nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. r 4, 5 character size of block 2 selection bits (cs30, cs31) indeterminate rw 7 out signal output switch bit (cs7) 0 : out signal output 1 : mute signal output (see note) indeterminate rw note: this erases a video signal on an entire screen. b3 b2 0 0 : minimum size 0 1 : medium size 1 0 : large size 1 1 : extra large size b5 b4 0 0 : minimum size 0 1 : medium size 1 0 : large size 1 1 : extra large size b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out output border selection bit (md10) 0 : same output as character output 1 : border output indeterminate 1 indeterminate 2 block 2 out output border selection bit (md20) 0 : same output as character output 1 : border output indeterminate rw rw rw 0 6, 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r block 1 out output switch bit (md11) 0 : border including character 1 : border only 3 indeterminate rw block 2 out output switch bit (md21) 0 : border including character 1 : border only 4 block 3 out output border selection bit (md30) 0 : same output as character output 1 : border output indeterminate rw 5 indeterminate rw block 3 out output switch bit (md31) 0 : border including character 1 : border only 109 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller b7 b6 b5 b4 b3 b2 b1 b0 crt control register 1 (cc) [address 00ea 16 ] b name functions after reset r w crt control register 1 0 all-blocks display control bit (cc0) (see note) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 block 2 display control bit (cc2) rw rw rw 7 0 note: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. fix this bit to 0. r w 0 3 0 : block 3 display off 1 : block 3 display on 0 block 3 display control bit (cc3) rw 4 0 : ordinary mode 1 : 1/2-character unit color specification mode 0 block 1 color specification mode switch bit (cc4) rw 5 0 : oscillation stopped 1 : oscillation enabled 0 display oscillation stop bit (cc5) rw 6 0 : ordinary 256 count mode 1 : double count mode 0 scanning line double count mode flag(cc6) rw crt contol register 1 color register n address 00ea 16 addresses 00e6 16 , 00e9 16 b7 b6 b5 b4 b3 b2 b1 b0 color register n (co0 to co3) (n = 0 to 3) [addresses 00e6 16 to 00e9 16 ] b name functions after reset r w color register n 0 0 1 b signal output selection bit (con1) 0 : no character is output 1 : character is output 0 2 g signal output selection bit (con2) 0 : no character is output 1 : character is output 0 3 r signal output selection bit (con3) 0 : no character is output 1 : character is output 0 4 b signal output (background) selection bit (con4) 0 : no background color is output 1 : background color is output 0 5 out signal output control bit (con5) 0 : character is output 1 : blank is output 0 6 g signal output (background) selection bit (con6) 0 : no background color is output 1 : background color is output 0 7 r signal output (background) selection bit (con7) 0 : no background color is output 1 : background color is output 0 (see notes 1,2) (see notes 1, 2) notes 1: when bit 5 = 0 and bit 4 = 1, there is output same as a character or border output from the out pin. 2: when bit 5 = 0 and bit 4= 0, there is no output from the out pin. rw rw rw rw rw rw rw rw i signal output selection bit (con0) 0 : no character is output 1 : character is output 110 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller crt port control register display block counter address 00eb 16 address 00ec 16 b7 b6 b5 b4 b3 b2 b1 b0 display block counter (cbc) [address 00eb 16 ] b name functions after reset r w display block counter 0 to 3 number of blocks which are being displayed or has displayed (incremented each time a block is displayed) indeterminate rw 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r 4 to 7 b7 b6 b5 b4 b3 b2 b1 b0 crt port control register (crtp) [address 00ec 16 ] b name functions after reset r w crt port control register 0h sync input polarity switch bit (hsyc) 0 : positive polarity 1 : negative polarity 0 1 0 : positive polarity 1 : negative polarity 0 2 r, g, b output polarity switch bit (r/g/b) 0 : positive polarity 1 : negative polarity 0 3 i output polarity switch bit (i) 0 : positive polarity 1 : negative polarity 0 4 out output polarity switch bit (out) 0 : positive polarity 1 : negative polarity 0 5 r signal output switch bit (r) 0 : r signal output 1 : mute signal output 0 6 g signal output switch bit (g) 0 : g signal output 1 : mute signal output 0 7 b signal output switch bit (b) 0 : b signal output 1 : mute signal output 0 v sync input polarity switch bit (vsyc) rw rw rw rw rw rw rw rw 111 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller a-d control register 1 wipe mode register address 00ed 16 address 00ef 16 b7 b6 b5 b4 b3 b2 b1 b0 wipe mode register (sl) [address 00ed 16 ] b name functions after reset r w wipe mode register 0, 1 wipe mode selection bits (sl0, sl1) b1 b0 0 0 : wipe is not available 0 1 : mode 1 1 0 : mode 2 1 1 : mode 3 0 2 direction mode selection bits (sl2) 0 rw rw 7 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. r 3, 4 wipe unit selection bits (sl3, sl4) 0 rw 0: down mode 1: up mode b4 b3 0 0 : 1h unit 0 1 : 2h unit 1 0 : 3h unit 1 1 : do not set 5, 6 stop mode selection bits (sl5, sl6) 0 rw b6 b5 0 0 : stop at the 312nd h 0 1 : stop at the 156th h 1 0 : stop at the 256th h 1 1 : stop at the 128th h b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (adm) [address 00ef 16 ] b after reset rw a-d control register 1 0 to 2 analog input pin selection bits (adm0 to adm2) name functions b2 b1 b0 0 0 0 : ad1 0 0 1 : ad2 0 1 0 : ad3 0 1 1 : ad4 1 0 0 : ad5 1 0 1 : ad6 1 1 0 : ad7 1 1 1 : ad8 4 storage bit of comparison result (adm4) 0: input voltage < reference voltage 1: input voltage > reference voltage 0 indeterminate 0 3, 5 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. rw r r 112 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller timer mode register 2 timer mode register 1 address 00f4 16 address 00f5 16 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 1 (tmr1) [address 00f4 16 ] b after reset w timer mode register 1 0 1 2 3 4 name functions timer 1 count source selection bit 1 (tmr10, tmr15) b5 b0 0 0: f(x in )/16 or f(x cin )/16 (see note) 0 1: f(x in )/4096 or f(x cin )/4096 (see note) 1 0: f(xc in ) 1 1: external clock from tim2 pin timer 2 count source selection bit 1 (tmr11) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin timer 1 count stop bit (tmr12) 0: count start 1: count stop timer 2 count stop bit (tmr13) 0: count start 1: count stop timer 2 count source selection bit 2 (tmr14) r 0 0 0 0 0 wr wr wr wr wr 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 6 timer 5 count source selection bit 2 (tmr16) 0: timer 2 overflow 1: timer 4 overflow 0wr 7 timer 6 internal count source selection bit (tmr17) 0wr 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tmr2) [address 00f5 16 ] b after reset rw timer mode register 2 0 name functions timer 3 count source selection bit (tmr20) 0 rw 1 timer 4 count source selection bit 2 (tmr21) 0rw 2 3 0 timer 3 count stop bit (tmr22) 0: count start 1: count stop timer 4 count stop bit (tmr23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tmr25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tmr26) 0: count start 1: count stop 0 rw rw rw rw rw 7 timer 5 count source selection bit 1 (tmr27) 0: count source selected by bit 0 of tmr3 1: count source selected by bit 6 of tmr1 0 : f(x in )/16 or f(x cin )/16 (see note) 1 : external clock from tim3 pin 0 : timer 3 overflow signal 1 : f(x in )/16 or f(x cin )/16 (see note) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. 4 timer 4 count source selection bit 1 (tmr24) 0rw 0: count source selected by bit 1 of tmr2 1 : f(x in )/2 or f(x cin )/2 (see note) 113 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller cpu mode register address 00fb 16 b7 b6 b5 b4 b3 b2 b1 b0 b after reset rw cpu mode register 0, 1 2 3 0 1 1 1 0 0 name functions processor mode bits (cm0, cm1) 0 0: single-chip mode 0 1: 1 0: not available 1 1: fix these bits to 1. 1 stack page selection bit (cm2) (see note 1) 1 b1 b0 0: 0 page 1: 1 page 00 cpu mode register (cpum) (cm) [address 00fb 16 ] rw rw rw 5 6 main clock (x in Cx out ) stop bit (cm6) rw rw x cout drivability selection bit (cm5) 0: low drive 1: high drive 0: oscillating 1: stopped 7 internal system clock selection bit (cm7) rw 0: x in Cx out selected (high-speed mode) 1: x cin Cx cout selected (high-speed mode) notes 1: this bit is set to 1 after the reset release. 2: the internal system clock f stops at high. 4 internal system clock output selection bit (cm4) (see note 2) 0: output is stopped 1: internal system clock f output rw 114 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller interrupt reguest register 2 interrupt reguest register 1 address 00fc 16 address 00fd 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc b name functions after reset rw interrupt request register 1 0 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit (tm1r) 1 timer 2 interrupt request bit (tm2r) 2 timer 3 interrupt request bit (tm3r) 3 timer 4 interrupt request bit (tm4r) 4 crt interrupt request bit (crtr) 5v sync interrupt request bit (vscr) 6 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] multi-master i 2 c-bus interface interrupt request bit (iicr) 0 : no interrupt request issued 1 : interrupt request issued ] 16 ] r r r r r r r 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. r 0 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd b name functions after reset rw interrupt request register 2 0 int1 interrupt request bit (itir) 0 : no interrupt request issued 1 : interrupt request issued 1 int2 interrupt request bit (it2r) 2 serial i/o interrupt request bit (sir) 4 f(x in )/4096 interrupt request bit (msr) 3,6 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 7 fix this bit to 0. 0 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 ] : 0 can be set by software, but 1 cannot be set. 0 ] 0 0 ] 0 ] 0 ] 0 : no interrupt request issued 1 : interrupt request issued 16 ] r r r r r rw 5 timer 5 ? 6 interrupt request bit (tm56r) 0 : no interrupt request issued 1 : interrupt request issued 0 ] r 115 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller interrupt control register 2 interrupt control register 1 address 00fe 16 address 00ff 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b name functions after reset rw interrupt control register 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 1 timer 2 interrupt enable bit (tm2e) 2 timer 3 interrupt enable bit (tm3e) 3 4 crt interrupt enable bit (crte) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 0 0 rw rw rw rw rw r r 6 timer 4 interrupt enable bit (tm4e) 0 : interrupt disabled 1 : interrupt enabled 5 v sync interrupt enable bit (vsce) 0 : interrupt disabled 1 : interrupt enabled 0rw multi-master i 2 c-bus interface interrupt enable bit (iice) 0 : interrupt disabled 1 : interrupt enabled w nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 7 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name functions after reset rw interrupt control register 2 0 int1 interrupt enable bit (it1e) 0 : interrupt disabled 1 : interrupt enabled 1 int2 interrupt enable bit (it2e) 2 serial i/o interrupt enable bit (sie) 3, 6 fix these bits to 0. 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 0 rw rw rw rw 4 f(x in )/4096 interrupt enable bit (mse) 0 : interrupt disabled 1 : interrupt enabled 0rw 5 timer 5 ? 6 interrupt enable bit (tm56e) 0 : interrupt disabled 1 : interrupt enabled 0rw 7 timer 5 ? 6 interrupt switch bit (tm56c) 0 : timer 5 1 : timer 6 0rw 116 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller serial i/o control register port control register address 0206 16 address 0207 16 b7 b6 b5 b4 b3 b2 b1 b0 port control register (p7d) [address 0206 16 ] b name functions after reset r w port control register 0, 1 port p7 data input bits (p7d0, p7d1) when only op1 = 0 and op0 = 1, input data is valid. (see note) indeterminate 2 d-a/ad3 function selection bit (p7d2) 0 rw rw 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. r 4p4 0 /x cin , p4 1 /x cout function selection bit (p7d4) 0 : p4 0 , p4 1 1 : x cin , x cout 0 rw note: op is the crt clock selection register. 0: ad3 1: d-a 3, 5 to 7 b7 b6 b5 b4 b3 b2 b1 b0 serial i/o control register (sic) [address 0207 16 ] b name functions after reset rw serial i/o control register 0 input signal to sift register selection bit (sic0) csio b0 0 0: input signal from s in1 0 1: input signal from s out1 (see note 1) 1 0: input signal from s in2 1 1: input signal from s out2 (see note 1) 1 serial i/o pin switch bit (csio) 0: s out1 , s clk1 , s in1 , s rdy1 1: s out2 , s clk2 , s in2 , s rdy2 0 0 rw rw notes 1: when inputting data from the s out pin, set ff 16 to the serial i/o register. 2: when using ports p4 4 Cp4 7 as serial i/o pins, set bit 1 of the serial i/o control register to 0. 3, 7 ports p4 7 function selection bits (sm3, sm7) (see note 2) p4 7 /s rdy1 /pwm8 p4 7 s rdy1 pwm8 0rw 4, 5 ports p4 4 , p4 5 function selection bits (sm4, sm6) (see note 2) 6 ports p4 6 function selection bits (sic6) (see note 2) b7 0 1 b3 5 0 1 p4 4 /s out1 / sda1 p4 4 s out1 sda1 0rw p4 5 /s clk1 / scl1 p4 5 s clk1 scl1 b5 0 1 b4 5 0 1 p4 6 /s in1 /pwm9 p4 6 pwm9 0rw b6 0 1 2 i 2 c-bus connection ports switch bit (sic2) 0: sda2, scl2, sda1, scl1 1: sda3, scl3 0rw 117 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller crt clock selection register crt control register 2 address 0208 16 address 0209 16 b7 b6 b5 b4 b3 b2 b1 b0 crt control register 2 (cbr) [address 0208 16 ] b name functions after reset r w crt control register 2 0 i signal output switch bit (cbr0) 0: i signal output 1: mute signal output 0 1 i/tim1 function switch bit (cbr1) 0 rw rw 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. r 0: i output or mute output 1: 1/2 clock ouput of timer 1 2 to 7 b7 b6 b5 b4 b3 b2 b1 b0 crt clock selection register (op) [address 0209 16 ] b name functions after reset r w crt clock selection register 0, 1 crt clock selection bits (op0, op1) 0 since the main clock is used as the clock for display, the oscillation frequency is limited. because of this, the character size in width (horizontal) direction is also limited. in this case, pins osc1 and osc2 are also used as input ports p7 0 and p7 1 respectively. the clock for display is supplied by connecting the following across the pins osc1 and osc2. ? a ceramic resonator only for crt display and a feedback resistor ? a quartz-crystal oscillator only for crt display and a feedback resistor (see note) 2 to 6 0 0 b1 the clock for display is supplied by connecting rc or lc across the pins osc1 and osc2. functions 10 b0 crt oscillation frequency = f(x in ) notes 1: it is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins x in and x out . 2: cc6 is the scnanning line double count mode flag. 0 1 11 rw r cc6 cc6 = 0 or 1 cc6 = 0 cc6 = 0 1 0 do not set. 7 0 fix this bits to 0. rw nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 118 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller timer mode register 3 a-d control register 2 address 020a 16 address 020b 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 2(adc) [address 020a 16 ] b after reset rw a-d control register 2 0 to 5 6, 7 indeterminate 0 name functions d-a converter set bits (adc0 to adc5) b0b1b2 b3 b4 b5 nothing is assigned. these bits are write disable bits. when these bits are reed out, the values are 0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3/128vcc : 5/128vcc : 123/128vcc : 125/128vcc : 127/128vcc : 1/128vcc rw r b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 3 (tmr3) [address 020b 16 ] b after reset rw timer mode register 3 0 name functions timer 5 count source selection bit 3 (tmr30) 0rw 0r 0 : f(x in )/16 or f(x cin )/16 (see note) 1 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. 1 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 119 mitsubishi microcomputers m37207mf-xxxsp/fp, M37207M8-XXXSP m37207efsp/fp single-chip 8-bit cmos microcomputer for voltage synthesizer and on-screen display controller rom correction enable register address 021b 16 b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 021b 16 ] b after reset rw rom correction enable register 0 block 1 enable bit (rc0) name functions 0: disabled 1: enabled 1 block 2 enable bit (rc1) 0: disabled 1: enabled 4 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 rw rw r 00 2, 3 fix these bits to0. 0 rw ?1997 mitsubishi electric corp. new publication, effective dec. 1997. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer? application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party? rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. rev. rev. no. date 1.0 first edition 971212 1.1 correct note (p76) 980731 m37207mf-xxxsp/fp, M37207M8-XXXSP, m37207efsp/fp data sheet (1/1) revision description revision description list |
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