s7030/s7031 series is a family of fft-ccd image sensors specifically designed for low-light-level detection in scientific appli cations. by using the binning operation, s7030/s7031 series can be used as a linear image sensor having a long aperture in the direction of the d evice length. this makes s7030/s7031 series ideally suited for use in spectrophotometry. the binning operation offers significant improvement in s /n and signal processing speed compared with conventional methods by which signals are digitally added by an external circuit. s7030/s7031 se ries also features low noise and low dark signal (mpp mode operation). this enables low-light-level detection and long integration time, thus achieving a wide dynamic range. s7030/s7031 series has an effective pixel size of 24 24 m and is available in image areas ranging from 12.288 (h) 1.392(v) mm 2 (512 58 pixels) up to a large image area of 24.576 (h) 6.000 (v) mm 2 (1024 250 pixels). features l non-cooled type: s7030 series one-stage te-cooled type: s7031 series l pixel size: 24 24 m l line, pixel binning l greater than 90 % quantum efficiency at peak sensitivity wavelength l wide spectral response range l low readout noise l wide dynamic range l mpp operation l high uv sensitivity with good stability applications l fluorescence spectrometer, icp l industrial inspection requiring l semiconductor inspection l dna sequencer l low-light-level detection image sensor ccd area image sensor back-thinned fft-ccd s7030/s7031 series selection guide type no. cooling number of total pixels number of active pixels active area [mm (h) mm (v)] suitable multichannel detector head s7030-0906 532 64 512 58 12.288 1.392 s7030-0907 532 128 512 122 12.288 2.928 s7030-0908 532 256 512 250 12.288 6.000 s7030-1006 1044 64 1024 58 24.576 1.392 s7030-1007 1044 128 1024 122 24.576 2.928 s7030-1008 non-cooled 1044 256 1024 250 24.576 6.000 c7040 s7031-0906s 532 64 512 58 12.288 1.392 s7031-0907s 532 128 512 122 12.288 2.928 s7031-0908s 532 256 512 250 12.288 6.000 s7031-1006s 1044 64 1024 58 24.576 1.392 s7031-1007s 1044 128 1024 122 24.576 2.928 s7031-1008s one-stage te-cooled 1044 256 1024 250 24.576 6.000 c7041 general ratings parameter s7030 series s7031 series pixel size 24 (h) 24 (v) m vertical clock phase 2 phases horizontal clock phase 2 phases output circuit one-stage mosfet source follower package 24 pin ceramic dip (refer to dimensional outlines) window * 1 quartz glass ar-coated sapphire *1: temporary window type (ex. s7030-0906n) is available upon request. (temporary window is fixed by tape to protect the ccd chip and wire bonding.) 1
ccd area image sensor s7030/s7031 series absolute maximum ratings (ta=25 c) parameter symbol min. typ. max. unit operating temperature * 2 topr -50 - +30 c storage temperature tstg -50 - +70 c od voltage v od -0.5 - +25 v rd voltage v rd -0.5 - +18 v isv voltage v isv -0.5 - +18 v ish voltage v ish -0.5 - +18 v igv voltage v ig1v , v ig2v -10 - +15 v igh voltage v ig1h , v ig2h -10 - +15 v sg voltage v sg -10 - +15 v og voltage v og -10 - +15 v rg voltage v rg -10 - +15 v tg voltage v tg -10 - +15 v vertical clock voltage v p1v , v p2v -10 - +15 v horizontal clock voltage v p1h , v p2h -10 - +15 v *2: chip temperature operating conditions (mpp mode, ta=25 c) parameter symbol min. typ. max. unit output transistor drain voltage v od 18 20 22 v reset drain voltage v rd 11.5 12 12.5 v output gate voltage v og 13 5v substrate voltage v ss - 0 - v test point (vertical input source) v isv -v rd -v test point (horizontal input source) v ish - v rd - v t est point (vertical input gate) v ig1v , v ig2v -9 test point (horizontal input gate) v ig1h , v ig2h -9 -8 - v high v p1vh , v p2vh 46 8 vertical shift register clock voltage low v p1vl , v p2vl -9 -8 -7 v high v p1hh , v p2hh 4 6 8 horizontal shift register clock voltage low v p1hl , v p2hl -9 -8 -7 v high v sgh 46 8 summing gate voltage low v sgl -9 -8 -7 v high v rgh 4 6 8 reset gate voltage low v rgl -9 -8 -7 v high v tgh 46 8 transfer gate voltage low v tgl -9 -8 -7 v electrical characteristics (ta=25 c) parameter symbol min. typ. max. unit signal output frequency fc - 0.25 1 mhz s703 * -0906 - 750 - s703 * -0907/-1006 1500 - s703 * -0908/-1007 3000 - vertical shift register capacitance s703 * -1008 c p1v , c p2v 6000 - pf s703 * -0906/-0907/-0908 110 horizontal shift register capacitance s703 * -1006/-1007/-1008 c p1h , c p2h - 180 -pf summing gate capacitance c sg - 30 - pf reset gate capacitance c rg -30 -pf s703 * -0906/-0907/-0908 55 transfer gate capacitance s703 * -1006/-1007/-1008 c tg - 75 - pf charge transfer efficiency * 3 cte 0.99995 0.99999 - - dc output level * 4 vout 14 16 18 v output impedance * 4 zo - 3 4 k ? power consumption * 4 * 5 p - 13 14 mw *3: charge transfer efficiency per pixel, measured at half of the full well capacity. *4: the values depend on the load resistance. (typical, v od =20 v, load resistance=22 k ? ) *5: power consumption of the on-chip amplifier. 2 - -8 v
ccd area image sensor s7030/s7031 series 0 10 100 200 wavelength (nm) transmittance (%) 300 400 500 600 700 800 900 1000 1100 1200 20 30 40 50 60 70 80 90 100 (typ. ta=25 ?c) quartz window ar coated sapphire quantum efficiency (%) wavelength (nm) (typ. ta=25 ? c) 0 200 400 600 800 1000 1200 10 20 30 40 50 60 70 80 90 100 front-sided front-sided (uv coat) back-thinned *14: spectral response with quartz glass or ar-coated sapphire are decreased by the transmittance. spectral response (without window) *14 spectral transmittance characteristics kmpdb0058ea kmpdb0110ea dark current vs. temperature 3 -50 -40 -30 -20 0 -10 10 20 30 temperature ( ? c) 0.01 1 0.1 10 100 1000 dark current (e - /pixel/s) (typ.) kmpdb0256ea c, unless otherwise noted) parameter symbol min. typ. max. unit saturation output voltage vsat - fw sv - v vertical 240 320 - full well capacity horizontal * 6 fw 800 1000 - ke - ccd node sensitivity sv 1.8 2.2 - v/e - 25 c - 100 1000 d ark current * 7 mpp mode (tentative data) 0 c ds - 10 100 e - /pixel/s readout noise * 8 nr - 8 16 e - rm s line binning 100000 125000 - - dynamic range * 9 area scanning dr 30000 40000 - - photo response non-uniformity * 10 prnu - 3 10 % spectral response range - 200 to 1100 - nm w hite spots - - 0 - point defect * 11 black spots - - 10 - cluster defect * 12 - - 3 - blemish column defect * 13 - - - 0 - *6: the linearity is 1.5 % . *7: dark current nearly doubles for every 5 to 7 c increase in temperature. *8: measured with a hamamatsu c4880 digital ccd camera with a cds circuit (sensor temperature: -40 c, operating frequency: 150 khz). *9: dynamic range (dr) = full well/readout noise *10: measured at one-half of the saturation output (full well capacity) using a white fluorescent lamp. *11: w hite spots pixels whose dark current is higher than 1 ke - after one-second integration at 0 c. black spots pixels whose sensitivity is lower than one-half of the average pixel output. (measured with uniform light producing one-half of the saturation charge) *12: 2 to 9 contiguous defective pixels *13: 10 or more contiguous defective pixels fixed pattern noise (peak to peak) signal 100 photo response non-uniformity (prnu) [%]
ccd area image sensor s7030/s7031 series device structure (conceptual drawing of top view) 23 22 21 20 14 15 24 1 2 12 11 89 3 4 5 2 bevel signal out 2 n 4 blank 4 blank v=58, 122, 250 h=512, 1024 4 bevel thinning thinning 1 23 45 2 3 4 5 v h 6 bevel 6 bevel 2 n signal out 13 10 kmpdc0016eb integration period (shutter must be open) vertical binning period (shutter must be closed) p1v p2v, tg p1h p2h, sg readout period (shutter must be closed) 3.. 62 3..126 3..254 63 127 255 64 128 256 58 + 6 (bevel): s703 * -0906/-1006 122 + 6 (bevel): s703 * -0907/-1007 250 + 6 (bevel): s703 * -0908/-1008 tpwv to v r tpwh, tpws tpwr 123 531 1043 532 1044 : s703 * -0906/-0907/-0908 : s703 * -1006/-1007/-1008 4..530 4..1042 12 d19 d2 d1 d20 d3..d10, s1..s1024, d11..d18 rg os s1..s512 : s703 * -0906/-0907/-0908 : s703 * -1006/-1007/-1008 timing chart kmpdc0017eb parameter symbol remark min. typ. max. unit pulse width tpwv 6 * 18 8 - s p1v, p2v, tg rise and fall time tprv, tpfv * 17 10 - - ns pulse width tpwh 500 2000 - ns rise and fall time tprh, tpfh 10 - - ns p1h, p2h duty ratio - * 17 - 50 - % pulse width tpws 500 2000 - ns rise and fall time tprs, tpfs 10 - - ns sg duty ratio - - - 50 - % pulse width tpwr 100 - - ns rg rise and fall time tprr, tpfr - 5 - - ns tg ? p1h overlap time tovr - 3 - - s *17: the clock pulses should be overlapped at 50 % of clock pulse amplitude. *18: in case of s7030-0908/-1007, s7031-0908s/-1007s line bininng 4
ccd area image sensor s7030/s7031 series parameter symbol remark min. typ. max. unit pulse width tpwv 6 * 20 8 - s p1v, p2v, tg rise and fall time tprv, tpfv * 19 10 - - ns pulse width tpwh 500 2000 - ns rise and fall time tprh, tpfh 10 - - ns p1h, p2h duty ratio - * 19 - 50 - % pulse width tpws 500 2000 - ns rise and fall time tprs, tpfs 10 - - ns sg duty ratio - - - 50 - % pulse width tpwr 100 - - ns rg rise and fall time tprr, tpfr - 5 - - ns tg - p1h overlap time tovr - 3 - - s *19: the clock pulses should be overlapped at 50 % of clock pulse amplitude. *20: in case of s7030-0908/-1007, s7031-0908s/-1007s 5 integration period (shutter must be open) p1v rg os p2v, tg p1h p2h, sg readout period (shutter must be closed) enlarged view tpwv to v r tpwr d1 d2 d3 d4 d18 d19 d20 d5..d10, s1..s1024, d11..d17 p2v, tg p1h p2h, sg rg os tpwh, tpws 123 s1..s512 : s703 *-0906/-0907/-0908 : s703 *-1006/-1007/-1008 4.. 63 4..127 4..255 64 58 + 6 (bevel): s703 *-0906/-1006 128 122 + 6 (bevel): s703 *-0907/-1007 256 250 + 6 (bevel): s703 *-0908/-1008 kmpdc0127ea area scanning: large full well mode
ccd area image sensor s7030/s7031 series 6 window 16.3 * 21 8.2 * 21 34.0 0.34 50.0 0.30 2.54 0.13 22.9 0.3 19.0 4.0 42.0 22.4 0.3 a 7.3 0.63 1.0 7.7 0.68 6.65 0.63 4.89 0.15 active area 12.29 photosensitive surface 1st pin indication pad 3.0 te-cooler s7031-0906s: a=1.392 s7031-0907s: a=2.928 s7031-0908s: a=6.000 (24 ) 0.5 0.05 4.4 0.44 4.8 0.49 2.35 0.15 3.75 0.44 photosensitive surface 1st pin indication pad 3.0 (24 ) 0.5 0.05 window 16.3 * 21 8.2 * 21 34.0 0.34 2.54 0.13 22.9 0.30 22.4 0.30 a active area 12.29 s7030-0906: a=1.392 s7030-0907: a=2.928 s7030-0908: a=6.000 s7030-0906/-0907/-0908 s7030-1006/-1007/-1008 kmpda0046ec kmpda0047ed s7031-0906s/-0907s/-0908s s7031-1006s/-1007s/-1008s kmpda0048ed kmpda0049ee 3.0 photosensitive surface 4.4 0.44 2.35 0.15 4.8 0.49 3.75 0.44 window 28.6 * 21 22.9 0.3 22.4 0.3 active area 24.58 a 8.2 * 21 44.0 0.44 2.54 0.13 1st pin indication pad s7030-1006: a=1.392 s7030-1007: a=2.928 s7030-1008: a=6.000 (24 ) 0.5 0.05 (24 ) 0.5 0.05 7.3 0.63 1.0 3.0 6.65 0.63 4.89 0.15 photosensitive surface 7.7 0.68 1st pin indication pad a 4.0 19.0 22.4 0.3 22.9 0.3 44.0 0.44 52.0 60.0 0.3 2.54 0.13 window 28.6 * 21 active area 24.58 8.2 * 21 s7031-1006s: a=1.392 s7031-1007s: a=2.928 s7031-1008s: a=6.000 te-cooler *21: size of window that guarantees the transmittance in the "spectral transmittance characteristics" graph
ccd area image sensor s7030/s7031 series pin connections s7030 series s7031 series pin no. symbol function symbol function remark (standard operation) 1 rd reset drain rd reset drain +12 v 2 os output transistor source os output transistor source r l =10 k to 100 k 3 od output transistor drain od output transistor drain +20 v 4 og output gate og output gate +3 v 5 sg summing gate sg summing gate same pulse as p2h 6 - - 7- - 8 p2h ccd horizontal register clock-2 p2h ccd horizontal register clock-2 9 p1h ccd horizontal register clock-1 p1h ccd horizontal register clock-1 10 ig2h test point (horizontal input gate-2) ig2h test point (horizontal input gate-2) -8 v 11 ig1h test point (horizontal input gate-1) ig1h test point (horizontal input gate-1) -8 v 12 ish test point (horizontal input source) ish test point (horizontal input source) connect to rd 13 tg * 22 transfer gate tg * 22 transfer gate same pulse as p2v 14 p2v ccd vertical register clock-2 p2v ccd vertical register clock-2 15 p1v ccd vertical register clock-1 p1v ccd vertical register clock-1 16 - th1 thermistor 17 - th2 thermistor 18 - p- te-cooler- 19 - p+ te-cooler+ 20 ss substrate (gnd) ss substrate (gnd) gnd 21 isv test point (vertical input source) isv test point (vertical input source) connect to rd 22 ig2v test point (vertical input gate-2) ig2v test point (vertical input gate-2) -8 v 23 ig1v test point (vertical input gate-1) ig1v test point (vertical input gate-1) -8 v 24 rg reset gate rg reset gate *22: isolation gate between vertical register and horizontal register. in standard operation, tg should be applied the same pul se as p2v. 0 1 2 3 voltage (v) ccd temperature ( ? c) 4 7 6 5 -40 -30 4 3 2 current (a) 1 0 -20 -10 0 10 20 30 (typ. ta=25 ? c) voltage vs. current ccd temperature vs. current 0 1 2 3 voltage (v) ccd temperature ( ? c) 4 7 6 5 -40 -30 2.0 1.5 1.0 current (a) 0.5 0 -20 -10 0 10 20 30 (typ. ta=25 ? c) voltage vs. current ccd temperature vs. current kmpdb0178ea kmpdb0179ea s7031-0906s/-0907s/-0908s s7031-1006s/-1007s/-1008s 7 specifications of built-in te-cooler (typ. reference data in vacuum condition) parameter symbol condition s7031-0906s/-0907s/-0908s s7031-1006s/-1007s/-1008s unit internal resistance rint ta=25 c 2.5 1.2 maximum current * 23 imax tc * 24 =th * 25 =25 c 1.5 3.0 a maximum voltage vmax tc * 24 =th * 25 =25 c 3.8 3.6 v maximum heat absorption * 26 qmax 3.4 5.1 w maximum temperature of heat radiating side - 70 70 c *23: maximum current imax: if the current greater than this value flows into the thermoelectric cooler, the heat absorption begins to decrease due to the joule heat. it should be noted that this value is not the damage threshold value. to protect the thermoelectric cooler and maintain stable operation, the supply current should be less than 60 % of this maximum current. *24: temperature of the cooling side of thermoelectric cooler *25: temperature of the heat radiating side of thermoelectric cooler *26: maximum heat absorption qmax. this is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the maximum current is supplied to the unit.
ccd area image sensor s7030/s7031 series hamamatsu photonics k.k., solid state division 1126-1 ichino-cho, higashi-ku, hamamatsu city, 435-8558 japan, telephone: (81) 53-434-3311, fax: (81) 53-434-5184, www.hamamats u.com u.s.a.: hamamatsu corporation: 360 foothill road, p.o.box 6910, bridgewater, n.j. 08807-0910, u.s.a., telephone: (1) 908-231-0 960, fax: (1) 908-231-1218 germany: hamamatsu photonics deutschland gmbh: arzbergerstr. 10, d-82211 herrsching am ammersee, germany, telephone: (49) 08152 -3750, fax: (49) 08152-2658 france: hamamatsu photonics france s.a.r.l.: 19, rue du saule trapu, parc du moulin de massy, 91882 massy cedex, france, teleph one: 33-(1) 69 53 71 00, fax: 33-(1) 69 53 71 10 united kingdom: hamamatsu photonics uk limited: 2 howard court, 10 tewin road, welwyn garden city, hertfordshire al7 1bw, unit ed kingdom, telephone: (44) 1707-294888, fax: (44) 1707-325777 north europe: hamamatsu photonics norden ab: smidesv ? gen 12, se-171 41 solna, sweden, telephone: (46) 8-509-031-00, fax: (46) 8-509-031-01 italy: hamamatsu photonics italia s.r.l.: strada della moia, 1/e, 20020 arese, (milano), italy, telephone: (39) 02-935-81-733, fax: (39) 02-935-81-741 information furnished by hamamatsu is believed to be reliable. however, no responsibility is assumed for possible inaccuracies or omissions. specifications are subject to change without notice. no patent rights are granted to any of the circuits described herein. ?200 7 hamamatsu photonics k.k. input symbol value supply voltage v d1 v a1+ v a1- v a2 v d2 vp v f +5 vdc, 200 ma +15 vdc, +100 ma -15 vdc, -100 ma +24 vdc, 30 ma +5 vdc, 30 ma (c7041) +5 vdc, 2.5 a (c7041) +12 vdc, 100 ma (c7041) master start ms hcmos logic compatible master clock mc hcmos logic compatible, 1 mhz features l c7040: for s7030 series c7041: for s7031 series l area scanning or full line-binnng operation l readout frequency: 250 khz l readout noise: 20 e - rms l t=50 ? c ( t changes by cooling method.) cat. no. kmpd1023e14 nov. 2007 dn multichannel detector heads c7040, c7041 precaution for use (electrostatic countermeasures) handle these sensors with bare hands or wearing cotton gloves. in addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge. provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to dis- charge. ground the tools used to handle these sensors, such as tweezers and soldering irons. it is not always necessary to provide all the electrostatic measures stated above. implement these measures according to the amount of damage that occurs. element cooling/heating temperature incline rate when cooling the ccd by an externally attached cooler, set the cooler operation so that the temperature gradient (rate of tempe ra- ture change) for cooling or allowing the ccd to warm back is less than 5 k/minute. specifications of built-in temperature sensor a chip thermistor is built in the same package with a ccd chip, and the ccd chip temperature can be monitored with it. a relati on between the thermistor resistance and absolute temperature is expressed by the following equation. r1 = r2 expb (1 / t1 - 1 / t2) where r1 is the resistance at absolute temperature t1 (k) r2 is the resistance at absolute temperature t2 (k) b is so-called the b constant (k) the characteristics of the thermistor used are as follows. r (298k) = 10 k b (298k / 323k) = 3450 k kmpdb0111eb 10 k 220 240 260 temperature (k) resistance 280 300 100 k 1 m 8
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