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tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 1/80 toshiba mos digital integrat e circuit silicon gate cmos 64m (4m 16 bits) cmos flash memory 1. description the tc58fvm6(t/b)5b is a 67108864-bit, 3v read-only electric ally erasable and programmable flash memory organized as 4194304 16 bits. the tc58fvm6(t/b)5b features commands for read, program and erase operations to allow easy interfacing with microprocessors. the commands are bas ed on the jedec standard. the program and erase operations are automatically executed in the chip. the tc58fvm6(t/b)5b also features a simultaneous read/write operation so that data can be read during a write or erase operation. 2. features ? power supply voltage v dd = 2.7v to 3.6v ? operating ambient temperature ta = -40 c to 85 c ? organization 4m 16 bits ? functions simultaneous read/write page read auto program, auto page program auto block erase, auto chip erase fast program mode/acceleration mode program suspend/resume erase suspend/resume data polling/toggle bit password block protection block protection/ boot block protection automatic sleep, support for hidden rom area common flash memory interface (cfi) ? block erase architecture 8 8 kbytes / 127 64 kbytes ? bank architecture 8m bits 8 bank ? boot block architecture tc58fvm6t5b top boot block tc58fvm6b5b bottom boot block ? mode control compatible with jedec standard commands ? erase/program cycles 10 5 cycles typ ? access time (random/page) 65ns / 25ns (cl=30pf) 70ns / 30ns (cl=100pf) ? page length: 8 words ? power consumption 10 a (standby) 15ma (program/erase operation) 5ma (page read operation) 55ma (random read operation) 11ma (address increment read operation) ? package tc58fvm6(t/b)5btg tsop 48-p-1220-0.50 (weight: 0.51g) tc58fvm6(t/b)5bxg p-tfbga56-0710-0.80dz (weight: 0.125g) ? lead-free lead - free
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 2/80 table of contents 64m (4m 16 bits) cmos flash memory .................................................................................................... .............................. 1 1. descri ption................................................................................................................. ................................................................ 1 2. feat ures .................................................................................................................... .................................................................. 1 3. ordering informat ion........................................................................................................ .................................................. 3 4.pin assignment (top view) .................................................................................................... ................................................ 4 5. block diagram............................................................................................................... ............................................................ 5 6. mode se lection .............................................................................................................. .......................................................... 6 7. id code table ............................................................................................................... .............................................................. 6 8. command sequences ........................................................................................................... ................................................... 7 9. simultaneous read/w rite oper ation........................................................................................... ................................. 9 10. operatio n mode s............................................................................................................ ...................................................... 10 10.1. read mode................................................................................................................ .............................................................. 10 10.2. id re ad mode............................................................................................................. ............................................................ 10 10.3. stan dby mode ............................................................................................................. ........................................................... 10 10.4. auto-s leep mode .......................................................................................................... .......................................................... 10 10.5. output disable mode...................................................................................................... ....................................................... 10 10.6. comman d write ............................................................................................................ ..........................................................11 10.7. software reset: read/reset command....................................................................................... ...........................................11 10.8. hardwa re reset ........................................................................................................... ...........................................................11 10.9. comparison between softwa re reset and ha rdware reset..................................................................... .............................11 10.10. auto-pro gram mode....................................................................................................... ...................................................... 12 10.11. auto-page program mode .................................................................................................. .................................................. 12 10.12. fast pr ogram mode ....................................................................................................... ...................................................... 12 10.13. accelera tion mode ....................................................................................................... ......................................................... 12 10.14. program susp end/resume mode ............................................................................................. ........................................... 13 10.15. auto chip erase mode .................................................................................................... ..................................................... 13 10.16. auto block er ase/auto multi-bl ock erase modes ........................................................................... ................................... 13 10.17. erase suspend/er ase resume modes ........................................................................................ ......................................... 14 10.18. block protec tion ........................................................................................................ ........................................................... 15 10.19. hidden rom area......................................................................................................... ....................................................... 20 10.20. cfi (common flas h memory in terface) ..................................................................................... ........................................ 21 10.21. hardware sequence flags................................................................................................. .................................... 24 11. data pr otection............................................................................................................ ....................................................... 26 11.1. protection against program/er ase caused by lo w supply voltage ............................................................ ........................ 26 11.2. protection against malf unction caused by glitches ........................................................................ .................................... 26 11.3. protection against malfunction at power-on ............................................................................... ......................................... 26 12. absolute ma ximum ratings................................................................................................... ......................................... 27 13. capacitance (t a = 25c, f = 1 mh z ) .............................................................................................................................. ....... 27 14. recommended dc op erating cond itions........................................................................................ ......................... 27 15. dc char acteristics......................................................................................................... .................................................... 28 16. ac test condit ions......................................................................................................... ..................................................... 28 17. ac characteristics an d operating co nditions ................................................................................ ................... 29 17.1. read cycle............................................................................................................... ............................................................... 29 17.2. block protect ............................................................................................................ .............................................................. 29 17.3. program and eras e characte ristics........................................................................................ ............................................... 30 17.4. command write/pr ogram/eras e cycle ........................................................................................ .......................................... 31 18. timing diagrams ............................................................................................................ ....................................................... 32 19. flowc harts ................................................................................................................. ........................................................... 48 20. block add ress ta bles ....................................................................................................... ................................................ 65 20.1. tc58fvm6t5b (top boot block) 1/5 ........................................................................................ ......................................... 65 20.2. tc58fvm6b5b (botto m boot bloc k) 1/5 ..................................................................................... ...................................... 70 21. block si ze t able........................................................................................................... ........................................................ 75 21.1. tc58fvm6t5b (t op boot block) ............................................................................................. ............................................. 75 21.2. tc58fvm6b5b (b ottom boot block).......................................................................................... .......................................... 76 22. package dimens ions......................................................................................................... .................................................. 77
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 3/80 3. ordering information tc58 f v m6 t 5 b xg 65 speed version 65 = 65ns package tg = tsop xg = bga design rule b = 0.13 m function/bank size 4 = page/burst /8m uniform bank 5 = page/8m uniform bank boot block architecture t = top boot block b = bottom boot block capacity m6 = 64mbits supply voltage v = 3 v system y = 1.8 v system device type f = nor flash memory toshiba cmos e 2 prom ordering type function boot block speed version package tc58fvm6t5bxg65 top tc58fvm6b5bxg65 bottom p-tfbga56-0710-0.80dz (lead-free) TC58FVM6T5BTG65 top tc58fvm6b5btg65 page bottom 65 ns tsop i 48-p-1220-0.50 (lead-free)
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 4/80 4.pin assignment (top view) tc58fvm6t5btg / tc58fvm6b5btg pin names a0~a21 address input dq0~dq15 data input/output ce chip enable input oe output enable input we write enable input by / ry ready/busy output reset hardware reset input /acc wp write protect / program acceleration input v dd power supply v ss ground n.c. no connection tc58fvm6t5bxg / tc58fvm6b5bxg 1 2 3 4 5 6 7 8 a nc nc b nc nc c a3 a7 by / ry we a9 a13 d a4 a17 /acc wp reset a8 a12 e a2 a6 a18 a21 a10 a14 f a1 a5 a20 a19 a11 a15 g a0 dq0 dq2 dq5 dq7 a16 h c dq8 dq10 dq12 dq14 nc j oe dq9 dq11 v dd dq13 dq15 k v ss dq1 dq3 dq4 dq6 v ss l nc nc m nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a 16 n.c. v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v ss a 0 oe ce a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 a21 a18 a17 a7 a6 a5 a4 a3 a2 a1 we reset /acc wp by / ry 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 5/80 5. block diagram by / ry buffer data latch control circuit command register i/o buffer memory cell array bank 7 memory cell array bank 6 memory cell array bank 0 v dd v ss dq0 by / ry dq15 we reset ce oe a0 a21 memory cell array bank 1 acc / wp address latch address buffer
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 6/80 6. mode selection mode ce oe we a9 a6 a1 a0 reset /acc wp dq0~dq15 read/page read l l h a9 a6 a1 a0 h * d out id read (manufacturer code) ll h v id lll h * code id read (device code) ll h v id llh h * code standby h * * * * * * h * high-z output disable * h h * * * * * * high-z write l h (1) a9 a6 a1 a0 h * d in block protect 1 l v id (1) v id lhl h * * block protect 2 l h h * lhl v id * * verify block protect l l h v id lhl h * code temporary block unprotect * * * * * * * v id * * hardware reset/standby * * * * * * * l * high-z boot block protect * * * * * * * * l * notes: * = v ih or v il , l = v il , h = v ih (1) pulse input 7. id code table code type a21~a12 a6 a1 a0 code (hex) manufacturer code x l l l 0098h tc58fvm6t5b x l l h 002dh device code tc58fvm6b5b x l l h 002eh verify block protect ba (1) l h l data (2) notes : x: v ih or v il l: v il h: v ih (1) ba: block address (2) 0001h-protected block 0000h- unprotected block
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 7/80 8. command sequences first bus write cycle second bus write cycle third bus write cycle fourth bus write cycle fifth bus write cycle sixth bus write cycle command sequence bus write cycles req?d addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h read/reset 3 555h aah 2aah 55h 555h f0h ra (1) rd (2) id read 3 555h aah 2aah 55h bk (3) + 555h 90h ia (4) id (5) auto program 4 555h aah 2aah 55h 555h a0h pa (6) pd (7) auto page program 11 555h aah 2aah 55h 555h e6h pa (6) pd (7) pa (6) pd (7) pa (6) pd (7) program suspend 1 bk (3) b0h program resume 1 bk (3) 30h auto chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h auto block erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba (8) 30h block erase suspend 1 bk (3) b0h block erase resume 1 bk (3) 30h fast program set 3 555h aah 2aah 55h 555h 20h fast program 2 xxxh a0h pa (6) pd (7) fast program reset 2 xxxh 90h xxxh f0h (9) block protect 2 (10) 3 xxxh 60h bpa (11) 60h xxxh 40h bpa (11) bpd (12) hidden rom mode entry 3 555h aah 2aah 55h 555h 88h hidden rom program 4 555h aah 2aah 55h 555h a0h pa (6) pd (7) hidden rom erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba (8) 30h hidden rom protect 5 555h aah 2aah 55h 555h 60h xx1ah 68h xx1ah 48h ra (1) rd (2) hidden rom exit 4 555h aah 2aah 55h 555h 90h xxxh 00h cfi 1 bk (3) + 55h 98h ca (13) cd (14) notes: the system should generate the following address patterns: 555h or 2aah on address pins a10~a0. dq8~dq15 are ignored. x : v ih or v il (0h-fh) (1) ra: read address (2) rd: read data output (3) bk: bank address = a21~a19 (4) ia: bank address and id read address (a6,a1,a0) bank address = a21~a19 manufacturer code = (0,0,0) device code = (0,0,1) (5) id: id code output (6) pa: program address input input continuous 8 addresses from (a0, a1, a2) = (0, 0, 0) to (a0, a1, a2) = (1, 1, 1) in page program. : read operations (7) pd: program data input input continuous 8 address from (a0, a1, a2) = (0, 0, 0) to (a0, a1, a2) = (1, 1, 1) in page program. (8) ba: block address = a21~a12 (9) f0h: 00h is valid too. (10) input vid to reset (11) bpa: block address and id read address (a6,a1,a0) block address = a21~a12 id read address = (0,1,0) (12) bpd: verify data output (13) ca: cfi address (14) cd: cfi data output
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 8/80 8. command sequences(continue) first bus write cycle second bus write cycle third bus write cycle fourth bus write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle command sequence bus write cycles req?d addr. data addr. data addr. data addr. data addr. data addr. data addr. data 555h aah 2aah 55h 555h 38h xx0h pd0 (1) 555h aah 2aah 55h 555h 38h xx1h pd1 (1) 555h aah 2aah 55h 555h 38h xx2h pd2 (1) password program 4 555h aah 2aah 55h 555h 38h xx3h pd3 (1) password unlock 7 555h aah 2aah 55h 555h 28h xx0h pd0 (1) xx1h pd1 (1) xx2h pd2 (1) xx3h pd3 ( 1 ) password verify 3 555h aah 2aah 55h 555h c8h pwa (2) pwd (3) password protection mode lock 5 555h aah 2aah 55h 555h 60h x0ah 68h x0ah 48h xxh pd(0) (4) non-password protection mode lock 5 555h aah 2aah 55h 555h 60h x12h 68h x12h 48h xxh pd(0) (4) ppb set 5 555h aah 2aah 55h 555h 60h ba (5) + xx02h 68h ba (5) + xx02h 48h xxh pd(0) (4) all ppb clear 5 555h aah 2aah 55h 555h 60h xx02h 60h ba (5) + xx02h 40h xxh pd(0) (4) verify block protect 3 555h aah 2aah 55h ba (5) + 555h 90h ba (5) + xx02h pd(0) (4) ppb lock set 3 555h aah 2aah 55h 555h 78h ppb lock verify 3 555h aah 2aah 55h 555h 58h ba (5) pd(1) (4) dpb set 4 555h aah 2aah 55h 555h 48h ba (5) x1h dpb clear 4 555h aah 2aah 55h 555h 48h ba (5) x0h dpb verify 3 555h aah 2aah 55h 555h 58h ba (5) pd(0) (4) notes: the system should generate the following address patterns: 555h or 2aah on address pins a10~a0. dq8~dq15 are ignored. x : v ih or v il (0h-fh) (1) pd0 : 1st password (data of 1-16bit) pd1 : 2nd password (data of 17-32bit) pd2 : 3rd password (data of 33-48bit) pd3 : 4th password (data of 49-64bit) (2) pwa: password address input (3) pwd: password data output (4) pd(0): data (1: set/ 0: reset) on dq0. pd(1): data (1: set/ 0: reset) on dq1. (5) ba: block address = a21~a12 : read operations
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 9/80 9. simultaneous read/write operation the tc58fvm6(t/b)5b features a simultaneous read/write operation. the simultaneous read/write operation enables the device to simultaneously write data to or erase data from a bank while reading data from another bank. the tc58fvm6(t/b)5b has a total of sixteen banks (8mbits x 8 banks). banks can be switched by using the bank addresses (a21~a19). for a description of bank blocks and addresses, please refer to the block address table and block size table. the simultaneous read/write operation cannot perform multiple operations within a single bank. the table below shows the operation modes in which simultan eous operation can be performed. note that during auto-program execution or auto block erase operation, the simult aneous read/write operation cannot read data from addresses in the same bank which have not been select ed for operation. data from th ese addresses can be read using the program suspend or erase suspend function, however. in order to perform simultaneous operation du ring automatic operation execution, when changing a bank, it is necessary to set oe to v ih . simultaneous read/write operation status of bank on which operation is being performed status of other banks read mode id read mode (1) auto-program mode auto-page program mode fast program mode (2) program suspend mode auto block erase mode auto multiple block erase mode (3) erase suspend mode program during erase suspend program suspend during erase suspend cfi mode read mode (1) only command mode is valid. (2) excluding times when acceleration mode is in use. (3) if the selected blocks are spread across all eigh t banks, simultaneous operation cannot be carried out.
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 10/80 10. operation modes in addition to the read, write and erase modes, the tc58fvm6(t/b)5b features many functions including bl ock protection and data polling. when incorporating the device into a design, please refer to the timing charts and flowcharts in combination with the descriptions below. 10.1. read mode to read data from the memory cell array, set the device to read mode. the device is automatically set to read mode immediately afte r power-on or on completion of an automatic operation. the software reset command releases the id read mode, releases the lock state when an automatic operation ends abnormally, and sets the device to read mode. hardwa re reset terminates operation of the device and resets it to read mode. when reading data without changing the address immediately after power-on, the host should inpu t hardware reset or change ce from h to l. 10.2. id read mode id read mode is used to read the device maker code and device code. the mode is useful in that it allows eprom programmers to identify the device type automatically. access time in id read mode is the same as that in read mode . for a list of the codes, please refer to the id code table. id read can be executed in two ways, as follows: (1) applying v id to a9 mainly eprom programmers use this method. applying v id to a9 sets the device to id read mode, outputting the maker code from address 00h and the devi ce code from address 01h. releasing v id from a9 returns the device to read mode. with this method, all banks are set to id read mode; thus, simultaneous operation cannot be performed. (2) input command sequence with this method simultaneous operation can be performed. inputting an id read command sets the specified bank to id read mode. banks are specified by inputting the bank addre ss (bk) in the third bus write cycle of the command cycle. to read an id code, the bank address as well as the id read address must be specified (with /acc wp = v ih or v il ). the maker code is output from address bk + 00; the device code is output from address bk + 01. from other banks, data is output from the memory cells. inputting a reset command rele ases id read mode and returns the device to read mode. 10.3. standby mode tc58fvm6(t/b)5b has two ways to put the device into standby mode. in standby mo de, dq is put into the high-impedance state. (1) control using ce and reset with the device in read mode, input v dd 0.3 v to ce and reset . the device will enter standby mode and the current will be reduced to the standby current (i dds1 ). however, if the device is in th e process of perfor ming simultaneous operation, the device will not enter standby mode bu t will instead cause the operating current to flow. (2) control using reset only with the device in read mode, input v ss 0.3 v to reset . the device will enter standby mode and the current will be reduced to the standby current (i dds1 ). even if the device is in the process of performing simultan eous operation, this method will terminate the current operation and set the device to standby mode. this is a hardware reset and is described later. 10.4. auto-sleep mode this function suppresses power dissipation during reading. if the a ddress input does not change for 150 ns, the device will automatically enter sleep mode and the current will be reduced to the standby current (i dds2 ). however, if the device is in the process of performing si multaneous operation, the device will not enter standby mode but will instead cause the operating current to flow. because the output data is latched, data is ou tput in sleep mode. when the addr ess is changed, sleep mode is automatically released, and data from the new address is output. 10.5. output disable mode inputting v ih to oe disables output from the device and sets dq to high-impedance.
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 11/80 10.6. command write the tc58fvm6(t/b)5b uses the standard jedec control commands for a single-power supply e 2 prom. a command of write is executed by in putting the address and data into the command register. the command is written by inputting a pulse to we with ce = v il and oe = v ih ( we control). the command can also be written by inputting a pulse to ce with we = v il ( ce control). the address is latche d on the falling edge of either we or ce . the data is latched on the rising edge of either we or ce . dq0~dq7 are valid for data input and dq8~dq15 are ignored. to abort input of the command sequence uses the reset command. the device w ill reset the command register and enter read mode. if an undefined command is input, the command register will be reset and the device will enter read mode. 10.7. software reset: read/reset command initiate the software reset by inputting a read/reset command . the software reset returns the device from id read mode or cfi mode to read mode, releases the lock state if au tomatic operation has ended abnormally, and clears the command register. 10.8. hardware reset a hardware reset initializes the device and sets it to read mode. when a pulse is input to reset for t rp , the device abandons the operation which is in progress and enters the read mode after t ready . note that if a hardware reset is applied during data overwriting, such as a write or erase operation, data at the addre ss or block being written to at the time of the reset will become undefined. after a hardware reset, the device enters read mode if reset = v ih or standby mode if reset = v il . the dq pins are high-impedance when reset = v il . after the device has entered read mode, read operations and input of any command are allowed. 10.9. comparison between software reset and hardware reset action software reset hardware reset releases id read mode or cfi mode. true true clears the command register. true true releases the lock state if automatic operation has ended abnormally. true true stops any automatic operation wh ich is in progress. false true stops any operation other than the above and returns the device to read mode. false true
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 12/80 10.10. auto-program mode the tc58fvm6(t/b)5b can be programmed in word units. auto-program mode is set using the program command. the program address and prog ram data is latched in the fourth bus write cycle. auto programming starts on the rising edge of the we signal in the fourth bus write cycle. the program and program verify commands are automatically executed by the chip. the device status during programming is indicated by the ha rdware sequence flag. to read the hardware sequence flag, specify the address to which th e write is being performed. during auto program execution, a command sequence for the bank on which execution is being performed cannot be accepted. to terminate execution, use a hardware reset. note that if the auto-program operation is terminated in this manner, the data written so far is invalid. any attempt to program a protected block is ignored. in this case, the device enters read mode 3 s after a latch of program data in the fourth bus write cycle. if an auto-program operation fails, the de vice remains in the programming state and does not automatically return to read mode. the device status is indicated by the hardware sequence flag. either a reset command or a hardware reset is required to return the device to read mode after a failure. if a progra mming operation fails, the device should not be used. to build a more reliable system, the host processor should take measures to prevent subseq uent use of failed blocks. the device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into cells which contain 0s. if this is attempted, execution of auto program will fail. this is a user error, not a device error. a cell contain ing 0 must be erased in order to set it to 1. 10.11. auto-page program mode auto-page program is a function which enables simultaneously pr ogramming or 8words of data. in this mode, the programming time for 64m bit is less than 60% compared with the auto program mode. in word mode, input the page program command during first bus write cycle to third bus writes cycle. in put program data and address of (a0, a1, a2) = (0, 0, 0) in the forth bus write cycle. input increment address and program data during the fifth bus write cycle to the eleventh bus write cycle. after inpu t of the eleventh bus write cycle, page program operation starts. 10.12. fast program mode fast program is a function wh ich enables execution of the command sequence for the auto program to be completed in two cycles. in this mode the first two cycles of the command sequence, which normally requ ires four cycles, ar e omitted. writing is performed in the remaining two cycles. to execute fast program, input the fast program command. writes in this mode uses the fast program command but operation is the same at that for ordinary auto-program. the status of the device is indicated by the hardware sequence flag and read operations can be performed as usual. to exit this mode, the fast program reset command must be input. when the command is input, the device will return to read mode. 10.13. acceleration mode the tc58fvm6(t/b)5b features an acceleration mode th at allows write time to be reduced. applying v acc pin to /acc wp automatically sets the device to accelera tion mode. in acceleration mode, block protect mode changes to temporary block unprotect mode. write mode changes to fast program mode. modes are switched by the /acc wp signal; thus, there is no need for a temporary block unprot ect operation or to set or rese t fast program mode. operation of write is the same as in auto-program mode. removing v acc from /acc wp terminates acceleration mode. this function can perform only auto program mode and auto page program mode. id read or other commands cannot be done.
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 13/80 10.14. program suspend/resume mode program suspend is used to enable data read by suspending the write operation. the device accepts a program suspend command in write mode (including write operations performe d during erase suspend) but ignores the command in other modes. when the command is inpu t, the address of the bank on wh ich write is being performed mu st be specified. in program suspend mode, it is invalid except a read command, a id read command, a cfi command, and a resume command. after input of the command, the device will en ter program suspend read mode after t susp . during program suspend, cell data read, id read and cfi data read can be performed. when data write is suspended, the address to which write was being perf ormed becomes undefined. id read and cfi data read are the same as usual. after completion of program suspend, input a program resume command to retu rn to write mode. when inputting the command, specify the address of the bank on which write is being performed. if the id read or cfi data read function is being used, abort the function before in putting the resume command. on receiving the resume command, the device returns to write mode and resumes outputting the hardware sequen ce flag for the bank to which data is being written. program suspend can be run in fast program mode or acceleration mode. however, note that when running program suspend in acceleration mode, v acc must not be released. 10.15. auto chip erase mode the auto chip erase mode is set using th e chip erase command. an auto chip eras e operation starts on the latch of the command in the sixth bus cycle. all memory cells are automatically preprogrammed to 0, erased an d verified as erased by the chip. the device status is indicated by the hardware sequence flag. command input is ignored during an auto chip erase. a hardware reset can interrupt an auto chip erase operation. if an auto chip erase operation is interrupted, it cannot be comple ted correctly. hence, an additi onal erase operation must be performed. any attempt to erase a protected block is ig nored. if all blocks are protected, the auto erase operation will not be executed and the device will enter read mode 400 s after the latch of command in the sixth bus cycle. if an auto chip erase operation fails, th e device will remain in the erasing state and will not return to the read mode. the device status is indicated by the hardware sequence flag. eith er a reset command or a hardware reset is required to return the device to read mode after a failure. in this case, it cannot be ascertained wh ich block the failure occurred in. either abandon use of the device altogether, or perform a block erase on each block, iden tify the failed blocks, and stop using them. to build a more reliable system, the host processor should take measures to pr event subsequent use of failed blocks 10.16. auto block erase/auto multi-block erase modes the auto block erase mode and auto multi-block erase mode are set using the block erase command. the block address is latched in the sixth bus cycle. the auto block erase starts as soon as the erase hold time (t beh ) has elapsed after the latch of the command. when multiple blocks are eras ed, the sixth bus write cycle is repeated with each block address and auto block erase command being input within the erase hold time (this constitutes an auto multi-block erase operation). if a command other than an auto block erase command or erase suspend command is input during the erase ho ld time, the device will reset the command register and enter read mode. the erase hold time restarts on each successive command latch. once operation starts, all memory cells in the se lected block are automatically preprogrammed to 0, erased and verified as erased by the chip. the device status is indicated by the setting of the hardware sequence flag. when the hardware sequence flag is read, the addresses of the blocks on which auto-erase operation is being performed must be specif ied. if the selected blocks ar e spread across all 8 banks, simultaneous operation cannot be carried out. all commands (except erase suspend) are ig nored during an auto block erase or au to multi-block erase operation. either operation can be aborted using a hardware reset. if an auto-era se operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing. any attempt to erase a protected block is ig nored. if all the selected blocks are pr otected, the auto-erase operation is not executed and the device returns to read mode 400 s after the latch of command in the last bus cycle. if an auto-erase operation fails, the device remains in the erasing state and does not return to read mode. the device status is indicated by the hardware sequence flag. after a failure, eith er a reset command or a hardware reset is required to return the device to read mode. if multiple blocks are selected, it will not be possible to ascertain the block in which the failure occurred. in this case either abandon use of the device altogether, or perform a block erase on each block, identify the failed blocks, and stop using them. to build a more reliable system, th e host processor should take me asures to prevent subsequent use of failed blocks.
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 14/80 10.17. erase suspend/erase resume modes erase suspend mode suspends auto block erase and reads data from or writes da ta to an unselected block. the erase suspend command is allowed during an au to block erase operation but is ignored in all other oreration modes. when the command is input, the address of the bank on which erase is bein g performed must be specified. in erase suspend mode, it is invalid except a read command, a id read command, a cfi command, a program command, and a resume command. if an erase suspen d command is input during an auto bl ock erase, the devi ce will enter erase suspend read mode after t suse . the device status (erase suspend read mode ) can be verified by checking the hardware sequence flag. if data is read consecutiv ely from the block selected for auto bloc k erase, the dq2 outp ut will toggle and the dq6 output will stop toggling and by / ry will be set to high-impedance. inputting a write command during an erase suspend enables a wr ite to be performed to a bloc k which has not been selected for the auto block erase. data is written in the usual manner. to resume the auto block erase, input an erase resume command. on input of the command, the address of the bank on which the write was being performed must be specified. on re ceiving an erase resume command, the device returns to the state it was in when the erase suspend command was input. if an erase suspend command is input during the erase hold time, the device will return to the state it was in at the start of the er ase hold time. at this time more blocks can be specif ied for erasing. if an erase resume command is input during an au to block erase, erase resumes. at this time toggle output of dq6 resumes and 0 is output on by / ry .
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 15/80 10.18. block protection tc58fvm6(t/b)5b has block protection that is a function for disabling writing and eras ing specific blocks. block protection features several level of block protection. (1) write protect ( /acc wp pin) [hardware protection] the tc58fvm6(t/b)5b has hardware block protection feature by /acc wp =v il . the tc58fvm6t5b protects ba133 and ba134 with /acc wp =v il . tc58fvm6b5b protects ba0 and ba1 with /acc wp =v il . this mode is released with /acc wp =v ih . when the device is programming operation or erasing operation, /acc wp pin has to fix to v ih or v il . (2) block protection 1 persistent protection bit (ppb) [v id protection] specify a device block address and make the following signal settings a9 = oe = v id , a1 = v ih and ce = a0 = a6 = v il . now when a pulse is input to we for t pplh , the device will start to write to the block protection circuit. block protection can be verified using the ve rify block protect command. inputting v il on oe sets the device to verify mode. 01h is output if the block is protected an d 00h is output if the block is unprotec ted. if block protection was unsuccessful, the operation must be repeated. releasing v id from a9 and oe terminates this mode. when the device state is password protection mode, the hosts have to execute the password unlock command before performing this protection command. (3) block protection 2 persistent protection bit (ppb) [v id protection] inputting the block protect 2 command with reset = v id also performs block protec tion. the first cycle of the command sequence is the set-up command. in the second cycl e, the block protect command is input, in which a block address and a1 = v ih and a0 = a6 = v il are input. now the device writes to the block protection circuit. there is a wait of t pplh until this write is completed; howeve r, no intervention is necessary duri ng this time. in the third cycle the verify block protect command is input. this command verifi es the write to the block pr otection circuit. read is performed in the fourth cycle. if the prot ection operation is complete, 01h is outp ut. if a value other than 01h is output, block protection is not complete and the block protect command must be input again. removing the v id input from reset , exits this mode. when the device state is password protection mode, the hosts have to execute the password unlock command before performing this protection command. (4) block protection 3 persistent protection bit(ppb) [software protection] this feature is the bloc k protection without v id . by using persistent protection bit, protection can be set to each block. the ppbs retains the state across power cycle. each ppb can be individually modifiable through the ppb set command. all ppb can be cleared by the ppb clear command at a time . the ppb verify command to the device can check the ppb status. the 5th and 6th write bus cycle of the ppb set are ppb veri fy cycle. when completely fi nish the ppb set, the device outputs ?1? on dq0 at the sixth bus writ e cycle. when device outputs ?0? on dq0 , the ppb set is not complete, then the hosts must retry from fourth bus write cycle. similarly, when completely finish the ppb clear, the device outputs ?0? on dq0 at the sixth bus write cycle. when th e device outputs ?1? on dq1, the ppb clea r is not complete, then the hosts must retry from fourth bus write cycle. when ppb is locked by the ppb lock set command, ppb is disabled for ppb set and ppb clear operation. the ppb lock verify command can check the ppb lock status on the dq1 (?1? is set state and ?0? is clear state). behaviors of ppb lock differ between password protection mode and non-password protection mode. at the time of the finishing ppb set, ppb clear, ppb lock set and ppb lock ve rify, the hosts have to inputting the hidden rom exit command. at the time of shipment, the ppbs and ppb lock are settled to ?0?. (5) block protection 4 dynamic protection bit (dpb) [software protection] this feature is the bloc k protection without v id . by using dynamic protection bit, pr otection can be set to each block. after power-up or hardware reset cycle, all dpb are settled to ?0? as clear. each dpb can be individually modifiable through the dpb set command and dpp clear command. the writing of the dpb verify command to the device can ch eck the set or clear of the dpb status. when completely finish the dpb set, device will be output ting ?1? on dq0 at the four th bus write cycle in the dpb verify. when device is outputting ?0? on dq0, the dpb set is not complete, then the hosts must retry from the dpb set command. similarly, when completely finish the dpb clear, th e device will be outputting ?0? on dq0 at the fourth bus write cycle in the dpb verify. when the device is outputting ?1? on dq0, the dpb cl ear is not complete, then the user must retry from the dpb clear command. at the time of the finishing dpb set, dpb cl ear, and dpb verify, the hosts have to inputting the hidden rom exit command.
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 16/80 10.18.1 relationship of the each block protection * a program of one of ppb and the dpb protects an object block. 10.18.2. block protection matrix hardware protection software protection block protect status /acc wp reset ppb dpb two boot block other block clear clear unprotected set x h x set protected l vid x x protected unprotected clear clear unprot ected unprotected set x h x set protected protected h vid x x unprotec ted unprotected notes x: h or l, set state or clear state device protect state block protection 1 block protection 2 block protection 3 (ppb) (non-password protection mode) ppb set dpb set dpb clea r ppb set ppb clea r block protection 3 (ppb) (password protection mode) block protection 4 (dpb) password unlock command power-up cycle or hardware reset ppb lock is a set state (ppb set/clear is disabled) power-up cycle or ppb lock set or hardware reset ppb lock is a cleared state (ppb set/clear is enabled) power-up power-up ppb lock is a cleared state (ppb set/clear is enabled) ppb lock is a set state (ppb set/clear is disabled) ppb lock set command power-up dpb is a cleared state
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 17/80 10.18.3. non-password protection m ode and password protection mode at block protection 3, there are two protection mode of non-password protection mode and password protection mode. operation of a ppb lock differs in each mode. the hosts need to choose either non-password protection mode or password protection mode before using of this device. non-password protection mode lock command sets the devi ce to non-password protection mode. password protection mode lock command sets the device to password protection mode. the respective program command can be executed only once, and mode lock erase is impossible. at the shipment, the non-password protection mode and the password protection mode aren?t set state. in the case of using non-password protection mode, the hosts have to execute a non-password protection mode lock in order to prevent the device from be ing changed to password protection mode. in the case of using password protection mode, th e hosts have to execute a password protection mode lock. once a pr otection mode is set, it is not eternally changeable. after latching the fourth bus write cycle command of " 68h", th e hosts have to wait 100us. th e 5th and 6th write bus cycles are protection mode verify command. when th e protection mode lock (set) is completely finished, the device will output ?1? on dq0 at the sixth bus write cycle. when the device is outputting ?0? on dq0, the protection mode lock (set) is not complete, then the hosts must retry from fourth bus write cycle. when the protection mode lock (set) is finished, the hosts have to execute the hidden rom exit command. non-password protection mode lock password protection mode lock device status 0 0 non-password protection mode (at shipment) programmed (?1?) 0 non-pa ssword protection mode 0 programmed (?1?) passw ord protection mode programmed (?1?) programmed (?1?) inhibit 10.18.4. ppb lock in non-password protect ion mode and password protection mode in the case of non-password protection mode, the ppb lock is cleared by power-up cycle and hardware reset. when ppb lock is set, the ppbs are disabled for mo dification by block protection 3. after power-up cycle and hardware reset again, ppb lock becomes ?0? as clear. in non-password protection mode, password unlock command is ignored. in the case of password protection mode, the ppb lock is set by power-up cycle and hardware reset. once password protection mode is set, ppb is disabl ed for modification by ppb set and clea r without the password unlock command. the state of ppb lock doesn?t differ before and after password protection mode lock command. ppb lock is set again by power-up cycle, hardware reset, or ppb lock set. in password protection mode, password program command and password verify command is permanently ignored. therefore, when the us er chooses the password protecti on mode, it is necessary to program a 64-bit password to this device before performing a password protection mode lock command. after password program command, the user has to chec k by password verify command whether the desired password is certainly programmed. once password protec tion mode was set, the user cannot check the password. at modifying ppb, the user has to use the password unlock command with a 64-bi t password. please set a password certainly. ppb lock status of the non-password protec tion mode and the password protection mode non-password protection mode password protection mode after power-up cycle and hardware reset ppb lock is ?0? (clear) ppb lock is ?1? (set) ppb lock status change method of the each protection mode non-password protection mode password protection mode ppb lock set ppb lock set ppb set command power-up cycle hardware reset ppb lock clear power-up cycle hardware reset password unlock command
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 18/80 10.18.5. description of password protection command (1) password program command the password protect command pe rmits programming the password that is used as part of the hardware protection scheme. the actual password length is 64-bits. the 64-bits pa ssword is split to four of 16-bits password program. in password protection mode, pa ssword program and password ve rify are disabled. during programming the password, simultaneous operation is disabled. read operations to any memory location is available after completion of the password programming. the status of pass word program operation can be checked by hardware sequence flags. when this mode is finished, the hosts have to execute the hi dden rom exit command. password is set as four words of ?ffffh? at the time of shipment. the hardware sequence flags of the password program dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 by / ry in progress 0 toggle 0 0 0 1 0 0 0 program complete 1 1 0 0 0 1 0 0 high-z program failed 0 toggle 1 0 0 1 0 0 0 (2) password verify command the password verify command is verify the password. verification of a password can be performed when the password protection mode lock is not pr ogrammed. in password protec tion mode, if the user attempts to verify the password, the device output "ffffh". the hosts have to execute the hidden rom entry command before password verify. during verification the password, simultaneous operation is disabled. at the forth bu s write cycle of password verify command, the hosts have to fix the two address bits (a 1, a0). when this mode is finished, the hosts have to execute the hidden rom exit command. (3) password unlock command the password unlock command clears the ppb lock bit when the user sets the password protection mode. in order to perform password unlock command, the exact password is necessary. it is necessary to input password unlock command at intervals of 2us or more. if the interv al is shorter than 2us, the command is ignored. at password unlock command the 64-bits password is input in four step at 4th, 5th, 6th, 7th write bus cycles. the address a1:a0 is 0:0 at 4th write bus cycle, a1:a0 is 0:1 at 5th write bus cycle, a1:a0 is 1;0 at 6th write bus cycle, and finally a1:a0 is 1:1 at 7th write bus cycle. a wrong password input at the password unlock se quence causes mismatch of password and ppb lock bit is not changed. when the password unlock command is entered, the by / ry pin is low, which is indicating the device is busy. the status of password unlock operation can be checked by hardwa re sequence flags. then flags are output by specifying the address of bank0 (bottom boot block) or bank7 (top boot block). inputting addre ss of the other bank then, actual cell array data is output. the hardware sequence flags indicate whether exact password is inputte d at 4-6th write bus cycles by intervals of 2us or more. during inputting password at 4-7th write bus cycles, dq6 is toggling. when the first password unlock is successful, by / ry pin is low and dq6 stop toggling. then user can input next password. when the password unlock command operation completes, the user has to perform hidden rom exit command. ppb lock bit should be read in order to check whether password unlock has completed successfully.
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 19/80 status flags of progressing the password unlock command dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 by / ry pwd unlock in progress 0 toggle 0 0 0 1 0 0 0 finished input pwd (1) 0 (2) 1 0 0 0 1 0 0 0 finished input pwd (1) 1 (3) 1 0 0 0 1 0 0 high-z finished input pwd (4) array data high-z notes: () specified ba within bank-0 (bottom boot bl ock device)/ bank-7 (top boot block device) () after inputting pwd at the 4th ,5th and 6th bus write cycles, dq7 is ?0? () after inputting pwd at the 7th bus write cycle, dq7 is ?1? () specified ba without bank-0 (bottom boot bl ock device)/ bank-7 (top boot block device) 10.18.6. temporary block unprotection the tc58fvm6(t/b)5b has a temporary block unprotection feature which disables block protecti on for all protected blocks. unprotection is enabl ed by applying v id to the reset pin. now write and erase operations can be performed on all blocks except the boot blocks which have been pr otected by the boot block prot ect operation. the device re turns to its previous state when v id is removed from the reset pin. that is, previously protecte d blocks will be protected again. 10.18.7. verify block protect the verify block protect command is used to ascertain whether a block is protected or unprotected. verification is performed either by inputting the verify bloc k protect command or by applying v id to the a9 pin . the verify block protect command, which can be performed simultaneously with operations in another bank, is performe d by setting the block address with a0 = a6 = v il and a1 = v ih . if the block is protected, 01h is output. if the block is unprotected, 00h is output. the status depends on ppb, dpb, /acc wp and reset state. inputting the verify block protect command sequence sets the specified bank to th e verify block protect mode. inputting a reset command releases this mode and returns the device to read mode. when verifying block protect across a bank boundary, a reset command is needed at the time of the change of a bank
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 20/80 10.19. hidden rom area the tc58fvm6(t/b)5b features a 64-kbyte hidden rom area, whic h is separate from the memory cells. the area consists of one block. data read, write and protect can be performed on this block. because protect cannot be released, once the block is protected, data in the block cannot be overwritten. the hidden rom area is located in the address space in dicated in the hidden rom area address table. to access the hidden rom area, input a hidden rom mode entry command. the device now enters hidden rom mode, allowing read, write, erase and block protect to be exec uted. write and erase operations are the sa me as auto operations except that the device is in hidden rom mode. to protect the hidden rom area, use the bl ock protection 1 function or the block protection 2 function. the operation of block protect 2 here is the same as a normal block protect except that v ih rather than v id is input to reset . when the ppb lock has been settled, hidden rom protect state cannot be changed by the block protecti on 1 function or the block protection 2 function. the hosts have to de cide the protection state of hidden rom ar ea before the ppb lock has been settled. once the block has been protecte d, protection cannot be released, even using th e temporary block unprot ection function. using block protection for hidden ro m area must be careful. note that in hidden rom mode, simultaneous operation cannot be performed for bank7 in top boot type and for bank0 in bottom boot type. to exit hidden rom mode, use the hidden rom mode exit command. this will return the device to read mode. hidden rom area address table type boot block architecture address range size tc58fvm6t5b top boot block 3f8000h~3fffffh 32 kwords tc58fvm6b5b bottom boot block 000000h~007fffh 32 kwords
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 21/80 10.20. cfi (common flash memory interface) the tc58fvm6(t/b)5b conforms to the cfi specifications. to read information from the device, input the query command followed by the address. in word mode dq8~dq15 all ou tput 0s. to exit this mode, input the reset command. cfi code table 1 (continue) address a6~a0 data dq15~dq0 description 10h 11h 12h 0051h 0052h 0059h ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 2: amd/fj standard type 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set 0: none exists 19h 1ah 0000h 0000h address for alternate oem extended table 1bh 0023h v dd (min) (write/erase) dq7~dq4: 1 v dq3~dq0: 100 mv 1ch 0036h v dd (max) (write/erase) dq7~dq4: 1 v dq3~dq0: 100 mv 1dh 0000h v pp (min) voltage 1eh 0000h v pp (max) voltage 1fh 0004h typical time-out per single word write (2 n s) 20h 0000h typical time-out for minimum size buffer write (2 n s) 21h 000ah typical time-out per individual block erase (2 n ms) 22h 0000h typical time-out for full chip erase (2 n ms) 23h 0005h maximum time-out for word write (2 n times typical) 24h 0006h maximum time-out for buffer write (2 n times typical) 25h 0004h maximum time-out per individual block erase (2 n times typical) 26h 0000h maximum time-out for full chip erase (2 n times typical) 27h 0017h device size (2 n byte) 17h:64mbit 28h 29h 0001h 0000h flash device interface description 1: x 16 2ah 2bh 0004h 0000h maximum number of bytes in multi-byte write (2 n )
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 22/80 cfi code table 2(sequel) address a6~a0 data dq15~dq0 description 2ch 0002h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information bits 0~15: y = block number bits 16~31: z = block size (z 256 bytes) 31h 32h 33h 34h 00feh 0000h 0000h 0001h erase block region 2 information 40h 41h 42h 0050h 0052h 0049h ascii string ?pri? 43h 0031h major version number, ascii 44h 0031h minor version number, ascii 45h 0000h address-sensitive unlock 0: required 1: not required 46h 0002h erase suspend 0: not supported 1: for read-only 2: for read & write 47h 0001h block protect 0: not supported x: number of blocks per group 48h 0001h block temporary unprotect 0: not supported 1: supported 49h 0007h block protect/unprotect scheme 4ah 0001h simultaneous operation 0: not supported 1: supported 4bh 0000h burst mode 0: not supported 4ch 0001h page mode 0: not supported 1: supported 4dh 0085h v acc (min) voltage dq7~dq4: 1 v dq3~dq0: 100 mv 4eh 00c6h v acc (max) voltage dq7~dq4: 1 v dq3~dq0: 100 mv 4fh 000xh top/bottom boot block flag x = 2: bottom boot block: tc58fvm6b5b x = 3: top boot block: tc58fvm6t5b 50h 0001h program suspend 0: not supported 1: supported
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 23/80 cfi code table 3(sequel) address a6~a0 data dq15~dq0 description 57h 0010h bank organization 00h: data at 4ah is zero x: number of banks 58h 00xxh bank0 region information xx: number of blocks bank0 top : 10h bottom:17h 59h 0010h bank1 region information number of blocks bank1 n=16 5ah 0010h bank2 region information number of blocks bank2 n=16 5bh 0010h bank3 region information number of blocks bank3 n=16 5ch 0010h bank4 region information number of blocks bank4 n=16 5dh 0010h bank5 region information number of blocks bank5 n=16 5eh 0010h bank6 region information number of blocks bank6 n=16 5fh 00xxh bank7 region information xx: number of blocks bank7 top : 17h bottom:10h
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 24/80 10.21. hardware sequence flags the tc58fvm6(t/b)5b has a hardware sequence flag which allows the device status to be dete rmined during an auto mode operation. the output data is read out us ing the same timing as that used when ce = oe = v il in read mode. the by / ry output can be either high or low. the device re-enters read mode automatically after an auto mode operation has been completed successfully. the hardware sequence flag is read to determine the device status and the re sult of the operation is verified by comparing the read-out data with the original data. status dq7 dq6 dq5 dq3 dq2 by / ry auto programming/auto page programming 7 dq (4) toggle 0 0 1 0 read in program suspend (1) data data data data data high-z selected (2) 0 toggle 0 0 toggle 0 erase hold time not-selected (3) 0 toggle 0 0 1 0 selected 0 toggle 0 1 toggle 0 in auto erase auto erase not-selected 0 toggle 0 1 1 0 selected 1 1 0 0 toggle high-z read not-selected data data data data data high-z selected 7 dq toggle 0 0 toggle 0 in progress in erase suspend programming not-selected 7 dq toggle 0 0 1 0 auto programming/auto page programming 7 dq (4) toggle 1 0 1 0 auto erase 0 toggle 1 1 n/a 0 time limit exceeded programming in erase suspend 7 dq toggle 1 0 n/a 0 notes:dq outputs cell data and by / ry goes high-impedence when the operation has been completed. dq0 and dq1 pins are reserved for future use. 0 is output on dq0, dq1 and dq4. (1) data output from an address to which write is being performed is undefined. (2) output when the block address selected for auto bl ock erase is specified and data is read from there. (3) output when a block address not selected for auto block erase of same bank as selected block is specified and data is read from there. during auto chip erase, all blocks are selected. (4) in case of page program operation is program data of (a0, a1, a2) = (1, 1, 1) in eleventh bus write cycle. 10.21.1. dq7 ( polling) during an auto-program or auto-erase operation, the device status can be de termined using the data polling function. data polling begins on the rising edge of we in the last bus cycle. in an auto-program operation, dq7 outputs inverted data during the programming oper ation and outputs actual data after programming has finished. in an auto-erase operation, dq7 outputs 0 during the erase operatio n and outputs 1 when the erase operatio n has finished. if an auto-program or auto-erase operation fails, dq7 simply outputs the data. when the operation has finished, the address latch is reset. data polling is asynchronous with the oe signal. 10.21.2. dq6 (toggle bit 1) the device status can be determined by the toggle bit function during an auto-program or au to-erase operation. the toggle bit begins toggling on the rising edge of we in the last bus cycle. dq6 alternately outputs a 0 or a 1 for each oe access while ce = v il while the device is busy. when th e internal operation has been comple ted, toggling stops and valid memory cell data can be read by subsequent reading. if the operation fails, the dq6 output toggles. if an attempt is made to execute an auto program operation on a protecte d block, dq6 will toggle for around 3 s. it will then stop toggling. if an attempt is made to execute an auto erase oper ation on a protected block, dq6 will toggle for around 400 s. it will then stop toggling. after toggling has stopped the device will return to read mode. data
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 25/80 10.21.3. dq5 (internal time-out) if an auto-program or auto-erase operates normally, dq5 outputs a 0. if the internal timer times out during a program or erase operation, dq5 outputs a 1. this indicates that the operation has not been completed within the allotted time. any attempt to program a 1 into a cell containing a 0 will fail (see auto-program mode). in this case, dq5 outputs a 1. in this case, dq5 doesn?t indicate defective device but mistaken usage. after an auto-program or auto-erase operation ends normally, the device outputs actual cell array data. therefor only with the data of dq5 can?t specify whether cell array data or hardware sequence flag. the hosts shuold check the state of device whether progrress or not, using dq7, dq6, or by / ry . in the case of internal time-out, either hardware reset or a software reset command is required to return the device to read mode. 10.21.4. dq3 (block erase timer) the block erase operation starts 50 s (the erase hold time) after the rising edge of we in the last command cycle. dq3 outputs a 0 for the duration of the block erase hold time and a 1 when the block erase operation starts. additional block erase commands can only be accepted du ring the block erase hold time. each bl ock erase command input within the hold time resets the timer, allowing additional blocks to be marked for erasing. dq3 outputs a 1 if the program or erase operation fails. 10.21.5. dq2 (toggle bit 2) dq2 is used to indicate which blocks have been selected for auto block erase or to indicate whether the device is in erase suspend mode. if data is read continuously from the se lected block during an auto block erase, the dq2 output will toggle. now 1 will be output from non-selected blocks ; thus, the selected block can be ascertained. if data is read continuously from the block selected for auto block erase while the device is in erase su spend mode, the dq2 output will toggle. because the dq6 output is not toggling, it can be determined that the device is in erase suspend mode. if data is read from the address to which data is being written during erase suspend in programming mode, dq2 will output a 1. 10.21.6. (ready/ ) the tc58fvm6(t/b)5b has a by / ry signal to indicate the device status to the host processor. a 0 (busy state) indicates that an auto-program or auto-erase operation is in progress. a 1 (ready state) indicates that the operation has finished and that the device can now accept a new command. by / ry outputs a 0 when an operation has failed. by / ry outputs a 0 after the rising edge of we in the last command cycle. during an auto block erase operation, comm ands other than erase suspend are ignored. by / ry outputs a 1 during an erase suspend operation. the output buffer for the by / ry pin is an open-drain type circuit, allowing a wired-or connection. a pull-up resistor must be inserted between v dd and the by / ry pin. by / ry busy
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 26/80 11. data protection the tc58fvm6(t/b)5b includes a function which guards against malfunction or data corruption. 11.1. protection against program/erase caused by low supply voltage to prevent malfunction at power-on or power-do wn, the device will not accept commands while v dd is below v lko . in this state, command input is ignored. if v dd drops below v lko during an auto operation, the device will term inate auto-program executio n. in this case, auto operation is not executed again when v dd returns to recommended v dd voltage. therefore, comm and need to be input to execute auto operation again. when v dd > v lko , make up countermeasure to be input accurately command in system side please. 11.2. protection against malfunction caused by glitches to prevent malfunction write du ring operation caused by noise from the syst em, the device will not accept pulses shorter than 3 ns (typ.) input on we , ce or oe . however, if a glitch exceeding 3 ns (typ.) occurs and the glitch is input to the device malfunction write may occur. the device uses standard jedec commands. it is conceivable th at, in extreme cases, system no ise may be misinterpreted as part of a command sequence inpu t and that the device will acknowledge it. then, ev en if a proper command is input, the device may not operate. to avoid this possibility, clear the command register before command input. in an environment prone to system noise, toshiba recommends input of a software or hardware reset before command input. 11.3. protection against malfunction at power-on to prevent damage to data caused by sudden nois e at power-on, when power is turned on with we = ce =v il the device does not latch the command on the first rising edge of we or ce . instead, the device automa tically resets the command register and enters read mode.
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 27/80 12. absolute maximum ratings symbol parameter range unit v dd v dd supply voltage ? 0.6~4.6v v v in input voltage ? 0.5~vdd+0.5v( Q 4.6) (1) v v dq input/output voltage ? 0.5~vdd+0.5v( Q 4.6) (1) v v id maximum input voltage for a9, oe and reset (2) 13.0 v v acc maximum input voltage for /acc wp (2) 13.0 v p d power dissipation 600 mw t solder soldering temperature (10s) 260 c tc58fvm6(t/b)5btg ? 55~150 c t stg storage temperature tc58fvm6(t/b)5bxg ? 55~125 c t opr operating temperature ? 40~85 c i oshort output short-circuit current (3) 100 ma (1) this level may undershoot to ? 2.0 v for periods < 20 ns, and may overshoot to + 2.0 v for periods < 20 ns. (2) do not apply v id /v acc when the supply voltage is not within the device's recommended operating voltage range. (3) outputs should be shorted for no more than one second. no more than one output should be shorted at a time. 13. capacitance (ta = 25c, f = 1 mhz) symbol parameter condition max unit c in input pin capacitance v in = 0 v 7 pf c out output pin capacitance v out = 0 v 12 pf c in2 control pin capacitance v in = 0 v 7 pf c in3 /acc wp capacitance v in = 0 v 14 pf this parameter is periodically sampled and is not tested for every device. 14. recommended dc operating conditions symbol parameter min max unit v dd v dd supply voltage 2.7 3.6 v ih input high-level voltage 0.7 v dd v dd + 0.3 v il input low-level voltage ? 0.3 0.2 v dd v id high-level voltage for a9, oe and reset 11.4 12.6 v acc high-level voltage for /acc wp 8.5 12.6 v ta operating ambient temperature ? 40 85 c
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 28/80 15. dc characteristics symbol parameter condition min typ max unit i li input leakage current 0 v Q v in Q v dd ? ? 1 i lo output leakage current 0 v Q v out Q v dd ? ? 1 a i oh = ? 0.1 ma v dd ? 0.4 ? ? v oh output high voltage i oh = ? 2.5 ma 0.85 x v dd ? ? v ol output low voltage i ol = 4. 0 ma ? ? 0.4 v i ddo1 v dd average random read current v in = v ih /v il , i out = 0 ma t rc = 100ns ? 37 55 i ddo2 v dd average program current v in = v ih /v il , i out = 0 ma ? 11 15 i ddo3 v dd average erase current v in = v ih /v il , i out = 0 ma ? 9 15 i ddo4 v dd average read-while-program current v in = v ih /v il , i out = 0 ma t rc = 100ns ? 48 70 i ddo5 v dd average read-while-erase current v in = v ih /v il , i out = 0 ma t rc = 100ns ? 46 70 i ddo6 v dd average program-while- erase-suspend current v in = v ih /v il , i out = 0 ma ? 11 15 i ddo7 v dd average page read current v in = v ih /v il , i out = 0 ma t prc = 25ns ? 2 5 i ddo8 v dd average address increment read current (2) v in = v ih /v il , i out = 0 ma t rc =100ns t prc = 25ns ? 5 11 ma i dds1 vdd standby current /acc wp = v dd and ce = reset = v dd or reset = v ss ? 3 10 i dds2 v dd standby current (automatic sleep mode (1) ) v ih = v dd v il = v ss ? 3 10 i id high-voltage input current for a9, oe and reset 11.4 v Q v id Q 12.6 v ? ? 35 a i acc high-voltage input current for /acc wp 8.5v Q v acc Q 12.6 v ? ? 20 ma v lko low-v dd lock-out voltage ? 1.0 ? 2.0 v (1) the device enters automatic sleep mode in which the address remains fixed for during 150 ns. (2) (i ddo1+ i ddo7 7) 8words 16. ac test conditions parameter condition input pulse level v dd , 0.0 v input pulse rise and fall time (10%~90%) 5 ns timing measurement reference level (input) v dd /2, v dd /2 timing measurement reference level (output) v dd /2, v dd /2 output load c l (100 pf) + 1 ttl gate / c l (30 pf) + 1 ttl gate
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 29/80 17. ac characteristics an d operating conditions 17.1. read cycle output load capacitance (cl) 30 pf 100 pf symbol parameter min max min max unit t rc read cycle time 65 ? 70 ? ns t prc page read cycle time 25 ? 30 ? ns t acc address access time ? 65 ? 70 ns t ce ce access time ? 65 ? 70 ns t oe oe access time ? 25 ? 30 ns t pacc page access time ? 25 ? 30 ns t oeh oe high-level hold time (read) 0 ? 0 ? ns t cee ce to output low-z 0 ? 0 ? ns t oee oe to output low-z 0 ? 0 ? ns t oh output data hold time 0 ? 0 ? ns t aoh output data hold time (page read) 0 ? 0 ? ns t df1 ce to output high-z ? 25 ? 25 ns t df2 oe to output high-z ? 25 ? 25 ns hardware reset ( reset ) symbol parameter min max unit t ready read mode recovery time from reset (during auto operation) ? 25 s t ready read mode recovery time from reset during non auto operation ? 500 ns t rp reset low level hold time 500 ? ns t rh recovery time from reset 50 ? ns t rpd reset goes low to standby mode 20 ? s
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 30/80 17.2. block protect symbol parameter min max unit t vpt v id transition time 4 ? s t vps v id set-up time 4 ? s t cesp ce set-up time 4 ? s t vph oe hold time 4 ? s t pplh we low-level hold time 100 ? s 17.3. program and erase characteristics symbol parameter min typ. max unit t ppw auto-program time (word mode) ? 11 300 s t ppw accelerated auto-program time (word mode) ? 8 300 s t ppaw auto-page program time ? 58 2400 s t ppaw accelerated auto-page program time ? 21 2400 s t pcew auto chip erase time (1) ? 94 675 s t pcew accelerated auto chip erase time (1) ? 81 675 s t pbew auto block erase time (1) ? 0.7 5 (2) s t ew erase/program cycle 10 5 ? ? cycle. (1) auto chip erase time and auto block erase time include internal pre program time. (2) minimum interval between resume and the following suspend command is 150 s. if it's shorter than 150 s, auto block erase time is expand more than maximum(5 s).
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 31/80 17.4. command write/program/erase cycle symbol parameter min max unit t cmd command write cycle time 60 ? ns t as address set-up time 0 ? ns t ah address hold time 30 ? ns t ds data set-up time 30 ? ns t dh data set-up time 0 ? ns t welh we low-level hold time ( we control) 30 ? ns t wehh we high-level hold time ( we control) 20 ? ns t ces ce set-up time to we active ( we control) 0 ? ns t ceh ce hold time from we high level ( we control) 0 ? ns t celh ce low-level hold time ( ce control) 30 ? ns t cehh ce high-level hold time ( ce control) 20 ? ns t wes we set-up time to ce active ( ce control) 0 ? ns t weh we hold time from ce high level ( ce control) 0 ? ns t oes oe set-up time 0 ? ns t oehp oe high level hold time (polling) 10 ? ns t oeht oe high level hold time (toggle read) 20 ? ns t ceht ce high level hold time (toggle read) 20 ? ns t aht address hold time (toggle) 0 ? ns t ast address set-up time (toggle) 0 ? ns t beh erase hold time 50 ? s t vds v dd set-up time 500 ? s program/erase valid to by / ry delay ? 90 ns t busy program/erase valid to by / ry delay during suspend mode ? 300 ns t rb by / ry recovery time 0 ? ns t susp program suspend command to suspend mode ? 2 s t suspa page program suspend command to suspend mode ? 2.5 s t resp program resume command to program mode ? 1 s t suse erase suspend command to suspend mode ? 25 s t rese erase resume command to erase mode ? 1 s
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 32/80 18. timing diagrams read/id read operation id read operation (apply v id to a9) address t rc we t df2 t cee t oeh ce t ce t acc t oh d out output data valid hi-z oe t oee t oe t df1 hi-z v ih or v il data invalid a0 a1 t rc t acc a6 ce t vps t ce t oe a9 oe v id v ih we d out manufacture r code device code hi-z hi-z hi-z read mode read mode id read mode
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 33/80 page read operation read after command input (only hidden rom/cfi read) address(a3-21))) address(0-2) t acc ce oe we d out hi-z hi-z t pacc d out t ce t oe t rc t prc d out d out d out t oh t aoh t prc t prc t pacc d out t aoh t pacc t df2 t df1 address we ce d out d out valid hi-z oe hi-z last command address command data t wehh + t acc
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 34/80 command write operation this is the timing of the command write o peration. the timing which is described in the following pages is essentially the same as the timing shown on this page. ? we control ? ce control address ce d in command address t as t cmd t ces t welh we t ceh t ah t dh t ds t wehh command data v dd t vds t cmd address d in command address t as t wes t weh we t ah t dh t ds t celh t cehh command data ce v dd t vds
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 35/80 id read operation (input command sequence) address we ce d in t cmd d out bk + 00h bk + 555h 2aah 555h t rc 55h 90h t oes bk: bank address oe bk + 01h aah manufacturer code device code hi-z read mode (input of id read command sequence) id read mode address we ce d in t cmd d out 555h 2aah 555h 55h oe aah f0h id read mode (input of reset command sequence) read mode (continued) hi-z
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 36/80 auto-program operation ( control) address ce we d in t cmd d out t oehp pa 555h 2aah 555h t ppw d out 7 dq t oes t vds notes: pa: program address pd: program data v dd oe pa hi-z aah 55h a0h pd we
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 37/80 auto page program operation ( control) we t cmd d out t vds notes: pa: program address pd: program data v dd d out 7 dq hi-z address(a0-2) 0h 1h 2h 3h 4h 5h 7h 6h t oehp t ppaw oe ce t oes e6h d in aah 55h pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 we address(a3-21) pa pa 7h 555h 2aah 555h
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 38/80 auto chip erase/auto block erase operation ( control) we ce oe we v dd address d in aah 55h 80h aah 55h 10h/30h t cmd t oes t vds 555h 2aah 555h 555h 2aah 555h/ba notes: ba: block address
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 39/80 auto-program operation ( control) address we d in t cmd d out t oehp pa 555h 2aah 555h t ppw d out 7 dq t oes t vds note: pa: program address pd: program data v dd oe pa hi-z aah 55h a0h pd ce ce
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 40/80 auto page program operation ( control) ce t cmd d out t vds notes: pa: program address pd: program data v dd d out 7 dq hi-z address(a0-2) 0h 1h 2h 3h 4h 5h 7h 6h t oehp t ppaw oe ce t oes e6h d in aah 55h pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 we address(a3-21) pa pa 7h 555h 2aah 555h
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 41/80 auto chip erase/auto block erase operation ( control) ce oe we v dd address 555h d in aah 55h 80h aah 55h 10h/30h t cmd t oes t vds 555h/ba 2aah 555h 555h 2aah note: ba: block address for auto block erase operation ce
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 42/80 program/erase suspend operation address ce we d in d out b0h d out ra: read address oe hi-z by / ry t ce t oe t susp /t suse suspend mode program/erase mode hi-z ra bk
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 43/80 program/erase resume operation address ce we d in d out pa: program address bk: bank address ba: block address ra: read address flag: hardware sequence flag oe hi-z by / ry 30h program/erase mode suspend mode hi-z ra pa/ba t oes t resp /t rese t df1 d out t df2 flag t ce t oe bk
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 44/80 during auto program/erase operation hardware reset operation (at the auto operation) read after ce we by / ry t busy command input sequence during operation reset we by / ry t rp t ready t rb reset address reset d out t rc t rh t acc d out _ t oh hi-z address reset d out t rc t rh t acc output data valid t oh hi-z by / ry
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 45/80 hardware sequence flag ( polling) hardware sequence flag (toggle bit) address ce oe d in we t oe t oeh t oeht dq2/6 stop* toggle valid toggl toggle * dq2/dq6 stops toggling when auto operation has been completed. t busy by / ry t ce last command data toggle t aht t aht t ast dat a address ce t cmd last command address t df1 t df2 pa/ba d in t ppw /t pcew /t pbew t oh last command data we t oehp t ce t oe dq0~dq6 invalid dq7 7 dq oe pa: program address ba: block address t busy valid valid t acc valid valid by / ry
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 46/80 block protect 1 operation (ppb set) address a0 block protect a6 a1 ba t vpt a9 v id v ih verify block protect ce oe we ba: block address * : 01h indicates that block is protected. d out hi-z t vps v id v ih t cesp t pplh 01h * t oe hi-z t vph t vph
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 47/80 block protect 2 operation (ppb set) address a0 a6 ce t cmd oe ba ba t oe ba: block address ba + 1: address of next block * : 01h indicates that block is protected. we a1 ba + 1 t cmd t cmd t rc t pplh 60h 40h 60h 60h 01h * d in d out hi-z v ih v id t vps reset ba
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 48/80 19. flowcharts auto-program address = address + 1 no yes auto-program command sequence (see below) data polling or toggle bit last address? start 555h/aah 2aah/55h program address/ program data 555h/a0h auto-program command sequence (address/data) auto-program completed
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 49/80 auto-page program 555h/aah 2aah/55h 555h/e6h program address (a2=0,a1=0,a0=0) / program data program address (a2=0,a1=0,a0=1) / program data program address (a2=0,a1=1,a0=0) / program data program address (a2=0,a1=1,a0=1) / program data program address (a2=1,a1=1,a0=1) / program data program address (a2=1,a1=1,a0=0) / program data program address (a2=1,a1=0,a0=1) / program data program address (a2=1,a1=0,a0=0) / program data address = address + 1 no yes data polling or toggle bit last address? start auto page program command sequence (see below ) auto-program completed
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 50/80 fast program address = address + 1 no yes fast program command sequence (see below) data polling or toggle bit last address? start xxxh/a0h program address/ program data fast program command sequence (address/data) fast program completed fast program set command sequence (see below) program sequence (see below) 555h/aah 2aah/55h 555h/20h fast program set command sequence (address/data) xxxh/90h xxxh/f0h fast program reset command sequence (address/data)
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 51/80 auto erase auto erase command sequence (see below) data polling or toggle bit start 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h block address/30h block address/30h block address/30h auto chip erase command sequence (address/data) auto block/auto multi-block erase command sequence (address/data) a dditional address inputs during a uto multi-block erase auto erase completed
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 52/80 dq7 polling dq6 toggle bit dat a yes no yes no read byte (dq0~dq7) addr. = va read byte (dq0~dq7) addr. = va start dq7 = data? dq5 = 1? dq7 = data? no yes 1) 1) : dq7 must be rechecked even if dq5 = 1 because dq7 may change at the same time as dq5. fail pass va: valid address for programming any of the addresses within the block being erased during a block erase operation ?don?t care? during a chip erase operation no no no yes read byte (dq0~dq7) addr. = va read byte (dq0~dq7) addr. = va start dq6 = to g g l e ? dq5 = 1? dq6 = to g g l e ? yes yes 1) 1) : dq6 must be rechecked even if dq5 = 1 because dq6 may stop toggling at the same times that dq5 changes to 1. fail pass
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 53/80 block protect 1 yes no plscnt = 1 we = v il start plscnt = 25? protect another block? data = 01h? plscnt = plscnt + 1 set up block address addr. = bpa oe = a9 = v id , ce = v il wait for 100 s verify block protect remove v id from a9 yes no oe = v il no yes bpa: block address and id read address (a6, a1, a0) id read address = (0, 1, 0) wait for 4 s wait for 4 s we = v ih wait for 4 s block protect complete device failed oe = v ih wait for 4 s
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 54/80 block protect 2 bpa: block address and id read address (a6, a1, a0) id read address = (0, 1, 0) no no block protect 2 command first bus write cycle (xxxh/60h) verify block protect start plscnt = 25? protect another block? wait for 100 s remove v id from reset yes no yes set up address addr. = bpa plscnt = 1 remove v id from reset plscnt = plscnt + 1 wait for 4 s reset = v id block protect 2 command second bus write cycle (bpa/60h) block protect 2 command third bus write cycle (xxxh/40h) data = 01h? reset command block protect complete reset command device failed
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 55/80 hidden rom exit command input start 555h/00h 555h/aah 2aah/55h 555h/90h finish
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 56/80 password protection mode locking set operation no verify lock bit start plscnt = 25? wait 100 s yes no plscnt = 1 plscnt = plscnt + 1 password protection mode lock bit set command sequence 4th bus write cycle (x0a/68h) yes data = x1h? hiddenrom exit command lock set complete hiddenrom exit command device failed 555h/aah 2aah/55h 555h/60h password protection mode lock bit set command sequence 5th bus write cycle (x0a/48h)
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 57/80 password program operation yes no read status start dq5 = 1? pwa = 3? yes no no pwa = 0 password program command sequence 4th bus write cycle (pwa/pwd) yes dq7 = 1? hiddenrom exit command password program complete hiddenrom exit command device failed 555h/aah 2aah/55h 555h/38h pwa = pwa +1
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 58/80 password verify operation start read password 1 (x0h/pwd) hiddenrom exit command password verify complete 555h/aah 2aah/55h 555h/c8h read password 0 (x0h/pwd) read password 1 (x1h/pwd) read password 2 (x2h/pwd) read password 3 (x3h/pwd)
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 59/80 password unlock command operation start read password 1 (x0h/pwd) hiddenrom exit command password unlock complete 555h/aah 2aah/55h 555h/28h write password 0 (x0h/pwd0) wait 2us or dq6= no toggle? write password 1 (x1h/pwd1) wait 2us or dq6= no toggle? write password 2 (x2h/pwd2) wait 2us or dq6= no toggle? write password 3 (x3h/pwd3) wait 2us dq7=1 or dq6= no toggle?
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 60/80 non-password protection mode locking set operation no verify lock bit start plscnt = 25? wait 100 s yes no plscnt = 1 plscnt = plscnt + 1 non-password protection mode lock bit set command sequence 4th bus cycle (x12/68h) yes data = x1h? hiddenrom exit command lock set complete hiddenrom exit command device failed 555h/aah 2aah/55h 555h/60h non-password protection mode lock bit set command sequence 5th bus cycle (x12/48h)
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 61/80 ppb set command sequence no no verify block protect start plscnt = 25? protect another block? wait 100 s yes no yes plscnt = 1 plscnt = plscnt + 1 ppb set command sequence 4th bus write cycle (ba+02n/68h) yes data = x1h? hiddenrom exit command block protect complete hiddenrom exit command device failed 555h/aah 2aah/55h 555h/60h ppb set command sequence 5th bus write cycle (ba+02h/48h) plscnt = 1
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 62/80 ppb clear command sequence no verify block protect start plscnt = 500? check all blocks? wait 10 ms yes no yes plscnt = 1, ba=0 plscnt = plscnt + 1 ppb clear command sequence 4th write cycle (xx02h/60h) yes data = x0h? hiddenrom exit command block protection complete device failed 555h/aah 2aah/55h 555h/60h ppb clear command sequence 5th write cycle (ba+02h/40h) ba=ba+1 no hiddenrom exit command
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 63/80 ppb lock operation ppb lock set ppb lock verify start power on or reset = vil complete ppb lock clear start program complete 555h/aah 2aah/55h 555h/78h ppb lock verify hiddenrom exit command hiddenrom exit command start complete 555h/aah 2aah/55h 555h/58h ppb lock verify dq1=1:ppb lock set dq1=0: ppb lock is cleared hiddenrom exit command
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 64/80 dpb command operation dpb set dpb verify dpb clear 1 start powe on or reset = vil erase complete dpb clear 2 start verify complete 555h/aah 2aah/55h 555h/58h no check another block? yes verify dpb(add = ba) dq0=1: dpp set dq0=0: dpp is cleared hiddenrom exit command start program complete 555h/aah 2aah/55h 555h/48h no protect another block? yes ba/x1h hiddenrom exit command start erase complete 555h/aah 2aah/55h 555h/48h no erase another block? yes ba/00h hiddenrom exit command
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 65/80 20. block address tables * : v ih or v il 20.1. tc58fvm6t5b (top boot block) 1/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba0 l l l l l l l * * * 000000h~007fffh ba1 l l l l l l h * * * 008000h~00ffffh ba2 l l l l l h l * * * 010000h~017fffh ba3 l l l l l h h * * * 018000h~01ffffh ba4 l l l l h l l * * * 020000h~027fffh ba5 l l l l h l h * * * 028000h~02ffffh ba6 l l l l h h l * * * 030000h~037fffh ba7 l l l l h h h * * * 038000h~03ffffh ba8 l l l h l l l * * * 040000h~047fffh ba9 l l l h l l h * * * 048000h~04ffffh ba10 l l l h l h l * * * 050000h~057fffh ba11 l l l h l h h * * * 058000h~05ffffh ba12 l l l h h l l * * * 060000h~067fffh ba13 l l l h h l h * * * 068000h~06ffffh ba14 l l l h h h l * * * 070000h~077fffh bk0 ba15 l l l h h h h * * * 078000h~07ffffh ba16 l l h l l l l * * * 080000h~087fffh ba17 l l h l l l h * * * 088000h~08ffffh ba18 l l h l l h l * * * 090000h~097fffh ba19 l l h l l h h * * * 098000h~09ffffh ba20 l l h l h l l * * * 0a0000h~0a7fffh ba21 l l h l h l h * * * 0a8000h~0affffh ba22 l l h l h h l * * * 0b0000h~0b7fffh ba23 l l h l h h h * * * 0b8000h~0bffffh ba24 l l h h l l l * * * 0c0000h~0c7fffh ba25 l l h h l l h * * * 0c8000h~0cffffh ba26 l l h h l h l * * * 0d0000h~0d7fffh ba27 l l h h l h h * * * 0d8000h~0dffffh ba28 l l h h h l l * * * 0e0000h~0e7fffh ba29 l l h h h l h * * * 0e8000h~0effffh ba30 l l h h h h l * * * 0f0000h~0f7fffh bk1 ba31 l l h h h h h * * * 0f8000h~0fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 66/80 20.1. tc58fvm6t5b (top boot block) 2/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba32 l h l l l l l * * * 100000h~107fffh ba33 l h l l l l h * * * 108000h~10ffffh ba34 l h l l l h l * * * 110000h~117fffh ba35 l h l l l h h * * * 118000h~11ffffh ba36 l h l l h l l * * * 120000h~127fffh ba37 l h l l h l h * * * 128000h~12ffffh ba38 l h l l h h l * * * 130000h~137fffh ba39 l h l l h h h * * * 138000h~13ffffh ba40 l h l h l l l * * * 140000h~147fffh ba41 l h l h l l h * * * 148000h~14ffffh ba42 l h l h l h l * * * 150000h~157fffh ba43 l h l h l h h * * * 158000h~15ffffh ba44 l h l h h l l * * * 160000h~167fffh ba45 l h l h h l h * * * 168000h~16ffffh ba46 l h l h h h l * * * 170000h~177fffh bk2 ba47 l h l h h h h * * * 178000h~17ffffh ba48 l h h l l l l * * * 180000h~187fffh ba49 l h h l l l h * * * 188000h~18ffffh ba50 l h h l l h l * * * 190000h~197fffh ba51 l h h l l h h * * * 198000h~19ffffh ba52 l h h l h l l * * * 1a0000h~1a7fffh ba53 l h h l h l h * * * 1a8000h~1affffh ba54 l h h l h h l * * * 1b0000h~1b7fffh ba55 l h h l h h h * * * 1b8000h~1bffffh ba56 l h h h l l l * * * 1c0000h~1c7fffh ba57 l h h h l l h * * * 1c8000h~1cffffh ba58 l h h h l h l * * * 1d0000h~1d7fffh ba59 l h h h l h h * * * 1d8000h~1dffffh ba60 l h h h h l l * * * 1e0000h~1e7fffh ba61 l h h h h l h * * * 1e8000h~1effffh ba62 l h h h h h l * * * 1f0000h~1f7fffh bk3 ba63 l h h h h h h * * * 1f8000h~1fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 67/80 20.1. tc58fvm6t5b (top boot block) 3/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba64 h l l l l l l * * * 200000h~207fffh ba65 h l l l l l h * * * 208000h~20ffffh ba66 h l l l l h l * * * 210000h~217fffh ba67 h l l l l h h * * * 218000h~21ffffh ba68 h l l l h l l * * * 220000h~227fffh ba69 h l l l h l h * * * 228000h~22ffffh ba70 h l l l h h l * * * 230000h~237fffh ba71 h l l l h h h * * * 238000h~23ffffh ba72 h l l h l l l * * * 240000h~247fffh ba73 h l l h l l h * * * 248000h~24ffffh ba74 h l l h l h l * * * 250000h~257fffh ba75 h l l h l h h * * * 258000h~25ffffh ba76 h l l h h l l * * * 260000h~267fffh ba77 h l l h h l h * * * 268000h~26ffffh ba78 h l l h h h l * * * 270000h~277fffh bk4 ba79 h l l h h h h * * * 278000h~27ffffh ba80 h l h l l l l * * * 280000h~287fffh ba81 h l h l l l h * * * 288000h~28ffffh ba82 h l h l l h l * * * 290000h~297fffh ba83 h l h l l h h * * * 298000h~29ffffh ba84 h l h l h l l * * * 2a0000h~2a7fffh ba85 h l h l h l h * * * 2a8000h~2affffh ba86 h l h l h h l * * * 2b0000h~2b7fffh ba87 h l h l h h h * * * 2b8000h~2bffffh ba88 h l h h l l l * * * 2c0000h~2c7fffh ba89 h l h h l l h * * * 2c8000h~2cffffh ba90 h l h h l h l * * * 2d0000h~2d7fffh ba91 h l h h l h h * * * 2d8000h~2dffffh ba92 h l h h h l l * * * 2e0000h~2e7fffh ba93 h l h h h l h * * * 2e8000h~2effffh ba94 h l h h h h l * * * 2f0000h~2f7fffh bk5 ba95 h l h h h h h * * * 2f8000h~2fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 68/80 20.1. tc58fvm6t5b (top boot block) 4/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba96 h h l l l l l * * * 300000h~307fffh ba97 h h l l l l h * * * 308000h~30ffffh ba98 h h l l l h l * * * 310000h~317fffh ba99 h h l l l h h * * * 318000h~31ffffh ba100 h h l l h l l * * * 320000h~327fffh ba101 h h l l h l h * * * 328000h~32ffffh ba102 h h l l h h l * * * 330000h~337fffh ba103 h h l l h h h * * * 338000h~33ffffh ba104 h h l h l l l * * * 340000h~347fffh ba105 h h l h l l h * * * 348000h~34ffffh ba106 h h l h l h l * * * 350000h~357fffh ba107 h h l h l h h * * * 358000h~35ffffh ba108 h h l h h l l * * * 360000h~367fffh ba109 h h l h h l h * * * 368000h~36ffffh ba110 h h l h h h l * * * 370000h~377fffh bk6 ba111 h h l h h h h * * * 378000h~37ffffh ba112 h h h l l l l * * * 380000h~387fffh ba113 h h h l l l h * * * 388000h~38ffffh ba114 h h h l l h l * * * 390000h~397fffh ba115 h h h l l h h * * * 398000h~39ffffh ba116 h h h l h l l * * * 3a0000h~3a7fffh ba117 h h h l h l h * * * 3a8000h~3affffh ba118 h h h l h h l * * * 3b0000h~3b7fffh ba119 h h h l h h h * * * 3b8000h~3bffffh ba120 h h h h l l l * * * 3c0000h~3c7fffh ba121 h h h h l l h * * * 3c8000h~3cffffh ba122 h h h h l h l * * * 3d0000h~3d7fffh ba123 h h h h l h h * * * 3d8000h~3dffffh ba124 h h h h h l l * * * 3e0000h~3e7fffh ba125 h h h h h l h * * * 3e8000h~3effffh ba126 h h h h h h l * * * 3f0000h~3f7fffh bk7 ba127 h h h h h h h * * * 3f8000h~3fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 69/80 20.1. tc58fvm6t5b (top boot block) 5/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba127 h h h h h h h l l l 3f8000h~3f8fffh ba128 h h h h h h h l l h 3f9000h~3f9fffh ba129 h h h h h h h l h l 3fa000h~3fafffh ba130 h h h h h h h l h h 3fb000h~3fbfffh ba131 h h h h h h h h l l 3fc000h~3fcfffh ba132 h h h h h h h h l h 3fd000h~3fdfffh ba133 h h h h h h h h h l 3fe000h~3fefffh bk7 ba134 h h h h h h h h h h 3ff000h~3fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 70/80 20.2. tc58fvm6b5b (bottom boot block) 1/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba0 l l l l l l l l l l 000000h~000fffh ba1 l l l l l l l l l h 001000h~001fffh ba2 l l l l l l l l h l 002000h~002fffh ba3 l l l l l l l l h h 003000h~003fffh ba4 l l l l l l l h l l 004000h~004fffh ba5 l l l l l l l h l h 005000h~005fffh ba6 l l l l l l l h h l 006000h~006fffh bk0 ba7 l l l l l l l h h h 007000h~007fffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 71/80 20.2. tc58fvm6b5b (bottom boot block) 2/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba8 l l l l l l h * * * 008000h~00ffffh ba9 l l l l l h l * * * 010000h~017fffh ba10 l l l l l h h * * * 018000h~01ffffh ba11 l l l l h l l * * * 020000h~027fffh ba12 l l l l h l h * * * 028000h~02ffffh ba13 l l l l h h l * * * 030000h~037fffh ba14 l l l l h h h * * * 038000h~03ffffh ba15 l l l h l l l * * * 040000h~047fffh ba16 l l l h l l h * * * 048000h~04ffffh ba17 l l l h l h l * * * 050000h~057fffh ba18 l l l h l h h * * * 058000h~05ffffh ba19 l l l h h l l * * * 060000h~067fffh ba20 l l l h h l h * * * 068000h~06ffffh ba21 l l l h h h l * * * 070000h~077fffh bk0 ba22 l l l h h h h * * * 078000h~07ffffh ba23 l l h l l l l * * * 080000h~087fffh ba24 l l h l l l h * * * 088000h~08ffffh ba25 l l h l l h l * * * 090000h~097fffh ba26 l l h l l h h * * * 098000h~09ffffh ba27 l l h l h l l * * * 0a0000h~0a7fffh ba28 l l h l h l h * * * 0a8000h~0affffh ba29 l l h l h h l * * * 0b0000h~0b7fffh ba30 l l h l h h h * * * 0b8000h~0bffffh ba31 l l h h l l l * * * 0c0000h~0c7fffh ba32 l l h h l l h * * * 0c8000h~0cffffh ba33 l l h h l h l * * * 0d0000h~0d7fffh ba34 l l h h l h h * * * 0d8000h~0dffffh ba35 l l h h h l l * * * 0e0000h~0e7fffh ba36 l l h h h l h * * * 0e8000h~0effffh ba37 l l h h h h l * * * 0f0000h~0f7fffh bk1 ba38 l l h h h h h * * * 0f8000h~0fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 72/80 20.2. tc58fvm6b5b (bottom boot block) 3/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba39 l h l l l l l * * * 100000h~107fffh ba40 l h l l l l h * * * 108000h~10ffffh ba41 l h l l l h l * * * 110000h~117fffh ba42 l h l l l h h * * * 118000h~11ffffh ba43 l h l l h l l * * * 120000h~127fffh ba44 l h l l h l h * * * 128000h~12ffffh ba45 l h l l h h l * * * 130000h~137fffh ba46 l h l l h h h * * * 138000h~13ffffh ba47 l h l h l l l * * * 140000h~147fffh ba48 l h l h l l h * * * 148000h~14ffffh ba49 l h l h l h l * * * 150000h~157fffh ba50 l h l h l h h * * * 158000h~15ffffh ba51 l h l h h l l * * * 160000h~167fffh ba52 l h l h h l h * * * 168000h~16ffffh ba53 l h l h h h l * * * 170000h~177fffh bk2 ba54 l h l h h h h * * * 178000h~17ffffh ba55 l h h l l l l * * * 180000h~187fffh ba56 l h h l l l h * * * 188000h~18ffffh ba57 l h h l l h l * * * 190000h~197fffh ba58 l h h l l h h * * * 198000h~19ffffh ba59 l h h l h l l * * * 1a0000h~1a7fffh ba60 l h h l h l h * * * 1a8000h~1affffh ba61 l h h l h h l * * * 1b0000h~1b7fffh ba62 l h h l h h h * * * 1b8000h~1bffffh ba63 l h h h l l l * * * 1c0000h~1c7fffh ba64 l h h h l l h * * * 1c8000h~1cffffh ba65 l h h h l h l * * * 1d0000h~1d7fffh ba66 l h h h l h h * * * 1d8000h~1dffffh ba67 l h h h h l l * * * 1e0000h~1e7fffh ba68 l h h h h l h * * * 1e8000h~1effffh ba69 l h h h h h l * * * 1f0000h~1f7fffh bk3 ba70 l h h h h h h * * * 1f8000h~1fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 73/80 20.2. tc58fvm6b5b (bottom boot block) 4/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba71 h l l l l l l * * * 200000h~207fffh ba72 h l l l l l h * * * 208000h~20ffffh ba73 h l l l l h l * * * 210000h~217fffh ba74 h l l l l h h * * * 218000h~21ffffh ba75 h l l l h l l * * * 220000h~227fffh ba76 h l l l h l h * * * 228000h~22ffffh ba77 h l l l h h l * * * 230000h~237fffh ba78 h l l l h h h * * * 238000h~23ffffh ba79 h l l h l l l * * * 240000h~247fffh ba80 h l l h l l h * * * 248000h~24ffffh ba81 h l l h l h l * * * 250000h~257fffh ba82 h l l h l h h * * * 258000h~25ffffh ba83 h l l h h l l * * * 260000h~267fffh ba84 h l l h h l h * * * 268000h~26ffffh ba85 h l l h h h l * * * 270000h~277fffh bk4 ba86 h l l h h h h * * * 278000h~27ffffh ba87 h l h l l l l * * * 280000h~287fffh ba88 h l h l l l h * * * 288000h~28ffffh ba89 h l h l l h l * * * 290000h~297fffh ba90 h l h l l h h * * * 298000h~29ffffh ba91 h l h l h l l * * * 2a0000h~2a7fffh ba92 h l h l h l h * * * 2a8000h~2affffh ba93 h l h l h h l * * * 2b0000h~2b7fffh ba94 h l h l h h h * * * 2b8000h~2bffffh ba95 h l h h l l l * * * 2c0000h~2c7fffh ba96 h l h h l l h * * * 2c8000h~2cffffh ba97 h l h h l h l * * * 2d0000h~2d7fffh ba98 h l h h l h h * * * 2d8000h~2dffffh ba99 h l h h h l l * * * 2e0000h~2e7fffh ba100 h l h h h l h * * * 2e8000h~2effffh ba101 h l h h h h l * * * 2f0000h~2f7fffh bk5 ba102 h l h h h h h * * * 2f8000h~2fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 74/80 20.2. tc58fvm6b5b (bottom boot block) 5/5 block address bank address bank # block # a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 address range ba103 h h l l l l l * * * 300000h~307fffh ba104 h h l l l l h * * * 308000h~30ffffh ba105 h h l l l h l * * * 310000h~317fffh ba106 h h l l l h h * * * 318000h~31ffffh ba107 h h l l h l l * * * 320000h~327fffh ba108 h h l l h l h * * * 328000h~32ffffh ba109 h h l l h h l * * * 330000h~337fffh ba110 h h l l h h h * * * 338000h~33ffffh ba111 h h l h l l l * * * 340000h~347fffh ba112 h h l h l l h * * * 348000h~34ffffh ba113 h h l h l h l * * * 350000h~357fffh ba114 h h l h l h h * * * 358000h~35ffffh ba115 h h l h h l l * * * 360000h~367fffh ba116 h h l h h l h * * * 368000h~36ffffh ba117 h h l h h h l * * * 370000h~377fffh bk6 ba118 h h l h h h h * * * 378000h~37ffffh ba119 h h h l l l l * * * 380000h~387fffh ba120 h h h l l l h * * * 388000h~38ffffh ba121 h h h l l h l * * * 390000h~397fffh ba122 h h h l l h h * * * 398000h~39ffffh ba123 h h h l h l l * * * 3a0000h~3a7fffh ba124 h h h l h l h * * * 3a8000h~3affffh ba125 h h h l h h l * * * 3b0000h~3b7fffh ba126 h h h l h h h * * * 3b8000h~3bffffh ba127 h h h h l l l * * * 3c0000h~3c7fffh ba128 h h h h l l h * * * 3c8000h~3cffffh ba129 h h h h l h l * * * 3d0000h~3d7fffh ba130 h h h h l h h * * * 3d8000h~3dffffh ba131 h h h h h l l * * * 3e0000h~3e7fffh ba132 h h h h h l h * * * 3e8000h~3effffh ba133 h h h h h h l * * * 3f0000h~3f7fffh bk7 ba134 h h h h h h h * * * 3f8000h~3fffffh
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 75/80 21. block size table 21.1. tc58fvm6t5b (top boot block) block # block size bank # bank size block count ba0~ba15 32 kwords x 16 bk0 512 kwords 16 ba16~ba31 32 kwords x 16 bk1 512 kwords 16 ba32~ba47 32 kwords x 16 bk2 512 kwords 16 ba48~ba63 32 kwords x 16 bk3 512 kwords 16 ba64~ba79 32 kwords x 16 bk4 512 kwords 16 ba80~ba95 32 kwords x 16 bk5 512 kwords 16 ba96~ba111 32 kwords x 16 bk6 512 kwords 16 ba112~ba134 32 kwords x 15 + 4 kwords x 8 bk7 512 kwords 23
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 76/80 21.2. tc58fvm6b5b (bottom boot block) block # block size bank # bank size block count ba0~ba22 32 kwords x 15 + 4 kwords x 8 bk0 512 kwords 23 ba23~ba38 32 kwords x 16 bk1 512 kwords 16 ba39~ba54 32 kwords x 16 bk2 512 kwords 16 ba55~ba70 32 kwords x 16 bk3 512 kwords 16 ba71~ba86 32 kwords x 16 bk4 512 kwords 16 ba87~ba102 32 kwords x 16 bk5 512 kwords 16 ba103~ba118 32 kwords x 16 bk6 512 kwords 16 ba119~ba134 32 kwords x 16 bk7 512 kwords 16
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 77/80 22. package dimensions unit: mm b a ll s i de
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 78/80 unit: mm
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 79/80 23. revision history date rev. description 2004-07-22 1.00 original version 2004-09-06 1.01 change of the address which makes password unlock possible. 2004-10-04 1.02 the state of the rdy pin in password mode is added. 2004-11-08 1.03 changed specification (tsusp) 2004-11-17 1.04 changed the hidden rom exit address. 2005-01-11 1.05 changed specification (tsuse/tready/tppaw) 2005-02-28 1.06 changed an explanation of simultane ous read/write operation (p.9), and package dimensions of tfgba. 2005-06-24 1.07 changed specification (vdd) 2005-08-02 1.08 added specification of pin capacitance. ( /acc wp ) 2005-08-22 1.09 added timing diagrams. 2005-08-29 1.10 changed tsop package name. (p.1) 2006-02-23 1.11 comment addition of "lead-free". (p.1) 2006-05-10 1.12 correct comment of program suspend/ resume and erase suspend/resume.
tc58fvm 6(t/b)5b(tg/xg)65 2006-05-10 80/80 ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringement s of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the qualit y and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fa il due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to av oid situations in which a malfunction or failure of such toshiba products coul d cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshi ba products are used within specified operating ranges as set forth in the most recent tosh iba products specifications. also, plea se keep in mind the precautions and conditions set forth in the ?handling guide for semico nductor devices,? or ?toshi ba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are int ended for usage in general electronics applications (computer, personal equipment, office equipment, m easuring equipment, industrial robotics, domestic appliances, etc.). these toshiba pr oducts are neither intended nor warr anted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). uninte nded usage include atomic en ergy control instruments, airplane or spaceship instruments, tr ansportation instruments, traffic sig nal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the downstr eam products which are prohibited to be produced and sold, under any law and regulations. 030619eb a restrictions on product use

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