View X9110TB15-27_6806890.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev 1.1.8 5/9/03 characteristics subject to change without notice. 1 of 21 www.xicor.com x9110 single digitally-controlled (xdcp ) potentiometer features 1024 resistor taps ?10-bit resolution spi serial interface for write, read, and transfer operations of the potentiometer wiper resistance, 40 ? typical @ 5v four non-volatile data registers non-volatile storage of multiple wiper positions power on recall. loads saved wiper position on power up. standby current < 3? max system v cc : 2.7v to 5.5v operation analog v+/v-: -5v to +5v 100k ? end to end resistance 100 yr. data retention endurance: 100, 000 data changes per bit per register 14-lead tssop, 15-lead csp (chip scale package). call factory for availability. dual supply version of the x9111 low power cmos description the x9110 integrates a single digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 1023 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and four non-volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. powerup recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. dual supply / low power / 1024-tap / spi bus a pplication n otes and d evelopment s ystem a v a i l a b l e an99 ?an115 ?an124 ?n133 ?an134 ?an135 functional diagram r h r l bus r w interface & control pot v cc v ss spi bus address data status write read wiper 1024-taps transfer nc nc 100k ? power on recall wiper counter register (wcr) data registers (dr0-dr3) control interface v+ v- preliminary information
x9110 ?preliminary information characteristics subject to change without notice. 2 of 21 rev 1.1.8 5/9/03 www.xicor.com circuit level applications vary the gain of a voltage ampli?r provide programmable dc reference voltages for comparators and detectors control the volume in audio circuits trim out the offset voltage error in a voltage ampli?r circuit set the output voltage of a voltage regulator trim the resistance in wheatstone bridge circuits control the gain, characteristic frequency and q-factor in ?ter circuits set the scale factor and zero point in sensor signal conditioning circuits vary the frequency and duty cycle of timer ics vary the dc biasing of a pin diode attenuator in rf circuits provide a control variable (i, v, or r) in feedback circuits system level applications adjust the contrast in lcd displays control the power level of led transmitters in communication systems set and regulate the dc biasing point in an rf power ampli?r in wireless systems control the gain in audio and home entertainment systems provide the variable dc bias for tuners in rf wireless systems set the operating points in temperature control systems control the operating point for sensors in industrial systems trim offset and gain errors in arti?ial intelligent systems detailed functional diagram cs sck a0 so si hold wp interface and control circuitry v - v+ v cc v ss dr0 dr1 dr2 dr3 wiper counter register (wcr) r h r l data r w 1024-taps 100k ? control power on recall
x9110 ?preliminary information characteristics subject to change without notice. 3 of 21 rev 1.1.8 5/9/03 www.xicor.com pin configuration pin assignments pin (tssop) pin (csp) symbol function 1 v+ analog supply voltage 2 so serial data output 3 a0 device address 4 sck serial clock 5wp hardware write protect 6 si serial data input 7v ss system ground 8v - analog supply voltage 9cs chip select 10 hold device select. pause the serial bus 11 r w wiper terminal of the potentiometer 12 r h high terminal of the potentiometer 13 r l low terminal of the potentiometer 14 v cc system supply voltage v cc r l vss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 a0 r w sck cs tssop r h x9110 csp s0 v+ si hold wp x9110 v- call factory for availability
x9110 ?preliminary information characteristics subject to change without notice. 4 of 21 rev 1.1.8 5/9/03 www.xicor.com pin descriptions bus interface pins s erial o utput (so) so is a serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out on the falling edge of the serial clock. s erial i nput (si) si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the rising edge of the serial clock. s erial c lock (sck) the sck input is used to clock data into and out of the x9110. h old (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. d evice a ddress (a0) the address input is used to set the 8-bit slave address. a match in the slave address serial data stream a0 must be made with the address input (a0) in order to initiate communication with the x9110. c hip s elect (cs ) when cs is high, the x9110 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9110, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. h ardware w rite p rotect i nput (wp ) the wp pin when low prevents nonvolatile writes to the data registers. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. bias supply pins s ystem s upply v oltage (v cc ) and s upply g round (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. a nalog s upply v oltages (v+ and v - ) these supplies are the analog voltage supplies for the potentiometer. the v+ supply is tied to the wiper switches while the v- supply is used to bias the switches and the internal p+ substrate of the integrated circuit. both of these supplies set the voltage limits of the potentiometer. principles of operation device description serial interface the x9110 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked-in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. array description the x9110 is comprised of a resistor array (figure 1). the array contains the equivalent of 1023 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within the individual array only one switch may be turned on at a time.
x9110 ?preliminary information characteristics subject to change without notice. 5 of 21 rev 1.1.8 5/9/03 www.xicor.com figure 1. detailed potentiometer block diagram serial data path from interface register 0 serial bus input parallel bus input counter register r h r l r w 10 10 c o u n t e r d e c o d e if wcr = 000[hex] then r w = r l if wcr = 3ff[hex] then r w = r h wiper (wcr) (dr0) circuitry register 1 (dr1) register 2 (dr2) register 3 (dr3) these switches are controlled by a wiper counter register (wcr). the 10-bits of the wcr (wcr[9:0]) are decoded to select, and enable, one of 1024 switches. wiper counter register (wcr) the x9110 contains a wiper counter register (see table 1) for the xdcp potentiometer. the wcr is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. the contents of the wcr can be altered in one of three ways: (1) it may be written directly by the host via the write wiper counter register instruction (serial load); (2) it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register; (3) it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9110 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. power- up guidelines are recommended to ensure proper loadings of the dr0 value into the wcr. data registers (dr) the potentiometer has four 10-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the wiper counter register. all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as regular memory locations for system parameters or user preference data. dr[9:0] is used to store one of the 1024 wiper position (0 ~1023). table 2. status register (sr) this 1-bit status register is used to store the system status (see table 3). wip: write in progress status bit, read only. when wip=1, indicates that high-voltage write cycle is in progress. when wip=0, indicates that no high-voltage write cycle is in progress.
x9110 ?preliminary information characteristics subject to change without notice. 6 of 21 rev 1.1.8 5/9/03 www.xicor.com table 1. wiper control register, wcr (10-b it), wcr9?cr0: used to store the current wiper position (volatile, v) table 2. data register, dr (10-bit), bit 9?it 0: used to store wiper positions or data (non-volatile, nv) table 3. status register, sr (1-bit) wcr9 wcr8 wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvvvv (msb) (lsb) bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nv nv nv nv nv nv nv nv nv nv msb lsb wip (lsb) device instructions identification byte (id and a) the ?st byte sent to the x9110 from the host, following a cs going high to low, is called the identi?ation byte. the most signi?ant four bits of the slave address are a device type identi?r. the id[3:0] bits is the device id for the x9110; this is ?ed as 0101[b] (refer to table 4). the a0 bit in the id byte is the internal slave address. the physical device address is de?ed by the state of the a0 input pin. the slave address is externally speci?d by the user. the x9110 compares the serial data stream with the address input state; a successful compare of the address bit is required for the x9110 to successfully continue the command sequence. only the device whose slave address matches the incoming device address sent by the master executes the instruction. the a0 input can be actively driven by cmos input signals or tied to v cc or v ss . the r/w bit is used to set the device to either read or write mode. instruction byte and register selection the next byte sent to the x9110 contains the instruction and register pointer information. the three most signi?ant bits are used provide the instruction opcode (i[2:0]). the rb and ra bits point to one of the four registers. the format is shown in table 5. table 4. identification byte format table 5. instruction byte format id3 id2 id1 id0 0 0 a0 r/w 0101 (msb) (lsb) device type identifier internal slave address read or write bit i2 i1 i0 0 rb ra 0 0 (msb) (lsb) instruction opcode register selection rb ra register 0 0 1 1 0 1 0 1 dr0 dr1 dr2 dr3
x9110 ?preliminary information characteristics subject to change without notice. 7 of 21 rev 1.1.8 5/9/03 www.xicor.com five of the seven instructions are four bytes in length. these instructions are: read wiper counter register ?read the current wiper position of the selected pot, write wiper counter register ?change current wiper position of the selected pot, read data register ?read the contents of the selected data register; write data register ?write a new value to the selected data register. read status ?this command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the basic sequence of the four byte instructions is illustrated in figure 3. these four-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between the potentiometer and one of its associated registers. the read status register instruction is the only unique format (see figure 4). two instructions require a two-byte sequence to complete (see figure 2). these instructions transfer data between the host and the x9110; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: xfr data register to wiper counter register ? this transfers the contents of one speci?d data register to the associated wiper counter register. xfr wiper counter register to data register ? this transfers the contents of the speci?d wiper counter register to the speci?d associated data register. see instruction format for more details. write in process (wip bit) the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command (see figure 4). power up and down requirements at all times, the v+ voltage must be greater than or equal to the voltage at r h or r l , and the voltage at r h or r l must be greater than or equal to the voltage at v-. during power up and power down, v cc , v+, and v- must reach their ?al values within 1msec of each other. figure 2. two-byte instruction sequence id3 id2 id1 id0 0 0 a0 i2 i1 i0 rb ra sck si cs 0101 r/w device id internal instruction opcode address register 0 0 0 0 address 0 0 0
x9110 ?preliminary information characteristics subject to change without notice. 8 of 21 rev 1.1.8 5/9/03 www.xicor.com figure 3. four-byte instruction sequence (write or read for wcr or data registers) figure 4. four-byte instruction sequence (read status registers) id3 id2 id1 id0 0 a0 r/w i2 0 0 sck si 0 0 x x0 0 xx x w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs i1 i0 0 rb ra 0101 0 xx x device id internal address instruction opcode register address wiper position 0 id3 id2 id1 id0 0 a0 r/w i2 0 0 sck si 1 0 x x0 0 xxx wip cs i1 i0 0 rb ra 0101 0 xx x device id internal address instruction opcode register address status bit x x 0 00 0 0 0 0 0 0
x9110 ?preliminary information characteristics subject to change without notice. 9 of 21 rev 1.1.8 5/9/03 www.xicor.com table 6. instruction set note: (1) 1/0 = data is one or zero instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) instruction instruction set operation r/w i 2 i 1 i 0 0rbra0 0 read wiper counter register 110000000 read the contents of the wiper counter register write wiper counter register 010100000 write new value to the wiper counter register read data register 110101/01/000 read the contents of the data register pointed to rb-ra write data register 011001/01/000 write new value to the data register pointed to rb-ra xfr data register to wiper counter register 111001/01/000 transfer the contents of the data register pointed to by rb-ra to the wiper counter register xfr wiper counter register to d ata register 011101/01/000 transfer the contents of the wiper counter register to the data register pointed to by rb-ra read status (wip bit) 101000001 read the status of the internal write cycle, by checking the wip bit (read status register). cs falling edge device type identi?r device addresses instruction opcode register addresses wiper position (sent by x9110 on so) wiper position (sent by x9110 on so) cs rising edge 010100a0 r/ w = 1 10000000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identi?r device addresses instruction opcode register addresses wiper position (sent by master on si) wiper position (sent by master on si) cs rising edge 010100a0 r/ w = 0 10100000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identi?r device addresses instruction opcode register addresses wiper position (sent by x9110 on so) wiper position (sent by x9110 on so) cs rising edge 010100a0 r/ w = 1 1010rbra00 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0
x9110 ?preliminary information characteristics subject to change without notice. 10 of 21 rev 1.1.8 5/9/03 www.xicor.com write data register (dr) transfer data register (dr) to wiper counter register (wcr) transfer wiper counter register (wcr) to data register (dr) read status register (sr) notes: (1) ?0? stands for the device address sent by the master. (2) wcrx refers to wiper position data in the wiper counter register (3) ?? don? care. cs falling edge device type identi?r device addresses instruction opcode register address wiper position or data (sent by master on si) wiper position or data (sent by master on si) cs rising edge high-voltage write cycle 010100a0 r/ w = 0 1100rbra00 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identi?r device addresses instruction opcode register address cs rising edge 010100 a 0 r/ w = 1 1100rbra00 cs falling edge device type identi?r device addresses instruction opcode register address cs rising edge high-voltage write cycle 010100 a 0 r/ w = 0 1110 rb ra 0 0 cs falling edge device type identi?r device addresses instruction opcode register addresses status data (sent by slave on so) status data (sent by slave on so) cs rising edge 010100 a 0 r/ w = 1 010x0001 xxxxxxxx 0000000wip
x9110 ?preliminary information characteristics subject to change without notice. 11 of 21 rev 1.1.8 5/9/03 www.xicor.com absolute maximum ratings temperature under bias.................... ?5? to +135? storage temperature......................... ?5? to +150? voltage on sck any address input with respect to v ss ................................. ?v to +7v voltage on v+ (referenced to v ss ) (4) ......................10v voltage on v- (referenced to v ss ) (4) ..................... -10v (v+) ?(v-) ..............................................................12v any voltage on r h / r l ............................................v+ any voltage on r l / r h ..............................................v- lead temperature (soldering, 10 seconds) ........ 300 c i w (10 seconds) ..................................................?ma comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog characteristics (over recommended industrial (2.7v) operation conditions unless otherwise stated.) symbol parameter limits test conditions min. typ. max. units r total end to end resistance 100 k ? end to end resistance tolerance ?0 % power rating 50 mw 25?, each pot i w wiper current ? ma r w wiper resistance 150 500 ? wiper current = 3ma, v cc = 3v r w wiper resistance 100 ? i w = 3ma, v cc = 5v vv+ voltage on v+ pin +4.5 +5.5 v x9110 (4) +2.7 +5.5 x9110-2.7 (4) vv- voltage on v- pin -5.5 -4.5 v x9110 (4) -5.5 -2.7 x9110-2.7 (4) v term voltage on any r h or r l pin v- v+ v v ss = 0v noise -120 dbv ref: 1v resolution 0.1 % absolute linearity (1) ? mi (3) r w(n)(actual) ?r w(n)(expected) , where n=8 to 1006 ?.5 mi (3) r w(n)(actual) ?r w(n)(expected) (5) relative linearity (2) ?.5 mi (3) r w(m + 1) ?[r w(m) + mi], where m=8 to 1006 ? mi (3) r w(m + 1) ?[r w(m) + mi] (5) temperature coefficient of r total 300 ppm/? ratiometric temp. coefficient 20 ppm/? c h /c l /c w potentiometer capacitancies 10/10/25 pf see macro model recommended operating conditions temp min. max. commercial 0 c +70 c industrial ?0 c +85 c device supply voltage (v cc ) limits (4) x9110 5v 10% x9110-2.7 2.7v to 5.5v
x9110 ?preliminary information characteristics subject to change without notice. 12 of 21 rev 1.1.8 5/9/03 www.xicor.com notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot / 1023 or (r h ?r l ) / 1023, single pot (4) v cc , v+, v- must reach their ?al values within 1 msec of each other. (5) n = 0, 1, 2, ?1023; m =0, 1, 2, ? 1022. d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) endurance and data retention capacitance power-up timing notes: (6) this parameter is not 100% tested (7) t pur and t puw are the delays required from the time the (last) power supply (vcc-) is stable until the speci? instruction can be issued. these parameters are not 100% tested. (8) esd rating on rh, rl, rw pins is 1.5kv (hbm, 1.0? leakage maximum), esd rating on all other pins is 2.0kv. symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 af sck = 2.5 mhz, so = open, v cc = 5.5v other inputs = v ss i cc2 v cc supply current (nonvolatile write) 1 5 ma f sck = 2.5mhz, so = open, v cc = 5.5v other inputs = v ss i sb v cc current (standby) 3 a sck = si = v ss , addr. = v ss , cs = v cc = 5.5v i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage ? v cc x 0.3 v v ol output low voltage 0.4 v i ol = 3ma v oh output high voltage v cc - 0.8 v i oh = -1ma, v cc +3v v oh output high voltage v cc - 0.4 v i oh = -0.4ma, v cc +3v parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c in/out (4)(6) input/output capacitance (si) 8 pf v out = 0v c out (6) output capacitance (so) 8 pf v out = 0v c in (6) input capacitance (a0, cs , wp , hold , and sck) 6 pf v in = 0v symbol parameter min. max. units t r v cc (6) v cc power-up rate 0.2 50 v/ms t pur (7) power-up to initiation of read operation 1 ms t puw (7) power-up to initiation of write operation 50 ms
x9110 ?preliminary information characteristics subject to change without notice. 13 of 21 rev 1.1.8 5/9/03 www.xicor.com
x9110 ?preliminary information characteristics subject to change without notice. 14 of 21 rev 1.1.8 5/9/03 www.xicor.com a.c. test conditions equivalent a.c. load circuit ac timing i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 symbol parameter min. max. units f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 400 ns t wh ssi/spi clock high time 150 ns t wl ssi/spi clock low time 150 ns t lead lead time 150 ns t lag lag time 150 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 50 ns t fi si, sck, hold and cs input fall time 50 ns t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 50 ns t hh hold hold time 50 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 100 ns t wpasu wp , a0 setup time 0 ns t wpah wp , a0 hold time 0 ns 5v 1462 ? 100pf so pin r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel 2714 ? 2.7v 1382 ? 100pf so pin 1217 ?
x9110 ?preliminary information characteristics subject to change without notice. 15 of 21 rev 1.1.8 5/9/03 www.xicor.com high-voltage write cycle timing xdcp timing symbol table symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instruc- tions) 510s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x9110 ?preliminary information characteristics subject to change without notice. 16 of 21 rev 1.1.8 5/9/03 www.xicor.com timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo
x9110 ?preliminary information characteristics subject to change without notice. 17 of 21 rev 1.1.8 5/9/03 www.xicor.com xdcp timing (for all load instructions) write protect and device address pins timing . ... cs sck si msb lsb r w t wrl ... so high impedance cs wp a0 a1 t wpasu t wpah (any instruction)
x9110 ?preliminary information characteristics subject to change without notice. 18 of 21 rev 1.1.8 5/9/03 www.xicor.com applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + v s v o r 2 r 1 } }
x9110 ?preliminary information characteristics subject to change without notice. 19 of 21 rev 1.1.8 5/9/03 www.xicor.com application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k ? + v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + r 2 + r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o
x9110 ?preliminary information characteristics subject to change without notice. 20 of 21 rev 1.1.8 5/9/03 www.xicor.com packaging information note: all dimensions in inches (in p arentheses in millimeters) 14-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x9110 ?preliminary information characteristics subject to change without notice. 21 of 21 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. rev 1.1.8 5/9/03 www.xicor.com ?icor, inc. 2003 patents pending ordering information device v cc limits blank = 5v 10% ?.7 = 2.7 to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package v14 = 14-lead tssop b15 = 15-lead csp (call factory for availiability) potentiometer organization pot t = 100k ? x9110 p t v y

▲Up To Search▲

Price & Availability of X9110TB15-27

	To Download X9110TB15-27 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .