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description the hcpl-7840 isolation amplifi er family was designed for current sensing in electronic motor drives. in a typical implementation, motor currents fl ow through an external resistor and the resulting analog voltage drop is sensed by the hcpl-7840. a diff erential output voltage is created on the other side of the hcpl-7840 optical isolation barrier. this diff erential output voltage is proportional to the motor current and can be converted to a single-ended signal by using an op-amp as shown in the recommended application circuit. since common-mode voltage swings of several hundred volts in tens of nanoseconds are common in modern switching inverter motor drives, the hcpl-7840 was designed to ignore very high common- mode transient slew rates (of at least 10 kv/s). the high cmr capability of the hcpl-7840 isolation amplifi er provides the precision and stability needed to accurately monitor motor current in high noise motor control environ-ments, providing for smoother control (less torque ripple) in various types of motor control applications. the product can also be used for general analog signal isolation applications requiring high accuracy, stability, and linearity under similarly severe noise con-ditions. for general applications, we recommend the hcpl-7840 (gain tolerance of 5%). the hcpl-7840 utilizes sigma delta (-) analog-to-digital converter technology, chopper stabilized amplifi ers, and a fully diff erential circuit topol- ogy fabricated using avagos 0.8 m cmos ic process. together, these features deliver unequaled isolation- mode noise rejection, as well as excellent off set and gain accuracy and stability over time and temperature. this performance is delivered in a compact, auto-insertable, industry standard 8-pin dip package that meets world- wide regulatory safety standards. (a gull-wing surface mount option #300 is also available). caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. 1 2 3 4 8 7 6 5 i dd1 v dd1 v in+ v in gnd1 i dd2 v dd2 v out+ v out gnd2 + + shield hcpl-7840 isolation amplifi er data sheet features ? 15 kv/s common-mode rejection at v cm = 1000 v ? compact, auto-insertable standard 8-pin dip package ? 0.00025 v/v/c gain drift vs. temperature ? 0.3 mv input off set voltage ? 100 khz bandwidth ? 0.004% nonlinearity ? worldwide safety approval: ul 1577 (3750 vrms/1 min.) and csa, iec/en/din en 60747-5-2 ? advanced sigma-delta (-) a/d converter technol- ogy ? fully diff erential circuit topology ? 0.8 m cmos ic technology applications ? motor phase and rail current sensing ? inverter current sensing ? switched mode power supply signal isolation ? general purpose current sensing and monitoring ? general purpose analog signal isolation functional diagram a 0.1 f bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8. lead (pb) free rohs 6 fully compliant rohs 6 fully co m pliant options available; -xxxe denotes a lead-f r ee p r oduct
2 ordering information hcpl-7840 is ul recognized with 3750 vrms for 1 minute per ul1577. option part rohs non rohs surface gull tape iec/en/din number compliant compliant package mount wing & reel en 60747-5-2 quantity -000e no option x 50 per tube -300e #300 x x x 50 per tube hcpl-7840 -500e #500 300 mil dip-8 x x x x 1000 per reel -060e #060 x 50 per tube -360e #360 x x x 50 per tube -560e #560 x x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-7840-560e to order product of gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval and rohs compliant. example 2: hcpl-7840 to order product of 300 mil dip package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since july 15, 2001 and rohs compliant will use Cxxxe.
3 note: initial or continued variation in the color of the hcpl-7840s white mold compound is normal and does not aff ect device performance or reliability. package outline drawings standard dip package 9.80 ?0.25 (0.386 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. a 7840 yyww date code 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). note: floating lead protrusion is 0.5 mm (20 mils) max. 5 6 7 8 4 3 2 1 5?typ. 0.20 (0.008) 0.33 (0.013) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) 3.56 ?0.13 (0.140 ?0.005)
4 gull wing surface mount option 300 0.635 ?0.25 (0.025 ?0.010) 12?nom. 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.80 ?0.25 (0.386 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 ?0.320 (0.043 ?0.013) 3.56 ?0.13 (0.140 ?0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc note: floating lead protrusion is 0.5 mm (20 mils) max. dimensions in millimeters (inches). tolerances (unless otherwise specified): xx.xx = 0.01 xx.xxx = 0.005 a 7840 yyww lead coplanarity maximum: 0.102 (0.004) 0.20 (0.008) 0.33 (0.013)
5 solder refl ow temperature profi le recommended pb-free ir profi le 0 time (seconds) temperature (?) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160? 140? 150? peak temp. 245? peak temp. 240? peak temp. 230? soldering time 200? preheating time 150?, 90 + 30 sec. 2.5? ?0.5?/sec. 3? + 1?/?.5? tight typical loose room temperature preheating rate 3? + 1?/?.5?/sec. reflow heating rate 2.5? ?0.5?/sec. 217 ? ramp-down 6 ?/sec. max. ramp-up 3 ?/sec. max. 150 - 200 ? 260 +0/-5 ? t 25 ? to peak 60 to 150 sec. 20-40 sec. time within 5 ? of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 ? to peak temperature = 8 minutes max. t smax = 200 ?, t smin = 150 ? note: non-halide fl ux should be used.. note: non-halide fl ux should be used.
6 regulatory information the hcpl-7840 has been approved by the following organizations: iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01. ul approval under ul 1577, com- ponent recognition program up to v iso = 3750 vrms. csa approved under csa component ac- ceptance notice #5, file ca 88324. iec/en/din en 60747-5-2 insulation characteristics* description symbol characteristic unit installation classifi cation per din vde 0110/1.89, table 1 for rated mains voltage 300 vrms i-iv for rated mains voltage 600 vrms i-iii climatic classifi cation 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 891 v peak input to output test voltage, method b** v iorm x 1.875 = v pr, 100% production test with v pr 1670 v peak t m = 1 sec, partial discharge < 5 pc input to output test voltage, method a** v iorm x 1.5 = v pr, type and sample test, v pr 1336 v peak t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage v iotm 8000 v peak (transient overvoltage t ini = 10 sec) safety-limiting valuesmaximum values allowed in the event of a failure. case temperature t s 175 c input current*** i s,input 400 ma output power*** p s,output 600 mw insulation resistance at t s , v io = 500 v r s >10 9 *insulation characteristics are guarant eed only within the safety maximum ratings which must be ensured by protective circuits within the application. surface mount classifi cation is class a in accordance with cecc00802. **refer to the optocoupler section of the isolation and control components designers cata- log, under product safety regulations section, iec/en/din en 60747-5-2, for a detailed descrip- tion of method a and method b partial discharge test profi les. ***refer to the following fi gure for dependence of p s and i s on ambient temperature. output power - p s , input current - i s 0 0 t a - case temperature - o c 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 175 p s (mw) i s (ma)
7 insulation and safety related specifi cations parameter symbol value unit conditions minimum external air gap (clearance) l(101) 7.4 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 8.0 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti >175 volts din iec 112/vde 0303 part 1 isolation group iii a material group (din vde 0110, 1/89, table 1) absolute maximum ratings parameter symbol min. max. unit note storage temperature t s -55 125 c operating temperature t a - 40 100 supply voltage v dd1 , v dd2 0 5.5 v steady-state input voltage 2 second transient input voltage v in+ , v in- -2.0 v dd1 +0.5 -6.0 v dd1 +0.5 output voltage v out -0.5 v dd2 +0.5 solder refl ow temperature profi le see solder refl ow temperature profi le section recommended operating conditions parameter symbol min. max. unit note ambient operating temperature t a -40 85 c supply voltage v dd1 , v dd2 4.5 5.5 v input voltage (accurate and linear) v in+ , v in- -200 200 mv 1 input voltage (functional) v in+ , v in- -2 2 v
8 dc electrical specifi cations unless otherwise noted, all typicals and fi gures are at the nominal operating conditions of v in+ = 0, v in- = 0 v, v dd1 = v dd2 = 5 v and t a = 25c; all min./max. specifi cations are within the recommended operating conditions. parameter symbol min. typ. max. unit test conditions fig. note input off set voltage v os -2.0 0.3 2.0 mv t a = 25c 1,2 -3.0 3.0 mv t a = -40c to +85c 1,2 magnitude of input off set change vs. temperature |v os /t a | 3.0 10.0 v/c 3 2 gain ( 5% tol.) g 7.60 8.00 8.40 v/v -200 mv < v in+ < 200 mv, t a = 25c 4,5,6 3 magnitude of v out gain change vs. temperature |g/t a | 0.00025 v/v/c 4 v out 200 mv nonlinearity nl 200 0.0037 0.35 % -200 mv < v in+ < 200 mv 7,8 5 magnitude of v out 200 mv nonlinearity change vs. temperature |dnl 200 /dt| 0.0002 % / c v out 100 mv nonlinearity nl 100 0.0027 0.2 % -100 mv < v in+ < 100 mv 6 maximum input voltage before v out clipping |v in+ | max 308.0 mv 9 input supply current i dd1 10.86 15.5 ma v in+ = 400 mv 10 7 output supply current i dd2 11.56 15.5 v in+ = -400 mv 8 input current i in+ -0.5 5.0 a 11 9 magnitude of input bias current vs. temperature coeffi cient |di in /dt| +0.45 na/c 11 output low voltage v ol 1.29 v 10 output high voltage v oh 3.80 v 10 output common-mode voltage v ocm 2.2 2.545 2.8 v output short-circuit current |i osc | 18.6 ma 11 equivalent input impedance r in 500 k v out output resistance r out 15 input dc common-mode rejection ratio cmrr in 76.1 db 12
9 ac electrical specifi cations unless otherwise noted, all typicals and fi gures are at the nominal operating conditions of v in+ = 0, v in- = 0 v, v dd1 = v dd2 = 5 v and t a = 25c; all min./max. specifi cations are within the recommended operating conditions. parameter symbol min. typ. max. unit test conditions fig. note v out bandwidth (-3 db) bw 50 100 khz v in+ = 200 mv pk-pk sine wave. 12,13 v out noise n out 31.5 mvrms v in+ = 0.0 v 13 v in to v out signal delay (50 C 10%) t pd10 2.03 3.3 s measured at output of mc34081 on figure 15. v in+ = 0 mv to 150 mv step. 14,15 v in to v out signal delay (50 C 50%) t pd50 3.47 5.6 v in to v out signal delay (50 C 90%) t pd90 4.99 9.9 v out rise/fall time (10 C 90%) t r/f 2.96 6.6 common mode transient immunity cmti 10.0 15.0 kv/s v cm = 1 kv, t a = 25c 16 14 power supply rejection psr 170 mvrms with recommended application circuit. 15 package characteristics parameter symbol min. typ. max. unit test conditions fig. note input-output momentary withstand voltage v iso 3750 vrms rh < 50%, t = 1 min., t a = 25c 16,17 resistance (input-output) r i-o >10 9 v i-o = 500 v dc 18 capacitance (input-output) c i-o 1.2 pf f = 1 mhz 18
10 notes: general note: typical values represen t the mean value of all characteriza- tion units at the nominal operating conditions. typical drift specifi ca- tions are determined by calculating the rate of change of the specifi ed parameter versus the drift pa-ramet er (at nominal operating conditions) for each characterization unit, and then averaging the individual unit rates. the corresponding drift fi gures are normalized to the nominal operating conditions and show how much drift occurs as the par-ticular drift parameter is varied from its nominal value, with all other param- eters held at their nominal operating values. note that the typical drift specifi cations in the tables below may diff er from the slopes of the mean curves shown in the corresponding fi gures. 1. avago recommends operation with v in- = 0 v (tied to gnd1). limiting v in+ to 100 mv will improve dc nonlinearity and nonlinear- ity drift. if v in- is brought above v dd1 C 2 v, an internal test mode may be activated. this test mode is for testing led coupling and is not intended for customer use. 2. this is the absolute value of input off set change vs. temperature. 3. gain is defi ned as the slope of the best-fi t line of diff erential output voltage (v out+ Cv out- ) vs. diff erential input voltage (v in+ Cv in- ) over the specifi ed input range. 4. this is the absolute value of gain change vs. temperature. 5. nonlinearity is defi ned as half of the peak-to-peak output deviation from the best-fi t gain line, expressed as a percentage of the full-scale diff erential output voltage. 6. nl 100 is the nonlinearity specifi ed over an input voltage range of 100 mv. 7. the input supply current decreases as the diff erential input voltage (v in+ Cv in- ) decreases. 8. the maximum specifi ed output supply current occurs when the diff erential input voltage (v in+ Cv in- ) = -200 mv, the maximum rec- ommended operat-ing input voltage. however, the out-put supply current will continue to rise for diff erential input voltages up to approximately -300 mv, beyond which the output supply current remains constant. 9. because of the switched-capacitor nature of the input sigma-delta con-verter, time-averaged values are shown. 10. when the diff erential input signal exceeds approximately 308 mv, the outputs will limit at the typical values shown. 11. short circuit current is the amount of output current generated when either output is shorted to v dd2 or ground. 12. cmrr is defined as the ratio of the differential signal gain (signal applied differentially between pins 2 and 3) to the common-mode gain (input pins tied together and the signal applied to both inputs at the same time), expressed in db. 13. output noise comes from two primary sources: chopper noise and sigma-delta quantization noise. chopper noise results from chopper stabilization of the output op-amps. it occurs at a specifi c frequency (typically 400 khz at room temperature), and is not at- tenuated by the internal output fi lter. a fi lter circuit can be easily added to the external post-amplifi er to reduce the total rms output noise. the internal output fi lter does eliminate most, but not all, of the sigma-delta quantization noise. the magnitude of the output quantization noise is very small at lower frequencies (below 10 khz) and increases with increasing frequency. 14. cmti (common mode transient immunity or cmr, common mode rejection) is tested by applying an exponentially rising/falling voltage step on pin 4 (gnd1) with respect to pin 5 (gnd2). the rise time of the test waveform is set to approximately 50 ns. the ampli- tude of the step is adjusted until the diff erential output (v out+ Cv out- ) exhibits more than a 200 mv deviation from the average output voltage for more than 1s. the hcpl-7840 will continue to func-tion if more than 10 kv/s common mode slopes are applied, as long as the breakdown voltage limitations are observed. 15. data sheet value is the diff erential amplitude of the transient at the output of the hcpl-7840 when a 1 v pk-pk , 1 mhz square wave with 40 ns rise and fall times is applied to both v dd1 and v dd2 . 16. in accordance with ul 1577, each optocoupler is proof tested by ap- plying an insulation test voltage 4500 vrms for 1 second (leakage detection current limit, i i-o 5 a). this test is performed before the 100% production test for partial discharge (method b) shown in iec/en/din en 60747-5-2 insulation characteristic table. 17. the input-output momentary with stand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the vde 0884 insula tion characteristics table and your equipment level safety specifi cation. 18. this is a two-terminal measurement: pins 1C4 are shorted together and pins 5C8 are shorted together.
11 figure 3. input off set vs. supply. figure 4. gain vs. temperature. figure 1. input off set voltage test circuit. figure 2. input off set voltage vs. temperature. figure 5. gain and nonlinearity test circuit. 0.1 ? v dd2 v out 8 7 6 1 3 hcpl-7840 5 2 4 0.1 ? 10 k 10 k v dd1 +15 v 0.1 ? 0.1 ? -15 v + ad624cd gain = 100 0.47 ? 0.47 ? 0.1 ? v dd2 8 7 6 1 3 hcpl-7840 5 2 4 0.01 ? 10 k 10 k +15 v 0.1 ? 0.1 ? -15 v + ad624cd gain = 4 0.47 ? 0.47 ? v dd1 13.2 404 v in v out +15 v 0.1 ? 0.1 ? -15 v + ad624cd gain = 10 10 k 0.47 ? 0.1 ? voltage t a C temperature C c 0.6 0.5 0.3 -25 0.8 35 95 0.2 0.7 -55 125 0.4 565 input offset v dd C supply voltage C v 0.37 0.36 0.39 4.75 5.0 0.33 vs. v dd1 4.5 5.5 5.25 vs. v dd2 0.34 0.38 0.35 gain t a C temperature C c 8.025 8.02 8.015 -35 8.035 25 85 8.01 8.03 -55 125 5 45 105 -15 65
12 gain v dd C supply voltage C v 8.028 8.032 4.75 5.0 8.024 4.5 5.5 5.25 8.03 8.026 vs. v dd1 vs. v dd2 nonlinearity t a C temperature C c 0.02 0.015 0.005 -25 0.03 35 95 0 0.025 -55 125 0.01 565 propagation delay t a C temperature C c 3.1 -25 5.5 56595 1.5 4.7 -55 125 3.9 2.3 35 tpd 10 tpd 50 tpd 90 tpd rise v o C output voltage C v v in C input voltage C v 2.6 1.8 -0.3 4.2 -0.1 0.1 0.3 v op v or 1.0 3.4 -0.5 0.5 nonlinearity v dd C supply voltage C v 0.005 4.75 5.0 0.002 4.5 5.5 5.25 0.004 0.003 vs. v dd1 vs. v dd2 supply current v in C input voltage C v 7 -0.3 13 -0.1 0.1 0.3 4 10 -0.5 0.5 i dd1 i dd2 input current v in C input voltage C v -3 -0.4 0 -0.2 0.2 0.4 -5 -1 -0.6 0.6 -2 -4 0 gain - db frequency (hz) -2 1 -4 0 10 100000 -1 -3 1000 100 10000 phase - degrees frequency (hz) -100 50 -300 0 10 100000 -50 -150 1000 -200 -250 100 10000 figure 12. gain vs. frequency. figure 13. phase vs. frequency. figure 14. propagation delay vs. temperature. figure 6. gain vs. supply. figure 7. nonlinearity vs. temperature. figure 8. nonlinearity vs. supply. figure 9. output voltage vs. input voltage. figure 10. supply current vs. input voltage. figure 11. input current vs. input volta ge.
13 figure 16. cmti test circuits. figure 15. propagation delay test circuits. 0.1 ? v dd2 v out 8 7 6 1 3 hcpl-7840 5 2 4 2 k 2 k +15 v 0.1 ? 0.1 ? -15 v + mc34081 0.1 ? 10 k 10 k 0.01 ? v dd1 v in v in impedance less than 10 . 0.1 ? v dd2 v out 8 7 6 1 3 hcpl-7840 5 2 4 2 k 2 k 78l05 +15 v 0.1 ? 0.1 ? -15 v + mc34081 150 pf in out 0.1 ? 0.1 ? 9 v pulse gen. v cm + 10 k 10 k 150 pf
14 application information power supplies and bypassing the recommended supply con-nections are shown in figure 17. a fl oating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 v using a simple zener diode (d1); the value of resistor r4 should be chosen to supply suffi cient current from the existing fl oating supply. the voltage from the current sensing resistor (rsense) is applied to the input of the hcpl-7840 through an rc anti-aliasing fi lter (r2 and c2). although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. the power supply for the hcpl -7840 is most often ob- tained from the same supply used to power the power transistor gate drive circuit. if a dedicated supply is re- quired, in many cases it is possible to add an additional winding on an existing transformer. otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency dc-dc converter. an inexpensive 78l05 three-terminal regulator can also be used to reduce the fl oating supply voltage to 5 v. to help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass fi lter with the regulators input bypass capacitor. figure 17. recommended supply and sense resistor connections. hcpl-7840 c1 0.1 ? r2 39 gate drive circuit floating power supply ? ? hv+ ? ? hv ? ? + r sense motor c2 0.01 ? d1 5.1 v + r1
15 as shown in figure 18, 0.1 f bypass capacitors (c1, c2) should be located as close as possible to the pins of the hcpl-7840. the bypass capacitors are required because of the high-speed digital nature of the signals inside the hcpl-7840. a 0.01 f bypass capacitor (c2) is also rec- ommended at the input due to the switched-capacitor also forms part of the anti-aliasing fi lter, which is recom- mended to prevent high-frequency noise from aliasing down to lower frequencies and interfering with the input signal. the input fi lter also performs an important reliabil- ity functionit reduces transient spikes from esd events fl owing through the current sensing resistor. 0.1 ? +5 v v out 8 7 6 1 3 u2 5 2 4 r1 2.00 k +15 v c8 0.1 ? 0.1 ? -15 v + mc34081 r3 10.0 k hcpl-7840 c4 r4 10.0 k c6 150 pf u3 u1 78l05 in out c1 c2 0.01 ? r5 68 gate drive circuit positive floating supply ? ? hv+ ? ? hv ? ? + r sense motor c5 150 pf 0.1 ? 0.1 ? c3 c7 r2 2.00 k figure 18: recommended application circuit. pc board layout the design of the printed circuit board (pcb) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. in addition, the layout of the pcb can also aff ect the isolation transient immunity (cmti) of the hcpl-7840, due primarily to stray capacitive coupling between the input and the output circuits. to obtain optimal cmti performance, the layout of the pc board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the pc board does not pass directly below or extend much wider than the body of the hcpl-7840. figure 19. example printed circuit board layout. c3 c2 c4 r5 to r sense+ to r sense to v dd1 to v dd2 v out+ v out
16 figure 20. motor output horsepower vs. motor phase current and supply voltage. the output voltage across the resistor is also reduced, which means that the off set and noise, which are fi xed, become a larger percentage of the signal amplitude. the selected value of the sense resistor will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specifi c design. when sensing currents large enough to cause signifi cant heating of the sense resistor, the temperature coeffi cient (tempco) of the resistor can introduce nonlinearity due to the signal dependent temperature rise of the resistor. the eff ect increases as the resistor-to-ambient ther-mal resistance increases. this eff ect can be minimized by reducing the thermal resistance of the current sensing resistor or by using a resistor with a lower tempco. lower- ing the thermal resistance can be accomplished by repo- sitioning the current sensing resistor on the pc board, by using larger pc board traces to carry away more heat, or by using a heat sink. for a two-terminal current sensing resistor, as the value of resistance decreases, the re-sistance of the leads become a signifi cant percentage of the total resistance. this has two primary eff ects on resistor accuracy. first, the eff ective resistance of the sense resistor can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the leads during assembly (these issues will be discussed in more detail shortly). second, the leads are typically made from a material, such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco overall. both of these eff ects are eliminated when a four-terminal current sensing resistor is used. a four-terminal resistor has two additional terminals that are kelvin-connected directly across the resistive element itself; these two ter- minals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. because of the kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. when laying out a pc board for the current sensing resistors, a couple of points should be kept in mind. the kelvin connections to the resistor should be brought together under the body of the resistor and then run very close to each other to the input of the hcpl-7840; this minimizes the loop area of the connection and reduces the possibility of stray mag- netic fi elds from interfering with the measured signal. if the sense resistor is not located on the same pc board as the hcpl-7840 circuit, a tightly twisted pair of wires can accomplish the same thing. current sensing resistors the current sensing resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely aff ect operation), and reasonable tolerance (to maintain overall circuit accuracy). choosing a par- ticular value for the resistor is usually a compro-mise between minimizing power dissipation and maximiz- ing accu-racy. smaller sense resistance decreases power dissipation, while larger sense resistance can improve circuit accuracy by utilizing the full input range of the hcpl -7840. the fi rst step in selecting a sense resistor is determining how much current the resistor will be sensing. the graph in figure 20 shows the rms current in each phase of a three-phase induction motor as a function of average motor output power (in horse-power, hp) and motor drive supply voltage. the maximum value of the sense re-sistor is determined by the current being measured and the maxi-mum recommended input voltage of the isolation amplifi er. the maximum sense resistance can be calculated by taking the maxi-mum recommended input voltage and dividing by the peak current that the sense resistor should see during normal operation. for example, if a motor will have a maximum rms current of 10 a and can experience up to 50% overloads during normal op-eration, then the peak current is 21.1 a (=10 x 1.414 x 1.5). assuming a maximum input voltage of 200 mv, the maximum value of sense resistance in this case would be about 10 m. the maximum average power dissipation in the sense resistor can also be easily calculated by multiplying the sense resistance times the square of the maximum rms current, which is about 1 w in the previous example. if the power dissipation in the sense resistor is too high, the resistance can be decreased below the maximum value to decrease power dissipation. the minimum value of the sense resistor is limited by precision and accuracy require- ments of the design. as the resistance value is reduced, motor phase current C a (rms) 15 5 40 10 25 30 0 35 035 25 10 20 440 v 380 v 220 v 120 v 30 20 5 15
17 also, multiple layers of the pc board can be used to increase current carrying capacity. numerous plated- through vias should surround each non-kelvin terminal of the sense resistor to help distribute the current between the layers of the pc board. the pc board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 a. making the current carrying traces on the pc board fairly large can also improve the sense resistors power dissipation capability by acting as a heat sink. liberal use of vias where the load current enters and exits the pc board is also recommended. sense resistor connections the recommended method for connecting the hcpl-7840 to the current sensing resistor is shown in figure 18. v in+ (pin 2 of the hpcl-7840) is connected to the positive terminal of the sense resistor resistor, while v in- (pin 3) is shorted to gnd1 (pin 4), with the power-supply return path functioning as the sense line to the negative termi- nal of the current sense resistor. this allows a single pair of wires or pc board traces to connect the hcpl-7840 circuit to the sense resistor. by referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the resistor are seen as a common-mode signal and will not interfere with the current-sense signal. this is important because the large load currents fl owing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and off sets that are relatively large compared to the small voltages that are being measured across the current sensing resistor. if the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very impor- tant that the connection from gnd1 of the hcpl-7840 to the sense resistor be the only return path for supply current to the gate drive power supply in order to elimi- nate potential ground loop problems. the only direct connection between the hcpl-7840 circuit and the gate drive circuit should be the positive power supply line. output side the op-amp used in the external post-amplifi er circuit should be of suffi ciently high precision so that it does not contribute a signifi cant amount of off set or off set drift relative to the contribution from the isolation amplifi er. generally, op-amps with bipolar input stages exhibit better off set performance than op-amps with jfet or mosfet input stages. in addition, the op-amp should also have enough bandwidth and slew rate so that it does not adversely aff ect the response speed of the overall circuit. the post-amplifi er circuit includes a pair of capacitors (c5 and c6) that form a single-pole low-pass fi lter; these capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isola-tion amplifi er. many diff erent op-amps could be used in the circuit, including: mc34082a (motorola), tlo32a, tlo52a, and tlc277 (texas instruments), lf412a (national semicon- ductor). the gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate cmrr and adequate gain toler-ance for the overall circuit. resistor networks can be used that have much better ratio toler- ances than can be achieved using discrete resistors. a resistor network also reduces the total number of com- ponents for the circuit as well as the required board space. please refer to avago applications note 1078 for addi- tional information on using isolation amplifi ers.
18 frequently asked questions about the hcpl-7840 1. the basics 1.1: why should i use the hcpl-7840 for sensing current when hall-eff ect sensors are available which dont need an isolated supply voltage? available in an auto-insertable, 8-pin dip package, the hcpl-7840 is smaller than and has better linearity, off set vs. temperature and common mode rejection (cmr) performance than most hall-eff ect sensors. additionally, often the required input-side power supply can be derived from the same supply that powers the gate-drive optocoupler. 2. sense resistor and input filter 2.1: where do i get 10 m resistors? i have never seen one that low. although less common than values above 10 , there are quite a few manufacturers of resistors suitable for measuring currents up to 50 a when combined with the hcpl- 7840. example product information may be found at dales web site (http://www.vishay.com/vishay/dale) and isoteks web site (http://www.isotekcorp.com). 2.2: should i connect both inputs across the sense resistor instead of grounding v in- directly to pin 4? this is not necessary, but it will work. if you do, be sure to use an rc fi lter on both pin 2 (v in+ ) and pin 3 (v in- ) to limit the input voltage at both pads. 2.3: do i really need an rc fi lter on the input? what is it for? are other values of r and c okay? the input anti-aliasing fi lter (r=39 , c=0.01 f) shown in the typical application circuit is recommended for fi l- tering fast switching voltage transients from the input signal. (this helps to attenuate higher signal frequencies which could otherwise alias with the input sampling rate and cause higher input off set voltage.) some issues to keep in mind using diff erent fi lter resistors or capacitors are: 1. (filter resistor:) input bias current for pins 2 and 3: this is on the order of 500 na. if you are using a single fi lter resistor in series with pin 2 but not pin 3 the ixr drop across this resistor will add to the off set error of the device. as long as this ir drop is small compared to the input off set voltage there should not be a problem. if larger- valued resistors are used in series, it is better to put half of the resistance in series with pin 2 and half the resistance in series with pin 3. in this case, the off set voltage is due mainly to resistor mismatch (typically less than 1% of the resistance design value) multiplied by the input bias. 2. (filter resistor:) the equivalent input resistance for -7840 is around 500 k. it is therefore best to ensure that the fi lter resistance is not a signifi cant percentage of this value; otherwise the off set voltage will be increased through the resistor divider eff ect. [as an example, if r fi lt = 5.5 k, then v os = (vin * 1%) = 2 mv for a maximum 200 mv input and v os will vary with respect with vin.] 3. the input bandwidth is changed as a result of this diff erent r-c fi lter confi guration. in fact this is one of the main reasons for changing the input-fi lter r-c time constant. 4. (filter capacitance:) the input capacitance of the -78xx is approximately 1.5 pf. for proper operation the switch- ing input-side sampling capacitors must be charged from a relatively fi xed (low impedance) voltage source. therefore, if a fi lter capacitor is used it is best for this capacitor to be a few orders of magnitude greater than the c input (a value of at least 100 pf works well.) 2.4: how do i ensure that the hcpl-7840 is not destroyed as a result of short circuit conditions which cause voltage drops across the sense resistor that exceed the ratings of the hcpl-7840s inputs? select the sense resistor so that it will have less than 5 v drop when short circuits occur. the only other require- ment is to shut down the drive before the sense resistor is damaged or its solder joints melt. this ensures that the input of the hcpl-7840 can not be damaged by sense resistors going open-circuit.
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. cop y right ? 2005-2012 avago technologies. all rights reserved. obsoletes av01-0569en av02-1289en - jul y 9, 2012 3. isolation and insulation 3.1: how many volts will the hcpl-7840 withstand? the momentary (1 minute) withstand voltage is 3750 v rms per ul 1577 and csa component acceptance notice #5. 4. accuracy 4.1: can the signal to noise ratio be improved? yes. some noise energy exists beyond the 100 khz bandwidth of the hcpl-7800(a). additional fi ltering using dif- ferent fi lter r,c values in the post-amplifi er application circuit can be used to improve the signal to noise ratio. for example, by using values of r3 = r4 = 10 k, c5 = c6 = 470 pf in the application circuit the rms output noise will be cut roughly by a factor of 2. in applications needing only a few khz bandwidth even better noise performance can be obtained. the noise spectral density is roughly 500 nv/ hz below 20 khz (input referred). 4.2: i need 1% tolerance on gain. does avago sell a more precise version? the hcpl-7800a is gain-trimmed and matched to within 1% tolerance (at room temperature.) 4.3: does the gain change if the internal led light output degrades with time? no. the led is used only to transmit a digital patter n. avago has accounted for led degradation in the design of the product to ensure long life. 5. power supplies and start-up 5.1: what are the output voltages before the input side power supply is turned on? v o+ is close to 1.29 v and v o- is close to 3.80 v. this is equivalent to the output response at the condition that led is completely off . 5.2: how long does the hcpl-7840 take to begin working properly after power-up? within 1 ms after v dd1 and v dd2 powered the device starts to work. but it takes longer time for output to settle down completely. in case of the off set measurement while both inputs are tied to ground there is initially v os adjustment (about 60 ms). the output completely settles down in 100 ms after device powering up. 6. miscellaneous 6.1: how does the hcpl-7840 measure negative signals with only a +5 v supply? the inputs have a series resistor for protection against large negative inputs. normal signals are no more than 200 mv in amplitude. such signals do not forward bias any junctions suffi ciently to interfere with accurate operation of the switched capacitor input circuit.

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