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| ae3.0e fujitsu semiconductor data sheet memory cmos 2 512k 32-bit 2-part dual part single data rate i/f fcram tm consummer/embeded application specific memory for sip mb811l646449-12/18 cmos 2-bank 524,288-word 32-bit 2-part dual part fast cycle random access memory(fcram) with sinlge data rate n description the fujitsu mb811l646449 is a dual part single data rate interface fast cycle random access memory (fcram*) containing 33,554,432 memory cells accessible in a 32-bit format for each part. the mb811l646449 features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb811l646449 is utilized using a fujitsu advanced fcram core technology and designed for low power consumption and low voltage operation than reguler synchronous dram (sdram). the mb811l646449 is dedicated for sip (system in a package), and ideally suited for various embedded/ consumer applications including digital avs and image processing where a large band width and low power consumption memory is needed. *: fcram is a trademark of fujitsu limited, japan. n product line & features parameter mb811l646449-12 mb811l646449-18 cl - t rcd - t rp cl = 2 2 - 2 - 2 clk min. 2 - 2 - 2 clk min. clock frequency 81 mhz max. 54 mhz max. burst mode cycle time cl = 2 12 ns min. 18 ns min. access time from clock cl = 2 9 ns max. 9 ns max. operating current 240ma max. 160ma max. power down mode current (i cc2ps ) 2 ma max. 2 ma max. self refresh current (i cc6 ) 5 ma max. 5 ma max.
2 mb811l646449-12/18 (ae3.0e) ? dual 32m bit (2 banks 512k words 32 bits) parts on a single chip ? independent lines of power suply, address, control and i/o lines for each part ? configurable as 2 banks 512k words 64 bits 1 part or 4 banks 512k words 32 bits 1 part as well as 2 banks 512k words 32 bits 2 parts, with external line connections ?v ccq : +3.3v supply 0.3v tolerance or +2.5v supply 0.2v tolerance ?v dd : +2.5 v supply 0.2 v tolerance ? lvcmos compatible i/o interface ? 2 k refresh cycles every 32 ms ? two bank operation for each part ? burst read/write operation and burst read/single write operation capability ? programmable burst type and burst length ? cas latency=2 ? auto-and self-refresh (every 15.6 m s) ? cke power down mode ? output enable and input data mask 3 mb811l646449-12/18 (ae3.0e) n pad layout vddl vssl ? dql<0> dql<15> vccql vssql dql<1> dql<14> dql<2> dql<13> dql<3> dql<12> dql<4> dql<11> dql<5> dql<10> dql<6> dql<9> vssql vccql dql<7> dql<8> vddl vddil vssl vssil dqm0l dqm1l webl casbl rasbl clkl csbl ckel al<9> bal<0> al<8> vddl vssl al<7> al<10> al<6> al<0> al<5> al<1> al<4> al<2> al<3> dsel dqm2l dqm3l vddl vddil vssl vssil dql<16> dql<31> vssql vccql dql<17> dql<30> dql<18> dql<29> dql<19> dql<28> dql<20> dql<27> dql<21> dql<26> dql<22> dql<25> vccql vssql dql<23> dql<24> vddl vssl bmel pad pad bmer vssr vddr ? dqr<24> dqr<23> vssqr vccqr dqr<25> dqr<22> dqr<26> dqr<21> dqr<27> dqr<20> dqr<28> dqr<19> dqr<29> dqr<18> dqr<30> dqr<17> vccqr vssqr dqr<31> dqr<16> vssir vssr vddir vddr dqm3r dqm2r dser ar<3> ar<2> ar<4> ar<1> ar<5> ar<0> ar<6> ar<10> ar<7> vssr vddr ar<8> bar<0> ar<9> cker csbr clkr rasbr casbr webr dqm1r dqm0r vssir vssr vddir vddr dqr<8> dqr<7> vccqr vssqr dqr<9> dqr<6> dqr<10> dqr<5> dqr<11> dqr<4> dqr<12> dqr<3> dqr<13> dqr<2> dqr<14> dqr<1> vssqr vccqr dqr<15> dqr<0> vssr vddr padno.176 padno.89 padno.88 padno.1 4 mb811l646449-12/18 (ae3.0e) notes: pad descriptions *left part or right part is defined by adding sufix lorr in the end of each pad name. symbol function v ccq , v dd, v ddi supply voltage dq 0 to dq 31 data i/o v ss , v ssq, v ssi ground dont bond we (web) write enable cas( casb) column address strobe ras (rasb) row address strobe cs (csb) chip select ba bank select (bank address) ap auto precharge enable a 0 to a 10 address input ? row: a 0 to a 10 ? column: a 0 to a 7 cke clock enable clk clock input dqm 0 to dqm 3 input mask/output enable dse disable (apply v ss except disable mode) bme burnin mode entry (apply v ss except burnin mode) 5 mb811l646449-12/18 (ae3.0e) n block diagram fig. 1 C mb811l646449 block diagram (for 1 part) bank-1 v dd v ss clk cke a 0 to a 9 , a 10 /ap dq 0 to dq 31 command decoder clock buffer address buffer/ register i/o data buffer/ register mode register ras cas we fcram core (2,048 256 32) col. addr. ras cas we cs bank-0 i/o row addr. to each block control signal latch v ddi ba column address counter dqm 0 to dqm 3 v ssq v ccq v ssi dse bme 6 mb811l646449-12/18 (ae3.0e) n functional truth table note *1 command truth table note *2, *3, and *4 notes: *1. v = valid, l = logic low, h = logic high, x = either l or h. *2. all commands assume no csus command on previous rising edge of clock. *3. all commands are assumed to be valid state transitions. *4. all inputs are latched on the rising edge of clock. *5. nop and desl commands have the same effect on the part. unless specifically noted, nop will represent both nop and desl command in later description. *6. read, reada, writ and writa commands should only be issued after the corresponding bank has been activated (actv command). refer to state diagram in section n functional description. *7. actv command should only be issued after corresponding bank has been precharged (pre or pall command). *8. required after power up. refer to power-up initialization in section n functional description. *9. mrs command should only be issued after all banks have been precharged (pre or pall command). refer to state diagram in section n functional description. function notes symbol cke cs ras cas we ba a 10 (ap) a 9 to a 8 a 7 to a 0 n-1 n device deselect *5deslhxhxxxxxxx no operation *5nophxlhhhxxxx burst stop bsthxlhhlxxxx read *6 read h x l h l h v l x v read with auto-precharge *6 reada h x l h l h v h x v write *6 writ h x l h l l v l x v write with auto-precharge *6 writa h x l h l l v h x v bank active *7actvhxllhhvvvv precharge single bank pre h x l l h l v l x x precharge all banks pall h x l l h l x h x x mode register set *8, *9mrshxll llxxvv 7 mb811l646449-12/18 (ae3.0e) dqm truth table notes: *1. i = 0, 1, 2, 3 *2. dqm 0 for dq 0 to dq 7 , dqm 1 for dq 8 to dq 15 , dqm 2 for dq 16 to dq 23 , dqm 3 for dq 24 to dq 31 , cke truth table notes: *1. the csus command requires that at least one bank is active. refer to state diagram in section n functional description. nop or dsel commands should only be issued after csus and pre(or pall) commands asserted at the same time. *2. ref and self commands should only be issued after all banks have been precharged (pre or pall command). refer to state diagram in section n functional description. *3. self and pd commands should only be issued after the last read data have been appeared on dq. *4. cke should be held high within one t rc period after t cksp . function symbol cke dqmi *1,*2 n-1 n data write/output enable enbi *1 hx l data mask/output disable maski *1 hx h current state function notes symbol cke cs ras cas we ba a 10 (ap) a 9 to a 0 n-1 n bank active clock suspend mode entry *1 csus h l x x x x x x x any (except idle) clock suspend continue *1 l l x x x x x x x clock suspend clock suspend mode exit l h x x x x x x x idle auto-refresh command *2 ref h h l l l h x x x idle self-refresh entry *2, *3 self h l l l l h x x x self refresh self-refresh exit *4 selfx lh l h h h x x x lhh x x x x x x idle power down entry *3 pd hl l h h h x x x hl h x x x x x x power down power down exit lh l h h h x x x lhh x x x x x x 8 mb811l646449-12/18 (ae3.0e) operation command table (applicable to single bank) note *1 (continued) current state cs ras cas we addr command function notes idle h x x x x desl nop lhhh x nop nop lhhl x bst nop l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv bank active after t rcd l l h l ba, ap pre/pall nop l l l h x ref/self auto-refresh or self-refresh *3, *6 llll mode mrs mode register set (idle after t rsc ) *3, *7 bank active h x x x x desl nop lhhh x nop nop lhhl x bst nop l h l h ba, ca, ap read/reada begin read; determine ap l h l l ba, ca, ap writ/writa begin write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall precharge; determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal 9 mb811l646449-12/18 (ae3.0e) (continued) (continued) current state cs ras cas we addr command function notes read hxxx x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end ? bank active) l h h l x bst burst stop ? bank active l h l h ba, ca, ap read/reada terminate burst, new read; determine ap l h l l ba, ca, ap writ/writa terminate burst, start write; determine ap *4 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge ? idle; determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal write hxxx x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end ? bank active) l h h l x bst burst stop ? bank active l h l h ba, ca, ap read/reada terminate burst, start read; determine ap *4 l h l l ba, ca, ap writ/writa terminate burst, new write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge; determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal 10 mb811l646449-12/18 (ae3.0e) (continued) (continued) current state cs ras cas we addr command function notes read with auto- precharge hxxx x desl nop (continue burst to end ? precharge ? idle) lhhh x nop nop (continue burst to end ? precharge ? idle) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal write with auto- precharge hxxx x desl nop (continue burst to end ? precharge ? idle) lhhh x nop nop (continue burst to end ? precharge ? idle) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal 11 mb811l646449-12/18 (ae3.0e) (continued) (continued) current state cs ras cas we addr command function notes pre- charging h x x x x desl nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l x bst nop (idle after t rp ) l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall nop (pall may affect other bank) *5 l l l h x ref/self illegal l l l l mode mrs illegal bank activating h x x x x desl nop (bank active after t rcd ) l h h h x nop nop (bank active after t rcd ) l h h l x bst nop (bank active after t rcd ) l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal 12 mb811l646449-12/18 (ae3.0e) (continued) abbreviations: ra = row address ba = bank address ca = column address ap = auto precharge notes: *1. all entries assume the cke was high during the proceeding clock cycle and the current clock cycle. illegal means dont used command. if used, power up sequence be asserted after power shout down. *2. illegal to bank in specified state; entry may be legal in the bank specified by ba, depending on the state of that bank. *3. illegal if any bank is not idle. *4. must satisfy bus contention, bus turn around, and/or write recovery requirements. refer to timing diagram - 11 & - 12 in section n timing diagrams. *5. nop to bank precharging or in idle state. may precharge bank specified by ba (and ap). *6. self command should only be issued after the last read data have been appeared on dq. *7. mrs command should only be issued on condition that all dq are in hi-z. current state cs ras cas we addr command function notes refreshing h x x x x desl nop (idle after t rc ) l h h x x nop/bst nop (idle after t rc ) lhlx x read/reada/ writ/writa illegal llhx x actv/ pre/pall illegal lllx x ref/self/ mrs illegal mode register setting h x x x x desl nop (idle after t rsc ) l h h h x nop nop (idle after t rsc ) l h h l x bst illegal lhlx x read/reada/ writ/writa illegal llxx x actv/pre/ pall/ref/ self/mrs illegal 13 mb811l646449-12/18 (ae3.0e) command truth table for cke note *1 (continued) current state cke n-1 cke n cs ras cas we addr function notes self- refresh hxxxxx x invalid lhhxxx x exit self-refresh (self-refresh recovery ? idle after t rc ) lhlhhh x exit self-refresh (self-refresh recovery ? idle after t rc ) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) self- refresh recovery lxxxxx x invalid h h h x x x x idle after t rc h h l h h h x idle after t rc h h l h h l x illegal h h l h l x x illegal h h l l x x x illegal hhxxxx x illegal hlxxxx x illegal *2 14 mb811l646449-12/18 (ae3.0e) (continued) (continued) current state cke n-1 cke n cs ras cas we addr function notes power down hxxxxx x invalid lhhxxx x exit power down mode ? idle lhlhhh x l l x x x x x nop (maintain power down mode) l h l l x x x illegal l h l h l x x illegal all banks idle hhhxxx mode refer to the operation command table. hhlhxx mode refer to the operation command table. hhl lhx mode refer to the operation command table. h h l l l h x auto-refresh hhllll mode refer to the operation command table. h l h x x x x power down h l l h h h x power down hllhhl x illegal h l l h l x x illegal h l l l h x x illegal h l l l l h x self-refresh *3 hlllll x illegal lxxxxx x invalid 15 mb811l646449-12/18 (ae3.0e) (continued) notes: *1. all entries in command truth table for cke are specified at cke(n) state and cke input from cke(nC1) to cke(n) state must satisfy corresponding set up and hold time for cke. *2. cke should be held high for t rc period after t cksp . *3. self command should only be issued after the last data have been appeared on dq. current state cke n-1 cke n cs ras cas we addr function notes bank active bank activating read/write hhxxxx x refer to the operation command table. h l x x x x x begin clock suspend next cycle lxxxxx x invalid clock suspend hxxxxx x invalid l h x x x x x exit clock suspend next cycle l l x x x x x maintain clock suspend any state other than listed above lxxxxx x invalid hhxxxx x refer to the operation command table. hlxxxx x illegal 16 mb811l646449-12/18 (ae3.0e) n functional description sdr i/f fcram basic function three major differences between this sdr i/f fcrams and conventional drams are: synchronized operation, burst mode, and mode register. the synchronized operation is the fundamental difference. an sdr i/f fcram uses a clock input for the synchronization, where the dram is basically asynchronous memory although it has been using two clocks, ras and cas . each operation of dram is determined by their timing phase differences while each operation of sdr i/f fcram is determined by commands and all operations are referenced to a positive clock edge. fig. 2 shows the basic timing diagram differences between sdr i/f fcrams and drams. the burst mode is a very high speed access mode utilizing an internal column address generator. once a column addresses for the first access is set, following addresses are automatically generated by the internal column address counter. the mode registe r is to justify the sdr i/f fcram operation and function into desired system conditions. mode register table shows how sdr i/f fcram can be configured for system requirement by mode register programming. fcram tm the mb811l646449 utilizes fcram core technology. the fcram is an acronym of fast cycle random access memory and provides very fast random cycle time, low latency and low power consumption than regular drams. clock input (clk) and clock enable (cke) all input and output signals of sdr i/f fcram use register type buffers. a clk is used as a trigger for the register and internal burst counter increment. all inputs are latched by a positive edge of clk. all outputs are validated by the clk. cke is a high active clock enable signal. when cke = low is latched at a clock input during active cycle, the next clock will be internally masked. during idle state (all banks have been precharged), the power down mode (standby) is entered with cke = low and this will make extremely low standby current. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and address input. when cs is high, command signals are negated but internal operation such as burst cycle will not be suspended. if such a control isnt needed, cs can be tied to ground level. command input (ras , cas and we ) unlike a conventional dram, ras , cas , and we do not directly imply sdr i/f fcram operation, such as row address strobe by ras . instead, each combination of ras , cas , and we input in conjunction with cs input at a rising edge of the clk determines sdr i/f fcram operation. refer to n functional truth table. address input (a 0 to a 10 ) address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. a total of nineteen address input signals are required to decode such a matrix. sdr i/f fcram adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv), eleven row addresses are initially latched and the remainder of eight column addresses are then latched by a column address strobe command of either a read command (read or reada) or write command (writ or writa). bank select (ba) this sdr i/f fcram has two banks in one part and each bank is organized as 512 k words by 32-bit. bank selection by ba occurs at bank active command (actv) followed by read (read or reada), write (writ or writa), and precharge command (pre). 17 mb811l646449-12/18 (ae3.0e) data input and output (dq 0 to dq 31 ) input data is latched and written into the memory at the clock following the write command input. data output is obtained by the following conditions followed by a read command input: t rac ; from the bank active command when t rcd (min) is satisfied. (this parameter is reference only.) t cac ; from the read command when t rcd is greater than t rcd (min). (this parameter is reference only.) t ac ; from the clock edge after t rac and t cac . the polarity of the output data is identical to that of the input. data is valid between access time (determined by the three conditions above) and the next positive clock edge (t oh ). data i/o mask (dqm) dqm is an active high enable input and has an output disable and input mask function. during burst cycle and when dqm 0 to dqm 3 = high is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. dqm 0 , dqm 1, dqm 2 , dqm 3 , controls dq 0 to dq 7, dq 8 to dq 15, dq 16 to dq 23, dq 24 to dq 31, respectively. burst mode operation and burst type the burst mode provides faster memory access. the burst mode is implemented by keeping the same row address and by automatic strobing column address. access time and cycle time of burst mode is specified as t ac and t ck , respectively. the internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary. in order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: the burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. but only the sequential mode is usable to the full column burst. the sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0). the interleave mode is a scrambled decoding scheme for a 0 and a 2 . if the first access of column address is even (0), the next address will be odd (1), or vice-versa. when the full burst operation is executed at single write mode, auto-precharge command is valid only at write operation. current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step mask command (normally 3 clock cycles) 2nd step write command after l owd burst write burst write write command burst write burst read read command burst read precharge precharge command burst write precharge precharge command 18 mb811l646449-12/18 (ae3.0e) full column burst and burst stop command (bst) the full column burst is an option of burst length and available only at sequential mode of burst type. this full column burst mode is repeatedly access to the same column. if burst mode reaches end of column address, then it wraps round to first column address (= 0) and continues to count until interrupted by the news read (read) /write (writ), precharge (pre), or burst stop (bst) command. the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. the bst command is applicable to terminate the burst operation. if the bst command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to bank active. when read mode is interrupted by bst command, the output will be in high-z. for the detail rule, please refer to timing diagram C 8 in section n timing diagrams. when write mode is interrupted by bst command, the data to be applied at the same time with bst command will be ignored. burst read & single write the burst read and single write mode provides single word write operation regardless of its burst length. in this mode, burst read operation does not be affected by this mode. burst length starting column address a 2 a 1 a 0 sequential mode interleave 2 x x 0 0 C 1 0 C 1 x x 1 1 C 0 1 C 0 4 x 0 0 0 C 1 C 2 C 3 0 C 1 C 2 C 3 x 0 1 1 C 2 C 3 C 0 1 C 0 C 3 C 2 x 1 0 2 C 3 C 0 C 1 2 C 3 C 0 C 1 x 1 1 3 C 0 C 1 C 2 3 C 2 C 1 C 0 8 0 0 0 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 0 0 1 1 C 2 C 3 C 4 C 5 C 6 C 7 C 0 1 C 0 C 3 C 2 C 5 C 4 C 7 C 6 0 1 0 2 C 3 C 4 C 5 C 6 C 7 C 0 C 1 2 C 3 C 0 C 1 C 6 C 7 C 4 C 5 0 1 1 3 C 4 C 5 C 6 C 7 C 0 C 1 C 2 3 C 2 C 1 C 0 C 7 C 6 C 5 C 4 1 0 0 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 1 0 1 5 C 6 C 7 C 0 C 1 C 2 C 3 C 4 5 C 4 C 7 C 6 C 1 C 0 C 3 C 2 1 1 0 6 C 7 C 0 C 1 C 2 C 3 C 4 C 5 6 C 7 C 4 C 5 C 2 C 3 C 0 C 1 1 1 1 7 C 0 C 1 C 2 C 3 C 4 C 5 C 6 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 19 mb811l646449-12/18 (ae3.0e) precharge and precharge option (pre, pall) sdr i/f fcram memory core is the same as conventional drams, requiring precharge and refresh operations. precharge rewrites the bit line and to reset the internal row address line and is executed by the precharge command (pre). with the precharge command, sdr i/f fcram will automatically be in standby state after precharge time (t rp ). the precharged bank is selected by combination of ap and ba when precharge command is asserted. if ap = high, all banks are precharged regardless of ba (pall). if ap = low, a bank to be selected by ba is precharged (pre). the auto-precharge enters precharge mode at the end of burst mode of read or write without precharge command assertion. this auto precharge is entered by ap = high when a read or write command is asserted. refer to n functional truth table. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the sdr i/f fcram auto-refresh command (ref) generates precharge command internally. all banks of sdr i/f fcram should be precharged prior to the auto- refresh command. the auto-refresh command should also be asserted every 15.6 m s or a total 2048 refresh commands within 32 ms period. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh function until cancelled by selfx. the self-refresh is entered by applying an auto-refresh command in conjunction with cke = low (self). once sdr i/f fcram enters the self-refresh mode, all inputs except for cke will be dont care (either logic high or low level state) and outputs will be in a high-z state. during a self-refresh mode, cke = low should be maintained. self command should only be issued after last read data has been appeared on dq notes: when the burst refresh method is used, a total of 2048 auto-refresh commands within 2 ms must be asserted prior to the self-refresh mode entry. self-refresh exit (selfx) to exit self-refresh mode, apply minimum t cksp after cke brought high, and then the no operation command (nop) or the deselect command (desl) should be asserted within one t rc period. cke should be held high within one t rc period after t cksp . refer to timing diagram-16 in section n timing diagrams for the detail. it is recommended to assert an auto-refresh command just after the t rc period to avoid the violation of refresh period. notes: when the burst refresh method is used, a total of 2048 auto-refresh commands within 2 ms must be asserted after the self-refresh exit. mode register set (mrs) the mode register of sdr i/f fcram provides a variety of different operations. the register consists of four operation fields; burst length, burst type, cas latency, and operation code. refer to n mode register table. the mode register can be programmed by the mode register set command (mrs). each field is set by the address line. once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command (or part loses power). mrs command should only be issued on condition that all dq is in hi-z. the condition of the mode register is undefined after the power-up stage. it is required to set each field after initialization of sdr i/f fcram. refer to power-up initialization below. 20 mb811l646449-12/18 (ae3.0e) power-up initialization the sdr i/f fcram internal condition after power-up will be undefined. it is required to follow the following power on sequence to execute read or write operation. 1. apply power (v dd and v ddi should be applied before or in parallel with v ccq )and start clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, and nop condition for a minimum of 100 m s. 3. precharge all banks by precharge (pre) or precharge all command (pall). 4. assert minimum of 2 auto-refresh command (ref). 5. program the mode register by mode register set command (mrs). in addition, it is recommended dqm and cke to track v dd to insure that output is high-z state. the mode register set command (mrs) can be set before 2 auto-refresh command (ref). disable this command entry doesnt require clock. when dse pad is applied high level, sdr i/f fcram entries disable mode. in disable mode,sdr i/f fcram current cousumption is less than i cc2ps and output is high-z. any command isnt accepted in this mode. to exit disable mode, apply low level to dse pad. burnin this command doesnt require clock. when bme pad is applied high level,sdr i/f fcram entries burnin mode. in burnin mode, self refresh function is asserted internaly. any command isnt accepted in this mode. to exit burnin mode,apply low level to bme pad. 21 mb811l646449-12/18 (ae3.0e) cas latency = 2 ras cas t si burst length = 4 active read/write precharge 22 mb811l646449-12/18 (ae3.0e) mode register set self refresh idle read suspend bank active auto refresh power down bank active suspend fig. 3 C state diagram (simplified for single bank operation state diagram) write write suspend power on precharge read write with auto precharge read with auto precharge writ read read writ bst bst mrs self selfx ref actv cke cke\(csus) cke cke read writ reada writa reada cke writa pre or pall pre or pall power applied definition of allows manual input automatic sequence writa reada pre or pall pre or pall cke\(pd) read suspend cke write suspend cke cke\(csus) cke\(csus) cke\(csus) cke\(csus) note: cke\ means cke goes low-level from high-level. 23 mb811l646449-12/18 (ae3.0e) n bank operation command table minimum clock latency or delay time for 1 bank operation notes: *1. if t rp (min.) 26 mb811l646449-12/18 (ae3.0e) n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (referenced to v ss ) notes: warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit voltage of v ccq supply relative to v ss v ccq C0.5 to +4.6 v voltage of v dd supply relative to v ss v dd , v ddi C0.5 to +3.6 v voltage at any pin relative to v ss v in , v out C0.5 to +4.6 v short circuit output current i out 50 ma power dissipation p d 1.0 w storage temperature t stg C55 to +125 c parameter notes symbol min. typ. max. unit supply voltage v ccq 3.3v i/o 3.0 3.3 3.6 v 2.5v i/o 2.3 2.5 2.7 v v dd , v ddi 2.3 2.5 2.7 v v ss , v ssq, v ssi 000v input high voltage *1 v ih 3.3v i/o 2.4 v ccq + 0.5 v 2.5v i/o 2.0 v ccq + 0.5 v input low voltage *2 v il C0.5 0.4 v ambient temperature t a 070 c *2. undershoot limit: v il (min) 4.6v v ih v il pulse width 5 ns *1. overshoot limit: v ih (max) 50% of pulse amplitude v ih v il -1.5v pulse width measured at 50% of pulse amplitude. = 4.6v for pulse width <= 5 ns acceptable, = v ss -1.5v for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude. 50% of pulse amplitude pulse width 5 ns v ih (min.) v il (max.) 27 mb811l646449-12/18 (ae3.0e) n capacitance (t a = 25 c, f = 1 mhz) parameter symbol min. typ. max. unit input capacitance, except for clk c in1 1.5 5.0 pf input capacitance for clk c in2 1.5 4.0 pf i/o capacitance c i/o 2.0 6.0 pf 28 mb811l646449-12/18 (ae3.0e) n dc characteristics (at recommended operating conditions unless otherwise noted.) note *1, *2, and *3 parameter symbol condition value unit min. max. output high voltage v oh(dc) 3.3v i/o i oh = C2 ma 2.4 v 2.5v i/o i oh = C0.5 ma 2.0 v output low voltage v ol(dc) 3.3v i/o i ol = 2 ma 0.4 v 2.5v i/o i ol = 0.5 ma 0.4 v input leakage current (any input except for dsel,dser,bmel,bmer) i li 0 v v in v ccq ; all other pins not under test = 0 v C5 5 m a input leakage current (dsel,dser,bmel,bmer) i lipd v in = 0 v all oher pins not under test = 0v C5 5 m a input pull down resistance (dsel,dser,bmel,bmer) r pd 520 k output leakage current i lo 0 v v in v ccq ; data out disabled C5 5 m a 29 mb811l646449-12/18 (ae3.0e) (continued) operating current (average power supply current) mb811l646449-12 i cc1 burst length = 1 t rc = min, t ck = min one bank active output pin open adrresses changed up to 1 - time during t rc (min) 0 v v in v il max v ih min v in v ccq 240 ma mb811l646449-18 160 precharge standby current (power supply current) i cc2p cke = v il all banks idle t ck = min power down mode 0 v v in v il max v ih min v in v ccq 4ma i cc2ps cke = v il all banks idle clk = v ih or v il power down mode 0 v v in v il max v ih min v in v ccq 2ma mb811l646449-12 i cc2n cke = v ih all banks idle, t ck = min nop commands only, input signals (except to cmd) are changed 1 time during 2 clocks 0 v v in v il max v ih min v in v ccq 24 ma mb811l646449-18 16 i cc2ns cke = v ih all banks idle clk = v ih or v il input signal are stable 0 v v in v il max v ih min v in v ccq 4ma 30 mb811l646449-12/18 (ae3.0e) (continued) notes: *1. all voltages are referenced to v ss . *2. dc characteristics are measured after following the power-up initialization procedure in sectio n functional description. *3. i cc depends on the output termination or load condition, clock cycle rate, signal clocking rate. the specified values are obtained with the output open and no termination register. parameter symbol condition value unit min. max. active standby current (power supply current) i cc3p cke = v il any bank active t ck = min 0 v v in v il max v ih min v in v ccq 4ma i cc3ps cke = v il any bank active clk = v ih or v il 0 v v in v il max v ih min v in v ccq 2ma mb811l646449-12 i cc3n cke = v ih any bank active t ck = min nop commands only, input signals (except to cmd) are changed 1 time during 2 clocks 0 v v in v il max v ih min v in v ccq 75 ma mb811l646449-18 50 i cc3ns cke = v ih any bank active clk = v ih or v il input signals are stable 0 v v in v il max v ih min v in v ccq 4ma burst mode current (average power supply current) mb811l646449-12 i cc4 t ck = min burst length = 4 output pin open all-banks active gapless data 0 v v in v il max v ih min v in v ccq 285 ma mb811l646449-18 190 refresh current #1 (average power supply current) mb811l646449-12 i cc5 auto-refresh; t ck = min t rc = min 0 v v in v il max v ih min v in v ccq 300 ma mb811l646449-18 200 refresh current #2 (average power supply current) i cc6 self-refresh; t ck = min cke 0.2 v 0 v v in v il max v ih min v in v ccq 5ma 31 mb811l646449-12/18 (ae3.0e) n ac characteristics (at recommended operating conditions unless otherwise noted.) note *1, *2, and *3 parameter notes symbol mb811l646449-12 mb811l646449-18 unit min. max. min. max. clock period cl = 2 t ck2 12 18 ns clock high time *5 t ch t ck x 0.3 t ck x 0.4 ns clock low time *5 t cl t ck x 0.3 t ck x 0.4 ns input setup time *5 t si 34ns input hold time *5 t hi 1.5 1.5 ns access time from clock(t ck =min) *5,*6,*7 cl = 2 t ac2 99ns output in low-z *5 t lz 00ns output in high-z *5,*8 cl = 2 t hz2 2929ns output hold time *5,*7 cl = 2 t oh 22ns time between auto-refresh command interval *4 t refi 15.6 15.6 m s time between refresh t ref 3232ms transition time t t 0.5100.510ns cke setup time for power down exit time *5 t cksp 34ns 32 mb811l646449-12/18 (ae3.0e) base values for clock count/latency clock count formula note *10 parameter notes symbol mb811l646449-12 mb811l646449-18 unit min. max. min. max. ras cycle time *9 t rc 72 108 ns ras precharge time t rp 24 36 ns ras active time t ras 48 110000 72 110000 ns ras to cas delay time t rcd 24 36 ns write recovery time t wr 18 18 ns ras to ras bank active delay time t rrd 24 36 ns data-in to precharge lead time t dpl 12 18 ns data-in to active/refresh command period cl=2 t dal2 1 cyc + t rp 1 cyc + t rp ns mode resister set cycle time t rsc 24 36 ns clock 3 (round up a whole number) base value clock period 33 mb811l646449-12/18 (ae3.0e) latency - fixed values (the latency values on these parameters are fixed regardless of clock period.) notes: *1. ac characteristics are measured after following the power-up initialization procedure in section n functional description. *2. ac characteristics assume t t = 1 ns, 10 pf of capacitive load and 50 w of terminated load. *3. 1.4 v is the reference level for 3.3 v i/o for measuring timing of input signals. 1.2 v is the reference level for 2.5 v i/o for measuring timing of input singnals. transition times are measured between v ih (min) and v il (max). *4. this value is for reference only. *5. if input signal transition time (t t ) is longer than 1 ns; [(t t /2) C 0.5] ns should be added to t ac (max), t hz (max), and t cksp (min) spec values, [(t t /2) C 0.5] ns should be subtracted from t lz (min), t hz (min), and t oh (min) spec values, and (t t C 1.0) ns should be added to t ch (min), t cl (min), t si (min), and t hi (min) spec values. *6. t ac also specifies the access time at burst mode. *7. t ac and t oh are measured under output load circuit shown in fig. 4. *8. specified where output buffer is no longer driven. *9. actual clock count of t rc (l rc ) will be sum of clock count of t ras (l ras ) and t rp (l rp ). *10. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). parameter notes sym- bol mb811l646449-12 mb811l646449-18 unit cke to clock disable l cke 1 1 cycle dqm to output in high-z l dqz 2 2 cycle dqm to input data delay l dqd 0 0 cycle last output to write command delay l owd 2 2 cycle write command to input data delay l dwd 0 0 cycle precharge to outputin high-z delay cl = 2 l roh2 2 2 cycle burst stop command to output in high-z delay cl = 2 l bsh2 2 2 cycle cas to cas delay (min) l ccd 1 1 cycle cas bank delay (min) l cbd 1 1cycle 34 mb811l646449-12/18 (ae3.0e) output note: by adding appropriate correlation factors to the test conditions, t ac and t oh measured when the output is coupled to the output load circuit are within specifications. fig. 4 C output load circuit r 1 = 50 w cl = 10 pf 1.4 v (3.3 v i/o) 1.2 v (2.5 v i/o) 35 mb811l646449-12/18 (ae3.0e) t si t hi t ch t ck t ac t hz t oh t lz t cl clk input (control, addr. & data) output 2.4 v(3.3 v i/o) 2.0 v(2.5 v i/o) 1.4 v (3.3v i/o) 1.2v (2.5v i/o) 0.4 v 0.4 v 0.4 v note: reference level of input signal is 1.4 v for lvcmos (3.3v i/o),1.2v for lvcmos (2.5v i/o ). access time is measured at 1.4 v for lvcmos (3.3v i/o),1.2v for lvcmos (2.5v i/o). ac characteristics are also measured in this condition. fig. 5 C timing diagram, setup, hold and delay time 2.4 v(3.3 v i/o) 2.0 v(2.5 v i/o) 1.4 v (3.3v i/o) 1.2v (2.5v i/o) 2.4 v(3.3 v i/o) 2.0 v(2.5 v i/o) 1.4 v (3.3v i/o) 1.2v (2.5v i/o) clk cke t cksp (min) nop dont care dont care command 1 clock (min) nop actv fig. 6 C timing diagram, delay time for power down exit 36 mb811l646449-12/18 (ae3.0e) fig. 7 C timing diagram, pulse width t rc , t rp , t ras , t rcd , t wr , t ref , t dpl , t dal , t rsc , t rrd , t cksp command command clk input (control) note: these parameters are a limit value of the rising edge of the clock from one command input to next input. t cksp is the latency value from the rising edge of cke. measurement reference voltage is 1.4 v (3.3v i/o) or 1.2v (2.5v i/o). fig. 8 C timing diagram, access time t ac (cas latency C 1) t ck clk command dq 0 to dq 31 (output) q(valid) read t ac q(valid) q(valid) t ac 37 mb811l646449-12/18 (ae3.0e) n timing diagrams timing diagram C 1 : clock enable - read and write suspend (@ bl = 4) q1 q2 (no change) q3 (no change) q4 d1 not written d2 not written d3 d4 clk cke clk (internal) dq 0 to dq 31 (read) dq 0 to dq 31 (write) notes: *1. the latency of cke (l cke ) is one clock. *2. during read mode, burst counter will not be incremented/decremented at the next clock of csus command. output data remain the same data. *3. during the write mode, data at the next clock of csus command is ignored. *1 *3 *3 *1 *2 *2 *2 *2 i cke (1 clock) i cke (1 clock) timing diagram C 2 : clock enable - power down entry and exit nop pd(nop) dont care nop actv clk cke command 1 clock (min) *1 *2 *3 nop *3 notes: *1. precharge command (pre or pall) should be asserted if any bank is active and in the burst mode. *2. precharge command can be posted in conjunction with cke after the last read data have been appeared on dq. *3. it is recommended to apply nop command in conjunction with cke. *4. the actv command can be latched after t cksp (min) + 1 clock (min). t cksp (min) t ref (max) *4 38 mb811l646449-12/18 (ae3.0e) timing diagram C 3 : column address to column address input delay clk ras cas row address column address address i ccd (1 clock) t rcd (min) note: cas to cas delay can be one or more clock period. i ccd i ccd i ccd column address column address column address column address timing diagram C 4 : different bank address input delay t rrd (min) clk ras cas row address address bank 0 bank 1 bank 1 bank 1 bank 0 bank 0 ba t rcd (min) i cbd (1 clock) i cbd column address row address column address column address column address t rcd (min) or more note: cas bank delay can be one or more clock period. 39 mb811l646449-12/18 (ae3.0e) timing diagram C 5 : dqm 0 to dqm 3 - input mask and output disable (@ bl = 4) clk dqm 0 to dqm 3 (@ read) dq 0 to dq 31 (@ read) dqm 0 to dqm 3 (@ write) dq 0 to dq 31 (@ write) q1 q2 hi-z q4 end of burst d1 masked d3 d4 end of burst i dqz (2 clocks) i dqd (same clock) timing diagram C 6 : precharge timing (applied to the same bank) t ras (min) clk command actv pre note: precharge means pre or pall. 40 mb811l646449-12/18 (ae3.0e) timing diagram C 7 : read interrupted by precharge (example @ cl = 2, bl = 4) clk command dq 0 to dq 31 command dq 0 to dq 31 command dq 0 to dq 31 command dq 0 to dq 31 hi-z q1 precharge q1 q2 q1 q2 q3 q1 q2 q3 q4 hi-z hi-z no effect (end of burst) note: in case of cl = 2, the l roh is 2 clocks. precharge means pre or pall. i roh (2 clocks) i roh (2 clocks) i roh (2 clocks) precharge precharge precharge 41 mb811l646449-12/18 (ae3.0e) timing diagram C 8 : read interrupted by burst stop (example @cl=2,bl = full column) clk command dq 0 to dq 31 hi-z q n q n+1 q nC1 q nC2 l bsh (2 clocks) bst timing diagram C 9 : write interrupted by burst stop (example @ bl = 2) clk command dq 0 to dq 31 last data-in masked by bst bst command 42 mb811l646449-12/18 (ae3.0e) timing diagram C 10 : write interrupted by precharge (example @ cl = 2) t rp (min) t dpl (min) clk command dq 0 to dq 31 actv data- last data-in masked by precharge note: the precharge command (pre) should only be issued after the t dpl of final data input is satisfied. precharge means pre or pall. precharge timing diagram C 11 : read interrupted by write (example @ cl = 2, bl = 4) clk command dqm (dqm 0 to dqm 3 ) dq 0 to dq 31 q 1 masked d 1 d 2 *1 *2 *3 writ notes: *1. first dqm makes high-impedance state high-z between last output and first input data. *2. second dqm makes internal output data mask to avoid bus contention. *3. third dqm also makes internal output data mask. if burst read ends (final data output) at or after the second clock of burst write, this third dqm is required to avoid internal bus contention. i dwd (same clock) i owd (2 clocks) i dqz (2 clocks) read 43 mb811l646449-12/18 (ae3.0e) (cl-1) t ck timing diagram C 12 : write to read timing (example @ cl = 2, bl = 4) clk command dq 0 to dq 31 dqm (dqm 0 to dqm 3 ) note: read command should be issued after t wr of final data input is satisfied. writ read d1 q2 q3 d3 masked by read t wr (min) d2 t ac (max) q1 44 mb811l646449-12/18 (ae3.0e) reada actv nop or desl actv q1 q2 t ras (min) 2 clocks (same value as bl) t rp (min) timing diagram C 13 : read with auto-precharge (exaple @ cl = 2, bl = 2 applied to same bank) clk command dqm (dqm 0 to dqm 3 ) dq 0 to dq 31 notes: *1. precharge at read with auto-precharge command (reada) is started from number of clocks that is the same as burst length (bl) after the reada command is asserted. *2. next actv command should be issued after bl+t rp (min) from reada command. bl+t rp (min) *1 *2 writa actv actv d1 d2 t dal (min) timing diagram C 14 : write with auto-precharge *1, *2, and *3 (example @ cl = 2, bl = 2 applied to same bank) clk command dqm (dqm 0 to dqm 3 ) dq 0 to dq 31 nop or desl notes: *1. even if the final data is masked by dqm, the precharge does not start the clock of final data input. *2. once auto precharge command is asserted, no new command within the same bank can be issued. *3. auto-precharge command doesnt affect at full column burst operation except burst read & single write. *4. precharge at write with auto-precharge is started after cl - 1 from the end of burst. *5. next command should be issued after bl+ t rp (min) at cl = 2 from writa command. t ras (min) bl+t rp (min) cl - 1 *4 *5 45 mb811l646449-12/18 (ae3.0e) timing diagram C 15 : auto-refresh timing t rc (min) t rc (min) clk command ba ref command nop ba *1 nop nop ref nop *4 dont care notes: *1. all banks should be precharged prior to the first auto-refresh command (ref). *2. bank select is ignored at ref command. the refresh address and bank select are selected by internal refresh counter. *3. either nop or desl command should be asserted during t rc period while auto-refresh mode. *4. any activation command such as actv or mrs command other than ref command should be asserted after t rc from the last ref command. *3 dont care *3 *3 *3 *2 *2 timing diagram C 16 : self-refresh entry and exit timing t rc (min) t cksp (min) clk cke command nop notes: *1. precharge command (pre or pall) should be asserted if any bank is active prior to self-refresh entry command (self). *2. the self-refresh exit command (selfx) is latched after t cksp (min). it is recommended to apply nop command in conjunction with cke. *3. either nop or desl command can be used during t rc period. *4. cke should be held high within one t rc period after t cksp . *5. cke level should be held less than 0.2 v during self-refresh mode. self dont care selfx command nop *2 nop *3 *1 t si (min) *4 *5 46 mb811l646449-12/18 (ae3.0e) timing diagram C 17 : mode register set timing clk command address mrs nop or desl mode row address actv notes: the mode register set command (mrs) should only be asserted after all banks have been precharged. t rsc (min) 47 mb811l646449-12/18 (ae3.0e) memo 48 mb811l646449-12/18 (ae3.0e) fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0111 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. |
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