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09005aef807397e5 dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 1 ?2003 micron technology, inc. 256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm ddr sdram dimm mt16vddt3264a ? 256mb mt16vddt6464a ? 512mb mt16vddt12864a ? 1gb for the latest data sheet, please refer to the micron web site: www.micron.com/moduleds features ? 184-pin, dual in-line memory module (dimm) fast data transfer rates: pc1600, pc2100, or pc2700 utilizes 200 mt/s, 266 mt/s, and 333 mt/s ddr sdram components 256mb (32 meg x 64), 512mb (64 meg x 64), 1gb (128 meg x 64) v dd = v dd q = +2.5v v ddspd = +2.3v to +3.6v 2.5v i/o (sstl_2 compatible) commands entered on each positive ck edge dqs edge-aligned with data for reads; centeraligned with data for writes internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle bidirectional data strobe (dqs) transmitted/ received with data?i.e., source-synchronous data capture differential clock inputs (ck and ck#) four internal device banks for concurrent operation programmable burst lengths: 2, 4, or 8 auto precharge option auto refresh and self refresh modes 15.6s (256mb), 7.8125s (512mb and 1gb ) maximum average periodic refresh interval serial presence detect (spd) with eeprom programmable read cas latency gold edge contacts figure 1: 184-pin dimm (mo-206) note: 1. consult micron for availability of lead-free products. 2. cl = cas (read) latency options marking package 184-pin dimm (standard) g 184-pin dimm (lead-free) 1 y memory clock, speed, cas latency 2 6ns/166mhz (333 mt/s) cl = 2.5 -335 7.5ns/133 mhz (266 mt/s) cl = 2 -262 7.5ns/133 mhz (266 mt/s) cl = 2 -26a 7.5ns/133 mhz (266 mt/s) cl = 2.5 -265 10ns/100 mhz (200 mt/s) cl = 2 -202 pcb 1.25in. (31.75mm) see page 2 note 1.25in. (31.75mm) table 1: address table 256mb 512mb 1gb refresh count 4k 8k 8k row addressing 4k (a0?a11) 8k (a0?a12) 8k (a0?a12) device bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) device configuration 16 meg x 8 32 meg x 8 64 meg x 8 column addressing 1k (a0?a9) 1k (a0?a9) 2k (a0?a9, a11) module rank addressing 2 (s0#, s1#) 2 (s0#, s1#) 2 (s0#, s1#)
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 2 ?2003 micron technology, inc. table 2: part numbers and timing parameters part number module density configuration module bandwidth memory clock/ data rate latency (cl - t rcd - t rp) mt16vddt3264ag-335__ 256mb 32 meg x 64 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt16vddt3264ay-335__ 256mb 32 meg x 64 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt16vddt3264ag-262__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt16vddt3264ay-262__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt16vddt3264ag-26a__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt16vddt3264ay-26a__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt16vddt3264ag-265__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt16vddt3264ay-265__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt16vddt3264ag-202__ 256mb 32 meg x 64 1.6 gb/s 10ns/200 mt/s 2-2-2 mt16vddt3264ay-202__ 256mb 32 meg x 64 1.6 gb/s 10ns/200 mt/s 2-2-2 mt16vddt6464ag-335__ 512mb 64 meg x 64 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt16vddt6464ay-335__ 512mb 64 meg x 64 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt16vddt6464ag-262__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt16vddt6464ay-262__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt16vddt6464ag-26a__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt16vddt6464ay-26a__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt16vddt6464ag-265__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt16vddt6464ay-265__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt16vddt6464ag-202__ 512mb 64 meg x 64 1.6 gb/s 10ns/200 mt/s 2-2-2 mt16vddt6464ay-202__ 512mb 64 meg x 64 1.6 gb/s 10ns/200 mt/s 2-2-2 mt16vddt12864ag-335__ 1gb 128 meg x 64 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt16vddt12864ay-335__ 1gb 128 meg x 64 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt16vddt12864ag-262__ 1gb 128 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt16vddt12864ay-262__ 1gb 128 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt16vddt12864ag-26a__ 1gb 128 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt16vddt12864ay-26a__ 1gb 128 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt16vddt12864ag-265__ 1gb 128 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt16vddt12864ay-265__ 1gb 128 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt16vddt12864ag-202__ 1gb 128 meg x 64 1.6 gb/s 10ns/200 mt/s 2-2-2 mt16vddt12864ay-202__ 1gb 128 meg x 64 1.6 gb/s 10ns/200 mt/s 2-2-2 note: all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt16vddt6464ag-265a1 .
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 3 ?2003 micron technology, inc. note: pin 115 is no connect for 256mb modules, or a12 for 512mb and 1gb modules. figure 2: pin locations: 184-pin dimm ta bl e 3 : pin assignment (184-pin dimm front ) pin symbol pin symbol pin symbol pin symbol 1v ref 24 dq17 47 dnu 70 v dd 2dq0 25 dqs2 48 a0 71 nc 3v ss 26 v ss 49 dnu 72 dq48 4dq1 27 a9 50 v ss 73 dq49 5dqs0 28 dq18 51 dnu 74 v ss 6dq2 29 a7 52 ba1 75 ck2# 7v dd 30 v ddq 53 dq32 76 ck2 8dq331dq19 54 v ddq 77 v ddq 9nc 32 a5 55 dq33 78 dqs6 10 nc 33 dq24 56 dqs4 79 dq50 11 v ss 34 v ss 57 dq34 80 dq51 12 dq8 35 dq25 58 v ss 81 v ss 13 dq9 36 dqs3 59 ba0 82 nc 14 dqs1 37 a4 60 dq35 83 dq56 15 v ddq 38 v dd 61 dq40 84 dq57 16 ck1 39 dq26 62 v ddq 85 v dd 17 ck1# 40 dq27 63 we# 86 dqs7 18 v ss 41 a2 64 dq41 87 dq58 19 dq10 42 v ss 65 cas# 88 dq59 20 dq11 43 a1 66 v ss 89 v ss 21 cke0 44 dnu 67 dqs5 90 nc 22 v ddq 45 dnu 68 dq42 91 sda 23 dq16 46 v dd 69 dq43 92 scl table 4: pin assignment (184-pin dimm back) pin symbol pin symbol pin symbol pin symbol 93 v ss 116 v ss 139 v ss 162 dq47 94 dq4 117 dq21 140 dnu 163 nc 95 dq5 118 a11 141 a10 164 v ddq 96 v ddq 119 dqs11/dm2 142 dnu 165 dq52 97 dqs9/dm0 120 v dd 143 v ddq 166 dq53 98 dq6 121 dq22 144 dnu 167 nc 99 dq7 122 a8 145 v ss 168 v dd 100 v ss 123 dq23 146 dq36 169 dqs15/dm6 101 nc 124 v ss 147 dq37 170 dq54 102 nc 125 a6 148 v dd 171 dq55 103 nc 126 dq28 149 dqs13/dm4 172 v ddq 104 v ddq 127 dq29 150 dq38 173 nc 105 dq12 128 v ddq 151 dq39 174 dq60 106 dq13 129 dqs12/dm3 152 v ss 175 dq61 107 dqs10/dm1 130 a3 153 dq44 176 v ss 108 v dd 131 dq30 154 ras# 177 dqs16/dm7 109 dq14 132 v ss 155 dq45 178 dq62 110 dq15 133 dq31 156 v ddq 179 dq63 111 cke1 134 dnu 157 s0# 180 v ddq 112 v ddq 135 dnu 158 s1# 181 sa0 113 nc 136 v ddq 159 dqs14/dm5 182 sa1 114 dq20 137 ck0 160 v ss 183 sa2 115 nc/ a12 138 ck0# 161 dq46 184 v ddspd pin 93 pin 144 pin 145 pin 184 pin 1 pin 52 pin 53 pin 92 indicates a v dd or v ddq pin indicates a v ss pin front view back view -202, -265, 26a, -262 speed grades -202, -265, 26a, -262 speed grades u1 u2 u3 u4 u5 u6 u7 u8 u20 u17 u16 u15 u14 u13 u12 u11 u10 pin 93 pin 144 pin 145 pin 184 pin 1 pin 52 pin 53 pin 92 indicates a v dd or v ddq pin indicates a v ss pin front view back view -335 speed grade -335 speed grade u1 u2 u3 u4 u6 u7 u8 u9 u19 u10 u11 u12 u13 u15 u16 u17 u18
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 4 ?2003 micron technology, inc. table 5: pin descriptions pin numbers may not correlate with symbols. refer to pin assignment tables on page 3 for more information pin numbers symbol type description 63, 65, 154 we#, cas#, ras# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 16, 17, 75, 76, 137, 138 ck0, ck0#, ck1, ck1#, ck2, ck2# input clock: ck, ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck,and negative edge of ck#. output data (dqs and dqs) is referenced to the crossings of ck and ck#. 21, 111 cke0, cke1 input clock enable: cke high activates and cke low deactivates the internal clock, input buffers and output drivers. taking cke low provides precharge power-down and self refresh operations (all device banks idle), or active power- down (row active in any device bank). cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be maintained high throughout read and write accesses. input buffers (excluding ck, ck# and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied and until cke is first brought high. after cke is brought high, it becomes an sstl_2 input only. 157, 158 s0#, s1# input chip selects: s# enables (registered low) and disables (registered high) the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. 52, 59 ba0, ba1 input bank address: ba0 and ba1 define to which device bank an active, read, write, or precharge command is being applied. 27, 29, 32, 37, 41, 43, 48, 115 (512mb, 1gb) , 118, 122, 125, 130, 141 a0-a11 (256mb) a0-a12 (512mb, 1gb) input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is loaded during the load mode register command. 5, 14, 25, 36, 56, 67, 78, 86 dqs0-dqs7 input/ output data strobe: output with read data, input with write data. dqs is edge-aligned with read data, centered in write data. used to capture data. 97, 107, 119, 129, 149, 159, 169, 177 dqs9/ dm0? dqs16/ dm7 input data write mask: dqs9-dqs16 function as dm0-dm7. dm low allows write operation. dm high blocks write operation. dm lines do not affect read operation.
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 5 ?2003 micron technology, inc. 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 dq0-dq63 input/ output data i/os: data bus. 92 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 181,182, 183 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 91 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence- detect device. 1v ref input sstl_2 reference voltage. 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 v ddq supply dq power supply: +2.5v 0.2v. 7, 38, 46, 70, 85, 108, 120, 148, 168 v dd supply power supply: +2.5v 0.2v. 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss supply ground. 184 v ddspd supply serial eeprom positive power supply: +2.3v to +3.6v. 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 dnu ? do not use: these pins are not connected on these modules, but are assigned pins on other modules in this product family. 9, 10, 71, 82, 90, 101, 102, 103, 113, 115 (256mb), 163, 167, 173 nc ? no connect: these pins should be left unconnected. table 5: pin descriptions (continued) pin numbers may not correlate with symbols. refer to pin assignment tables on page 3 for more information pin numbers symbol type description
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 6 ?2003 micron technology, inc. figure 3: functional block diagram -262, -26a, -265, and -202 speed grades a0 sa0 serial pd u20 sda a1 sa1 a2 sa2 ba0, ba1 a0-a11 (256mb) a0-a12 (512mb, 1gb) ras# ba0, ba1: ddr sdrams a0-a11: ddr sdrams a0-a12: ddr sdrmas ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams u1, u3, u6, u8, u11, u13, u14, u16 cke1: ddr sdrams u2, u4, u5, u7, u10, u12, u15, u17 we#: ddr sdrams cas# cke0 cke1 we# v ref v ss ddr sdrams ddr sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u6 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u14 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u13 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u11 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs9/dm0 s0# u3 wp scl u10 dq dq dq dq dq dq dq dq u2 u12 u5 dq dq dq dq dq dq dq dq s1# dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dqs13/dm4 dqs4 dqs10/dm1 dqs1 dqs14/dm5 dqs5 u15 dm cs# dqs dqs11/dm2 dqs2 dqs15/dm6 dqs6 dm cs# dqs dm cs# dqs u16 u7 dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs12/dm3 dqs3 dqs16/dm7 dqs7 u4 dm cs# dqs u17 dm cs# dqs v ddq v dd ddr sdrams ddr sdrams ddr sdram x 4 ck0 ck0# 120 ddr sdram x 6 ck1 ck1# 120 ddr sdram x 6 ck2 ck2# 120 v ddspd spd dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq 3pf note: 1. all resistor values are 22 unless otherwise specified. 2. per industry standard, micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide . mt46v16m8tg = ddr sdram, 256mb module mt46v32m8tg = ddr sdram, 512mb module mt46v64m8tg = ddr sdram, 1gb module
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 7 ?2003 micron technology, inc. figure 4: functional block diagram -335 speed grade a0 sa0 serial pd u19 sda a1 sa1 a2 sa2 ba0, ba1 a0-a11 (256mb) a0-a12 (512mb, 1gb) ras# ba0, ba1: ddr sdrams a0-a11: ddr sdrams a0-a12: ddr sdrmas ras#: ddr sdrams cas#: ddr sdrams we#: ddr sdrams cke0: ddr sdrams u1, u3, u6, u8, u11, u13, u14, u16 cke1: ddr sdrams u2, u4, u5, u7, u10, u12, u15, u17 cas# we# cke1 cke0 v ref v ss ddr sdrams ddr sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u6 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u13 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u14 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u16 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs9/dm0 s0# u3 wp scl u17 dq dq dq dq dq dq dq dq u2 u15 u5 dq dq dq dq dq dq dq dq s1# dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dqs13/dm4 dqs4 dqs10/dm1 dqs1 dqs14/dm5 dqs5 u12 dm cs# dqs dqs11/dm2 dqs2 dqs15/dm6 dqs6 dm cs# dqs dm cs# dqs u11 u7 dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs12/dm3 dqs3 dqs16/dm7 dqs7 u4 dm cs# dqs u10 dm cs# dqs v ddq v dd ddr sdrams ddr sdrams ddr sdram x 4 ck0 ck0# 120 ddr sdram x 6 ck1 ck1# 120 ddr sdram x 6 ck2 ck2# 120 v ddspd spd dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq 3pf 3 3 3 3 3 3 note: 1. all resistor values are 22 unless otherwise specified. 2. per industry standard, micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide . ddr sdram = mt46v16m8tg, 256mb module ddr sdram = mt46v32m8tg, 512mb module ddr sdram = mt46v64m8tg, 1gb module
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 8 ?2003 micron technology, inc. general description the mt16vddt3264a, mt16vddt6464a, and mt16vddt12864a are high-speed cmos, dynamic random-access, 256mb, 512mb and 1gb memory modules organized in x64 configuration. ddr sdram modules use internally configured quad-bank ddr sdram devices. ddr sdram modules use a double data rate archi- tecture to achieve high-speed operation. double data rate architecture is essentially a 2 n -prefetch architec- ture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram module effectively consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two corre- sponding n -bit wide, one-half-clock-cycle data trans- fers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is an intermittent strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr sdram modules operate from differential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and out- put data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to ddr sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select devices bank; a0?a11 select device row for 256mb; a0?a12 select device row for 512mb, 1gb). the address bits registered coincident with the read or write command are used to select the device bank and the starting device column loca- tion for the burst access. ddr sdram modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr sdram modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are com- patible with the jedec standard for sstl_2. all out- puts are sstl_2, class ii compatible. for more information regarding ddr sdram operation, refer to the 128mb, 256mb and 512mb ddr sdram compo- nent data sheets. serial presence-detect operation ddr sdram modules incorporate serial presence- detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be pro- grammed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresses. write protect (wp) is tied to ground on the module, permanently disabling hard- ware write protect. mode register definition the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in figure 5, mode register definition diagram, on page 9. the mode register is programmed via the mode reg- ister set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is pro- grammed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed cor- rectly. the mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. vio- lating either of these requirements will result in unspecified operation. mode register bits a0?a2 specify the burst length, a3 specifies the type of burst (sequential or inter- leaved), a4?a6 specify the cas latency, and a7?a11 (256mb) or a7?a12 (512mb, 1gb) specify the operat- ing mode.
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 9 ?2003 micron technology, inc. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 6, burst definition table, on page 10. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being program- mable, as shown in figure 5, mode register definition diagram. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1?a i when the burst length is set to two, by a2-a i when the burst length is set to four and by a3- a i when the burst length is set to eight (where a i is the most significant column address bit for a given config- uration; see note 5, of table 6, burst definition table, on page 10). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. read latency the read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 2 or 2.5 clocks, as shown in figure 6, cas latency diagram. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . figure 7, cas latency (cl) table, indicates the operating fre- quencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 5: mode register definition diagram m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * m14 and m13 (ba1 and ba0) must be ?0, 0? to select the base mode register (vs. the extended mode register). m9 m10 m12 m11 burst length cas latency bt 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 operating mode a10 a11 ba0 ba1 10 11 12 13 * m13 and m12 (ba1and ba0) must be ?0, 0? to select the base mode register (vs. the extended mode register). 256mb module 512mb and 1gb modules
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 10 ?2003 micron technology, inc. note: 1. for a burst length of two, a1?a i select the two-data- element block; a0 selects the first access within the block. 2. for a burst length of four, a2?a i select the four-data- element block; a0?a1 select the first access within the block. 3. for a burst length of eight, a3?a i select the eight-data- element block; a0?a2 select the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 for 256mb and 512mb modules; i = 9, 11 for 1gb modules. figure 6: cas latency diagram operating mode the normal operating mode is selected by issuing a mode register set command with bits a7?a11 (256mb), or a7?a12 (512mb, 1gb) each set to zero, and bits a0?a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9?a11 (256mb), or a7 and a9?a12 (512mb, 1gb) each set to zero, bit a8 set to one, and bits a0?a6 set to the desired values. although not required by the micron device, jedec specifications recommend when a load mode register com- mand is issued to reset the dll, it should always be followed by a load mode register command to select normal operating mode. all other combinations of values for a7?a11 (256mb), or a7?a12 (512mb, 1gb) are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable and out- put drive strength. these functions are controlled via the bits shown in figure 7, extended mode register definition diagram. the extended mode register is table 6: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 table 7: cas latency (cl) table allowable operating clock frequency (mhz) speed cl = 2 cl = 2.5 -335 75 f 133 75 f 167 -262 75 f 133 75 f 133 -26a 75 f 133 75 f 133 -265 75 f 100 75 f 133 -202 75 f 100 n/a ck ck# command dq dqs cl = 2 read nop nop nop read nop nop nop burst length = 4 in the cases shown shown with nominal t ac, t dqsck, and t dqsq ck ck# command dq dqs cl = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don?t care transitioning data
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 11 ?2003 micron technology, inc. programmed via the load mode register com- mand to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is pro- grammed again or the device loses power. the enabling of the dll should always be followed by a load mode register command to the mode regis- ter (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements could result in unspecified oper- ation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debug or evalua- tion. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. figure 7: extende d mode register definition diagram note: 1. ba1 and ba0 (e13 and e12 for 256mb, e14 and e13 for 512mb, 1gb) must be ?0, 1? to select the extended mode register (vs. the base mode register). 2. the qfc# option is not supported. operating mode reserved reserved 0 ? 0 ? valid ? 0 1 dll enable disable dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 e0 e1 2 0 e0 e1, operating mode a10 a11 a12 ba1 ba0 10 11 12 13 14 e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 0 ? e12 ds dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 operating mode a10 a11 ba1 ba0 10 11 12 13 ds 256mb module 512mb and 1gb modules 0 ? e2 2 drive strength normal
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 12 ?2003 micron technology, inc. commands figure 8, commands truth table, and figure 9, dm operation truth table, provide a general reference of available commands. for a more detailed description of commands and operations, refer to the 128mb, 256mb, or 512mb ddr sdram component data sheets. note: 1. deselect and nop are functionally interchangeable. 2. ba0?ba1 provide device bank address and a0?a11 (256mb) or a0?a12 (512mb, 1gb) provide row address. 3. ba0?ba1 provide device bank address; a0?a9 (256mb, 512mb ) or a0?a9, a11(1gb), provide column address; a10 high enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 4. applies only to read bursts with auto precharge disabled; th is command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 5. a10 low: ba0?ba1 determine which device bank is precha rged. a10 high: all device banks are precharged and ba0? ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. ba0?ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other combinat ions of ba0?ba1 are reserved). a0?a11 (256mb) or a0?a12 (512mb, 1gb) provide the op-code to be written to the selected mode register. table 8: commands truth table cke is high for all commands shown except self refresh name (function) cs# ras# cas# we# addr notes deselect (nop) hxxx x 1 no operation (nop) l hhh x 1 active (select bank and activate row) l l h h bank/row 2 read (select bank and column, and start read burst) l h l h bank/col 3 write (select bank and column, and start write burst) l h l l bank/col 3 burst terminate lhhl x 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) lllh x 6, 7 load mode register l l l l op-code 8 table 9: dm operation truth table used to mask write data; provided coincident with the corresponding data name (function) dm dqs write enable l valid write inhibit hx
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 13 ?2003 micron technology, inc. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd supply relative to vss . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on v dd q supply relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on v ref and inputs relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on i/o pins relative to v ss . . . . . . . . . . . . -0.5v to vddq +0.5v operating temperature t a (ambient) . . . . . . . . . . . . . . . . . . . . .. 0c to +70c storage temperature (plastic) . . . . . . -55c to +150c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 16w short circuit output current. . . . . . . . . . . . . . . 50ma table 10: dc electrical characteristics and operating conditions notes: 1?5, 14, 48; notes appear on pages 21?24; 0c t a +70c parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v 32, 36 i/o supply voltage v dd q 2.3 2.7 v 32, 36, 39 i/o reference voltage v ref 0.49 v dd q0.51 v dd q v6, 39 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 7, 39 input high (logic 1) voltage v ih ( dc )v ref + 0.15 v dd + 0.3 v 25 input low (logic 0) voltage v il ( dc )-0.3v ref - 0.15 v 25 input leakage current any input 0v vin vdd, vref pin 0v vin 1.35v (all other pins not under test = 0v) command/ address, ras#, cas#, we# i i -32 32 a 47 cke, s# -16 16 ck0, ck0# -8 8 ck1, ck1# ck2, ck2# -12 12 dm -4 4 output leakage current (dqs are disabled; 0v vout vddq) dq, dqs i oz -10 10 a 47 output levels high current (v out = v dd q-0.373v, minimum v ref , minimum v tt ) low current (v out = 0.373v, maximum v ref , maximum v tt ) i oh -16.8 ? ma 33, 34 i ol 16.8 ? ma table 11: ac input operating conditions notes: 1?5, 14, 48; notes appear on pages 21?24; 0c t a +70c; v dd = v dd q = +2.5v 0.2v parameter/condition symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref + 0.310 ? v 12, 25, 35 input low (logic 0) voltage v il ( ac )?v ref - 0.310 v 12, 25, 35 i/o reference voltage v ref ( ac ) 0.49 v dd q0.51 v dd q v6
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 14 ?2003 micron technology, inc. ta bl e 1 2 : i dd specifications and co nditions ? 256mb module ddr sdram components only notes: 1?5, 8, 10, 14, 48; notes appear on pages 21?24; 0c t a +70c; v dd = v dd q = +2.5v 0.2v max parameter/condition sym -335 -262 -26a/ -265/- 202 units notes operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd0 a 1,024 904 864 ma 20, 42 operating current: one device bank; active -read precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 1,104 984 984 ma 20, 42 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2n b 24 24 24 ma 21, 28, 44 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 360 360 320 ma 45 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 200 200 160 ma 21, 28, 44 active standby current: cs# = hi gh; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm anddqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 400 400 360 ma 40 operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs chan-ging once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 1,144 1,064 1,024 ma 20, 42 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 1,144 1,024 984 ma 20 auto refresh current t rc = t refc(min) i dd5 b 2,120 1,760 1,760 ma 20, 24, 44 t refc = 15.625s i dd5a b 40 40 40 ma 20, 24, 44 self refresh current: cke 0.2v i dd6 b 24 24 16 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read, or write commands i dd7 a 2,864 2,664 2,624 ma 20, 43 note: a: value calculated as one module rank in this operating condition, and all other module ranks in i dd 2p (cke low) mode. b: value calculated reflects all module ranks in this operating condition.
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 15 ?2003 micron technology, inc. ta bl e 1 3 : i dd specifications and co nditions ? 512mb module ddr sdram components only notes: 1?5, 8, 10, 14, 48; notes appear on pages 21?24; 0c t a +70c; v dd = v dd q = +2.5v 0.2v max parameter/condition sym -335 -262 -26a/ -265 -202 units notes operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd0 a 1,032 1,032 872 992 ma 20, 42 operating current: one device bank; active -read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); iout = 0ma; address and control inputs changing once per clock cycle i dd1 a 1,392 1,312 1,192 1,272 ma 20, 42 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 64 64 64 64 ma 21, 28, 44 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. vin = vref for dq, dqs, and dm i dd2f b 800 720 720 720 ma 45 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 480 400 400 480 ma 21, 28, 44 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm anddqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 960 800 800 800 ma 40 operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); iout = 0ma i dd4r a 1,432 1,232 1,232 1,432 ma 20, 42 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 1,272 1,112 1,112 1,552 ma 20 auto refresh current t rc = t refc(min) i dd5 b 4,080 3,760 3,760 3,920 ma 20, 44 t refc = 7.8125s i dd5a b 96 96 96 96 ma 20, 44 self refresh current: cke 0.2v i dd6 b 64 64 64 64 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read, or write commands i dd7 a 3,272 2,832 2,832 2,952 ma 20, 43 note: a: value calculated as one module rank in this operating condition, and all other module ranks in i dd 2p (cke low) mode. b: value calculated reflects all module ranks in this operating condition.
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 16 ?2003 micron technology, inc. ta bl e 1 4 : i dd specifications and conditions ? 1gb module ddr sdram components only notes: 1?5, 8, 10, 14, 48; notes appear on pages 21?24; 0c t a +70c; v dd = v dd q = +2.5v 0.2v max parameter/condition sym -335 -262 -26a/ -265/ -202 units notes operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd0 a 1,080 1,080 960 ma 20, 42 operating current: one device bank; active -read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 1,320 1,320 1,200 ma 20, 42 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 80 80 80 ma 21, 28, 44 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 720 720 640 ma 45 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 560 560 480 ma 21, 28, 44 active standby current: cs# = hi gh; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm anddqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 720 720 640 ma 40 operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 1,360 1,360 1,200 ma 20, 42 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 1,280 1,280 1,120 ma 20 auto refresh current t rc = t refc (min) i dd5 b 4,640 4,640 4,480 ma 20, 44 t refc = 7.8125s i dd5a b 160 160 160 ma 20, 44 self refresh current: cke 0.2v i dd6 b 80 80 80 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read, or write commands i dd7 a 3,280 3,240 2,840 ma 20, 43 note: a: value calculated as one module rank in this operating condition, and all other module ranks in i dd 2p (cke low) mode. b: value calculated reflects all module ranks in this operating condition.
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 17 ?2003 micron technology, inc. table 15: capacitance (all modules) note: 11; notes appear on pages 21?24 parameter symbol min max units input/output capacitance: dq, dqs, dm c io 8.0 10.0 pf input capacitance: command and address c i 1 32.0 48.0 pf input capacitance: s#, cke c i 1 16.0 24.0 pf input capacitance: ck0, ck0# c i 2 11.0 15.0 pf input capacitance: ck1, ck1#; ck2, ck2# c i 3 12.0 18.0 pf input capacitance: sda c i 4 ?8.0 pf input capacitance: scl, sa0, sa2 c i 5 ?6.0 pf table 16: ddr sdram component electrical characteristics and recommended ac operating conditions (-335, -262) notes: 1?5, 13-15, 29, 48; notes appear on pages 21?24; 0c t a +70c; v dd = v dd q = +2.5v 0.2v ac characteristics -335 -262 units notes parameter symbol min max min max access window of dqs from ck/ck# t ac -0.7 +0.7 -0.75 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl=2.5 t ck (2.5) 6 13 7.5 13 ns 41, 46 cl=2 t ck (2) 7.5 13 7.5/10 13 ns 41, 46 dq and dm input hold time relative to dqs t dh 0.45 0.5 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.45 0.5 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 ns 27 access window of dqs from ck/ck# t dqsck -0.60 +0.60 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.45 0.5 ns 22, 23 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl ns 31 data-out high-impedance window from ck/ck# t hz +0.70 +0.75 ns 16, 37 data-out low-impedance window from ck/ck# t lz -0.70 -0.75 ns 16, 38 address and control input hold time (fast slew rate) t ih f 0.75 0.90 ns 12 address and control input setup time (fast slew rate) t is f 0.75 0.90 ns 12 address and control input hold time (slow slew rate) t ih s 0.80 1 ns 12 address and control input setup time (slow slew rate) t is s 0.80 1 ns 12 address and control input pulse width (for each input) t ipw 2.2 2.2 ns load mode register command cycle time t mrd 12 15 ns
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 18 ?2003 micron technology, inc. dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.55 0.75 ns active to precharge command t ras 42 70,000 40 120,000 ns 31 active to read with auto precharge command t rap 18 15 ns active to active/auto refresh command period t rc 60 60 ns auto refresh command period t rfc 72 75 ns 44 active to read or write delay t rcd 18 15 ns precharge command period t rp 18 15 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 37 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 12 15 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 ns 18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 ns internal write to read command delay t wtr 11 t ck data valid output window na t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command interval 256mb t refc 140.6 140.6 s 21 512mb, 1gb 70.3 70.3 s 21 average periodic refresh interval 256mb t refi 15.6 15.6 s 21 512mb, 1gb 7.8 7.8 s 21 terminating voltage delay to v dd t vtd 00ns exit self refresh to non-read command t xsnr 75 75 ns exit self refresh to read command t xsrd 200 200 t ck table 16: ddr sdram component electrical characteristics and recommended ac operating conditions (-335, -262) (continued) notes: 1?5, 13-15, 29, 48; notes appear on pages 21?24; 0c t a +70c; v dd = v dd q = +2.5v 0.2v ac characteristics -335 -262 units notes parameter symbol min max min max
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 19 ?2003 micron technology, inc. table 17: ddr sdram component electrical characteristics and recommended ac operating conditions (-26a, -265, -202) notes: 1?5, 13-15, 29, 48; notes appear on pages 21?24; 0c t a +70c; v dd = v dd q = +2.5v 0.2v ac characteristics -26a/-265 -202 units notes parameter symbol min max min max access window of dqs from ck/ck# t ac -0.75 +0.75 -0.8 +0.8 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl=2.5 t ck (2.5) 7.5 13 8 13 ns 41, 46 cl=2 t ck (2) 7.5/10 13 10 13 ns 41, 46 dq and dm input hold time relative to dqs t dh 0.5 0.6 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.5 0.6 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 2 ns 27 access window of dqs from ck/ck# t dqsck -0.75 +0.75 -0.8 +0.8 ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.5 0.6 ns 22, 23 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl ns 31 data-out high-impedance window from ck/ck# t hz +0.75 +0.8 ns 16, 37 data-out low-impedance window from ck/ck# t lz -0.75 -0.8 ns 16, 38 address and control input hold time (fast slew rate) t ih f .90 1.1 ns 12 address and control input setup time (fast slew rate) t is f .90 1.1 ns 12 address and control input hold time (slow slew rate) t ih s 11.1ns12 address and control input setup time (slow slew rate) t is s 11.1ns12 address and control input pulse width (for each input) t ipw 2.2 2.2 ns load mode register command cycle time t mrd 15 16 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.75 1 ns active to precharge command t ras 40 120,000 40 120,000 ns 31 active to read with auto precharge command t rap 20 20 ns active to active/auto refresh command period t rc 65 70 ns auto refresh command period t rfc 75 80 ns 44 active to read or write delay t rcd 20 20 ns precharge command period t rp 20 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 37 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 20 ?2003 micron technology, inc. active bank a to active bank b command t rrd 15 15 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 ns 18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 ns internal write to read command delay t wtr 11 t ck data valid output window na t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command interval 256mb t refc 140.6 140.6 s 21 512mb, 1gb 70.3 70.3 s 21 average periodic refresh interval 256mb t refi 15.6 15.6 s 21 512mb, 1gb 7.8 7.8 s 21 terminating voltage delay to v dd t vtd 00ns exit self refresh to non-read command t xsnr 75 80 ns exit self refresh to read command t xsrd 200 200 t ck table 17: ddr sdram component electrical characteristics and recommended ac operating conditio ns (-26a, -265, -202) (continued) notes: 1?5, 13-15, 29, 48; notes appear on pages 21?24; 0c t a +70c; v dd = v dd q = +2.5v 0.2v ac characteristics -26a/-265 -202 units notes parameter symbol min max min max
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 21 ?2003 micron technology, inc. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci- fications are guaranteed for the specified ac input levels under normal use conditions. the mini- mum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v dd q/2 of the transmit- ting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd q/2, vref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time at cl = 2 for -262, -26a, and -202, cl = 2.5 for -335 and -265 with the outputs open. 9. enables on-chip refresh and address counters. 10. i dd specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. this parameter is sampled. v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v, v ref = v ss , f = 100 mhz, t a = 25c, v out (dc) = v dd q/2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 12. for slew rates less than 1 v/ns and greater than or equal to 0.5 v/ns. if slew rate is less than 0.5 v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from 500mv/ns, while t ih is unaffected. if slew rate exceeds 4.5v/ns, functionality is uncertain. 13. the ck/ck# input reference level (for timing ref- erenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabi- lizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd q is recognized as low. 15. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 16. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the intent of the don?t care state after completion of the postamble is the dqs-driven signal should either be high, low, or high-z and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high [above v ihdc (min)] then it must not transition low (below v ihdc ) prior to t dqsh(min). 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low ) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 20. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measurements is the largest multi- ple of t ck that meets the maximum absolute value for t ras. output (v out ) reference point 50 ? v tt 30pf
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 22 ?2003 micron technology, inc. 21. the refresh period 64ms. this equates to an aver- age refresh rate of 15.625s (256mb) or 7.8125s (512mb, 1gb). however, an auto refresh com- mand must be asserted at least once every 140.6s (256mb) or 70.3s (512mb, 1gb); burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the valid data window is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle varia- tion of 45/55, beyond which functionality is uncertain. figure 8, derating data valid window, shows derating curves for duty cycles ranging between 50/50 and 45/55. 23. each byte lane has a corresponding dqs. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b. reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc). 26. jedec specifies ck and ck# input slew rate must be 1v/ns (2v/ns differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/ dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncer- tain. 28. v dd must not vary more than 4 percent if cke is not active while any bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 30. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively during bank active. figure 8: derating data valid window 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 3.400 3.350 3.300 3.250 3.200 3.150 3.100 3.050 3.000 2.950 2.900 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 clock duty cycle ns -26a/-265 @ t ck = 10ns -202 @ t ck = 10ns -26a/-265 @ t ck = 7.5ns -202 @ t ck = 8ns -335 @ t ck = 6ns na
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 23 ?2003 micron technology, inc. 31. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis- fied prior to the internal precharge command being issued. 32. any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mv or 2.9v, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either 300mv or 2.2v, whichever is more positive. however, the dc average cannot be below 2.3v minimum. 33. normal output drive curves: a. the full variation in driver pull-down current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the v-i curve of figure 9, pull-down characteristics. b. the variation in driver pull-down current within nominal limits of voltage and tempera- ture is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 9, pull-down characteristics. c. the full variation in driver pull-up current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the v-i curve of figure 10, pull-up characteristics. d. the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 10, pull-up characteristics. e. the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 volt, and at the same voltage and temperature. f. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source volt- ages from 0.1v to 1.0v. 34. the voltage levels used are derived from a mini- mum vdd level and the referenced test load. in practice, the voltage levels obtained from a prop- erly terminated bus will provide significantly dif- ferent voltage values. 35. v ih overshoot: v ih (max) = v dd q + 1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. vil undershoot: v il (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. v dd and v dd q must track each other. 37. this maximum value is derived from the refer- enced test load. in practice, the values obtained in a typical terminated design may reflect up to 310ps less for t hz (max) and the last dvw. thz (max) will prevail over t dqsck(max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 38. for slew rates greater than 1v/ns the (lz) transi- tion will start about 310ps earlier. 39. during initialization, v dd q, v tt , and v ref must be equal to or less than vdd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v dd q are 0v, provided a minimum of 42 of series resistance is used between the v tt supply and the input pin. figure 9: pull-down characteristics figure 10: pull-up characteristics
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 24 ?2003 micron technology, inc. 40. for -335, -262, -26a and -265 speed grades, i dd 3n is specified to be 35ma per ddr sdram at 100 mhz. 41. the current micron part operates below the slow- est jedec operating frequency of 83 mhz. as such, future die may not reflect this option. 42. random addressing changing and 50 percent of data changing at every transfer. 43. random addressing changing and 100 percent of data changing at every transfer. 44. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. 45. i dd 2n specifies the dq, dqs, and dm to be driven to a valid high or low logic level. i dd 2q is similar to i dd 2f except i dd 2q specifies the address and control inputs to remain stable. although i dd 2f, i dd 2n, and i dd 2q are similar, i dd 2f is ?worst case.? 46. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 47. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. when an input signal is high or low, it is defined as a steady state logic high or logic low.
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 25 ?2003 micron technology, inc. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (as shown in figure 11, data validity, and figure 12, defi- nition of start and stop). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (as shown in fig- ure 13, acknowledge response from receiver). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 11: data validity figure 12: definition of start and stop figure 13: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 26 ?2003 micron technology, inc. figure 14: spd eeprom timing diagram table 18: eeprom device select code the most significant bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 sa2 sa1 sa0 rw protection register select code 0 1 1 0 sa2 sa1 sa0 rw table 19: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1? random address read 0v ih or v il 1 start, device select, rw = ?0?, address 1v ih or v il 1 restart, device select, rw = ?1? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0? page write 0v il 16 start, device select, rw = ?0? scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 27 ?2003 micron technology, inc. note: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop conditi on of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. table 20: serial presence-detect eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v ddspd 2.3 3.6 v input high voltage: logic 1; all inputs v ih v dd 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd +0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = v ss or v dd i sb ?30a power supply current: scl clock frequency = 100 khz i cc ?2ma table 21: serial presence-detect eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f 300 ns 2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time constant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock frequency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 28 ?2003 micron technology, inc. table 22: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes appear on page 30 byte description entry (version) mt16vddt3264a mt16vddt6464a mt16vddt12864a 0 number of spd bytes used by micron 128 80 80 80 1 total number of bytes in spd device 256 08 08 08 2 fundamental memory type sdram ddr 07 07 07 3 number of row addresses on assembly 12, 13 0c 0d 0d 4 number of column addresses on assembly 10, 11 0a 0a 0b 5 number of physical ranks on dimm 20222 6 module data width 64 40 40 40 7 module data width (continued) 0000000 8 module voltage interface levels sstl 2.5v 04 04 04 9 sdram cycle time, ( t ck) (cas latency = 2.5) (see note 1) 6ns (-335) 7ns (-262/-26a) 7.5ns (-265) 8ns (-202) 60 70 75 80 60 70 75 80 60 70 75 80 10 sdram access from clock,( t ac) (cas latency = 2.5) 0.7ns (-335) 0.75ns (-262/-26a/-265) 0.8ns (-202) 70 75 80 70 75 80 70 75 80 11 module configuration type none 00 00 00 12 refresh rate/type 15.62s, 7.8s/self 80 82 82 13 sdram device width (primary ddr sdram) 8080808 14 error-checking ddr sdram data width none 00 00 00 15 minimum clock delay, back-to-back random column access 1 clock 01 01 01 16 burst lengths supported 2, 4, 8 0e 0e 0e 17 number of banks on ddr sdram device 4040404 18 cas latencies supported 2, 2.5 0c 0c 0c 19 cs latency 0010101 20 we latency 1020202 21 sdram module attributes unbuffered/diff. clock 20 20 20 22 sdram device attributes: general fast/concurrent ap c0 c0 c0 23 sdram cycle time, ( t ck) (cas latency = 2) 7.5ns (-335/-262/-26a) 10ns (-265/-202) 75 a0 75 a0 75 a0 24 sdram access from ck , ( t ac) (cas latency = 2) 0.7ns (-335) 0.75ns (-262/-26a/-265) 0.8ns (-202) 70 75 80 70 75 80 70 75 80 25 sdram cycle time, ( t ck) (cas latency = 1.5) n/a 00 00 00 26 sdram access from ck , ( t ac) (cas latency = 1.5) n/a 00 00 00 27 minimum row precharge time, ( t rp) 18ns (-335) 15ns (-262) 20ns (-26a/-265/-202) 48 3c 50 48 3c 50 48 3c 50 28 minimum row active to row active, ( t rrd) 12ns (-335) 15ns (-262/-26a/-265/-202) 30 3c 30 3c 30 3c
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 29 ?2003 micron technology, inc. 29 minimum ras# to cas# delay, ( t rcd) 18ns (-335) 15ns (-262) 20ns (-26a/-265/-202) 48 3c 50 48 3c 50 48 3c 50 30 minimum ras# pulse width, ( t ras), (see note 2) 42ns (-335) 45ns (-262/-26a/-265) 40ns (-202) 2a 2d 28 2a 2d 28 2a 2d 28 31 module rank density 128mb, 256mb, 512mb 20 40 80 32 address and command setup time, ( t is), (see note 4) 0.8ns (-335) 1.0ns (-262-26a/-265) 1.1ns (-202) 80 a0 b0 80 a0 b0 80 a0 b0 33 address and command hold time, ( t ih), (see note 4) 0.8ns (-335) 1.0ns (-262/-26a/-265) 1.1ns (-202) 80 a0 b0 80 a0 b0 80 a0 b0 34 data/data mask input setup time, ( t ds) 0.45ns (-335) 0.5ns (-262/-26a/-265) 0.6ns (-202) 45 50 60 45 50 60 45 50 60 35 data/data mask input hold time, ( t dh) 0.45ns (-335) 0.5ns (-262/-26a/-265) 0.6ns (-202) 45 50 60 45 50 60 45 50 60 36-40 reserved 00 00 00 41 min active auto refresh time ( t rc) 60ns (-335/-262) 65ns (-26a/-265) 70ns (-202) 3c 41 46 3c 41 46 3c 41 46 42 minimum auto refresh to active/ auto refresh command period, ( t rfc) 72ns (-335) 75ns (-262/-26a/-265) 80ns (-202) 48 4b 50 48 4b 50 48 4b 50 43 sdram device max cycle time ( t ck max ) 12ns (-335) 13ns (-262/-26a/-265/-202) 30 34 30 34 30 34 44 sdram device max dqs-dq skew time ( t dqsq) 0.45ns (-335) 0.5ns (-262/-26a/-265) 0.6ns (-202) 2d 32 3c 2d 32 3c 2d 32 3c 45 sdram device max read data hold skew factor ( t qhs) 0.55ns (-335) 0.75ns (-262/-26a/-265) 1.0ns (-202) 55 75 a0 55 75 a0 55 75 a0 46-61 reserved 00 00 00 47 dimm height standard 01 01 01 46-61 reserved 00 00 00 62 spd revision release 1.0 10 10 10 63 checksum for bytes 0-62 -335 -262 -26a -265 -202 05 98 c5 f5 90 28 bb e8 18 b3 69 fc 29 59 f4 64 manufacturer?s jedec id code micron 2c 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff ff 72 manufacturing location 01?12 01?0c 01?0c 01?0c 73-90 module part number (ascii) variable data variable data variable data table 22: serial presence-detect matrix (continued) ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes appear on page 30 byte description entry (version) mt16vddt3264a mt16vddt6464a mt16vddt12864a
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 30 ?2003 micron technology, inc. note: 1. value for -26a t ck set to 7ns (0x70) for optimum bios compatibility. actual device spec. value is 7.5ns. 2. the value of t ras used for -26a/-265 modul es is calculated from t rc - t rp. actual device spec. value is 40 ns. 3. the jedec spd specification allows fast or slow slew rate va lues for these bytes. the worst-case (slow slew rate) value is represented here. systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met. 91 pcb identification code 1-9 01-09 01-09 01-09 92 identification code (continued) 0000000 93 year of manufacture in bcd variable data variable data variable data 94 week of manufacture in bcd variable data variable data variable data 95-98 module serial number variable data variable data variable data 99-127 manufacturer-specific data (rsvd) ?? ? table 22: serial presence-detect matrix (continued) ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes appear on page 30 byte description entry (version) mt16vddt3264a mt16vddt6464a mt16vddt12864a
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 31 ?2003 micron technology, inc. figure 15: standard 184- pin ddr dimm dimensions, -202, -265, -26a, and -262 speed grades note: all dimensions are in inches (millimeters); or typical where noted. 1.256 (31.9) 1.244 (31.6) pin 1 0.700 (17.78) typ. 0.098 (2.50) d (2x) 0.091 (2.30) typ. 0.250 (6.35) typ. 4.750 (120.65) 0.050 (1.27) typ. 0.091 (2.30) typ. 0.040 (1.02) typ. 0.079 (2.00) r (4x) pin 92 front view back view 0.054 (1.37) 0.046 (1.17) 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) pin 184 pin 93 0.150 (3.80) 0.150 (3.80) typ. 0.394 (10.00) typ. 0.157 (4.00) max 0.035 (0.90) r u17 u16 u15 u14 u13 u12 u11 u10 u1 u2 u3 u4 u5 u6 u7 u8 u20 max min
256mb, 512mb, 1gb (x64) 184-pin ddr sdram dimm 09005aef807397e5 micron technology, inc., reserves the right to change products or specifications without notice.. dd16c32_64_128x64ag_b.fm - rev. a 8/03 en 32 ?2003 micron technology, inc ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 16: standard 184- pin ddr dimm dimensions, -335 speed grade note: all dimensions are in inches (millimeters); or typical where noted. data sheet designation released (no mark): this data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifica- tions are subject to change, as further product devel- opment and data characterization sometimes occur. 1.256 (31.9) 1.244 (31.6) pin 1 0.700 (17.78) typ. 0.098 (2.50) d (2x) 0.091 (2.30) typ. 0.250 (6.35) typ. 4.750 (120.65) 0.050 (1.27) typ. 0.091 (2.30) typ. 0.040 (1.02) typ. 0.079 (2.00) r (4x) pin 92 front view back view 0.054 (1.37) 0.046 (1.17) 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) pin 184 pin 93 0.150 (3.80) 0.150 (3.80) typ. 0.394 (10.00) typ. 0.157 (4.00) max 0.035 (0.90) r u10 u11 u12 u13 u15 u16 u17 u18 u1 u2 u3 u4 u6 u7 u8 u9 u19 max min

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