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1. general description the pca8565a is a cmos 1 real-time clock (rtc) and calendar optimized for low power consumption. a programmable clock output, interrupt output, and voltage-low detector are also provided. all addresses and data are transferred serially via a two-line bidirectional i 2 c-bus. maximum bus speed is 400 kbit/s. the built-in word address register is incremented automatically after each written or read data byte. aec-q100 compliant for automotive applications. 2. features n provides year, month, day, weekday, hours, minutes, and seconds based on 32.768 khz quartz crystal n clock operating voltage: 1.8 v to 5.5 v n extended operating temperature range: - 40 c to +125 c n low backup current: typical 0.65 m a at v dd = 3.0 v and t amb =25 c n 400 khz two-line i 2 c-bus interface (at v dd = 1.8 v to 5.5 v) n programmable clock output for peripheral devices (32.768 khz, 1.024 khz, 32 hz, and 1 hz) n alarm and timer functions n two integrated oscillator capacitors n internal power-on reset (por) n i 2 c-bus slave address: read a3h; write a2h n open-drain interrupt pin n century ?ag 3. applications n automotive n industrial n applications that require a wide operating temperature range pca8565a real-time clock/calendar rev. 02 4 december 2009 product data sheet 1. the de?nition of the abbreviations and acronyms used in this data sheet can be found in section 18 .
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 2 of 38 nxp semiconductors pca8565a real-time clock/calendar 4. ordering information [1] not to be used for new designs. 5. marking table 1. ordering information type number package name description delivery form version die type 1 [1] pca8565au/5ba/1 pca8565au wire bond die; 9 bonding pads unsawn wafer; thickness 280 m m pca8565au die type 2 pca8565au/5bb/1 pca8565au wire bond die; 9 bonding pads unsawn wafer; thickness 280 m m pca8565au table 2. marking codes type number marking code pca8565au/5ba/1 pc8565a-1 pca8565au/5bb/1 pc8565a-1
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 3 of 38 nxp semiconductors pca8565a real-time clock/calendar 6. block diagram fig 1. block diagram of pca8565a 001aah662 oscillator 32.768 khz divider clock out interrupt clkout int monitor power on reset watch dog i 2 c-bus interface osci scl sda osco v dd v ss timer function timer_control 0e timer 0f control control_status_1 00 control_status_2 01 clkout_control 0d time vl_seconds 02 minutes 03 hours 04 days 05 alarm function minute_alarm 09 hour_alarm 0a day_alarm 0b weekday_alarm 0c weekdays 06 century_months 07 years 08 pca8565a clkoe c osci c osco
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 4 of 38 nxp semiconductors pca8565a real-time clock/calendar 7. pinning information 7.1 pinning 7.2 pin description [1] the substrate (rear side of the die) is wired to v ss but should not be electrically contacted. viewed from active side. for mechanical details, see figure 22 . fig 2. pin con?guration for pca8565a 1 2 3 4 5 6 7 8 9 x y pca8565a 013aaa216 osci osco int sda clkout v dd clkoe scl v ss 0,0 table 3. pin description symbol pin description osci 1 oscillator input osco 2 oscillator output int 3 interrupt output (open-drain; active low) v ss 4 ground supply voltage [1] sda 5 serial data input and output scl 6 serial clock input clkout 7 clock output (open-drain) v dd 8 supply voltage clkoe 9 clkout output enable input
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 5 of 38 nxp semiconductors pca8565a real-time clock/calendar 8. functional description the pca8565a contains 16 8-bit registers with an auto-incrementing address register, an on-chip 32.768 khz oscillator with two integrated capacitors, a frequency divider which provides the source clock for the rtc, a programmable clock output, a timer, an alarm, a voltage low detector, and a 400 khz i 2 c-bus interface. all 16 registers (see t ab le 4 ) are designed as addressable 8-bit parallel registers although not all bits are implemented. the ?rst two registers (memory address 00h and 01h) are used as control and/or status registers. the memory addresses 02h through 08h are used as counters for the clock function (seconds up to years counters). address locations 09h through 0ch contain alarm registers which de?ne the conditions for an alarm. address 0dh controls the clkout output frequency. 0eh and 0fh are the timer control and timer registers, respectively. the seconds, minutes, hours, days, weekdays, months, years, as well as the minute alarm, hour alarm, day alarm, and weekday alarm registers are all in binary coded decimal (bcd) format. when one of the rtc registers is read, the contents of all time counters are frozen. therefore, faulty reading of the clock and calendar during a carry condition is prevented. 8.1 clkout output a programmable square wave is available at the clkout pin. frequencies of 32.768 khz, 1.024 khz, 32 hz and 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. clkout is an open-drain output, and if disabled it becomes high-impedance.
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 6 of 38 nxp semiconductors pca8565a real-time clock/calendar 8.2 register organization table 4. register overview bit positions labelled as - are not implemented. bit positions labelled as n should always be written with logic 0. after reset, all registers are set according to t ab le 29 . address register name bit 7 6 5 4 3 2 1 0 control registers 00h control_status_1 test1 n stop n testc n n n 01h control_status_2 n n n ti_tp af tf aie tie time and date registers 02h vl_seconds vl seconds (0 to 59) 03h minutes - minutes (0 to 59) 04h hours - - hours (0 to 23) 05h days - - days (1 to 31) 06h weekdays - ---- weekdays (0 to 6) 07h century_months c - - month (1 to 12) 08h years years (0 to 99) alarm registers 09h minute_alarm ae_m minute_alarm (0 to 59) 0ah hour_alarm ae_h - hour_alarm (0 to 23) 0bh day_alarm ae_d - day_alarm (1 to 31) 0ch weekday_alarm ae_w ---- weekday_alarm (0 to 6) clkout control register 0dh clkout_control - -----fd timer registers 0eh timer_control te -----td 0fh timer timer
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 7 of 38 nxp semiconductors pca8565a real-time clock/calendar 8.3 control registers 8.3.1 register control_status_1 [1] default value. [2] bits labeled as n should always be written with logic 0. 8.3.2 register control_status_2 [1] bits labeled as n should always be written with logic 0. [2] default value. table 5. control_status_1 - control and status register 1 (address 00h) bit description bit symbol value description reference 7 test1 0 [1] normal mode; must be set logic 0 during normal operations section 8.9 1 ext_clk test mode 6n 0 [2] default value 5stop0 [1] rtc clock runs section 8.10 1 rtc clock is stopped; all rtc divider chain ?ip-?ops are asynchronously set logic 0; the rtc clock is stopped (clkout at 32.768 khz is still available); i 2 c-bus watchdog doesnt work 4n 0 [2] default value 3 testc 0 power-on reset (por) override facility is disabled; set logic 0 for normal operation section 8.11.1 1 [1] power-on reset (por) override is enabled 2 to 0 n 000 [2] default value table 6. control_status_2 - control and status register 2 (address 01h) bit description bit symbol value description reference 7 to 5 n 000 [1] default value 4 ti_tp 0 [2] int active when tf or af is active (subject to the status of tie and aie) section 8.3.2.1 and section 8.8 1 int pulses active according to t ab le 9 (subject to the status of tie); remark: if af and aie are active then int will be permanently active 3af 0 [2] read: alarm ?ag inactive section 8.3.2.1 write: alarm ?ag is cleared 1 read: alarm ?ag active write: alarm ?ag remains unchanged 2tf 0 [2] read: timer ?ag inactive section 8.3.2.1 write: timer ?ag is cleared 1 read: timer ?ag active write: timer ?ag remains unchanged 1 aie 0 [2] alarm interrupt disabled section 8.3.2.1 1 alarm interrupt enabled 0 tie 0 [2] timer interrupt disabled section 8.3.2.1 1 timer interrupt enabled
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 8 of 38 nxp semiconductors pca8565a real-time clock/calendar 8.3.2.1 interrupt output bits tf and af: when an alarm occurs, af is set logic 1. similarly, at the end of a timer countdown, tf is set logic 1. these bits maintain their value until overwritten using the interface. if both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. to prevent one ?ag being overwritten while clearing another, logic and is performed during a write access. a ?ag is cleared by writing logic 0 whilst a ?ag is not cleared by writing logic 1. writing logic 1 will result in the ?ag value remaining unchanged. the following two tables are showing an example for clearing bit af, but leaving bit tf unaffected. the ?ag is cleared by a write command, therefore bits 7 to 4 and 1 to 0 must be written with their previous values. repeatedly re-writing these bits has no in?uence on the functional behavior. t ab le 8 shows what instruction must be sent to clear bit af. in this example, bit tf is unaffected. bits tie and aie: these bits activate or deactivate the generation of an interrupt when tf or af is asserted, respectively. the interrupt is the logical or of these two conditions when both aie and tie are set. table 7. af and tf ?ag location in register control_status_2 register bit 7 6 5 4 3 2 1 0 control_status_2 ----aftf-- table 8. example to clear only af (bit 3) in register control_status_2 register bit 7 6 5 4 3 2 1 0 control_status_2 ----01-- when bits tie and aie are disabled, pin int will remain high-impedance. fig 3. interrupt scheme 013aaa087 te countdown counter af: alarm flag clear set to interface: read af 0 1 tf: timer clear set pulse generator 2 clear trigger tie int from interface: clear tf from interface: clear af set alarm flag af to interface: read tf ti_tp aie e.g. aie 0 1
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 9 of 38 nxp semiconductors pca8565a real-time clock/calendar countdown timer interrupts: the pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value n. as a consequence, the width of the interrupt pulse varies (see t ab le 9 ). [1] tf and int become active simultaneously. [2] n = loaded countdown value. timer stops when n = 0. table 9. int operation (bit ti_tp = 1) [1] source clock (hz) int period (s) n=1 [2] n>1 [2] 4096 1 8192 1 4096 64 1 128 1 64 1 1 64 1 64 1 60 1 64 1 64
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 10 of 38 nxp semiconductors pca8565a real-time clock/calendar 8.4 time and date registers the majority of the registers are coded in the bcd format to simplify application use. 8.4.1 register vl_seconds [1] start-up value. 8.4.1.1 voltage-low detector and clock monitor the pca8565a has an on-chip voltage-low detector (see figure 4 ). when v dd drops below v low , bit vl in the vl_seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. the vl ?ag can only be cleared by using the interface. table 10. vl_seconds - seconds and clock integrity status register (address 02h) bit description bit symbol value place value description 7 vl 0 - clock integrity is guaranteed 1 [1] - integrity of the clock information is not guaranteed 6 to 4 seconds 0 to 5 tens place actual seconds coded in bcd format, see t ab le 11 3 to 0 0 to 9 unit place table 11. seconds coded in bcd format seconds value in decimal upper-digit (tens place) digit (unit place) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 0000000 01 0000001 02 0000010 : ::::::: 09 0001001 10 0010000 : ::::::: 58 1011000 59 1011001 fig 4. voltage-low detection vl set normal power operation period of battery operation t v dd v low mgr887
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 11 of 38 nxp semiconductors pca8565a real-time clock/calendar the vl ?ag is intended to detect the situation when v dd is decreasing slowly, for example under battery operation. should the oscillator stop or v dd reach v low before power is re-asserted, then the vl ?ag is set. this will indicate that the time may be corrupted. 8.4.2 register minutes 8.4.3 register hours 8.4.4 register days [1] the pca8565a compensates for leap years by adding a 29th day to february if the year counter contains a value which is exactly divisible by 4, including the year 00. 8.4.5 register weekdays table 12. minutes - minutes register (address 03h) bit description bit symbol value place value description 7 - - - unused 6 to 4 minutes 0 to 5 tens place actual minutes coded in bcd format 3 to 0 0 to 9 unit place table 13. hours - hours register (address 04h) bit description bit symbol value place value description 7 to 6 - - - unused 5 to 4 hours 0 to 2 tens place actual hours coded in bcd format 3 to 0 0 to 9 unit place table 14. days - days register (address 05h) bit description bit symbol value place value description 7 to 6 - - - unused 5to4 days [1] 0 to 3 tens place actual day coded in bcd format 3 to 0 0 to 9 unit place table 15. weekdays - weekdays register (address 06h) bit description bit symbol value description 7 to 3 - - unused 2 to 0 weekdays 0 to 6 actual weekday values, see t ab le 16 .
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 12 of 38 nxp semiconductors pca8565a real-time clock/calendar [1] de?nition may be re-assigned by the user. 8.4.6 register century_months [1] this bit may be re-assigned by the user. [2] this bit is toggled when the register years over?ows from 99 to 00. table 16. weekday assignments day [1] bit 2 1 0 sunday 0 0 0 monday 0 0 1 tuesday 0 1 0 wednesday 0 1 1 thursday 1 0 0 friday 1 0 1 saturday 1 1 0 table 17. century_months - century ?ag and months register (address 07h) bit description bit symbol value place value description 7c [1] 0 [2] - indicates the century is x 1 - indicates the century i sx+1 6 to 5 - - - unused 4 months 0 to 1 tens place actual month coded in bcd format, see t ab le 18 3 to 0 0 to 9 unit place table 18. month assignments in bcd format month upper-digit (tens place) digit (unit place) bit 4 bit 3 bit 2 bit 1 bit 0 january 0 0 0 0 1 february 0 0 0 1 0 march 0 0 0 1 1 april 0 0 1 0 0 may00101 june00110 july00111 august 0 1 0 0 0 september 0 1 0 0 1 october 1 0 0 0 0 november 1 0 0 0 1 december 1 0 0 1 0
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 13 of 38 nxp semiconductors pca8565a real-time clock/calendar 8.4.7 register years 8.5 setting and reading the time figure 5 shows the data ?ow and data dependencies starting from the 1 hz clock tick. during read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. this prevents ? faulty reading of the clock and calendar during a carry condition ? incrementing the time registers, during the read cycle after this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read access is serviced. a maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see figure 6 ). as a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. failing to comply with this method could result in the time becoming corrupted. table 19. years - years register (08h) bit description bit symbol value place value description 7 to 4 years 0 to 9 tens place actual year coded in bcd format 3 to 0 0 to 9 unit place fig 5. data ?ow for the time function 013aaa092 1 hz tick weekday seconds minutes hours days leap year calculation months years c
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 14 of 38 nxp semiconductors pca8565a real-time clock/calendar as an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. a similar problem exists when reading. a roll over may occur between reads thus giving the minutes from one moment and the hours from the next. recommended method for reading the time: 1. send a start condition and the slave address for write (a2h). 2. set the address pointer to 2 (vl_seconds) by sending 02h. 3. send a restart condition or stop followed by start. 4. send the slave address for read (a3h). 5. read vl_seconds. 6. read minutes. 7. read hours. 8. read days. 9. read weekdays. 10. read century_months. 11. read years. 12. send a stop condition. fig 6. access time for read/write operations t < 1 s 013aaa215 slave address data stop data start
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 15 of 38 nxp semiconductors pca8565a real-time clock/calendar 8.6 alarm registers 8.6.1 register minute_alarm [1] default value. 8.6.2 register hour_alarm [1] default value. 8.6.3 register day_alarm [1] default value. 8.6.4 register weekday_alarm [1] default value. table 20. minute_alarm - minute alarm register (address 09h) bit description bit symbol value place value description 7 ae_m 0 - minute alarm is enabled 1 [1] - minute alarm is disabled 6 to 4 minute_alarm 0 to 5 tens place minute alarm information coded in bcd format 3 to 0 0 to 9 unit place table 21. hour_alarm - hour alarm register (address 0ah) bit description bit symbol value place value description 7 ae_h 0 - hour alarm is enabled 1 [1] - hour alarm is disabled 6 - - - unused 5 to 4 hour_alarm 0 to 2 tens place hour alarm information coded in bcd format 3 to 0 0 to 9 unit place table 22. day_alarm - day alarm register (address 0bh) bit description bit symbol value place value description 7 ae_d 0 - day alarm is enabled 1 [1] - day alarm is disabled 6 - - - unused 5 to 4 day_alarm 0 to 3 tens place day alarm information coded in bcd format 3 to 0 0 to 9 unit place table 23. weekday_alarm - weekday alarm register (address 0ch) bit description bit symbol value description 7 ae_w 0 weekday alarm is enabled 1 [1] weekday alarm is disabled 6 to 3 - - unused 2 to 0 weekday_alarm 0 to 6 weekday alarm information coded in bcd format
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 16 of 38 nxp semiconductors pca8565a real-time clock/calendar 8.6.5 alarm ?ag by clearing the msb of one or more of the alarm registers, ae_x (alarm enable), the corresponding alarm condition(s) are active. when an alarm occurs, af is set logic 1. the asserted af can be used to generate an interrupt ( int). the af is cleared by using the interface. the registers at addresses 09h through 0ch contain alarm information. when one or more of these registers is loaded with minute, hour, day or weekday, and its corresponding alarm enable bit (ae_x) is logic 0, then that information is compared with the current minute, hour, day, and weekday. when all enabled comparisons ?rst match, the alarm flag (af in register control_status_2) is set logic 1. the generation of interrupts from the alarm function is controlled via bit aie. if bit aie is enabled, the int pin follows the condition of bit af. af will remain set until cleared by using the interface. once af has been cleared, it will only be set again when the time increments to match the alarm condition once more. alarm registers which have their ae_x bit at logic 1 are ignored. 8.7 register clkout_control and clock output frequencies of 32.768 khz (default), 1.024 khz, 32 hz, and 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. to enable pin clkout pin clkoe must be set high. when disabled, clkout is high-impedance. (1) only when all enabled alarm settings are matching. its only on increment to a matched case that the alarm ?ag is set, see section 8.6.5 . fig 7. alarm function block diagram 013aaa088 weekday alarm ae_w weekday time = day alarm ae_d day time = hour alarm ae_h hour time = minute alarm ae_m minute time = check now signal set alarm flag af (1) ae_m = 1 1 0 example
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 17 of 38 nxp semiconductors pca8565a real-time clock/calendar [1] default value. 8.8 timer function the 8-bit countdown timer at address 0fh is controlled by the timer control register at address 0eh. the timer control register determines one of 4 source clock frequencies for the timer (4.096 khz, 64 hz, 1 hz, or 1 60 hz) and enables or disables the timer. the timer counts down from a software-loaded 8-bit binary value. at the end of every countdown, the timer sets the timer flag (tf) in the register control_status_2. the tf may only be cleared by software. the asserted tf can be used to generate an interrupt (on pin int). the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the state of tf. bit ti_tp is used to control this mode selection. when reading the timer, the current countdown value is returned. 8.8.1 register timer_control [1] default value. [2] these bits determine the source clock for the countdown timer; when not in use, td[1:0] should be set to 1 60 hz for power saving. 8.8.2 register timer table 24. clkout_control - clkout control register (address 0dh) bit description bit symbol value description 7 to 2 - - unused 1 to 0 fd[1:0] frequency output at pin clkout 00 [1] 32.768 khz 01 1.024 khz 10 32 hz 11 1 hz table 25. timer_control - timer control register (address 0eh) bit description bit symbol value description 7te 0 [1] timer is disabled 1 timer is enabled 6 to 2 - - unused 1 to 0 td[1:0] timer source clock frequency select [2] 00 4.096 khz 01 64 hz 10 1 hz 11 [2] 1 60 hz table 26. timer - timer register (address 0fh) bit description bit symbol value description 7 to 0 timer[7:0] 00h to ffh countdown period in seconds: where n is the countdown value countdownperiod n sourceclockfrequency -------------------------------------------------------------- - =
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 18 of 38 nxp semiconductors pca8565a real-time clock/calendar the timer register is an 8-bit binary countdown timer. it is enabled or disabled via the timer_control register. the source clock for the timer is also selected by the timer_control register. other timer properties such as single or periodic interrupt generation are controlled via the register control_status_2 (address 01h). for accurate read back of the count down value, it is recommended to read the register twice and check for consistent results, since it is not possible to freeze the countdown timer counter during read back. 8.9 ext_clk test mode a test mode is available which allows for on-board testing. in such a mode it is possible to set up test conditions and control the operation of the rtc. the test mode is entered by setting bit test1 in register control_status_1. then pin clkout becomes an input. the test mode replaces the internal 64 hz signal with the signal applied to pin clkout. every 64 positive edges applied to pin clkout will then generate an increment of one second. the signal applied to pin clkout should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. the internal 64 hz clock, now sourced from clkout, is divided down to 1 hz by a 2 6 divide chain called a prescaler. the prescaler can be set into a known state by using the bit stop. when the stop bit is set, the prescaler is reset to logic 0 (stop must be cleared before the prescaler can operate again). from a stop condition, the ?rst 1 second increment will take place after 32 positive edges on pin clkout. thereafter, every 64 positive edges will cause a one-second increment. remark: entry into ext_clk test mode is not synchronized to the internal 64 hz clock. when entering the test mode, no assumption as to the state of the prescaler can be made. operation example: 1. set ext_clk test mode (control_status_1, bit test1 = 1). 2. set bit stop (control_status_1, bit stop = 1). 3. clear bit stop (control_status_1, bit stop = 0). 4. set time registers to desired value. 5. apply 32 clock pulses to pin clkout. 6. read time registers to see the ?rst change. 7. apply 64 clock pulses to pin clkout. 8. read time registers to see the second change. repeat steps 7 and 8 for additional increments. table 27. timer register bits value range bit 7 6 5 4 3 2 1 0 128 64 32 16 8 4 2 1
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 19 of 38 nxp semiconductors pca8565a real-time clock/calendar 8.10 stop bit function the function of the stop bit is to allow for accurate starting of the time circuits. the stop bit function will cause the upper part of the prescaler (f 2 to f 14 ) to be held in reset and thus no 1 hz ticks will be generated (see figure 8 ). the time circuits can then be set and will not increment until the stop bit is released (see figure 9 and t ab le 28 ). the stop bit function will not affect the output of 32.768 khz on clkout, but will stop the generation of 1.024 khz, 32 hz, and 1 hz. the lower two stages of the prescaler (f 0 and f 1 ) are not reset; and because the i 2 c-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between zero and one 8.192 khz cycle (see figure 9 ). fig 8. stop bit functional diagram 013aaa089 oscillator 32768 hz 16384 hz oscillator stop detector f 0 f 1 f 13 reset f 14 reset f 2 reset 2 hz 1024 hz 32 hz 1 hz tick stop clkout source reset 8192 hz 4096 hz 32768 hz 1 hz fig 9. stop bit release timing 001aaf912 8192 hz stop released 0 m s to 122 m s
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 20 of 38 nxp semiconductors pca8565a real-time clock/calendar [1] f 0 is clocked at 32.768 khz. the ?rst increment of the time circuits is between 0.507813 s and 0.507935 s after stop bit is released. the uncertainty is caused by the prescaler bits f 0 and f 1 not being reset (see t ab le 28 ) and the unknown state of the 32 khz clock. 8.11 reset the pca8565a includes an internal reset circuit which is active whenever the oscillator is stopped. in the reset state the i 2 c-bus logic is initialized including the address pointer and all registers are set according to t ab le 29 . i 2 c-bus communication is not possible during reset. table 28. first increment of time circuits after stop bit release bit prescaler bits [1] 1 hz tick time comment stop f 0 f 1 -f 2 to f 14 hh:mm:ss clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally stop bit is activated by user. f 0 f 1 are not reset and values cannot be predicted externally 1 xx-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen new time is set by user 1 xx-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen stop bit is released by user 0 xx-0 0000 0000 0000 08:00:00 prescaler is now running xx-1 0000 0000 0000 08:00:00 - xx-0 1000 0000 0000 08:00:00 - xx-1 1000 0000 0000 08:00:00 - : :: 11-1 1111 1111 1110 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of f 14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : :: 11-1 1111 1111 1111 08:00:01 - 00-0 0000 0000 0000 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : :- 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of f 14 increments the time circuits 013aaa076 0.507813 to 0.507935 s 1.000000 s
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 21 of 38 nxp semiconductors pca8565a real-time clock/calendar [1] registers marked x are unde?ned at power-up and unchanged by subsequent resets. 8.11.1 power-on reset (por) override the por duration is directly related to the crystal oscillator start-up time. due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the por and hence speed up on-board test of the device. the setting of this mode requires that the i 2 c-bus pins, sda and scl, be toggled in a speci?c order as shown in figure 10 . all timings are required minimums. once the override mode has been entered, the device immediately stops, being reset, and normal operation may commence, i.e., entry into the ext_clk test mode via i 2 c-bus access. the override mode may be cleared by writing logic 0 to testc. testc must be set logic 1 before re-entry into the override mode is possible. setting testc logic 0 during normal operation has no effect, except to prevent entry into the por override mode. table 29. register reset values [1] address register name bit 7 6 5 4 3 2 1 0 00h control_status_1 0 0 0 0 1 0 0 0 01h control_status_2 0 0 0 0 0 0 0 0 02h vl_seconds 1 x x x x x x x 03h minutes x x x x x x x x 04h hours x x x x x x x x 05h days xxxxxxxx 06h weekdays x x x x x x x x 07h century_months x x x x x x x x 08h years x x x x x x x x 09h minute_alarm 1 x x x x x x x 0ah hour_alarm 1 x x x x x x x 0bh day_alarm 1 x x x x x x x 0ch weekday_alarm 1 x x x x x x x 0dh clkout_control x x x x x x 0 0 0eh timer_control 0 x x x x x 1 1 0fh timer x x x x x x x x fig 10. por override sequence mgm664 scl 500 ns 2000 ns sda 8 ms override active power-on
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 22 of 38 nxp semiconductors pca8565a real-time clock/calendar 9. characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal (see figure 11 ). 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is de?ned as the start condition (s). a low-to-high transition of the data line, while the clock is high, is de?ned as the stop condition (p); see figure 12 . 9.3 system con?guration a device generating a message is a transmitter; a device receiving a message is a receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves (see figure 13 ). fig 11. bit transfer mbc621 data line stable; data valid change of data allowed sda scl fig 12. de?nition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 23 of 38 nxp semiconductors pca8565a real-time clock/calendar 9.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is shown in figure 14 . fig 13. system con?guration mba605 master transmitter receiver slave receiver slave transmitter receiver master transmitter master transmitter receiver sda scl fig 14. acknowledgement on the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 24 of 38 nxp semiconductors pca8565a real-time clock/calendar 9.5 i 2 c-bus protocol 9.5.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed ?rst. the addressing is always carried out with the ?rst byte transmitted after the start procedure. the pca8565a acts as a slave receiver or slave transmitter. therefore, the clock signal scl is only an input signal, but the data signal sda is a bidirectional line. two slave addresses are reserved for the pca8565a: read: a3h (10100011) write: a2h (10100010) the pca8565a slave address is shown in figure 15 . 9.5.2 clock and calendar read or write cycles the i 2 c-bus con?guration for the different pca8565a read and write cycles is shown in figure 16 , figure 17 , and figure 18 . the word address is a 4-bit value that de?nes which register is to be accessed next. the upper four bits of the word address are not used. fig 15. slave address mce189 1 0 1 0 0 0 1 r/w group 1 group 2 fig 16. master transmits to slave receiver (write mode) s 0a slave address word address a a data p acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w auto increment memory word address mbd822 n bytes
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 25 of 38 nxp semiconductors pca8565a real-time clock/calendar 9.5.3 interface watchdog timer during read/write operations, the time counting circuits are frozen. to prevent a situation where the accessing device becomes locked and does not clear the interface, the pca8565a has a built in watchdog timer. should the interface be active for more than 1 s from the time a valid slave address is transmitted, then the pca8565a will automatically clear the interface and allow the time counting circuits to continue counting. the watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access. each time the watchdog period is exceeded, 1 s will be lost from the time counters. the watchdog will trigger between 1 s and 2 s after receiving a valid slave address. (1) at this moment master transmitter becomes master receiver and pca8565a slave receiver becomes slave transmitter. fig 17. master reads after setting word address (write word address; read data) s 0a slave address word address a a r/w a data 013aaa041 p 1 auto increment memory word address last byte r/w s1 n bytes (1) acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave no acknowledgement from master auto increment memory word address slave address data fig 18. master reads slave immediately after ?rst byte (read mode) s 1a slave address data a1 data acknowledgement from slave acknowledgement from master no acknowledgement from master r/w auto increment word address mgl665 auto increment word address n bytes last byte p
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 26 of 38 nxp semiconductors pca8565a real-time clock/calendar 10. internal circuitry fig 19. device diode protection 001aab724 sda 45 v ss scl 36 int clkout 2 7 osco clkoe 1 9 osci pca8565a v dd 8
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 27 of 38 nxp semiconductors pca8565a real-time clock/calendar 11. limiting values [1] pass level; human body model (hbm) according to ref . 4 jesd22-a114 . [2] pass level; machine model (mm), according to ref . 5 jesd22-a115 . [3] pass level; latch-up testing, according to ref . 7 jesd78 at maximum ambient temperature (t amb(max) = +125 c). [4] according to the nxp store and transport requirements (see ref . 9 nx3-00092 ) the devices have to be stored at a temperature of +8 cto+45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. table 30. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.5 v i dd supply current - 50 +50 ma i ss ground supply current - 50 +50 ma v i input voltage - 0.5 +6.5 v v o output voltage - 0.5 +6.5 v i i input current - 10 +10 ma i o output current - 10 +10 ma p tot total power dissipation - 300 mw v esd electrostatic discharge voltage hbm [1] die type 1 - 2000 v die type 2 - 3500 v mm [2] die type 1 - 200 v die type 2 - 250 v i lu latch-up current all pins but osci [3] - 100 ma t stg storage temperature [4] - 65 +150 c
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 28 of 38 nxp semiconductors pca8565a real-time clock/calendar 12. static characteristics table 31. static characteristics v dd = 1.8 v to 5.5 v; v ss =0v;t amb = - 40 c to +125 c; f osc = 32.768 khz; quartz r s =40k w ;c l = 8 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dd supply voltage i 2 c-bus active; f scl = 400 khz 1.8 - 5.5 v for clock data integrity v low - 5.5 v i dd supply current interface active; t amb = - 40 c to +125 c f scl = 400 khz - 100 250 m a f scl = 100 khz - 25 100 m a interface inactive (f scl = 0 hz); clkout = v dd [1] [2] t amb = 125 c v dd = 5.0 v - 1100 1800 na v dd = 3.0 v - 1000 1600 na v dd = 2.0 v - 950 1500 na t amb = 105 c v dd = 5.0 v - 850 1500 na v dd = 3.0 v - 775 1300 na v dd = 2.0 v - 750 1200 na t amb =85 c v dd = 5.0 v - 600 1200 na v dd = 3.0 v - 550 1000 na v dd = 2.0 v - 550 900 na t amb =25 c v dd = 5.0 v - 600 1200 na v dd = 3.0 v - 550 1000 na v dd = 2.0 v - 550 900 na t amb = - 40 c v dd = 5.0 v - 850 1500 na v dd = 3.0 v - 775 1300 na v dd = 2.0 v - 750 1200 na t amb = - 40 c to +85 c v dd = 1.8 v - 550 - na
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 29 of 38 nxp semiconductors pca8565a real-time clock/calendar [1] timer source clock = 1 60 hz, level of pins scl and sda is v dd or v ss . [2] worst case is at high temperature and high supply voltage. [3] tested on sample basis. i dd supply current interface inactive (f scl = 0 hz); clkout enabled at 32 khz [1] [2] t amb = 125 c v dd = 5.0 v - 1300 2500 na v dd = 3.0 v - 1100 1900 na v dd = 2.0 v - 1000 1700 na t amb = 105 c v dd = 5.0 v - 1100 2200 na v dd = 3.0 v - 900 1600 na v dd = 2.0 v - 800 1400 na t amb =85 c v dd = 5.0 v - 900 1900 na v dd = 3.0 v - 700 1300 na v dd = 2.0 v - 600 1100 na t amb =25 c v dd = 5.0 v - 900 1900 na v dd = 3.0 v - 700 1300 na v dd = 2.0 v - 600 1100 na t amb = - 40 c v dd = 5.0 v - 1100 2200 na v dd = 3.0 v - 900 1600 na v dd = 2.0 v - 800 1400 na inputs v il low-level input voltage v ss - 0.3 - 0.3v dd v v ih high-level input voltage pins scl, sda, clkoe, osci 0.7v dd -- v i li input leakage current pins scl, sda; v i =v dd or v ss - 10+1 m a c i input capacitance [3] --7pf outputs i ol low-level output current output sink current; v ol = 0.4 v; v dd =5v pin sda 3 - - ma pin int 1 - - ma pin clkout; v o =v dd or v ss 1-- ma i lo output leakage current - 10+1 m a voltage detector and temperature v low low voltage - 0.9 1.7 v t amb ambient temperature - 40 - +125 c table 31. static characteristics continued v dd = 1.8 v to 5.5 v; v ss =0v;t amb = - 40 c to +125 c; f osc = 32.768 khz; quartz r s =40k w ;c l = 8 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 30 of 38 nxp semiconductors pca8565a real-time clock/calendar 13. dynamic characteristics [1] integrated load capacitance, c l(itg) , is a calculation of c osci and c osco in series: . [2] unspeci?ed for f clkout = 32.768 khz. [3] all timing values are valid within the operating supply voltage range at ambient temperature and referenced to v il and v ih with an input voltage swing of v ss to v dd . [4] a detailed description of the i 2 c-bus speci?cation is given in ref . 10 um10204 . [5] i 2 c-bus access time between two starts or between a start and a stop condition to this device must be less than one second. table 32. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss =0v; t amb = - 40 c to + 125 c; f osc = 32.768 khz; quartz r s =40k w ; c l = 8 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit oscillator c l(itg) integrated load capacitance [1] 6810pf d f osc /f osc relative oscillator frequency variation d v dd = 200 mv; t amb =25 c - 0.2 - ppm clkout output d clkout duty cycle on pin clkout [2] -50- % timing characteristics: i 2 c-bus [3] [4] f scl scl clock frequency [5] - - 400 khz t hd;sta hold time (repeated) start condition 0.6 - - m s t su;sta set-up time for a repeated start condition 0.6 - - m s t low low period of the scl clock 1.3 - - m s t high high period of the scl clock 0.6 - - m s t r rise time of scl and sda signals - - 0.3 m s t f fall time of scl and sda signals - - 0.3 m s c b capacitive load for each bus line - - 400 pf t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - m s t w(spike) spike pulse width tolerable - - 50 ns c litg () c osci c osco () c osci c osco + () -------------------------------------------- =
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 31 of 38 nxp semiconductors pca8565a real-time clock/calendar 14. application information fig 20. i 2 c-bus timing waveforms sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat connect clkoe to an appropriate level. fig 21. application diagram 001aab725 scl sda v ss osci osco clock/calendar pca8565a sda scl master transmitter/ receiver v dd v dd sda scl rr v dd (i 2 c-bus) 1 f
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 32 of 38 nxp semiconductors pca8565a real-time clock/calendar 15. bare die outline fig 22. bare die outline references outline version european projection issue date iec jedec jeita pca8565au pca8565au_do 09-08-29 09-09-09 unit mm max nom min 0.28 1.26 1.05 0.22 0.9 0.1 0.1 0.09 a dimensions die type 2 note 1. chip dimensions including sawline. 2. marking code: pc8565a-1 wire bond die; 9 bonding pads pca8565au d (1) e (1) 1.89 ee 1 e 2 p 1 p 2 0.09 p 3 p 4 unit mm max nom min 0.28 1.27 1.05 0.22 0.9 0.1 0.1 0.09 a dimensions die type 1 d (1) e (1) 1.9 ee 1 e 2 p 1 p 2 0.09 p 3 p 4 0 0.5 1 mm scale a detail x p 2 p 1 p 4 p 3 e 2 e 1 e x (2) y 0,0 x d e
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 33 of 38 nxp semiconductors pca8565a real-time clock/calendar 16. handling information all input and output pins are protected against electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. table 33. pin description all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see figure 22 . symbol pad x y osci 1 - 523.0 m m 689.4 m m osco 2 - 523.0 m m 469.4 m m int 3 - 523.0 m m - 429.8 m m v ss 4 - 523.0 m m - 684.4 m m sda 5 524.9 m m - 523.8 m m scl 6 524.9 m m - 138.6 m m clkout 7 524.9 m m 162.5 m m v dd 8 524.9 m m 443.3 m m clkoe 9 524.9 m m 716.3 m m fig 23. alignment marks table 34. alignment mark description all x/y coordinates represent the position of the ref point (see figure 23 ) with respect to the center (x/y = 0) of the chip; see figure 22 . symbol size ( m m) x y c1 100 100 465.2 m m - 826.3 m m c2 100 100 - 523.5 m m 890.0 m m f90 117 - 569.9 m m - 885.5 m m ref ref c2 c1 f 013aaa036 ref
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 34 of 38 nxp semiconductors pca8565a real-time clock/calendar 17. packing information 17.1 wafer information bad die are inked out. fig 24. wafer layout x saw lane detail x marking code straight edge of the wafer 013aaa037 pin 1 18 m m die type 1 = 84 m m die type 2 = 74 m m die type 1 = 84 m m die type 2 = 74 m m seal ring plus gap to active circuit ~18 m m 18 m m
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 35 of 38 nxp semiconductors pca8565a real-time clock/calendar 18. abbreviations table 35. abbreviations acronym description aec automotive electronics council bcd binary coded decimal cmos complementary metal oxide semiconductor hbm human body model i 2 c inter-integrated circuit ic integrated circuit mm machine model mos metal oxide semiconductor msb most signi?cant bit por power-on reset rtc real time clock scl serial clock line sda serial data line
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 36 of 38 nxp semiconductors pca8565a real-time clock/calendar 19. references [1] an10706 handling bare die [2] iec 60134 rating systems for electronic tubes and valves and analogous semiconductor devices [3] iec 61340-5 protection of electronic devices from electrostatic phenomena [4] jesd22-a114 electrostatic discharge (esd) sensitivity testing human body model (hbm) [5] jesd22-a115 electrostatic discharge (esd) sensitivity testing machine model (mm) [6] jesd22-c101 field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components [7] jesd78 ic latch-up test [8] jesd625-a requirements for handling electrostatic-discharge-sensitive (esds) devices [9] nx3-00092 nxp store and transport requirements [10] um10204 i 2 c-bus speci?cation and user manual 20. revision history table 36. revision history document id release date data sheet status change notice supersedes pca8565a_2 20091204 product data sheet - pca8565a_1 modi?cations: ? added new product type pca8565au/5bb/1 pca8565a_1 20080222 product data sheet - -
pca8565a_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 37 of 38 nxp semiconductors pca8565a real-time clock/calendar 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 21.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 21.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. bare die all die are tested on compliance with their related technical speci?cations as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 21.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca8565a real-time clock/calendar ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 4 december 2009 document identifier: pca8565a_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 clkout output . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 register organization . . . . . . . . . . . . . . . . . . . . 6 8.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3.1 register control_status_1 . . . . . . . . . . . . . . . . 7 8.3.2 register control_status_2 . . . . . . . . . . . . . . . . 7 8.3.2.1 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.4 time and date registers . . . . . . . . . . . . . . . . . 10 8.4.1 register vl_seconds . . . . . . . . . . . . . . . . . . . 10 8.4.1.1 voltage-low detector and clock monitor . . . . . 10 8.4.2 register minutes. . . . . . . . . . . . . . . . . . . . . . . 11 8.4.3 register hours . . . . . . . . . . . . . . . . . . . . . . . . 11 8.4.4 register days . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.4.5 register weekdays. . . . . . . . . . . . . . . . . . . . . 11 8.4.6 register century_months. . . . . . . . . . . . . . . . 12 8.4.7 register years . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5 setting and reading the time. . . . . . . . . . . . . . 13 8.6 alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 15 8.6.1 register minute_alarm . . . . . . . . . . . . . . . . . . 15 8.6.2 register hour_alarm . . . . . . . . . . . . . . . . . . . 15 8.6.3 register day_alarm . . . . . . . . . . . . . . . . . . . . 15 8.6.4 register weekday_alarm . . . . . . . . . . . . . . . . 15 8.6.5 alarm ?ag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.7 register clkout_control and clock output . . 16 8.8 timer function . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.8.1 register timer_control . . . . . . . . . . . . . . . . . . 17 8.8.2 register timer . . . . . . . . . . . . . . . . . . . . . . . . 17 8.9 ext_clk test mode . . . . . . . . . . . . . . . . . . . . 18 8.10 stop bit function . . . . . . . . . . . . . . . . . . . . . . 19 8.11 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.11.1 power-on reset (por) override . . . . . . . . . . 21 9 characteristics of the i 2 c-bus. . . . . . . . . . . . . 22 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2 start and stop conditions . . . . . . . . . . . . . 22 9.3 system con?guration . . . . . . . . . . . . . . . . . . . 22 9.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.5 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 24 9.5.1 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.5.2 clock and calendar read or write cycles . 24 9.5.3 interface watchdog timer . . . . . . . . . . . . . . . . 25 10 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 26 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27 12 static characteristics . . . . . . . . . . . . . . . . . . . 28 13 dynamic characteristics . . . . . . . . . . . . . . . . . 30 14 application information . . . . . . . . . . . . . . . . . 31 15 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 32 16 handling information . . . . . . . . . . . . . . . . . . . 33 17 packing information . . . . . . . . . . . . . . . . . . . . 34 17.1 wafer information . . . . . . . . . . . . . . . . . . . . . . 34 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35 19 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 36 21 legal information . . . . . . . . . . . . . . . . . . . . . . 37 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 37 21.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 21.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37 22 contact information . . . . . . . . . . . . . . . . . . . . 37 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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