64mbit C high speed sdram data sheet 8mx8, 4mx16 hsdram enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.1 page 1 of 10 features jedec standard pc-133 sdram fast 4.6 ns cl3 clock access time fast 13.75 ns cl1 clock access time (-7.5f) low latency operation (3:2:2 @ 133 mhz) cas latency = 3 ras to cas delay = 2 precharge delay = 2 fast random access time (34.6 ns) fast random cycle time (52.5 ns) programmable burst length (1, 2, 4, 8, full page) programmable cas latency (1, 2, 3) low power suspend, self refresh, and power down modes supported 4k refresh / 64 ms single 3.3v 5% power supply 54-pin tsop-ii ( 0.8mm pin pitch) block diagram (4mx16 shown) description the enhanced memory systems sm3603 and sm3604 high- speed sdram (hsdram) devices are high performance versions of the proposed jedec pc-133 sdram. while compatible with standard sdram, they provide the faster clock access time (4.6 ns), shorter random access latency (34.6 ns), and fast bank cycle time (52.5 ns) needed to improve system stability, capacity, and performance in systems operating at 133 mhz and higher bus speeds. the hsdram is ideal for any high performance system including pcs, workstations, servers, communications switches, dsp systems, 3-d graphics, and embedded computers. address buffers row decoder ba1 ba0 a(11:0) data i/o buffers dq(15:0) clk cke /cs /ras /cas /we udqm, ldqm command decoder and timing generator sense amplifiers column decoder bank a 4k rows x 256 col x 16 bits bank b 4k rows x 256 col x 16 bits bank c 4k rows x 256 col x 16 bits bank d 4k rows x 256 col x 16 bits sense amplifiers column decoder sense amplifiers column decoder sense amplifiers column decoder
64mbit C high speed sdram 8mx8, 4mx16 hsdram data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 2 of 10 revision 1.1 pin assignments (top view) 4mx16 8mx8 vdd vdd 1 54 vss vss dq0 dq0 2 53 dq15 dq7 vdd vdd 3 52 vss vss nc dq1 4 51 dq14 nc dq1 dq2 5 50 dq13 dq6 vss vss 6 49 vdd vdd nc dq3 7 48 dq12 nc dq2 dq4 8 47 dq11 dq5 vdd vdd 9 54 pin tsop-ii 46 vss vss nc dq5 10 45 dq10 nc dq3 dq6 11 400 x 875 mils 44 dq9 dq4 vss vss 12 43 vdd vdd nc dq7 13 0.8 mm pitch 42 dq8 nc vdd vdd 14 41 vss vss nc ldqm 15 40 nc nc /we /we 16 39 udqm dqm /cas /cas 17 38 clk clk /ras /ras 18 37 cke cke /cs /cs 19 36 nc nc ba0 ba0 20 35 a11 a11 ba1 ba1 21 34 a9 a9 a10/ap a10/ap 22 33 a8 a8 a0 a0 23 32 a7 a7 a1 a1 24 31 a6 a6 a2 a2 25 30 a5 a5 a3 a3 26 29 a4 a4 vdd vdd 27 28 vss vss
64mbit C high speed sdram data sheet 8mx8, 4mx16 hsdram enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.1 page 3 of 10 pin descriptions symbol type function clk input clocks: all sdram input signals are sampled on the positive edge of clk. cke input clock enable: cke activate (high) or deactivate (low) the clk signals. deactivating the clock initiates the power-down and self-refresh operations (all banks idle), or clock suspend operation. cke is synchronous until the device enters power-down and self- refresh modes where it is asynchronous until the mode is exited. cs# input chip select: cs# enables (low) or disables (high) the command decoder. when the command decoder is disabled, new commands are ignored but previous operations continue. ras#, cas#, we# input command inputs: sampled on the rising edge of clk, these inputs define the command to be executed. ba1, ba0 input bank addresses: these inputs define to which of the 4 banks a given command is being applied. a0-a11 input address inputs: a0-a11 define the row address during the bank activate command. a0- a8 define the column address during read and write commands. a10/ap invokes the auto-precharge operation. during manual precharge commands, a10/ap low specifies a single bank precharge while a10/ap high precharges all banks. the address inputs are also used to program the mode register. dq0-dq15 input/ output data i/o: data bus inputs and outputs. for write cycles, input data is applied to these pins and must be set-up and held relative to the rising edge of clock. for read cycles, the device drives output data on these pins after the cas latency is satisfied. dqm, udqm, ldqm input data i/o mask inputs: dqm inputs mask write data (zero latency) and acts as a synchronous output enable (2-cycle latency) for read data. v dd supply power supply: +3.3 v v ss supply ground nc - no connect - open pin.
64mbit C high speed sdram 8mx8, 4mx16 hsdram data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 4 of 10 revision 1.1 electrical characteristics absolute maximum ratings description symbol value power supply voltage v dd -1v to +4.6v voltage on any pin with respect to ground v in , v out -0.5v to +4.6v operating temperature (ambient) t a 0 c to +70 c storage temperature t stg -55 c to +125 c power dissipation p d 1.0 w dc output current (i/o pins) i out 50ma stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these, or any other conditions above those listed in the operational section of the specification, is not implied. exposure to conditions at absolute maximum ratings for extended periods may affect device reliability. dc operating conditions (t a = 0 c to 70 c) symbol parameter min typical max units notes v dd supply voltage 3.135 3.3 3.465 v v ih input high voltage 2.0 3.3 v dd + 0.3 v v il input low voltage -0.3 0.0 0.8 v i i(l) input leakage current - - 1 m a i o(l) output leakage current - - 1 m a v oh output high voltage (i out = -4ma) 2.4 - v dd v v ol output low voltage (i out = +4ma) 0.0 - 0.4 v capacitance (t a = 25 c, f = 1mhz, vdd = 3.3v 5%, not 100% tested) symbol parameter min typical max units notes c in1 input capacitance (ba1, ba0, a0-11) 2.5 3.3 4.0 pf c in2 input capacitance (all control inputs) 2.5 3.3 4.0 pf c i/o i/o capacitance (dq0-15) 3.5 4.5 5.5 pf
64mbit C high speed sdram data sheet 8mx8, 4mx16 hsdram enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.1 page 5 of 10 ac characteristics (t a = 0 c to 70 c) 1. an initial pause of 200 m s is required after power-up, then a precharge all banks command must be given followed by a minimum of eight auto (cbr) refresh cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the v tt = 1.4v crossover point. t setup t hold clock input output t lz t ac t oh t t vih vtt vil v tt output z 0 = 50 ohm c load = 50pf ac output load circuit v tt r t = 50 ohm 3. the transition time is measured between v ih and v il (or between v ih and v il ). 4. ac measurements assume t t = 1ns. 5. in addition to meeting the transition rate specification, the clock and cke must transition v ih and v il (or between v ih and v il ) in a monotonic manner.
64mbit C high speed sdram 8mx8, 4mx16 hsdram data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 6 of 10 revision 1.1 ac operating conditions (t a = 0 c to 70 c) -7.5 symbol parameter min max units notes clock and clock enable parameters t ck3 clock cycle time, cl = 3 7.5 ns t ck2 clock cycle time, cl = 2 10 ns t ck1 clock cycle time, cl = 1 20 ns t ckh3 , t ckl3 clock high & low times, cl=3 2.5 - ns 1 t ckh2 , t ckl2 clock high & low times, cl=2 3.5 - ns 1 t ckh1 , t ckl1 clock high & low times, cl=1 4.5 - ns 1 t ckes clock enable set-up time 1.5 - ns t ckeh clock enable hold time 0.8 - ns t cksp cke set-up time (power down mode) 1.5 - ns t t transition time (rise and fall) - 4 ns common parameters t cs command and address set-up time 1.5 - ns t ch command and address hold time 0.8 - ns t rcd ras to cas delay time 15 - ns t rc bank cycle time 52.5 120k ns t ras bank active time 37.5 120k ns t rp precharge time 15 - ns t rrd bank to bank delay time (alt. bank) 15 - ns t ccd cas to cas delay time (same bank) 7.5 - ns t mrd mode register set to active delay 2 - clk notes: 1. assumes clock rise and fall times are equal to 1ns. if rise or fall time exceeds 1ns, other ac timing parameters must be co mpensated by an additional [(t rise +t fall )/2-1] ns.
64mbit C high speed sdram data sheet 8mx8, 4mx16 hsdram enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.1 page 7 of 10 -7.5 symbol parameter min max units notes read and write parameters t ac3 clock access time, cl = 3 - 4.6 ns 1,2,8 t ac2 clock access time, cl = 2 - 6.0 ns 1,2 t ac1 clock access time, cl = 1 (-7.5 device) clock access time, cl = 1 (-7.5f device) - 15.0 13.75 ns 1,2 t oh3 data output hold time (cl=3) 2.7 - ns t oh2 data output hold time (cl=2) 3.0 - ns t oh1 data output hold time (cl=1) 3.5 - ns t lz data output to low-z time 1 - ns t hz2 data output to high-z time (cl=2, 3) - 4.6 ns 3 t hz1 data output to high-z time (cl=1) - 7.0 ns 3 t dqz dqm data output disable time 2 - clk t ds data input set-up time 1.5 - ns t dh data input hold time 0.8 - ns t dpl data input to precharge 15 - ns t dal data input to actv/refresh 30 - ns 4 t dqw data write mask latency 0 - clk refresh parameters t ref refresh period - 64 ms 5, 6 t srex self refresh exit time 2clk+t rc - ns 7 notes: 1. access time is measured at 1.4v (lvttl) at max clock rate for the cas latency specified. see ac test load. 2. access time is based on a clock rise time of 1ns. if clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time. 3. referenced to the time at which the output achieves an open circuit condition. 4. t dal is equal to t dpl + t rp . 5. 4096 cycles. 6. any time that the refresh period has been exceeded, a minimum of two auto-refresh (cbr) comm ands must be given to wake up the device. 7. self-refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self-refresh exi t is not completed until t rc is satisfied once the self-refresh exit command is registered. 8. for 4mx16 devices, the clock access time (cl=3) is 5.0 ns.
64mbit C high speed sdram 8mx8, 4mx16 hsdram data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 8 of 10 revision 1.1 operating currents (t a = 0 c to 70 c) parameter symbol test condition value units notes operating current (one bank active) i cc1a bl = 1, cl = 3, read or write, cke ? v ih (min), t rc = min., t ck = 7.5ns 120 ma 1 i cc2p cke ? v il , t ck = 7.5ns, input change every two cycles 2.5 ma standby current in power down mode (dram precharged) i cc2ps cke ? v il , t ck = infinity, no input change 2.0 ma i cc2n cke ? v ih , t ck = 7.5ns 30 ma standby current in non-power down mode (dram precharged) i cc2ns cke ? v ih , t ck = infinity 10 ma i cc3n cke ? v ih , t ck = 7.5ns, input change every two cycles 65 ma device deselected (dram active) i cc3p cke ? v il , t ck = 7.5ns, input change every two cycles 3 ma i cc4a bl = full page, cl = 1, read or write, t rc = infinity, t ck = min. 70 ma 1,2 burst operating current (both banks active) i cc4b bl = full page, cl = 2,3, read or write, t rc = infinity, t ck = min. 130 ma 1,2 i cc5f cl = 3, t ck = 7.5ns, t rc = t rc (min). 170 ma 3,4,5 auto (cbr) refresh current i cc5d cl = 3, t ck = 7.5ns, t rc = 15.625 m s 30 ma 3,4,5 self refresh current i cc6 cke ?91r,qsxw&kdqjh 4 ma notes: 1. the specified value is obtained with the outputs open. 2. the specified value is obtained when the programmed burst length is executed to completion without intereuption by a subsequ ent burst read or burst write cycle. 3. the specified value is valid when addresses are changed no more than once during t ck (min). 4. the specified value is valid when no operation commands are registered on every rising clock edge during t rc (min). 5. the specified value is valid when data inputs (dqs) are stable during t rc (min).
64mbit C high speed sdram data sheet 8mx8, 4mx16 hsdram enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.1 page 9 of 10 revision log revision date summary of changes 1.0 - first release of document. 1.1 4/17/00 added C7.5f versions of this device. added revision log.
64mbit C high speed sdram 8mx8, 4mx16 hsdram data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 1999 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 10 of 10 revision 1.1 ordering information part number cas latencies i/o width i/o type package power supply maximum operating frequency (mhz) sm3603t-7.5 1, 2, 3 x8 lvttl 54-pin tsop ii 3.3v 133 sm3604t-7.5 1, 2, 3 x16 lvttl 54-pin tsop ii 3.3v 133 sm3603t-7.5f 1, 2, 3 x8 lvttl 54-pin tsop ii 3.3v 133 sm3604t-7.5f 1, 2, 3 x16 lvttl 54-pin tsop ii 3.3v 133
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