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TCD2561D 2003-05-06 1 toshiba ccd linear image sensor ccd (charge coupled device) TCD2561D the TCD2561D is a high sensitive and low dark current 5340 elements 4 line ccd color image sensor which includes ccd drive circuit, clamp circuit. the sensor is designed for scanner. the device contains a row of 5340 elements 4 line photodiodes which provide a 24 lines/mm across a a4 size paper. the device is operated by 5 v pulse and 12 v power supply. features x number of image sensing elements: 5340 elements 4 line x image sensing element size: 7 p m 7 p m on 7 p m centers x photo sensing region: high sensitive pn photodiode x distanced between photodiode array: color (28 p m, 4 lines), b/w-color (56 p m, 8 lines) x clock: 2 phase (5 v) x power supply: 12 v power supply voltage x internal circuit: clamp circuit x package: 22 pin cerdip package x color filter: red, green, blue maximum ratings (note1) characteristic symbol rating unit clock pulse voltage v i v shift pulse voltage v sh v reset pulse voltage v rs v clamp pulse voltage v cp v changeover switch voltage v sw 0.3~8.0 v power supply voltage v od 0.3~15 v operating temperature t opr 0~60 c storage temperature t stg 25~85 c note 1: all voltage are with respect to ss terminals (ground). weight: 5.2 g (typ.) os2 22 os1 od ss 1 sw i 2a3 21 20 19 18 17 16 os3 1 2 3 4 5 6 7 ss rs cp 2 sw i 1a3 ss nc i 2a1 i 1a1 sh0 15 14 13 12 8 9 10 11 i 2a2 i 1a2 sh3 sh2 sh1 1 red 5340 1 1 5340 5340 green blue 1 5340 black & white pin connections (top view)
TCD2561D 2003-05-06 2 circuit diagram pin names os3 signal output 3 (red) os2 signal output 2 (green) ss ground os1 signal output 1 (blue) rs reset gate od power cp clamp gate ss ground 2 sw changeover switch 2 (color and b/w) 1 sw changeover switch 1 (color and b/w) i 1a3 clock 3 (phase 1) i 2a3 clock 3 (phase 2) ss ground nc non connection i 2a2 clock 2 (phase 2) i 2a1 clock 1 (phase 2) i 1a2 clock 2 (phase 1) i 1a1 clock 1 (phase 1) sh3 shift gate 3 sh0 shift gate 0 sh2 shift gate 2 sh1 shift gate 1 3 ccd analog shift register (even) shift gate sh0 d26 shift gate sh0 ccd analog shift register (odd) clamp clamp clamp clamp clamp 4 18 19 20 9 8 15 13 os2 os1 od ss 1 sw i 2a3 ss rs cp i 1a3 i 2a1 sh0 i 2a2 i 1a2 7 6 17 1 22 21 os3 sw1 sw1 sw2 sw2 d27 d28 d125 d126 d127 s1 s2 s5340 d128 9e 148 d149 s5339 s5338 photo diode (black & white) d26 d27 d28 d125 d126 d127 s1 s2 s5340 d128 9e 148 d149 s5339 s5338 photo diode (blue) shift gate sh1 ccd analog shift register d26 shift gate sh2 ccd analog shift register d27 d28 d125 d126 d127 s1 s2 s5340 d128 9e 148 d149 s5339 s5338 photo diode (green) d26 d27 d28 d125 d126 d127 s1 s2 s5340 d128 9e 148 d149 s5339 s5338 photo diode (red) shift gate sh3 ccd analog shift register 5 2 sw 12 sh1 14 i 1a1 11 sh2 10 sh3
TCD2561D 2003-05-06 3 optical/electrical characteristics (ta 25c, v od 12 v, v i i i i v rs v sh v cp 5 v (pulse), f i i i i 1.0 mhz, f rs 1.0 mhz, load resistance 100 k : : : : , t int (integration time) 10 ms, light source a light source cm500s filter (t 1.0 mm)) characteristics symbol min typ. max unit note r b/w 16.8 21.0 25.2 r r 6.3 9.0 11.7 r g 7.3 10.5 13.7 sensitivity r b 3.8 5.5 7.2 v/(lx :/ s) (note 2) prnu (1) 10 20 % (note 3) photo response non uniformity prnu (3) 3 12 mv (note 4) image lag il 1 % (note 5) saturation output voltage (b/w) v sat (b/w) 3.2 3.5 v (note 6) saturation output voltage (color) v sat (color) 3.2 3.5 v (note 6) saturation exposure se 0.1 lx :/ s (note 7) dark signal voltage v drk 0.4 2.0 mv (note 8) dark signal non uniformity dsnu 7 12 mv (note 8) dc power dissipation p d 480 690 mw total transfer efficiency tte 92 % output impedance z o 0.3 1.0 k : dc signal output voltage v os 5.0 6.0 7.0 v (note 9) random noise n d v 1.0 mv (note 10) reset noise v rsn 0.5 1.0 v (note 9) note 2: sensitivity is defined for each color of signal outputs average when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature. note 3: prnu (1) is defined for each color on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature. ' x prnu (1) x u 100 (%) when x is average of total signal output and ' x is the maximum deviation from x . the amount of incident light is shown below. 1 1 1 red 2 se, green 2 se, blue 4 se note 4: prnu (3) is defined as maximum voltage with next pixel, where measured 5% of se (typ.)
TCD2561D 2003-05-06 4 note 5: image lag is defined as follows. note 6: v sat is defined as minimum saturation output of all effective pixels. note 7: definition of se: note 8: v drk is defined as average dark signal voltage of all effective pixels. dsnu is defined as different voltage between v drk and v mdk when v mdk is maximum dark signal voltage. note 9: dc signal output voltage and reset noise is defined as follows, but reset noise is a fixed pattern noise. sh os led off on signal (500 mv) image lag v sat se r b/w (lx :/ s) v mdk v drk dsnu ss v os v rsn os
TCD2561D 2003-05-06 5 note 10: random noise is defined as the standard deviation (sigma) of the output level difference between two adjacent effective pixels under no illumination (i.e. dark conditions) calculated by the following procedure. (1) two adjacent pixels (pixel n and n 1) in one reading are fixed as measurement points. (2) each of the output level at video output periods averaged over 200 ns period to get v (n) and v (n 1). (3) v (n 1) is subtracted from v (n) to get ' v. ' v v (n) v (n 1) (4) the standard deviation of ' v is calculated after procedure (2) and (3) are repeated 30 times (30 readings) | ' ' 30 1 vi 30 1 v i | ' ' v _ _ 30 1 i 2 ) v v ( 30 1 i 9 (5) procedure (2), (3) and (4) are repeated 10 times to get sigma value. (6) 10 sigma values are averaged. | v v 10 1 j j 10 1 (7) v value calculated using the above procedure is observed 2 times larger than that measured relative to the ground level. so we specify random noise as follows. v v 2 1 n d output waveform (effective pixels under dark condition) video output video output 200 ns 200 ns pixel (n) pixel (n 1) ' v
TCD2561D 2003-05-06 6 operating condition characteristics symbol min typ. max unit note ?h? level 4.5 5.0 5.5 clock pulse voltage ?l? level v i a 0 0.5 v ?h? level 4.5 5.0 5.5 shift pulse voltage ?l? level v sh 0 0.5 v ?h? level 4.5 5.0 5.5 reset pulse voltage ?l? level v rs 0 0.5 v ?h? level 4.5 5.0 5.5 clamp pulse voltage ?l? level v cp 0 0.5 v ?h? level 4.5 5.0 5.5 switch pulse voltage ?l? level v sw 0 0.5 v power supply voltage v od 11.4 12.0 13.0 v clock characteristics (ta 25c) characteristics symbol min typ. max unit clock pulse frequency f i 0.3 1.0 16 mhz reset pulse frequency f rs 0.3 1.0 10 mhz clamp pulse frequency f cp 0.3 1.0 10 mhz clock1 capacitance (note 11) c i 1 160 240 pf clock2 capacitance (note 11) c i 2 130 195 pf shift gate capacitance c sh 30 60 pf reset gate capacitance c rs 10 40 pf clamp gate capacitance c cp 10 40 pf switch gate capacitance c sw 10 40 pf note 11: v od 12 v
TCD2561D 2003-05-06 7 timing chart 1: bit clamp mode (color mode) sh1, 2, 3 1 line readout period (5490 elements) dummy outputs (26 elements) light shield outputs (96 elements) (6 elements) dummy outputs (3 elements) test outputs (1 elements) dummy outputs (12 elements) dummy outputs (128 elements) signal outputs (5340 elements) os1, 2, 3 (color) (6 elements) dummy outputs (22 elements) d132 d133 d145 d146 d134 d130 s2618 s2617 s2616 d147 d148 s1 d125 d124 d123 d122 d121 d60 d26 d12 d13 d1 d0 d127 d126 d149 d25 d61 d62 d63 d64 s2606 s2607 s2608 s2609 s2610 d128 d129 s5340 d131 t int (integration time) i 1a i 2a rs cp sh0 (?h?)
TCD2561D 2003-05-06 8 timing chart 2: line clamp mode (color mode) sh1, 2, 3 1 line readout period (5490 elements) dummy outputs (26 elements) light shield outputs (96 elements) (6 elements) dummy outputs (3 elements) test outputs (1 elements) dummy outputs (12 elements) dummy outputs (128 elements) signal outputs (5340 elements) os1, 2, 3 (color) (6 elements) dummy outputs (22 elements) d132 d133 d145 d146 d134 d130 s2618 s2617 s2616 d147 d148 s1 d125 d124 d123 d122 d121 d60 d26 d12 d13 d1 d0 d127 d126 d149 d25 d61 d62 d63 d64 s2606 s2607 s2608 s2609 s2610 d128 d129 s5340 d131 t int (integration time) i 1a i 2a rs cp sh cp ?h? sh0 (?h?)
TCD2561D 2003-05-06 9 timing chart 3: bit clamp mode (b/w mode) sh0 1 line readout period (2745 elements) dummy outputs (13 elements) light shield outputs (48 elements) (3 elements) dummy output (1 element) test output (1 element) dummy outputs (6 elements) dummy outputs (64 elements) (3 elements) dummy outputs (11 elements) os1 (b/w) signal outputs (2670 elements) d133 d147 d135 d131 d129 s5340 d149 s2 d125 d123 d121 d27 d25 d3 d1 d127 d51 d53 s116 s118 s120 s122 s124 s126 s128 s130 t int (integration time) i 1a i 2a rs cp os2 (b/w) d132 d146 d134 d130 d128 s5339 d148 s1 d124 d122 d120 d26 d24 d2 d0 d126 d50 d52 s115 s117 s119 s121 s123 s125 s127 s129 sh1, 2, 3 (?h?)
TCD2561D 2003-05-06 10 timing chart 4: line clamp mode (b/w mode) sh0 1 line readout period (2745 elements) dummy outputs (13 elements) light shield outputs (48 elements) (3 elements) dummy output (1 element) test output (1 element) dummy outputs (6 elements) dummy outputs (64 elements) (3 elements) dummy outputs (11 elements) os1 (b/w) signal outputs (2670 elements) d133 d147 d135 d131 d129 s5340 d149 s2 d125 d123 d121 d27 d25 d3 d1 d127 d51 d53 s116 s118 s120 s122 s124 s126 s128 s130 t int (integration time) i 1a i 2a rs os2 (b/w) d132 d146 d134 d130 d128 s5339 d148 s1 d124 d122 d120 d26 d24 d2 d0 d126 d50 d52 s115 s117 s119 s121 s123 s125 s127 s129 cp sh cp ?h? sh1, 2, 3 (?h?)
TCD2561D 2003-05-06 11 timing requirements i 1 i 2 gnd 3.5 v (max) 1.5 v (min) t1 t2 t3 t4 t5 t6 t7 rs cp sh i 1a cp sh (line clamp mode) t8 b/w o color mode: 1 sw (?l? o ?h?) color o b/w mode: 2 sw (?l? o ?h?) b/w o color mode: 2 sw (?h? o ?l?) color o b/w mode: 1 sw (?h? o ?l?) video signal peak t21 t19 t18 t17 10% t16 t15 t14 t13 t9 t10 t11 t12 i 2 i 1 90% 90% 10% to the peak 10% to the peak 10% os (line clamp mode) os (bit clamp mode) rs cp t20 10%
TCD2561D 2003-05-06 12 timing requirements (cont.) characteristics symbol min typ. (note 12) max unit t1 120 1000 pulse timing of sh and i 1 t5 800 1000 ns sh pulse rise time, fall time t2, t4 0 50 ns sh pulse width t3 3000 5000 ns pulse timing of sh and cp t6 200 500 ns pulse timing of sh and cp (line clamp mode) t7 10 100 ns pulse timing of sh and sw t8 100 500 t3 100 ns i 1, i 2 pulse rise time, fall time t9, t10 0 50 ns rs pulse rise time, fall time t11, t12 0 20 ns rs pulse width t13 10 (20) 80 ns pulse timing of rs and cp t14 0 40 ns pulse timing of i 1a , i 2a and cp t15 0 20 ns cp pulse rise time, fall time t16, t17 0 20 ns cp pulse width (note 13) t18 30 (3000) 80 (5000) ns reference level settle time (bit clamp mode) t19 20 40 (note 16) ns video data delay time (note 14) t20 20 40 (note 15) ns reference level settle time (line clamp mode) t21 30 50 (note 16) ns note 12: typ. is the case of f rs 1.0 mhz. note 13: line clamp mode inside ( ). note 14: load resistance is 100 k : . note 15: typical settle time to about 1% of final value. note 16: typical settle time to about 1% of the peak. clamp mode clamp means cp input pulse bit clamp cp pulse line clamp ?h? or sh changeover switch mode output type 1 sw input pulse 2 sw input pulse sh input pulse color ?h? ?l? sh1, 2, 3 sh pulse, sh0 ?h? b/w ?l? ?h? sh0 sh pulse, sh1, 2, 3 ?h?
TCD2561D 2003-05-06 13 typical spectral response wavelength o o o o (nm) spectral response 400 0 0.2 0.4 1.0 450 500 550 600 650 700 0.6 0.8 red ta 25c green blue
TCD2561D 2003-05-06 14 typical drive circuit 1 sw rs cp 2 sw os2 os1 od ss i 2a3 os3 ss i 1a3 ss nc i 2a1 i 1a1 sh0 i 2a2 i 1a2 sh3 sh2 sh1 21 22 19 20 17 18 15 16 14 12 13 2 1 4 3 6 5 8 7 9 11 10 TCD2561D ic1, 2, 3 : tc74ac04 ic4, 5 : tc74hc04 12 v 47 p f/25 v 1 p f/25 v ic4 sh0 sh1 sh2 sh3 rs cp 12 v 1 p f/25 v 47 p f/25 v os3 os2 os1 i 2a3 i 1a3 ic3 5 v 1 p f/25 v 47 p f/25 v i 2a1 i 1a1 ic1 5 v 1 p f/25 v 47 p f/25 v i 2a2 i 1a2 ic2 5 v 1 p f/25 v 47 p f/25 v 2 sw ic5 5 v 1 p f/25 v 47 p f/25 v 1 sw 5 v 1 p f/25 v 47 p f/25 v
TCD2561D 2003-05-06 15 caution window glass the dust and stain on the glass window of the package degrade optical performance of ccd sensor. keep the glass window clean by saturating a cotton swab in alcohol and lightly wiping the surface, and allow the glass to dry, by blowing with filtered dry n2. care should be taken to avoid mechanical or thermal shock because the glass window is easily to damage. 1. electrostatic breakdown store in shorting clip or in conductive foam to avoid electrostatic breakdown. ccd image sensor is protected against static electricity, but interior puncture mode device due to static electricity is sometimes detected. in handing the device, it is necessary to execute the following static electricity preventive measures, in order to prevent the trouble rate increase of the manufacturing system due to static electricity. a. prevent the generation of static electricity due to friction by making the work with bare hands or by putting on cotton gloves and non-charging working clothes. b. discharge the static electricity by providing earth plate or earth wire on the floor, door or stand of the work room. c. ground the tools such as soldering iron, radio cutting pliers of or pincer. it is not necessarily required to execute all precaution items for static electricity. it is all right to mitigate the precautions by confirming that the trouble rate within the prescribed range. 2. incident light ccd sensor is sensitive to infrared light. note that infrared light component degrades resolution and prnu of ccd sensor. 3. lead frame forming since this package is not strong against mechanical stress, you should not reform the lead frame. we recommend to use a ic-inserter when you assemble to pcb. 4. soldering soldering by the solder flow method cannot be guaranteed because this method may have deleterious effects on prevention of window glass soiling and heat resistance. using a soldering iron, complete soldering within ten seconds for lead temperatures of up to 260c, or within three seconds for lead temperatures of up to 350c.
TCD2561D 2003-05-06 16 package dimensions weight: 5.2 g (typ.) unit: mm wdip22-g-400-2.54d (g) note 1: top of chip to bottom of package. note 2: glass thickness (n 1.5) note 3: no.1 sensor element (s1) to edge of no.1 pin. 52.6 r 0.5 lead frame thickness (note 3) (note 1) (note 2)
TCD2561D 2003-05-06 17 x toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. x the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. x the products described in this document are subject to the foreign exchange and foreign trade laws. x the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. x the information contained herein is subject to change without notice. 000707eba restrictions on product use

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