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features ? 2.5 a maximum peak output current ? 2.0 a minimum peak output current ? 250 khz maximum switching speed ? high speed response: 200 ns maximum propagation delay over temperature range ? 10 kv/s minimum common mode rejection (cmr) at v cm = 1500 v ? under voltage lock-out protection (uvlo) with hysteresis ? wide operating temperature range: C40c to 100c ? wide v cc operating range: 10 v to 20 v ? 20 ns typical pulse width distortion ? safety approvals: C ul approval, 3750 v rms for 1 minute C csa approval C iec/en/din en 60747-5-2 approval applications ? plasma display panel (pdp) ? distributed power architecture (dpa) ? switch mode rectifer (smr) ? high performance dc/dc converter ? high performance switching power supply (sps) ? high performance uninterruptible power supply (ups) ? isolated igbt/power mosfet gate drive functional diagram 1 3 shield 2 4 8 6 7 5 n/c cathode anode n/c v cc v o v o v ee description this family of devices consists of a gaasp led. the led is optically coupled to an integrated circuit with a power stage. these optocouplers are ideally suited for high frequency driving of power igbts and mosfets used in plasma display panels, high performance dc/dc convert - ers, and motor control inverter applications. a 0.1 f bypass capacitor must be con - nected between pins v cc and ground. HCPL-3180 2.5 amp output current, high speed, gate drive optocoupler data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product
2 package outline drawings HCPL-3180 standard dip package 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 option code* type number * marking code letter for option numbers "v" = option 060 option numbers 300 and 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. 3.56 0.13 (0.140 0.005) ordering information HCPL-3180 is ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount gull wing tape & reel iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant HCPL-3180 -000e no option 300 mil dip-8 50 per tube -300e -300 x x 50 per tube -500e -500 x x x 1000 per reel -060e -060 x 50 per tube -360e -360 x x x x 50 per tube -560e -560 x x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: HCPL-3180-560e to order product of 300 mil dip gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval in rohs compliant. example 2: HCPL-3180 to order product of 300 mil dip package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe.
3 HCPL-3180 gull wing surface mount option 300 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) solder refow temperature profle 0 time (seconds) temperature (c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160c 140c 150c peak temp. 245c peak temp. 240c peak temp. 230c soldering time 200c preheating tim e 150c, 90 + 30 sec. 2.5c 0.5c/sec. 3c + 1c/?0.5c tight typical loose room temperature preheating rate 3c + 1c/?0.5c/sec. reflow heating rate 2.5 c 0.5c/sec. note: non-halide fux should be used.
4 regulatory information the HCPL-3180 has been approved by the following organizations: iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01 (option 060 only) ul approval under ul 1577, component recognition program up to v iso = 3750 v rms . file e55361. csa approval under csa component acceptance notice #5, file ca 88324. iec/en/din en 60747-5-2 insulation characteristics (HCPL-3180 option 060) description symbol HCPL-3180 unit installation classifcation per din en 0110 1997-04 for rated mains voltage f 150 v rms i - iv for rated mains voltage f 300 v rms i - iii for rated mains voltage f 600 v rms i-ii climatic classifcation 55/100/21 pollution degree (din en 0110 1997-04) 2 maximum working insulation voltage v iorm 630 v peak input to output test voltage, method b* v iorm x 1.875=v pr , 100% production test with v pr 1181 v peak t m =1 sec, partial discharge < 5 pc input to output test voltage, method a* v iorm x 1.5=v pr , type and sample test, t m =60 sec, v pr 945 v peak partial discharge < 5 pc highest allowable overvoltage v iotm 6000 v peak (transient overvoltage t ini = 10 sec) safety-limiting values C maximum values allowed in the event of a failure. case temperature t s 175 c input current** i s,input 230 ma output power** p s, output 600 mw insulation resistance at t s , v io = 500 v r s >10 9 ? * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section iec/ en/din en 60747-5-2 for a detailed description of method a and method b partial discharge test profles. ** refer to the following fgure for dependence of p s and i s on ambient temperature. recommended pb-free ir profle 217 c ramp -dow n 6 c/sec. max. ramp -up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak tempera ture t p t s prehea t 60 to 180 sec. t l t l t smax t smin 25 t p time tempera ture notes: the time from 25 c to peak tempera ture = 8 minutes max. t smax = 200 c, t smin = 150 c note: non-halide fux should be used.
5 absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c junction temperature t j -40 125 c average input current i f(avg) 25 ma 1 peak transient input current i f(tran) 1.0 a (<1 s pulse width, 300 pps) reverse input voltage v r 5 v high peak output current i oh(peak) 2.5 a 2 low peak output current i ol(peak) 2.5 a 2 supply voltage v cc -v ee -0.5 25 v output voltage v o(peak) 0 v cc v output power dissipation p o 250 mw 3 total power dissipation p t 295 mw 4 lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see package outline drawings section output power ? p s , input current ? i s 0 0 t s ? case temperature ? c 200 600 400 25 800 50 75 100 200 150 175 p s (mw) 125 100 300 500 700 i s (ma) i nsulation and safety related specifcations parameter symbol HCPL-3180 units conditions minimum external air gap l(101) 7.1 mm measured from input terminals to output (clearance) terminals, shortest distance through air. minimum external tracking l(102) 7.4 mm measured from input terminals to output (creepage) terminals, shortest distance path along body. minimum internal plastic gap 0.08 mm through insulation distance conductor to (internal clearance) conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance cti >175 v din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia material group (din vde 0110, 1/89, table 1) note: option 300 C surface mount classifcation is class a in accordance with cecc 00802.
6 recommended operating conditions parameter symbol min. max. units note power supply v cc -v ee 10 20 v input current (on) i f(on) 10 16 ma input voltage (off) v f(off) - 3.6 0.8 v operating temperature t a -40 100 c electrical specifcations (dc) over recommended operating conditions unless otherwise specifed. test parameter symbol min. typ. max. units conditions fig. note high level output current i oh 0.5 a v o = v cc - 4 2, 3, 17 5 2.0 a v o = v cc -10 2, 3, 17 2 low level output current i ol 0.5 a v o = v ee +2.5 5, 6, 18 5 2.0 a v o = v ee +10 5, 6, 18 2 high level output voltage v oh v cc -4 v i o = -100 ma 1, 3, 19 6, 7 low level output voltage v ol 0.5 v i o = 100 ma 4, 6, 20 high level supply current i cch 3.0 6.0 ma output open 7, 8 i f = 10 to 16 ma low level supply current i ccl 3.0 6.0 ma output open 7, 8 v f = 3.0 to 0.8 ma threshold input current i flh 8.0 ma low to high i o = 0 ma, 9, 15, 21 threshold input voltage v fhl 0.8 v v o > 5 v high to low input forward voltage v f 1.2 1.5 1.8 v i f = 10 ma 16 temperature coefcient of d v f / d t a C1.6 mv/c i f = 10 ma input forward voltage uvlo threshold v uvlo+ 7.9 v i f = 10 ma, v uvloC 7.4 v v o > 5 v 22, 33 uvlo hysteresis uvlo hyst 0.5 v input reverse breakdown bv r 5 v i r = 10 a voltage input capacitance c in 60 pf f = 1 mhz, v f = 0 v
7 package characteristics test parameter symbol min. typ. max. units conditions fig. note input-output momentary v iso 3750 v rms t a = 25c, 8,9 withstand voltage rh < 50% input-output resistance r i-o 10 [11] ? v i-o = 500 v 9 input-output capacitance c i-o 1 pf freq = 1 mhz notes: 1. derate linearly above +70c free air temperature at a rate of 0.3 ma/c. 2. maximum pulse width = 10 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with io peak minimum = 2.0 a. see application section for additional details on limiting iol peak. 3. derate linearly above +70c, free air temperature at the rate of 4.8 mw/c. 4. derate linearly above +70c, free air temperature at the rate of 5.4 mw/c. the maximum led junction temperature should not exceed +125c. 5. maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. in this test, v oh is measured with a dc load current. when driving capacitive load v oh will approach v cc as i oh approaches zero amps. 7. maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage > 4500 v rms for 1 second (leakage detec - tion current limit i i-o < 5 a). 9. device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. pwd is defned as |t phl - t plh | for any given device. 11. pin 1 and 4 need to be connected to led common. 12. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse v cm to assure that the output will remain in the high state (i.e. v o > 10.0 v). 13. common mode transient immunity in a low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the out - put will remain in a low state (i.e. v o < 1.0 v). 14. t phl propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of the v o signal. 15. the diference between t phl and t plh between any two HCPL-3180 parts under same test conditions. switching specifcations (ac) over recommended operating conditions unless otherwise specifed. test parameter symbol min. typ. max. units conditions fig. note propagation delay time to t plh 50 150 200 ns 10, 11, 14 high output level i f = 10 ma, 12, 13, propagation delay time to t phl 50 150 200 ns r g = 10 , 14, 23 low output level f = 250 khz, pulse width distortion pwd 20 65 ns duty cycle = 50%, 10 propagation delay pdd -90 90 ns c g = 10 nf 34, 35 10 diference between any (t phl- t plh ) two parts or channels rise time t r 25 ns cl = 1 nf, 23 fall time t f 25 ns r g = 0 uvlo turn on delay t uvlo on 2.0 s 22 uvlo turn of delay t uvlo off 0.3 s 22 output high level common |cm h | 10 kv/s t a = 25c, 24 11, 12 mode transient immunity i f = 10 to 16 ma, output low level common |cm l | 10 kv/s v cm = 1.5 kv, 24 11, 13 mode transient immunity v cc = 20 v
8 figure 1. v oh vs. temperature. figure 2. i oh vs. temperature. figure 3. v oh vs. i oh . figure 4. v ol vs. temperature. figure 5. i ol vs. temperature. figure 6. v ol vs. i ol . figure 7. i cc vs. temperature. figure 8. i cc vs. v cc . figure 9. i flh vs. temperature. (v oh ? v cc ) ? high output voltage drop ? v -40 -3.0 t a ? temperature ? c 100 -0.5 -1.0 -1.5 -2.0 -20 0 02 04 0 -2.5 60 80 i f = 10 to 16 ma i out = -100 ma v cc = 10 to 20 v v ee = 0 v i oh ? output high current ? a -40 0 t a ? temperature ? c 100 2.0 1.5 -20 2.5 02 04 0 0.5 60 80 i f = 10 to 16 ma v out = (v cc - 4 v) v cc = 10 to 20 v v ee = 0 v 1.0 (v oh ? v cc ) ? output high voltage drop ? v 0 -6 i oh ? output high current ? a 4 -2 -3 1 -1 2 -5 3 i f = 10 to 16 ma v cc = 10 to 20 v v ee = 0 v -4 100 c 25 c -40 c v ol ? output low voltage ? v -40 0 t a ? temperature ? c -20 0.30 0.25 02 0 0.05 100 0.15 0.20 0.10 40 60 80 v f (off) = -3.0 to 0.8 v i out = 100 ma v cc = 10 to 20 v v ee = 0 v i ol ? output low current ? a -40 0 t a ? temperature ? c -20 3.0 02 0 1.0 0.5 100 1.5 2.0 2.5 40 60 80 v f (off) = -3.0 to 0.8 v v out = 2.5 v v cc = 10 to 20 v v ee = 0 v v ol ? output low voltage ? v 0 0 i ol ? output low current ? a 2.5 3 0.5 4 1.0 1.5 1 2.0 v f(off) = -3.0 to 0.8 v v cc = 10 to 20 v v ee = 0 v 2 100 c 0 c 25 c i cc ? supply current ? ma -40 0 1.5 1.0 0.5 t a ? temperature ? c 100 3.0 2.5 -20 4.0 3.5 02 04 0 2.0 60 80 v cc = 20 v v ee = 0 v i f = 10 ma for i cch i f = 0 ma for i ccl i cch i ccl i cc ? supply current ? ma 10 2.5 v cc ? supply voltage ? v 20 3.3 3.1 2.9 3.5 12 14 2.7 16 18 i f = 10 ma for i cch i f = 0 ma for i ccl t a = 25 c v ee = 0 v i cch i ccl i flh ? low to high current threshold ? ma -40 0 t a ? temperature ? c -20 5 02 0 1 100 2 3 40 60 80 v cc = 10 to 20 v v ee = 0 v output = open 4
9 figure 10. propagation delay vs. v cc . figure 11. propagation delay vs. i f . figure 12. propagation delay vs. temperature. figure 13. propagation delay vs. r g . figure 14. propagation delay vs. c g . figure 15. transfer characteristics. figure 16. input current vs. forward voltage. t p ? propagation delay ? ns 10 50 v cc ? supply voltage ? v 25 200 150 250 15 100 20 i f = 10 ma t a = 25c r g = 10 ? c g = 10 nf duty cycle = 50% f = 250 khz t phl t plh t p ? propagation delay ? ns 6 50 i f ? forward led current ? ma 16 200 150 250 10 100 12 v cc = 20 v, v ee = 0 v r g = 10 ?, c g = 10 nf t a = 25 c f = 250 khz duty cycle = 50% t plh t phl 14 8 t p ? propagation delay ? ns -40 50 t a ? temperature ? c 100 200 150 -20 250 02 04 0 100 60 80 t phl t plh i f = 10 ma v cc = 20 v, v ee = 0 v r g = 10 ?, c g = 10 nf f = 250 khz duty cycle = 50% t p ? propagation delay ? ns 50 r g ? series load resistance ? ? 50 200 150 10 250 30 100 40 t plh t phl i f = 10 ma t a = 25c f = 250 khz c g = 10 nf duty cycle = 50% 20 t p ? propagation delay ? ns 50 c g ? load capacitance ? nf 25 200 150 5 250 10 100 15 20 t phl t plh i f = 10 ma t a = 25c rg = 10 ?? f = 250 khz c g = 10 nf duty cycle = 50% v o ? output voltage ? v 0 0 i f ? forward led current ? ma 1 20 2 5 5 10 15 34 i f ? forward current ? ma 1.10 0.001 v f ? forward voltage ? volts 1.60 10 1.0 0.1 1.20 1000 1.30 1.40 1.50 t a = 25c i f v f + ? 0.01 100
10 figure 17. i oh test circuit. figure 18. i ol test circuit. figure 19. v oh test circuit. figure 20. v ol test circuit. figure 21. i flh test circuit. figure 22. uvlo test circuit. 0.1 f v cc = 10 to 20 v 1 3 i f = 10 to 16 ma + ? 2 4 8 6 7 5 + ? 4 v/10 i oh 0.1 f v cc = 10 to 20 v 1 3 + ? 2 4 8 6 7 5 2.5 v/10 v i ol + ? 0.1 f v cc = 10 to 20 v 1 3 i f = 10 to 16 ma + ? 2 4 8 6 7 5 100 ma v oh 0.1 f v cc = 10 to 20 v 1 3 + ? 2 4 8 6 7 5 100 ma v ol 0.1 f v cc = 10 to 20 v 1 3 i f + ? 2 4 8 6 7 5 v o > 5 v 0.1 f v cc 1 3 i f = 10 ma + ? 2 4 8 6 7 5 v o > 5 v
11 figure 25. recommended led drive and application circuit for HCPL-3180. figure 23. t plh , t phl , t r and t f test circuit and waveform. figure 24. cmr test circuit and waveform. applications information eliminating negative igbt gate drive to keep the igbt frmly of, the HCPL-3180 has a very low maximum v ol specifcation of 0.4 v. the HCPL-3180 realizes the very low v ol by using a dmos transistor with 1 w (typical) on resistance in its pull down circuit. when the HCPL-3180 is in the low state, the igbt gate is shorted to the emitter by r g + 1 w . minimizing r g and the lead inductance from the HCPL-3180 to the igbt gate and emitter (possibly by mounting HCPL-3180 on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applications as shown in figure 25. care should be taken with such a pc board design to avoid routing the igbt collector or emitter traces close to the HCPL-3180 input as this can result in unwanted coupling of transient signals into the input of HCPL-3180 and degrade performance. (if the igbt drain must be routed near the HCPL-3180 input, then the led should be reverse biased when in the of state to prevent the transient signals coupled from the igbt drain from turning on the HCPL-3180.) 0.1 pf v cc = 20 v 10 : 1 3 i f = 10 to 16 ma v o + ? + ? 2 4 8 6 7 5 250 khz 50% duty cycle 500 : 10 nf i f v out t phl t plh t f t r 10% 50% 90% 0.1 pf v cc = 20 v 1 3 i f v o + ? + ? 2 4 8 6 7 5 a + ? b v cm = 1500 v 5 v v cm 't 0 v v o switch at b: i f = 0 ma v o switch at a: i f = 10 ma v ol v oh 't v cm gv gt = + hvdc 3-phase ac - hvdc 0.1 pf v cc = 15 v 1 3 + ? 2 4 8 6 7 5 270 : +5 v control input rg q1 q2 74xxx open collector
12 selecting the gate resistor (r g ) for HCPL-3180 step 1: calculate r g minimum from the i ol peak specifcation. the igbt and r g in figure 25 can be analyzed as a simple rc circuit with a voltage supplied by the HCPL-3180. the v ol value of 3 v in the previous equation is the v ol at the peak current of 2 a. (see figure 6.) step 2: check the HCPL-3180 power dissipation and increase r g if necessary. the HCPL-3180 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ). p t = p e + p o p e = i f * v f * duty cycle p o = p o(bias) + p o(switching) = i cc * v cc + e sw (r g ;q g ) * f for the circuit in figure 25 with i f (worst case) = 16 ma, r g = 10 , max duty cycle = 80%, q g = 100 nc, f = 200 khz and t amax = +75c: p e = 16 ma * 1.8 v * 0.8 = 23 mw p o = 4.5 ma * 20 v + 0.85 * 200 khz = 260 mw 226 mw (p o(max) @ 75c = 250 mw (5c * 4.8 mw/c)) the value of 4.5 ma for i cc in the previous equation was obtained by derating the i cc max of 6 ma to i cc max at +75c. since p o for this case is greater than the p o(max) , r g must be increased to reduce the HCPL-3180 power dissipa - tion. p o(switching max) = p o(max) C p o(bias) = 226 mw C 90 mw = 136 mw e sw(max) = p o(switching max) f = 136 mw 200 khz = 0.68 w for q g = 100 nc, a value of e sw = 0.68 w gives a r g = 15 w . = 20 C 3 2 = 8.5 figure 26. energy dissipated in the HCPL-3180 and for each igbt. r g v cc C v ol i olpeak e sw ? energy per switching cycle ? pj 0 0 r g ? gate resistance ? : 50 0.6 10 2.0 1.4 1.6 1.8 20 0.4 30 40 1.2 q g = 100 nc 1.0 0.8 0.2
13 thermal model (discussion applies to HCPL-3180) the steady state thermal model for the HCPL-3180 is shown in figure 27. the thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. as shown by the model, all heat generated fows through q ca which raises the case temperature tc accordingly. the value of q ca depends on the conditions of the board design and is, therefore, determined by the designer. the value of t je = p e * (256c/w + q ca ) + p d * (57c/w + q ca ) + t a t jd = p e * (57c/w + q ca ) + p d * (111c/w + q ca ) + t a for example, given p e = 45 mw, p o = 250 mw, t a = +70 c and q ca = +83 c/w: t je = p e * 339c/w + p d * 140c/w + t a = 45 mw * 339c/w + 250 mw * 140c/w + 70c = 120c t jd = p e * 140c/w + p d * 194c/w + t a = 45 mw * 140c/w + 250 mw * 194c/w + 70c = 125c t je and t jd should be limited to +125 c based on the board layout and part placement ( q ca ) specifc to the application. figure 27. thermal model. q ca = +83 c/w was obtained from thermal measure - ments using a 2.5 x 2.5 inch pc board, with small traces (no ground plane), a single hcpl- 3180 soldered into the center of the board and still air. the absolute maximum power dissipation derating specifcations assume a q ca value of +83 c/w. from the thermal mode in figure 27, the led and detector ic junction temperatures can be expressed as: t ld = 442 qc/w t je t jd t lc = 467 qc/w t dc = 126 qc/w t ca = 83 qc/w* t c t a t je = led junction temperature t jd = detector ic junction temperature t c = case temperature measured at the center of the package bottom t lc = led-to-case thermal resistance t ld = led-to-detector thermal resistance t dc = detector-to-case thermal resistance t ca = case-to-ambient thermal resistance *t ca will depend on the board design and the placement of the part. t je = p e * ( q lc // q ld + q dc ) + q ca ) + p d * [ + q ca ] + t a q lc * q dc q lc + q dc + q ld t jd = p e * [ + q ca ] + p d * ( q lc // q ld + q dc ) + q ca ) + t a q lc * q dc q lc + q dc + q ld
14 figure 28. optocoupler input to output capacitance model for unshielded optocouplers. figure 29. optocoupler input to output capacitance model for shielded optocouplers. figure 30. equivalent circuit for figure 25 during common mode transient. cmr with the led on (cmr h ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by over-driving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. a minimum led current of 10 ma provides adequate margin over the maximum i flh of 8 ma to achieve 10 kv/s cmr. led drive circuit considerations for ultra high cmr performance without a detector shield, the dominant cause of op - tocoupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 28. the HCPL-3180 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the ca - pacitive coupling between the led and optocoupler pins 5-8 as shown in figure 29. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or of ) during common mode tran - sients. for example, the recommended application circuit (figure 25), can achieve 10 kv/s cmr while minimizing component complexity. techniques to keep the led in the proper state are dis - cussed in the next two sections. 1 3 2 4 8 6 7 5 c ledp c ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield c ledo1 c ledo2 r g 1 3 v sat 2 4 8 6 7 5 + v cm i ledp c ledp c ledn shield * the arrows indicate the direction of current flow during ?dv cm /dt. +5 v + ? v cc = 20 v ? ? ? ? ? ? 0.1 f + ? ? cmr with the led of (cmr l ) a high cmr led drive circuit must keep the led of (v f f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 30, the current fowing through c ledp also fows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) , the led will remain of and no common mode failure will occur. the open collector drive circuit, shown in figure 31, cannot keep the led of during a +dv cm /dt transient, since all the current fowing through c ledn must be supplied by the led, and it is not recommended for ap - plications requiring ultra high cmr l performance. figure 32 is an alternative drive circuit, which like the recom - mended application circuit (figure 25), does achieve ultra high cmr performance by shunting the led in the of state.
figure 31. not recommended open collector drive circuit. figure 32. recommended led drive circuit for ultra-high cmr. figure 33. under voltage lock out. under voltage lockout feature the HCPL-3180 contains an under voltage lockout (uvlo) feature that is designed to protect the igbt under fault conditions which cause the HCPL-3180 supply voltage (equivalent to the fully charged igbt gate voltage) to drop below a level necessary to keep the igbt in a low resistance state. when the HCPL-3180 output is in the high state and the supply voltage drops below the hcpl- 3180 v uvlo- threshold (typ 7.5 v) the optocoupler output will go into the low state. when the HCPL-3180 output is in the low state and the supply voltage rises above the HCPL-3180 v uvlo+ threshold (typ 8.5 v) the optocoupler output will go into the high state (assume led is on). ipm dead time and propagation delay specifcations the HCPL-3180 includes a propagation delay diference (pdd) specifcation intended to help designers minimize dead time in their power inverter designs. dead time is the time during which the high and low side power tran - sistors are of. any overlap in q1 and q2 conduction will result in large currents fowing through the power devices from the high voltage to the low-voltage motor rails. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn of of led1) so that under worst-case conditions, transistor q1 has just turned of when transistor q2 turns on, as shown in figure 34. the amount of delay necessary to achieve this condition is equal to the maximum value of the propa - gation delay diference specifcation, pdd max , which is specifed to be 90 ns over the operating temperature range of -40 c to +100 c. figure 34. minimum led skew for zero dead time. 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v q1 i ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v v o ? output voltage ? v 0 0 (v cc - v ee ) ? supply voltage ? v 10 5 20 14 16 18 10 15 2 20 6 8 4 12 t phl max t plh min pdd* max = (t phl - t plh ) max = t phl max - t plh min *pdd = propagation delay difference note: for pdd calculations, the propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on
figure 35. waveforms for dead time. delaying the led signal by the maximum propagation delay diference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the diference between the maximum and minimum propagation delay diference specifcation as shown in figure 35. the maximum dead time for the HCPL-3180 is 180 ns (= 90 ns-(- 90 ns)) over the operating temperature range of C40 c to +100 c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts. t plh min maximum dead time (due to optocoupler) = (t phl max - t phl min ) + (t plh max - t plh min ) = (t phl max - t plh min ) ? (t phl min - t plh max ) = pdd* max ? pdd* min v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on t phl min t phl max t plh max pdd* max (t phl- t plh ) max *pdd = propagation delay difference note: for dead time and pdd calculations, all propagation delays are taken at the same temperature and test conditions. for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. av02-0165en - march 10, 2009

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