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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 1 ?2002, micron technology inc. 32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance ? small-outline syncflash ? module mt8lsft3232(r)h, mt8lsft3264(r)h, mt8lsft32128(r)h for the latest data sheet, please refer to the micron web- site: www.micron.com/syncflash features ? pc100 and pc133 sdram-compatible read timing jedec-standard form factor, 144-pin, small-outline, dual in-line memory module (sodimm) utilizes 133 mhz syncflash/sdram components unbuffered 32mb (4 meg x 64) syncflash memory + 32mb, 64mb, or 128mb sdram single +3.3v 0.3v power supply fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access programmable burst lengths lvttl-compatible inputs and outputs serial presence-detect (spd) package: 144-pin sodimm (gold) . 144-pin small-outline dimm note: 1. (r) specifies on-board reset controller. 2. all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult fac- tory for current revision codes. example: mt8lsft32128(r)h-13ea1 . 3. all modules have 32mb syncflash. general description the mt8lsft3232(r)h, mt8lsft3264(r)h, and mt8lsft32128(r)h are syncflash/sdram-based memory modules organized in a x64 configuration. these modules use internally configured quad-bank syncflash/sdram devices with a synchronous inter- face (all signals are registered on the positive edge of the clock signals ck0?ck1). read accesses to the syncflash/sdram module are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, followed by a read or write command. the address bits registered coinci- dent with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank, options marking on-board reset controller r frequency/cas latency 133 mhz/cl = 2 133 mhz/cl = 3 -13e -133 timing parameters module marking pc133 (cl - t rcd - t rp) pc100 (cl - t rcd - t rp) -13e 2 - 3 - 2 2 - 3 - 2 -133 3 - 4 - 3 2 - 3 - 2 address table 32mb syncflash 32mb sdram 64mb sdram 128mb sdram refresh count 4k 4k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) device configuration 4 meg x 16 8 meg x 16 16 meg x 16 row addressing 4k (a0?a11) 4k (a0?a11) 8k (a0?a12) column addressing 256 (a0?a7) 512 (a0?a8) 512 (a0?a8) part numbers part number 1, 2 config. 3 version mt8lsft3232(r)h-13e__ 32mb sdram 133 mhz, cl = 2 mt8lsft3232(r)h-133__ 32mb sdram 133 mhz, cl = 3 mt8lsft3264(r)h-13e__ 64mb sdram 133 mhz, cl = 2 mt8lsft3264(r)h-133__ 64mb sdram 133 mhz, cl = 3 mt8lsft32128(r)h-13e__ 128mb sdram 133 mhz, cl = 2 mt8lsft32128(r)h-133__ 128mb sdram 133 mhz, cl = 3
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 2 ?2002, micron technology inc. a0?a11 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the syncflash modules provide for programmable read and write burst lengths of 1, 2, 4, or 8 loca- tions, or the full page (sdram only), with a burst ter- minate option. these syncflash/sdram modules use an internal pipelined architecture to achieve high-speed opera- tion. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. these modules are designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs, outputs, and clocks are lvttl-compatible. syncflash modules offer substantial advances in flash operating performance, including the ability to synchronously burst data at a high data rate with auto- matic column-address generation, the ability to inter- leave between internal banks, and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding syncflash operation, refer to the 64mb, x16 syncflash data sheet. serial presence-det ect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. these nonvolatile storage devices contain 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various syncflash orga- nizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals. syncflash initialization options the syncflash device must be powered up and ini- tialized in a predefined manner. operational proce- dures other than those specified may result in undefined operation. initializing module without on-board reset controller systems that do not have an rp# signal can initialize syncflash memory through software. using the ini- tialize device command, the rp# pin does not require the low-to-high transition that would other- wise be required for initialization. after the initialize device command has been issued, the power-up ini- tialization process will complete within 100s. refer to the mt28s4m16b1lc data sheet for details on soft- ware command sequences. for systems that have an rp# signal, rp# must be brought from low to high. a 100s delay is required after rp# transitions high to complete internal device initialization. initializing module with on-board reset controller for systems that do not have an rp# signal, an optional on-board reset controller is used to fully auto- mate the reset of the syncflash devices after power-up. the rp# line is held low for 10ms after v dd reaches 2.85v (see figure 1). the syncflash devices will be ready for normal operation 100s after the rp# line goes high. figure 1: on-board reset operation rp# 10ms dimm operational v cc
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 3 ?2002, micron technology inc. pin assignment (front view) pin front pin back pin front pin back 1v ss 2v ss 73 rp# 74 ck1 3 dq0 4 dq32 75 v ss 76 v ss 5 dq1 6 dq33 77 nc 78 nc 7 dq2 8 dq34 79 nc 80 nc 9 dq3 10 dq35 81 v dd 82 v dd 11 v dd 12 v dd 83 dq16 84 dq48 13 dq4 14dq3685dq1786dq49 15 dq5 16dq3787dq1888dq50 17 dq6 18dq3889dq1990dq51 19 dq7 20 dq39 91 v ss 92 v ss 21 v ss 22 v ss 93 dq20 94 dq52 23dqmb024dqmb4 95 dq21 96 dq53 25dqmb126dqmb5 97 dq22 98 dq54 27 v dd 28 v dd 99 dq23 100 dq55 29 a0 30 a3 101 v dd 102 v dd 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 v ss 36 v ss 107 v ss 108 v ss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 v dd 114 v dd 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 v dd 46 v dd 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 v ss 120 v ss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 v ss 56 v ss 127 dq27 128 dq59 57 nc 58 nc 129 v dd 130 v dd 59 nc 60 nc 131 dq28 132 dq60 61 ck0 62 cke0 133 dq29 134 dq61 63 v dd 64 v dd 135 dq30 136 dq62 65 ras# 66 cas# 137 dq31 138 dq63 67 we# 68 cke1 139 v ss 140 v ss 69 s0# 70 a12 141 sda 142 scl 71 s1# 72 rfu (a13) 143 v dd 144 v dd note: symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only.
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 4 ?2002, micron technology inc. functional block diagram (32mb syncflash with 32mb/64mb/128mb sdram) u1?u4 = mt48lc4m16a2tg sdram for 32mb u1?u4 = mt48lc8m16a2tg sdram for 64mb u1?u4 = mt48lc16m16a2tg sdram for 128mb u5?u8 = mt28s4m16b1lctg syncflash for 32mb dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmh u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s0# ras# cas# cke0 cke1 we# ras#: syncflash, sdram u1?u8 cas#: syncflash, sdram u1?u8 cke: sdram u1?u4 cke: syncflash u5?u8 we#: syncflash, sdram u1?u8 a0?a11: syncflash, sdram u1?u8 a0?a12: syncflash, sdram u1?u8 ba0?ba1: syncflash, sdram u1?u8 a0?a11 (32mb, 64mb) a0?a12 (128mb) ba0?ba1 v dd v ss syncflash, sdram u1?u8 syncflash, sdram u1?u8 ck0 u1 u2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb1 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb3 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmh u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb5 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmh u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb7 s0# u3 u4 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmh u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s1# dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb1 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb3 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmh u7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb5 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmh u8 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb7 s1# ck1 u5 u6 u7 u8 a0 spd scl sda a1 a2 rp# rp# rp# rp# rp# rp# rp#: syncflash u5?u8 v dd rp# s0# s1# cs#: sdram u1?u4 cs#: syncflash u5?u8,
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 5 ?2002, micron technology inc. pin descriptions pin numbers symbol type description 65?67 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s0#) define the command being entered. 61, 74 ck0, ck1 input clock: ck0 and ck1 are driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and controls the output registers. 62, 68 cke0, cke1 input clock enable: cke0 and cke1 activate (high) and deactivate (low) the ck0?ck1 signals. deactivating the clock provides power-down and self refresh operation (all banks idle) or clock suspend operation (burst access in progress). cke0 and cke1 are synchronous except after the device enters power-down and self refresh modes, where cke0 and cke1 become asynchronous until after exiting the same mode. the input buffers, including ck0?ck1, are disabled during power-down and self refresh modes, providing low standby power. 69, 71 s0#, s1# input chip select: s0# and s1# enable (registered low) and disable (registered high) the command decoder. all commands are masked when s0# and s1# are registered high. s0# and s1# are considered part of the command code. 23?26, 115?118 dqmb0? dqmb7 input input mask: dqmb is an input mask signal for write accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (after a two-clock latency) when dqmb is sampled high during a read cycle. 106, 110 ba0, ba1 input bank address: ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. ba0 is also used to program the twelfth bit of the mode register. 29?34, 103?105, 109, 111, 112, 70 (128mb) a0?a11 (32mb, 64mb) a0?a12 (128mb) input address inputs: a0?a11/a12 are sampled during the active command (row address a0?a11/a12) and read write command (column address a0?a7/ a8), to select one location out of the memory array in the respective bank. the address inputs provide the op-code during load mode register command and the operation code during a load command register command. 142 scl input serial clock for presence-detect: scl is used to synchronize the presence- detect data transfer to and from the module. 73 rp# input device initialize: rp# must be held high during normal operation (not reset). when rp# = v hh , all protection modes are ignored during program and erase. 3?10, 13?20, 37?44, 47?54, 83?90, 93?100, 121?128, 131?138 dq0?dq63 input/ output data i/os: data bus. 141 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 11, 12, 27, 28, 45, 46, 63, 64, 81, 82, 101, 102, 113, 114, 129, 130, 143, 144 v dd supply power supply: +3.3v 0.3v.
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 6 ?2002, micron technology inc. 1, 2, 21, 22, 35, 36, 55, 56, 75, 76, 91, 92, 107,108, 119, 120, 139, 140 v ss supply ground. 57, 58, 59, 60, 77, 78, 79, 80 nc no connect these pins should be left unconnected. 72 rfu ? reserved for future use: this pin should be left unconnected. pin descriptions (continued) pin numbers symbol type description
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 7 ?2002, micron technology inc. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (fig- ures 2 and 3). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. figure 2: data validity spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 4). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode, the spd device will transmit eight bits of data, release the sda line, and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is gen- erated by the master, the slave will continue to trans- mit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. figure 3: definition of start and stop figure 4: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 8 ?2002, micron technology inc. serial presence-detect matrix (notes: 1, 2) byte description entry (version) mt8lsft 3 0 number of bytes used by micron 128 80 1 total number of spd memory bytes 256 08 2 memory type syncflash + sdram 24 3 syncflash/sdram number of row addresses 32mb/32mb 32mb/64mb 32mb/128mb 0c cc cd 4 syncflash/sdram number of column addresses 32mb/32mb 32mb/64mb 32mb/128mb 08 89 89 5 number of module banks 202 6 module data width 64 40 7 module data width (continued) 000 8 module voltage interface levels lvttl 01 9 syncflash/sdram cycle time, t ck (cas latency = 3) 7 (-13e) 7.5 (-133) 70 75 10 syncflash/sdram acce ss from clock, t ac (cas latency = 3) 5.4(-13e/-133) 54 11 module configuration type nonparity 00 12 sdram refresh rate/type 15.6s/self 7.81s/self (128mb) 80 82 13 sdram device width 16 10 14 error-checking syncflash data width none 00 15 minimum clock delay, t ccd 101 16 syncflash/sdram burst lengths supported (read only) 1, 2, 4, 8, page 8f 17 number of banks on syncflash/sdram device 404 18 cas latencies supported 2, 3 06 19 cs latency 001 20 we latency 001 21 syncflash/sdram module attributes unbuffered 00 22 syncflash/sdram device attributes: general 0e 0e 23 syncflash/sdram cycle time, t ck (cas latency = 2) 7.5 (-13e) 10 (-133) 75 a0 24 syncflash/sdram access from clk, t ac (cas latency = 2) 5.4 (-13e) 6 (-133) 54 60 25 syncflash/sdram cycle time, t ck (cas latency = 1) ?00 26 syncflash/sdram access from clk, t ac (cas latency = 1) ?00 27 sdram: minimum row precharge time, t rp 15 (-13e) 20 (-133) 0f 14 28 minimum row active to row active, t rrd 14 (-13e) 15 (-133) 0e 0f 29 minimum ras# to cas# delay, t rcd 22 (-13e) 25 (-133) 16 19
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 9 ?2002, micron technology inc. note: 1. ?1?/?0?: serial data, ?driven to high?/?driven to low.? 2. x = variable data. 3. values are in hexadecimal. 4. dimm memory mix: 0 (bank 0 = syncflash, bank 1 = unpopulated); 1 (bank 0 = syncflash, bank 1 = syncflash); 2 (bank 0 = sdram, bank 1 = syncflash). 30 minimum ras# pulse width, t ras 45 (-13e) 45 (-133) 2d 2d 31 density of each bank on module 32mb/32mb 64mb/32mb 128mb/32mb 08 18 28 32 command and address setup time 1.5 (-13e/-133) 15 33 command and address hold time 0.8 (-13e/-133) 08 34 data signal input setup time 1.5 (-13e/-133) 15 35 data signal input hold time 0.8 (-13e/-133) 08 36?61 reserved ?00 62 spd revision 1.2 (-13e/-133) 12 63 checksum for bytes 0?62 -13e -133 tbd 64 manufacturer?s jedec id code micron 2c 65?71 manufacturer?s jedec id code (cont.) ?00 72 manufacturing location ?01 02 03 04 05 06 73?90 module part number (ascii) ?x 91 pcb identification code 1 2 3 4 01 02 03 04 92 identification code (cont.) 000 93 year of manufacture in bcd ?00 94 week of manufacture in bcd ?00 95?98 module serial number x00 99 memory mix 4 sdram + syncflash 02 100?125 manufacturer-specific data (rsvd) ?00 126 system frequency 100 mhz/ 133 mhz 64 127 syncflash/sdram component and clock detail cf cf serial presence-detect matrix (continued) (notes: 1, 2) byte description entry (version) mt8lsft 3
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 10 ?2002, micron technology inc. commands truth table 1 provides a quick reference of available commands for sdram-compatible operation. for a more detailed description of commands and opera- tions, refer to the syncflash and sdram data sheets. note: 1. cke is high for all commands shown. 2. a0?a11 provide row address, and ba0 and ba1 determine which bank is made active. 3. a0?a7 provide column address, and ba0 and ba1 dete rmine which bank is being read from or written to. 4. a program setup command sequence (see mt28s4m16b1lc data sheet) must be completed prior to executing a write. 5. active terminate is functionally equivalent to the sdram precharge command; however, precharge (deacti- vate row in bank or banks) is not required for syncflash memory. a10 low: ba0 and ba1 determine the bank to be active terminated. a10 high: all banks are active terminated and ba0 and ba1 are ?don?t care.? 6. a0?a7 define the com-code, and a8?a11 are ?don?t care? for this operation. see mt28s4m16b1lc data sheet. 7. load command register (lcr) replaces the sdram auto re fresh or self refresh mode, which is not required for syncflash memory. see mt28s4m16b1lc data sheet. 8. a0?a11 define the op-code written to the mode register. the mode register can be dynamically loaded each cycle, provided t mrd is satisfied. the default mode register value is stored in the nvmode register. the contents of the nvmode register are automatically loaded into the mode register during device initialization. 9. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). truth table 1 sdram-compatible interface commands and dqm operation (note: 1) name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) hxxxxxx no operation (nop) l hhhxxx active (select bank and activate row) llhhxbank/ row x2 read (select bank, column, and start read burst) lhlhxbank/ col x3 write (select bank, column, and start write) lhl lxbank/ col valid 3, 4 burst terminate lhhlxxactive active terminate/precharge l lhlxxx5 load command register/refresh lllhxcom- code x6, 7 load mode register llllxop- code x8 write enable/output enable ????l?active9 write inhibit/output high-z ????h?high-z9
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 11 ?2002, micron technology inc. figure 5: mode register definition note: 1. for a burst length of two, a1?a7 select the block- of-two burst; a0 selects th e starting column within the block. 2. for a burst length of four, a2?a7 select the block- of-four burst; a0?a1 select the starting column within the block. 3. for a burst length of eight, a3?a7 select the block- of-eight burst; a0?a2 select the starting column within the block. 4. for a full-page burst, the full row is selected and a0?a7 select the starting column. 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0?a7 select the unique column to be accessed, and mode register bit m3 is ignored. 7. burst write of 1, 2, 4, or 8 dwords is supported (not full page). 8. the contents of the mode register can be read using the read device configuration com- mand (004h). m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved m6 0 0 0 0 1 1 1 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 burst length burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 10 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *program m11, m10 = ?0, 0? to ensure compatibility with future devices. table 1: burst definition table burst length starting column address order of accesses within a burst ty pe = sequential ty pe = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0?a7 (location 0?y) cn, cn+1, cn+2 cn+3, cn+4... ?cn-1, cn? not supported
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 12 ?2002, micron technology inc. absolute maximum ratings* voltage on rp# relative to v ss ....................... -1v to +9v voltage on v dd supply relative to v ss ....... -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss .......................................... -1v to +4.6v operating temperature, t a (ambient)....... 0c to +70c storage temperature (plastic) ............... -55c to +125c power dissipation ....................................................... 8w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up. 3. v ih overshoot: v ih (max) = v dd + 2v for a pulse width 10ns, and the pulse width cannot be greater than one-third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one-third of the cycle rate. 4. ck0 = 20a. dc electrical characteristics and operating conditions (notes: 1, 2) v dd = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd 33.6v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 3 input low voltage: logic 0; all inputs v il -0.3 0.8 v 3 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) ck0, ck1, s0#, s1#, cke0, cke1 i i 1-2020a 4 ras#, cas#, we#, ba0, ba1, a0?a11 i i 2-4040a dqmb0?dqmb7 i i 3-5 5a output leakage current: dqs are disabled; 0v v out v dd dq0?dq63 i oz -40 40 a output levels: output high voltage (i out = -4ma) output low voltage (i out = 4ma) v oh 2.4 ? v v ol ?0.4v hardware protect voltage (rp# only) v hh 7.0 8.5 v
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 13 ?2002, micron technology inc. *dram components only. a - value calculated as one module bank in this operating condition, and all other module banks in power-down mode. b - value calculated reflects all module banks in this operating condition. i dd specifications and conditions (syncflash) (notes: 1, 2, 3; notes appear following the parameter tables); commercial temperature (0oc t a +70oc); v dd = +3.3v 0.3v parameter/condition symbol max units notes -13e -133 operating current: active mode; burst = 2; read; t rc = t rc (min); cas latency = 3 i ddr 1 500 480 ma 4, 5, 6 operating current: burst mode; continuous burst; all banks active; read; cas latency = 3 i ddr 2 320 280 ma 4, 5, 6 standby current: active mode; cs# = high; cke = low; all banks active; no burst in progress i dds 1 200 200 ma standby current: power-down mode; cke = low; no burst in progress i dds 28 8ma deep power-down current: rp# = v ss 0.2v i dddp 400 400 a program current i ddw 240 240 ma erase current i dde 320 320 ma i dd specifications and conditions* (32mb sdram) (notes: 1, 15, 16, 17, 18; notes appear following the parameter tables); v dd , v dd q = +3.3v 0.3v parameter/condition symbol max units notes -13e -133 operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 a 500 460 ma 8, 11, 12, 13 standby current: power-down mode; all banks idle; cke = low i dd 2 b 88ma13 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3 a 180 180 ma 8, 11, 12, 13 operating current: burst mode; continuous burst; read or write; all banks active i dd 4 a 600 560 ma 8, 11, 12, 13 auto refresh current t rfc = t rfc (min) i dd 5 b 920 840 ma 8, 10, 11, 12, 13, 14 cs# = high; cke = high t rfc = 15.625s i dd 6 b 12 12 ma self refresh current: cke 0.2v i dd 7 b 44ma9
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 14 ?2002, micron technology inc. *dram components only. a - value calculated as one module bank in this operating condition, and all other module banks in power-down mode. b - value calculated reflects all module banks in this operating condition. . i dd specifications and conditons* (64mb sdram) (notes: 1, 15, 16, 17, 18; notes appear following the parameter tables); v dd , v dd q = +3.3v 0.3v parameter/condition symbol max units notes -13e -133 operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 a 508 468 ma 8, 11, 12, 13 standby current: power-down mode; all banks idle; cke = low i dd 2 b 88ma13 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3 a 188 188 ma 8, 11, 12, 13 operating current: burst mode; continuous burst; read or write; all banks active i dd 4 a 608 568 ma 8, 11, 12, 13 auto refresh current cs# = high; cke = high t rfc = t rfc (min) i dd 5 b 920 840 ma 8, 10, 11, 12, 13, 14 t rfc = 15.625s i dd 6 b 12 12 ma self refresh current: cke 0.2v i dd 7 b 44ma9 i dd specifications and conditons* (128mb sdram) (notes: 1, 15, 16, 17, 18; notes appear following the parameter tables); v dd , v dd q = +3.3v 0.3v parameter/condition symbol max units notes -13e -133 operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 a 648 608 ma 8, 11, 12, 13 standby current: power-down mode; all banks idle; cke = low i dd 2 b 88ma13 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3 a 208 208 ma 8, 11, 12, 13 operating current: burst mode; continuous burst; read or write; all banks active i dd 4 a 668 608 ma 8, 11, 12, 13 auto refresh current t rfc = t rfc (min) i dd 5 b 1320 1240 ma 8, 10, 11, 12, 13, 14 cs# = high; cke = high t rfc = 7.8s i dd 6 b 12 12 ma self refresh current: cke 0.2v i dd 7 b 88ma9
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 15 ?2002, micron technology inc. capacitance parameter symbol -13e -133 units notes min max min max input capacitance: s0#, s1#, cke0, cke1, ck0, ck1 c i 122342234pf 7 input capacitance: all other input-only pins c i 212181218pf 7 input capacitance: dqmb0#?dqmb7# c i 37 10 4 6 pf 7 input/output capacitance: dq0?dq63 c io 110156 8pf7
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 16 ?2002, micron technology inc. *specifications for the syncflash/sdram components used on the module. syncflash/sdram component* ac electrical characteristics (notes: 19?22; notes appear following the parameter tables) commercial temperature (0oc t a +70oc); v dd = +3.3v 0.3v ac characteristics -13e -133 parameter symbol min max min max units notes access time from clk (positive edge) cl = 3 t ac 5.4 5.4 ns cl = 2 t ac 5.4 6 ns address hold time t ah 0.8 0.8 ns address setup time t as 1.5 1.5 ns clk high-level width t ch 2.5 2.5 ns clk low-level width t cl 2.5 2.5 ns clock cycle time cl = 3 t ck 7 7.5 ns 24 cl = 2 t ck 7.5 10 ns 24 cke hold time t ckh 0.8 0.8 ns cke setup time t cks 1.5 1.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 ns 23 cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 ns 23 data-in hold time t dh 0.8 0.8 ns data-in setup time t ds 1.5 1.5 ns data-out high-z time cl = 3 t hz 5.4 5.4 ns 25 cl = 2 t hz 5.4 6 ns 25 data-out low-z time t lz 1 1 ns data-out hold time (load) t oh 3 3 ns data-out hold time (no load) t ohn 1.8 1.8 ns 26 active to active command period t rc 60 66 ns active to read or write delay t rcd 22.5 25 ns active bank a to active bank b command t rrd 14 15 ns transition time t t 0.3 1.2 0.3 1.2 ns 27 sdram component* ac electrical characteristics (notes: 19?22; notes appear following the parameter tables) commercial temperature (0oc t a +70oc); v dd = +3.3v 0.3v ac characteristics -13e -133 parameter symbol min max min max units notes active to precharge command t ras 37 120,000 44 120,000 ns active to read or write delay t rcd 15 20 ns refresh period (4,096 and 8,192 rows) t ref 64 64 ns auto refresh period t rfc 66 66 ns precharge command period t rp 15 20 ns 28 write recovery time t wr 1 ck + 7.5ns 1 ck + 7.5ns ? 14 15 exit self refresh to active command t xsr 67 75 ns 29
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 17 ?2002, micron technology inc. syncflash/sdram ac functional characteristics (notes: 19?22; notes appear following the parameter tables) commercial temperature (0oc t a +70oc); v dd = +3.3v 0.3v parameter symbol -13e -133 units notes read/write command to read/load command register t ccd 1 1 t ck 30 cke to clock disable or power-down entry mode t cked 1 1 t ck 31 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 30 dqm to input data delay t dqd 0 0 t ck 30 dqm to data mask during writes t dqm 0 0 t ck 30 dqm to data high-z during reads t dqz 2 2 t ck 32 write command to input data delay t dwd 0 0 t ck 30 data-in to active command t dal 4 5 t ck 33 data-in to active terminate command t dpl 2 2 t ck 33 load mode register command to active command t mrd 2 2 t ck last data-in to active terminate command t rdl 2 2 t ck 33 sdram ac functional characteristics (notes: 19?22; notes appear following the parameter tables) commercial temperature (0oc t a +70oc); v dd = +3.3v 0.3v parameter symbol -13e -133 units last data-in to burst stop command t bdl 4 5 t ck last data-in to new read/write command t cdl 2 2 t ck data-out to high-impedance from precharge command cl = 3 t roh(3) 2 2 t ck cl = 2 t roh(2) 2 2 t ck
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 18 ?2002, micron technology inc. serial presence-detect eeprom dc operating conditions (note: 1) v dd = +3.3v 0.3v parameter/condition symbol min max units supply voltage v dd 33.6v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% i sb ?30a power supply current: scl clock frequency = 100 khz i dd ?2ma serial presence-detect eeprom ac operating conditions (note: 1) v dd = +3.3v 0.3v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 s start condition hold time t hd:sta 4 s clock high period t high 4 s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 34
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 19 ?2002, micron technology inc. notes 1. all voltages referenced to v ss . 2. an initial pause of 200ms is required after power- up. (v cc and v cc q must be powered up simulta- neously. v ss and v ss q must be at same potential.) 3. i dd specifications are tested after the device is properly initialized. 4. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 5. the i dd current will decrease as the cas latency is reduced. this is because the maximum cycle rate is slower as the cas latency is reduced. 6. address transitions average one transition every 30ns. 7. this parameter is sampled. v cc = v cc q; f = 1 mhz, t a = +25 o c. 8. i dd is dependent on output loading and cycle rates. specified values are obtained with mininum cycle time and the outputs open. 9. enables on-chip refresh and address counters. 10. other input signals are allowed to transition no more than once every two clocks and are other- wise at valid v ih or v il levels. 11. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 12. address transitions average one transition every two clocks. 13. for -13e, cl = 2 and t ck = 7.5ns; for -133, cl = 3 and t ck = 7.5ns. 14. cke is high during refresh command period t rfc (min), else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 15. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0 o c t a +70 o c for commercial). 16. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at the same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 17. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the isv crossover point. refer to technical note, tn-48-09, ?lvttl derat- ing for sdram slew rate violations,? for addi- tional information on sdram timing. 18. i dd specifications are tested after the device is properly initialized. 19. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 o c t a +70 o c) is ensured. 20. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 21. outputs measured at 1.5v with equivalent load: 22. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 23. 3ns < t pdl < 5ns. 24. the clock frequency must remain constant during access or precharge states (read and write commands). cke may be used to reduce the data rate. 25. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 26. parameter guaranteed by design. 27. ac characteristics assume t t = 1ns. 28. auto precharge mode only. the precharge timing budget ( t rp) begins 7.5ns/7ns after the first clock delay, after the last write is executed. 29. clk must be toggled a minimum of two times during this period. 30. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 31. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 32. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 33. based on t ck = 133 mhz. 34. timing actually specified by t wr. q 50pf
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 20 ?2002, micron technology inc. spd eeprom timing diagram scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined serial presence-detect timing parameters symbol min max units t aa 0.3 3.5 s t buf 4.7 s t dh 300 ns t f 300 ns t hd:dat 0s t hd:sta 4s t high 4s t low 4.7 s t r 1s t su:dat 250 ns t su:sta 4.7 s t su:sto 4.7 s serial presence-detect timing parameters symbol min max units
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, syncflash, and the micron and m logos are trademarks and/or service marks of micron technology, inc. 32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm ?2002, micron technology inc. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 21 144-pin sodimm (32mb syncflash/32mb, 64mb, 128mb sdram) note: all dimensions in inches (millimet ers) or typical where noted. data sheet designation advance: this datasheet contains initial descriptions of products still under development. .150 (3.80) max .043 (1.10) .035 (0.90) 1.255 (31.88) 1.245 (31.62) pin 1 2.666 (67.72) 2.656 (67.45) .787 (20.00) typ .071 (1.80) (2x) 2.386 (60.60) .0315 (.80) typ .130 (3.30) (2x) .024 (.60) typ .079 (2.00) r (2x) pin 143 (pin 144 on backside) front view .079 (2.00) .236 (6.00) 2.504 (63.60) .100 (2.55) .059 (1.50) typ .157 (4.00) max min
32mb syncflash/ 32mb, 64mb, 128mb sdram sodimm advance 32mb syncflash/32mb, 64mb, 128mb sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. mt8lsft32_128(r)h_3.fm - rev.3, pub. 9/02 22 ?2002, micron technology inc. revision history rev. 3, advance............................................................................................................... .............................................8/02 changed timing parameters t rcd updated the serial presence-detect matrix rev. 2, advance............................................................................................................... .............................................5/02 updated general description and initializing module with on-board reset controller text updated rp# text in pin description table original document, rev. 1, advance ............................................................................................ .............................4/02

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