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1 description the cat24fc32 is a 32-kb serial cmos eeprom internally organized as 4k x 8 bits. the device is compatible with the fast-mode i 2 c bus specification and operates down to 1.8 v at up to 400 khz and 1 mhz at v cc 2.5 v. extended addressing capability allows up to 8 devices to share the same bus. catalyst's advanced cmos technology substantially reduces device power * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. requirements. the device is optimized for high performance applications, where low power, low voltage and high speed operation are required. the cat24fc32 is available in 8-pin dip, 8-pin soic (jedec and eiaj) and 8-pin tssop packages. pin configuration block diagram cat24fc32 32-kb fast mode i 2 c serial cmos eeprom fast mode i 2 c bus compatible* max clock frequency: 400 khz for v cc = 1.8 v to 3.6 v 1 mhz for v cc = 2.5 v to 3.6 v hardware write protect for entire array cascadable for up to eight devices 32-byte page or byte write modes self-timed write cycle with autoclear 5 ms max write cycle time features dip package (p) soic package (j,k) ? 2003 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1020, rev. i v cc wp scl sda 1 2 3 4 8 7 6 5 a 0 v cc wp scl sda 1 2 3 4 8 7 6 5 a 1 a 2 v ss a 0 a 1 a 2 v ss 8 7 6 5 1 2 3 4 a 0 a 1 a 2 v ss v cc wp scl sda tssop package (u) d out ack sense amps shift registers control logic word address buffers start/stop logic state counters slave address comparators eeprom 128 x 256 v cc external load column decoders xdec data in storage high voltage/ timing control v ss wp scl a 0 a1 a2 sda 128 256 random and sequential read modes schmitt trigger inputs zero standby current industrial and extended temperature ranges 1,000,000 program/erase cycles 100 years data retention 8-pin pdip, 8-pin soic (150 and 200 mil) and 8-pin tssop packages h a l o g e n f r e e tm l e a d f r e e
cat24fc32 2 doc. no. 1020, rev. i note: (1) the minimum dc input voltage is C0.5 v. during transitions, inputs may undershoot to C2.0 v for periods of less than 20 ns. maximum dc voltage on output pins is v cc + 0.5 v, which may overshoot to v cc + 2.0 v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1 v to v cc + 1 v. absolute maximum ratings* temperature under bias ................. C55 c to +125 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ............ C2.0 v to v cc + 2.0 v v cc with respect to ground ............. C2.0 v to +7.0 v package power dissipation capability (t a = 25 c) .................................. 1.0 w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ....................... 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. pin functions pin name function a0, a1, a2 device address inputs sda serial data/address scl serial clock wp write protect v cc power supply v ss ground reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 supply voltage range device 1.8 v to 3.6 v cat24fc32 recommended operating conditions temperature range minimum maximum industrial -40?c +85?c automotive -40?c +105?c extended -40?c +125?c
cat24fc32 3 doc. no. 1020, rev. i symbol parameter min typ max units test conditions i li input leakage current (4) -10 10 av in = gnd to v cc i lo output leakage current (4) -10 10 av in = gnd to v cc i cc1 power supply current 3 ma f scl = 400 khz (operating write) v cc = 3.6 v i cc2 power supply current 400 af scl = 400 khz (operating read) v cc = 3.6 v i sb (1) standby current 0 av cc = 3.6 v v in = gnd or v cc v il (2) input low voltage -0.5 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v 2.5 v v cc 3.6 v i ol = 3.0 ma v ol2 output low voltage 0.2v cc v 1.8 v v cc < 2.5 v i ol = 3 ma d.c. operating characteristics over recommended operating conditions, unless otherwise specified note: (1) standby current, i sb < 900 na; a0, a1, a2, wp connected to gnd; scl, sda = gnd or vcc. (2) v il min and v ih max are reference values only and are not tested. (3) this parameter is characterized initially and after a design or process change that affects the parameter. not 100% tested. (4) i/o pins, sda and scl do not obstruct the bus lines if v cc is switched off. capacitance t a = 25 c, f = 1.0 mhz, v cc = 3.6 v symbol test max. units conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a0, a1, a2, scl, wp) 6 pf v in = 0v
cat24fc32 4 doc. no. 1020, rev. i note: (1) test conditions according to "ac test conditions" table. (2) this parameter is characterized initially and after a design or process change that affects the parameter. not 100% tested. (3) the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cy cle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high and the device does not respond to its slav e address. (4) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. a.c. characteristics over recommended operating conditions, unless otherwise specified (note 1). read & write cycle limits symbol parameter 1.8 v - 3.6 v 2.5 v - 3.6 v units min max min max f scl clock frequency 400 1,000 khz t sp input filter spike 50 50 ns suppression (sda, scl) t low clock low period 1.3 0.6 s t high clock high period 0.6 0.4 s t r (2) sda and scl rise time 20 300 20 300 ns t f (2) sda and scl fall time 20 300 20 100 ns t hd:sta start condition hold time 0.6 0.25 s t su:sta start condition setup time 0.6 0.25 s (for a repeated start) t hd:dat data input hold time 0 0 ns t su:dat data in setup time 100 50 ns t su:sto stop condition setup time 0.6 0.25 s t su:wp wp setup time 0 0 s t hd:wp wp hold time 2.5 1 s t aa scl low to data out valid 900 550 ns t dh data out hold time 50 50 ns t buf (2) time the bus must be free before 1.3 0.5 s a new transmission can start t of (2) output fall time from v ih min to 20 250 20 100 ns v il max t wc (3) write cycle time (byte or page) 5 5 ms power-up timing (2)(4) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms
cat24fc32 5 doc. no. 1020, rev. i ac test conditions input pulse voltages v cc x 0.2 to v cc x 0.8 input rise and fall times 50 ns input reference voltages v cc x 0.3, v cc x 0.7 output reference voltage v cc x 0.5 output load current source: i ol = 3 ma; cl: 400 pf for f scl max = 400 khz & 100 pf for f scl max = 1 mhz figure 3. write cycle timing figure 2. wp timing figure 1. bus timing t wr stop condition start condition address ack 8th bit byte n scl sda 1891 8 a 7 a 0 d 7 d 0 t su:wp t hd:wp 2nd byte address data scl sda wp t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh
cat24fc32 6 doc. no. 1020, rev. i wp: write protect this input controls the device write protect feature. wp pin connected to v ss allows write operations to the entire memory. when this pin is connected to vcc, the entire memory is write protected. when left floating, an internal pull-down resistor on this input will keep the memory unprotected. read operations are not affected. a0, a1, a2: device address inputs these inputs are used for extended addressing capability. the a0, a1, a2 pins can be hardwired to v cc or v ss , or left unconnected. when hardwired, up to eight cat24fc32s may be addressed on a single bus system. when the pins are left unconnected, the default values are zero. the levels on these inputs are compared with corresponding bits, a2, a1, a0, from the slave address byte. pin description scl: serial clock the serial clock input clocks all data transferred into or out of the device. the scl line requires a pull-up resistor if it is driven by an open drain output. sda: serial data/address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. a pull-up resistor must be connected from sda line to vcc. the value of the pull-up resistor, rp, can be calculated based on minimum and maximum values from figure 4 and figure 5. (see note). note: according to the fast mode i 2 c bus specification, for bus capacitance up to 200 pf, the pull up device can be a resistor. for bus loads between 200 pf and 400 pf, the pull-up device can be a current source (imax = 3 ma) or a switched resistor circuit. figure 4 figure 5 minimum r p as a function of supply voltage (iol = 3 ma @ volmax) 2.5 2 1.5 1 0.5 0 1.6 2 2.4 2.8 3.2 3.6 4 v cc (v) r p min (kohm) minimum r p value versus bus capacitance (fast mode i 2 c bus / tr max = 300 ns) 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 50 100 150 200 250 300 350 400 cbus (pf) r p max (kohm)
cat24fc32 7 doc. no. 1020, rev. i functional description the cat24fc32 supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat24fc32 operates as a slave device. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition (figure 6). start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat24fc32 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing after the bus master sends a start condition, a slave address byte is required to enable the cat24fc32 for a read or write operation (figure 7). the four most significant bits of the 8-bit slave address are fixed as binary 1010. the cat24fc32 uses the next three bits as address bits. the address bits a2, a1 and a0 are used to select which device is accessed from maximum eight devices on the same bus. these bits must compare to their hardwired input pins. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is initiated, and when set to 0, a write operation is selected. following the start condition and the slave address byte, the cat24fc32 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat24fc32 then performs a read or write operation depending on the state of the r/w bit. figure 6. start/stop timing start bit sda stop bit scl 1 0 1 0 a2 a1 a0 r/w figure 7. slave address bits
cat24fc32 8 doc. no. 1020, rev. i acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the sda line remains stable low during the high period of the acknowledge related clock pulse (figure 8). the cat24fc32 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. the cat24fc32 does not generate acknowledge if an internal write cycle is in progress. when the cat24fc32 begins a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat24fc32 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. the master must then issue a stop condition to return the cat24fc32 to the standby power mode and place the device in a known state. figure 8. acknowledge timing write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends two 8-bit address words that are to be written into the address pointers of the cat24fc32. after receiving another acknowledge from the slave, the master device transmits the data to be written into the addressed memory location. the cat24fc32 acknowledges once more and the master generates the stop condition. at this time, the device begins an internal programming cycle to nonvolatile memory. while the cycle is in progress, the device will not respond to any request from the master device. page write the cat24fc32 writes up to 32 bytes of data, in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the master is allowed to send up to 31 additional bytes. after each byte has acknowledge 1 start scl from master 89 data output from transmitter data output from receiver figure 9. byte write timing a 15 a 8 slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t a 7 a 0 byte address a c k x x xx x = don't care bit
cat24fc32 9 doc. no. 1020, rev. i figure 10. page write timing been transmitted, cat24fc32 will respond with an acknowledge, and internally increment the five low order address bits by one. the high order bits remain unchanged. if the master transmits more than 32 bytes before sending the stop condition, the address counter wraps around, and previously transmitted data will be overwritten. when all 32 bytes are received, and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the cat24fc32 in a single write cycle. acknowledge polling disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the hosts write operation, cat24fc32 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if cat24fc32 is still busy with the write operation, no ack will be returned. if cat24fc32 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection the write protection feature allows the user to protect against inadvertent programming of the memory array. if the wp pin is connected to v cc , the entire memory array is protected and becomes read only. the cat24fc32 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the devices failure to send an acknowledge after the first byte of data is received. the wp input is sampled in the end of acknowledge pulse after second address byte, accordingly with setup and hold times relative to negative clock edge (figure 2). read operations the read operation for the cat24fc32 is initiated in the same manner as the write operation with one exception, that r/w bit is set to one. three different read operations are possible: immediate/current address read, selective/random read and sequential read. immediate/current address read the cat24fc32s address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address figure 11. immediate address read timing scl sda 8th bit stop no ack data out 89 slave address s a c k bus activity: master sda line s t a r t n o a c k data s t o p p x=don't care bit a 15 a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 a 0 byte address data n+31 data a c k s t o p a c k data n a c k p a c k x xx x
cat24fc32 10 doc. no. 1020, rev. i n, the read immediately following would access data from address n + 1. if n = e (where e = 4095), then the counter will wrap around to address 0 and continue to clock out data. after the cat24fc32 receives its slave address information (with the r/w bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. the master device does not send an acknowledge, but will generate a stop condition. selective/random read selective/random read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte addresses of the location it wishes to read. after cat24fc32 acknowledges, the master device sends the start condition and the slave address again, this time with the r/w bit set to one. the cat24fc32 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat24fc32 sends the initial 8-bit byte requested, the master will respond with an acknowledge which tells the device it requires more data. the cat24fc32 will continue to output an 8-bit byte for each acknowledge sent by the master. the operation will terminate when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from cat24fc32 is outputted sequentially with data from address n followed by data from address n + 1. the read operation address counter increments all of the cat24fc32 address bits so that the entire memory array can be read during one operation. after the last memory address is read out, the counter will wrap around and continue to clock out data bytes. figure 12. selective read timing x = don't care bit figure 13. sequential read timing bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address xx a 15 a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 a 0 byte address slave address s a c k n o a c k s t a r t data p s t o p xx
cat24fc32 11 doc. no. 1020, rev. i ordering information notes: (1) the device used in the above example is a cat24fc32ji-te13 (soic, industrial temperature, 1.8 volt to 3.6 volt operating voltage, tape & reel) temperature range prefix device # suffix 24fc32 j i te13 product number tape & reel te13: 2000/reel package p: pdip k: soic (eiaj) j: soic (jedec) u: tssop operating voltage blank: 1.8 v - 3.6 v x cat optional company id
cat24fc32 12 doc. no. 1020, rev. i revision history date rev. reason 9/22/2003 h eliminated commercial temperature range class updated marking 12/9/2003 i removed automotive temperatur range changed industrial temp to i from blank in ordering information
cat24fc32 13 doc. no. 1020, rev. i catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 1020 revison: i issue date: 12/9/03 type: final

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